Vertical Field Effect Transistor Device and Method for Manufacturing the Same

Abstract

Provided is a vertical field effect transistor (VFET) device and a method for manufacturing the same. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure and a conductor layer formed on a lower portion of the gate dielectric layer; a top source / drain (S / D) region formed above the fin structure and the gate structure; a bottom S / D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer and between the top S / D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S / D region. A top surface of the gate dielectric layer is positioned at the same or substantially the same height as a top surface of the top spacer, or is positioned lower than the top surface of the top spacer and higher than the top surface of the conductor layer.

Description

Technical Field

[0001] An apparatus consistent with exemplary embodiments of the inventive concept relates to a vertical field effect transistor (VFET). Background Art

[0002] It is known that VFETs are superior to conventional planar field effect transistors (FETs) in scale, because semiconductor cells of even smaller sizes can be designed and manufactured.

[0003] As is well known, a VFET is characterized in that a vertical fin structure is formed on a substrate, and top source / drain (S / D) regions and bottom S / D regions are formed on and under the fin structure, respectively. In addition, a gate structure is formed along sidewalls of the fin structure to surround the fin structure. Like in a planar FET, the gate structure of a VFET that receives an input signal to activate the VFET and its gate controllability are factors improving overall VFET performance.

[0004] Accordingly, improved techniques and process methods for forming a gate structure of a VFET will be needed. Summary of the Invention

[0005] Exemplary embodiments of the inventive concept relate to a vertical field effect transistor (VFET) device and a method of manufacturing the VFET device.

[0006] These embodiments may provide a VFET device having improved gate structure performance and a method of implementing an improved VFET device.

[0007] According to an exemplary embodiment, there is provided a VFET device, which may include: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure and a conductor layer formed on a lower portion of the gate dielectric layer; a top source / drain (S / D) region formed on the fin structure and the gate structure; a bottom S / D region formed under the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer and between the top S / D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S / D region. A top surface of the gate dielectric layer is positioned at the same or substantially the same height as a top surface of the top spacer, or is positioned lower than the top surface of the top spacer and higher than the top surface of the conductor layer.

[0008] According to an exemplary embodiment, a VFET device is provided. The VFET device may include: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure and a conductor layer formed on a lower portion of the gate dielectric layer; a top source / drain (S / D) region formed on the fin structure to cover the gate structure; a bottom S / D region formed under the fin structure and the gate structure; an interlayer formed outside the gate structure and the top S / D region; an air gap spacer formed between the top S / D region and a top surface of the conductor layer of the gate structure and between the gate structure and the interlayer; and a bottom spacer formed between the gate structure and the bottom S / D region.

[0009] According to an exemplary embodiment, a method of manufacturing a VFET device is provided. The method may include: providing a stack including a bottom S / D region, a fin structure, a gate structure on a sidewall of the fin structure, an interlayer on a sidewall of the gate structure, and a mask layer on the fin structure, the stack further including a bottom spacer on the bottom S / D region and under the gate structure and the interlayer, and the gate structure including a gate dielectric layer on the sidewall of the fin structure and a conductor layer on the gate dielectric layer; etching the stack from a top surface of the stack to remove the gate dielectric layer and the conductor layer by different depths from the top surface of the stack and to remove the mask layer to leave an upper portion of the gate dielectric layer and the fin structure such that the upper portion of the gate dielectric layer is positioned above a plane where a top surface of the conductor layer is located; and forming a top S / D region on a top surface of the fin structure, a top surface of the gate structure, and a sidewall of the interlayer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects of the inventive concept will become more apparent to those of ordinary skill in the art by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0011] Figures 1A to 1C A process of manufacturing a VFET according to an exemplary embodiment is shown;

[0012] Figures 2A to 2C A process of manufacturing a VFET according to another exemplary embodiment is shown;

[0013] Figures 3A to 3C A process of manufacturing a VFET according to another exemplary embodiment is shown; and

[0014] Figures 4A to 4C A process of manufacturing a VFET according to another exemplary embodiment is shown. DETAILED DESCRIPTION

[0015] Various embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. These embodiments are exemplary and may be embodied in many different forms and should not be construed as limiting the inventive concept. Rather, these embodiments are provided only to make the present disclosure thorough and complete and to fully convey the inventive concept to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of each layer and region may have been exaggerated. Accordingly, the drawings are not necessarily to scale, and some features may be exaggerated to show details of particular components or elements. Thus, the specific structural and functional details disclosed herein are not to be construed as limiting, but rather as a representative basis for teaching those skilled in the art various ways of using the embodiments.

[0016] The embodiments provided herein are not excluded from being associated with one or more features of another example or another embodiment that is also provided herein or that is not provided herein but is consistent with the inventive concept. For example, even if the content described in a particular embodiment is not described in a different embodiment, the content may be understood to be relevant to or combined with the different embodiment, unless otherwise mentioned in its description.

[0017] Hereinafter, for the purpose of description, the terms "upper", "lower", "top", "bottom", "left", and "right" and their derivatives may be related to the disclosed structures based on the context as they are oriented in the drawings. The same reference numerals in different drawings may refer to the same structural components or their elements.

[0018] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0019] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of...", when following a list of elements, modify the entire list of elements, rather than individual elements in the list. Thus, for example, both "at least one of A, B, or C" and "A, B, and / or C" represent A, B, C, or any combination thereof.

[0020] As used herein, the term "surface" may refer to one end or endpoint of a corresponding element and is not limited to a plane. Thus, a "surface" may indicate a non-flat area or point. For example, a "top (bottom) surface" may refer to the top (bottom) end or endpoint of a corresponding element.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. It will also be understood that terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0022] Figures 1A to 1C A process for fabricating a VFET according to an exemplary embodiment is shown.

[0023] First, Figure 1A The semiconductor stack 100 shown is provided for further processing to complete the VFET. According to an exemplary embodiment, the semiconductor stack 100 may be provided by a chemical mechanical polishing (CMP) operation that includes chemical mechanical planarization using a chemical reaction. However, the method of providing the semiconductor stack 100 is not limited to a specific process such as a CMP operation.

[0024] The semiconductor stack 100 includes a bottom S / D region 110 formed on a substrate (not shown), a fin structure 120 configured to become the channel of the VFET, and a gate structure 130 formed on sidewalls of the fin structure 120. Here, the gate structure 130 may be conformally formed along the sidewalls of the fin structure 120. The gate structure 130 includes at least a gate dielectric layer 131 and a conductor layer 132, and the gate dielectric layer 131 includes at least an interface layer 131-1 formed on the sidewalls of the fin structure 120 and a high-κ dielectric layer 131-2 formed on the interface layer 131-1. The semiconductor stack 100 further includes an interlayer 140 formed on sidewalls of the gate structure 130, a mask layer 150 formed on the fin structure 120, and a bottom spacer 160 formed on the bottom S / D region 110 and under the gate structure 130 and the interlayer 140.

[0025] The fin structure 120 may be formed of a semiconductor epitaxial (or epitaxial layer) that grows on a substrate (not shown) and is formed of a material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and / or silicon-containing materials (but not limited thereto). The bottom S / D region 110 may be formed by doping the semiconductor epitaxial with one or more dopants such as boron (B) for a p-channel VFET and phosphorus (P) for an n-channel VFET (but not limited thereto).

[0026] The interface layer 131-1 of the gate dielectric layer 131 may have been formed using a material selected from silicon monoxide (SiO), silicon dioxide (SiO 2) and / or at least one material of silicon oxynitride (SiON) and is formed along the sidewalls of the fin structure 120 by at least one of chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), and atomic layer deposition (ALD), but not limited thereto. The interface layer 131-1 can be provided to not only protect the fin structure 120 but also facilitate the growth of the high-κ dielectric layer 131-2 thereon and provide an interface with the necessary characteristics of the fin structure 120.

[0027] The high-κ dielectric layer 131-2 can be formed of a metal oxide material or a metal silicate having a dielectric constant value greater than 7 (such as oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof), but not limited thereto. Preferably but not necessarily, the material of the high-κ dielectric layer 131-2 can be HfO 2 and / or HfSiON, but not limited thereto. The high-κ dielectric layer 131-2 can be provided to allow for an increased gate capacitance without associated current leakage at the gate structure 130 in the VFET.

[0028] The conductor layer 132 can include a metal or a metal compound, such as Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, or combinations thereof, but not limited thereto.

[0029] One of the parameters affecting the performance of the gate structure 130 can be the lateral thickness of the gate dielectric layer 131 formed along the sidewalls of the fin structure 120. The smaller the lateral thickness of the gate dielectric layer 131, the better the performance the gate structure 130 can have.

[0030] The interlayer 140 insulates the VFET from an external power source and can be formed of a nitride, an oxide, or a combination thereof, but not limited thereto. The mask layer 150 protects the fin structure 120 from the etching operations to be described in the subsequent processes of manufacturing the VFET. A photoresist or silicon nitride (SiN) can be used as the mask material, but not limited thereto.

[0031] After providing Figure 1A the semiconductor stack 100 as shown, an etching operation is applied to the semiconductor stack 100 to remove the mask layer 150 and a given portion of the gate structure 130 from the initial top surface of the gate structure 130, thereby leaving only a specific vertical length of the fin structure 120 above the plane where the top surface 130T of the gate structure 130 is located between the interlayers 140, as Figure 1B shown. Thus, the fin structure 120 at the upper portion 120U takes the form of protruding from the plane where the top surface 130T of the gate structure 130 is located between the interlayers 140.

[0032] According to an exemplary embodiment, the foregoing etching operation applied to the semiconductor stack 100 may include wet etching to selectively remove specific materials, namely, portions of the gate structure 130 and the mask layer 150, which may be formed of a nitride material such as silicon nitride (SiN), but is not limited thereto.

[0033] After the above etching operation, a top spacer 170 and a top S / D region 180 are formed to complete the VFET, as Figure 1C shown.

[0034] By using at least one of CVD, PECVD, and ALD (but not limited thereto), the top spacer 170 is formed over the gate structure 130 and between the fin structure 120 and the interlayer 140. The top spacer 170 and the bottom spacer 160 may be formed of at least one material selected from silicon oxide (SiO 2 ), silicon nitride (SiN), and any low-k material having a dielectric constant value less than 3.5, such as SiCOH or SiBCN, but is not limited thereto. The top spacer 170 and the bottom spacer 160 may be formed of the same or different materials and may be used to electrically isolate the gate structure 130 from the top S / D region 180 and the bottom S / D region 110, respectively.

[0035] The top S / D region 180 is formed at a position over the fin structure 120 and the top spacer 170 and between the interlayers 140. To form the top S / D region 180, a semiconductor epitaxial layer may be grown on the bottom surface 120T of the protruding fin structure 120, and then the semiconductor epitaxial layer may be doped with one or more dopants, such as boron (B) for a p-channel VFET and phosphorus (P) for an n-channel VFET, but is not limited thereto.

[0036] However, in this embodiment, as Figure 1C shown, the upper portion 131U of the gate dielectric layer 131 thickens in the lateral direction from the sidewall of the fin structure 120 and the conductor layer 132 thins in the lateral direction from the sidewall of the fin structure 120. That is, the equivalent oxide thickness (EOT) of the gate dielectric layer 131 increases at the upper portion 131U. Therefore, the gate dielectric layer 131 is thicker at the upper portion 131U than at the lower portion 131L, and the conductor layer 132 is thinner at the upper portion 132U than at the lower portion 132L. The inventors of the present application have confirmed that this increase in the EOT may be caused by, for example, silicon monoxide (SiO), silicon dioxide (SiO 2) and / or an oxide material such as silicon oxynitride (SiON) to form at least an interface layer 131-1 that is exposed to air during subsequent operations for forming a VFET, thereby causing oxidation or re-oxidation of the top surface 131T of the gate dielectric layer 131 including the interface layer 131-1. The inventors also recognize that an increase in the EOT at the gate dielectric layer 131 adversely affects the performance of the gate structure 130.

[0037] Accordingly, referring to Figures 2A to 2C and Figures 3A to 3C new embodiments are provided.

[0038] Figures 2A to 2C FIG. shows a process for manufacturing a VFET according to another exemplary embodiment.

[0039] Similar to the previous embodiment, this embodiment begins by providing Figure 2A the semiconductor stack 200 shown in FIG. for further processing to complete the VFET. The semiconductor stack 200 includes a bottom S / D region 210, a fin structure 220, and a gate structure 230. The gate structure 230 includes a gate dielectric layer 231 and a conductor layer 232, where the gate dielectric layer 231 is formed of at least an interface layer 231-1 and a high-κ dielectric layer 231-2. The semiconductor stack 200 also includes an interlayer 240, a mask layer 250, and a bottom spacer 260. Since the materials, structures, and functions of the above elements included in the semiconductor stack 200 can be the same as those included in the semiconductor stack 100, repeated descriptions thereof are omitted.

[0040] However, the etching operations and the top spacer formation operations described below with reference to Figure 2B and Figure 2C are different from those described with reference to Figure 1B and Figure 1C described.

[0041] Referring to Figure 2B , after providing Figure 2A the semiconductor stack 200 shown in FIG., an etching operation is performed on the semiconductor stack 200 to remove portions of the gate structure 230 and the mask layer 250. Here, the gate structure 230 is etched such that portions of the gate dielectric layer 231 and portions of the conductor layer 232 are removed from Figure 2AThe top surface of the gate structure 230 shown has different depths removed. In other words, the gate dielectric layer 231 is etched to a depth smaller than the depth to which the conductor layer 232 is etched, or the conductor layer 232 is etched to a depth greater than the depth to which the gate dielectric layer 231 is etched, such that after the etching operation, a portion of a specific vertical length of the gate dielectric layer 231 that is above the plane in which the top surface 232T of the conductor layer 232 lies (hereinafter referred to as the "upper portion 231U of the gate dielectric layer 231") remains on the sidewall 220S of the fin structure 220 at the upper portion 220U of the fin structure 220. Thus, the upper portion 220U of the fin structure 220, together with the upper portion 231U of the gate dielectric layer 231, takes the form of protruding from the plane in which the top surface 232T of the conductor layer 232 lies between the interlayers 240. In addition, by this etching operation, the top surface 231T of the gate dielectric layer 231 is positioned higher than the top surface 232T of the conductor layer 232 and is coplanar or substantially coplanar with the top surface 220T of the fin structure 220.

[0042] Accordingly, the upper portion 231U of the gate dielectric layer 231 (where the EOT described in the previous embodiments may increase laterally due to oxidation or re-oxidation, including the portion where the EOT may be the largest) remains above the plane in which the top surface 232T of the conductor layer 232 lies. That is, on one side of the upper portion 231U of the gate dielectric layer 231, there is no portion of the conductor layer 232 provided. Thus, even if an EOT increase occurs at the upper portion 231U of the gate dielectric layer 231, the lower portion 231L of the gate dielectric layer 231 that lies below the plane in which the top surface 232T of the conductor layer 232 lies (where no EOT increase occurs) can maintain a uniformly thin or substantially uniformly thin lateral thickness along the sidewall 220S of the fin structure 220, thereby not adversely affecting gate controllability.

[0043] The etching operation of the present embodiment can also be performed by the same wet etching as performed in the previous embodiments as Figure 1B shown. Accordingly, a repetitive description thereof is omitted.

[0044] In Figure 2B After the etching operation shown, a top spacer 270 and a top S / D region 280 are formed to complete the VFET, as Figure 2C shown. Since the materials, structures, and functions of the top spacer 270 and the top S / D region 280 can be the same as those described above with reference to Figure 1C a repetitive description thereof is omitted.

[0045] However, compared with Figure 1CUnlike the previous embodiment shown (where the bottom surface of the top spacer 170 contacts the entire top surface 130T of the gate structure 130 including the gate dielectric layer 131 and the conductor layer 132), the top spacer 270 of this embodiment is formed such that the bottom surface of the top spacer 270 of the VFET contacts only the top surface 232T of the conductor layer 232 in the gate structure 230. Further, according to this embodiment, the top surface 270T of the top spacer 270 is coplanar or substantially coplanar with the top surface 231T of the gate dielectric layer 231 including the interface layer 231-1 and the high-κ dielectric layer 231-2.

[0046] Thus, even if the EOT increases at the upper portion 231U of the gate dielectric layer 231, the upper portion 231U of the gate dielectric layer 231 where the EOT increases is vertically located within the top spacer 270 at the side where the conductor layer 232 is not formed in the gate dielectric layer 231, and the lateral thicknesses of the lower portion 231L of the gate dielectric layer 231 and the conductor layer 232 outside the top spacer 270 do not change or substantially do not change along the lower portion 220L of the fin structure 220.

[0047] Thus, by preventing the performance degradation of the gate structure 230 that may occur in the previous embodiment, the etching operation according to this embodiment and the subsequent operation of forming the top spacer 270 can form an improved VFET.

[0048] In addition, Figure 2B the amount of the upper portion 231U of the gate dielectric layer 231 to be retained after the etching operation can be determined such that the vertical length of the portion of the upper portion 231U of the gate dielectric layer 231 (where the EOT increases and causes performance degradation of the gate structure 230) can be less than or equal to the vertical thickness of the top spacer 270.

[0049] Figures 3A to 3C FIG. shows a process of manufacturing a VFET according to another exemplary embodiment.

[0050] Similar to the previous embodiment, this embodiment begins by providing Figure 3AThe semiconductor stack 300 shown is for further processing to complete the VFET. The semiconductor stack 300 includes a bottom S / D region 310, a fin structure 320, and a gate structure 330. The gate structure 330 includes a gate dielectric layer 331 and a conductor layer 332, where the gate dielectric layer 331 is formed of at least an interface layer 331-1 and a high-κ dielectric layer 331-2. The semiconductor stack 300 further includes an interlayer 340, a mask layer 350, and a bottom spacer 360. Since the materials, structures, and functions of the above elements included in the semiconductor stack 300 can be the same as those included in the semiconductor stacks 100 and 200, the repetitive description thereof is omitted.

[0051] However, the etching operations and top spacer formation operations described below with reference to Figure 3B and Figure 3C are different from those described with reference to Figure 1B 、 Figure 1C 、 Figure 2B and Figure 2C .

[0052] With reference to Figure 3B , after providing the semiconductor stack 300 shown in Figure 3A , an etching operation is performed on the semiconductor stack 300 to remove a portion of the gate structure 330 and the mask layer 350. Here, the gate structure 330 is etched such that portions of the gate dielectric layer 331 and the conductor layer 332 are removed from the top surface of the gate structure 330 shown in Figure 3A by different depths. In other words, the gate dielectric layer 331 is etched to a depth smaller than the depth to which the conductor layer 332 is etched, or the conductor layer 332 is etched to a depth greater than the depth to which the gate dielectric layer 331 is etched, such that after the etching operation, a portion of the gate dielectric layer 331 having a specific vertical length above the plane in which the top surface 332T of the conductor layer 332 is located (hereinafter referred to as the "upper portion 331U of the gate dielectric layer 331") remains on the sidewall 320S of the fin structure 320 at the upper portion 320U of the fin structure 320. Thus, the upper portion 320U of the fin structure 320 and the upper portion 331U of the gate dielectric layer 331 together take the form of protruding from the plane in which the top surface 332T of the conductor layer 332 is located between the interlayers 340.

[0053] However, Figure 3B the etching operation according to the present embodiment shown in Figure 2BThe difference from the previous embodiment is that the amount of the upper portion 331U of the gate dielectric layer 331 retained by the etching operation of the semiconductor stack 300 is less than the amount of the upper portion 231U of the gate dielectric layer 231 retained after the etching operation in the previous embodiment. That is, the vertical length of the upper portion 331U of the gate dielectric layer 331 is less than the vertical length of the upper portion 320U of the fin structure 320, and the upper portion 320U of the fin structure 320 takes the form of protruding from the plane of the top surface 332T of the conductor layer 332, and the top surface 332T of the conductor layer 332 is formed to be lower than the top surface 320T of the fin structure 320.

[0054] However, Figure 3B the purpose and result of the etching operation can still be the same as those of Figure 2B In other words, the upper portion 331U of the gate dielectric layer 331 (where the EOT may increase laterally due to oxidation or re-oxidation, including the part where the EOT may be the largest) remains above the plane of the top surface 332T of the conductor layer 332. That is, on one side of the upper portion 331U of the gate dielectric layer 331, there is no part of the conductor layer 332 provided. Therefore, even if the EOT increase occurs at the upper portion 331U of the gate dielectric layer 331, the lower portion 331L of the gate dielectric layer 331 located below the plane of the top surface 332T of the conductor layer 332 (where the EOT increase does not occur) can maintain a uniform thin lateral thickness or a substantially uniform thin lateral thickness along the sidewall 320S of the fin structure 320, thus not adversely affecting the gate controllability.

[0055] The etching operation of this embodiment can also be performed by the same wet etching as performed in the previous embodiments shown in Figure 1B and Figure 2B Therefore, the repetitive description thereof is omitted.

[0056] After Figure 3B the etching operation shown, a top spacer 370 and a top S / D region 380 are formed to complete the VFET, as shown in Figure 3C Since the materials, structures, and functions of the top spacer 370 and the top S / D region 380 can be the same as those described above with reference to Figure 1C and Figure 2C the repetitive description thereof is omitted.

[0057] Figure 3C The operation of forming the top spacer 370 according to this embodiment shown in Figure 2C is similar to the operation performed in the previous embodiment shown in

[0058] However, different from the previous embodiments Figure 2C shown, in which the top surface 270T of the top spacer 270 is coplanar or substantially coplanar with the top surface 231T of the gate dielectric layer 231, the top spacer 370 of the present embodiment is formed such that the top surface 370T of the top spacer 370 is positioned higher than the top surface 331T of the gate dielectric layer 331 including the interface layer 331-1 and the high-κ dielectric layer 331-2.

[0059] Accordingly, even if the EOT increases at the upper portion 331U of the gate dielectric layer 331, the upper portion 331U of the gate dielectric layer 331 where the EOT increases is vertically located within the top spacer 370 where no conductor layer 332 is formed, and the lower portion 331L of the gate dielectric layer 331 and the lateral thickness of the conductor layer 332 outside the top spacer 370 do not change or substantially do not change along the lower portion 320L of the fin structure 320.

[0060] Accordingly, by preventing the performance degradation of the gate structure 330, which may occur in Figures 1A to 1C the previous embodiments shown, the etching operation according to the present embodiment and the subsequent operation of forming the top spacer 370 can also form an improved VFET.

[0061] In addition, Figure 3B the amount of the upper portion 331U of the gate dielectric layer 331 to be retained after the etching operation in

[0062] Figures 4A to 4C can be determined such that the vertical length of the portion of the upper portion 331U of the gate dielectric layer 331 (where the EOT increases and causes the performance degradation of the gate structure 330) can be less than the vertical thickness of the top spacer 370.

[0063] Similar to the previous embodiments, the present embodiment begins with providing Figure 4A the semiconductor stack 400 shown by a CMP operation (but not limited thereto) for further processing to complete the VFET. The semiconductor stack 400 includes a bottom S / D region 410, a fin structure 420, and a gate structure 430, where the gate structure 430 includes a gate dielectric layer 431 and a conductor layer 432, and the gate dielectric layer 431 is formed of at least an interface layer 431-1 and a high-κ dielectric layer 431-2. The semiconductor stack 400 further includes an interlayer 440, a mask layer 450, and a bottom spacer 460. Since the materials, structures, and functions of the above elements included in the semiconductor stack 400 can be the same as those included in the semiconductor stacks 100 to 300, the repeated description thereof is omitted.

[0064] In addition,Figure 4B The etching operation of the present embodiment shown is similar to Figure 2B the etching operation of the previous embodiment shown. That is, an etching operation is performed on the semiconductor stack 400 to remove the gate dielectric layer 431 and the conductor layer 432 from the top surface of the gate structure 430 by different depths and to remove the mask layer 450, whereby the upper portion 420U of the fin structure 420 and the upper portion 431U of the gate dielectric layer 431 formed along the upper portion 420U of the fin structure 420 take the form of protruding from the plane of the top surface 432T of the conductor layer 432 between the interlayers 440. After this etching operation, the top surface 431T of the gate dielectric layer 431 is coplanar or substantially coplanar with the top surface 420T of the fin structure 420.

[0065] Next, with reference to Figure 4C , with the fin structure 420 laterally surrounded by the gate dielectric layer 431, an epitaxial growth 480 is grown on the top surface 420T of the fin structure 420, whereby the epitaxial growth 480 grows in the upward direction and extends to the upper portion of the interlayer 440, thereby forming an air gap spacer 470 below the epitaxial growth 480 and above the conductor layer 432 and between the gate dielectric layer 431 and the interlayer 440. Here, the air gap spacer 470 can serve as a top spacer for sealing the high-κ dielectric layer 431-2 in the present embodiment for a VFET. That is, the air gap spacer 470 can also be regarded as a kind of top spacer. The epitaxial growth 480 can be a semiconductor epitaxial growth formed of a material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), and / or a silicon-containing material, without being limited thereto. Later, the epitaxial growth 480 will be doped with one or more dopants in a subsequent operation (not shown) to form top S / D regions.

[0066] Since the growth of the epitaxial growth 480 generates an air gap spacer 470 on one side of the gate dielectric layer 431 and above the conductor layer 432 instead of a top spacer having a dielectric constant greater than that of air, the possible parasitic capacitance occurring between the top S / D regions, the top spacer, and the gate structure can be reduced, thereby improving the performance of the VFET formed by the present embodiment.

[0067] The foregoing is a description of exemplary embodiments and is not to be construed as limiting thereof. Although some exemplary embodiments have been described, those skilled in the art will readily recognize that many modifications can be made in the above embodiments without substantially departing from the inventive concept.

[0068] This application claims the priority of U.S. Provisional Application No. 62 / 846,153, filed on May 10, 2019, with the United States Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A vertical field effect transistor device, comprising: a fin structure formed on a substrate; a gate structure, the gate structure comprising: a gate dielectric layer formed on an upper portion of a sidewall of the fin structure; and a conductor layer formed on a lower portion of the gate dielectric layer; a top source / drain region formed above the fin structure and the gate structure; a bottom source / drain region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer and between the top source / drain region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom source / drain region, wherein a top surface of the gate dielectric layer is positioned at the same height as a top surface of the top spacer or is positioned lower than the top surface of the top spacer and higher than the top surface of the conductor layer, wherein an upper portion of the gate dielectric layer on which the top spacer is formed is laterally thicker than a lower portion of the gate dielectric layer, and the lower portion of the gate dielectric layer has a uniform lateral thickness along a lower portion of the sidewall of the fin structure.

2. The vertical field effect transistor device according to claim 1, wherein the top surface of the gate dielectric layer is positioned at the same height as the top surface of the top spacer and is positioned at the same height as a top surface of the fin structure.

3. The vertical field effect transistor device according to claim 1, wherein the top surface of the gate dielectric layer is positioned lower than the top surface of the top spacer, and wherein a portion of the top spacer is formed on the top surface of the gate dielectric layer.

4. The vertical field effect transistor device according to claim 1, wherein the greater lateral thickness at the upper portion of the gate dielectric layer is caused by at least oxidation or re-oxidation of the gate dielectric layer.

5. The vertical field effect transistor device according to claim 1, wherein the gate dielectric layer comprises: an interface layer conformally formed on the sidewall of the fin structure; and a high-k dielectric layer conformally formed on the interface layer, except at a position where the high-k dielectric layer extends and is formed on a top surface of the bottom spacer.

6. The vertical field effect transistor device according to claim 5, wherein the interface layer comprises at least one of silicon monoxide, silicon dioxide, and silicon oxynitride, and wherein the high-k dielectric layer has a dielectric constant value greater than 7 and comprises a metal oxide or metal silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof.

7. The vertical field effect transistor device according to claim 6, wherein the high-κ dielectric layer has a dielectric constant value greater than 15 and comprises at least one of HfO 2 and HfSiON.

8. The vertical field effect transistor device according to claim 1, further comprising an interlayer formed on sidewalls of the conductor layer, sidewalls of the top spacer, and sidewalls of the top source / drain region to insulate the vertical field effect transistor device from an external power source, the interlayer comprising a nitride, an oxide, or a combination thereof.

9. The vertical field effect transistor device according to claim 1, wherein a vertical thickness of the top spacer is greater than or equal to a vertical length of an upper portion of the gate dielectric layer.

10. A vertical field effect transistor device comprising: a fin structure formed on a substrate; a gate structure, the gate structure comprising: a gate dielectric layer formed on an upper portion of a sidewall of the fin structure; and a conductor layer formed on a lower portion of the gate dielectric layer; a top source / drain region formed on the fin structure to cover the gate structure; a bottom source / drain region formed under the fin structure and the gate structure; a spacer layer formed outside the gate structure and the top source / drain region; an air gap spacer formed between the top source / drain region and a top surface of the conductor layer of the gate structure and between the gate structure and the spacer layer; and a bottom spacer formed between the gate structure and the bottom source / drain region.

11. The vertical field effect transistor device according to claim 10, wherein the gate dielectric layer comprises: an interface layer conformally formed on the sidewall of the fin structure; and a high-k dielectric layer conformally formed on the interface layer, except at a position where the high-k dielectric layer extends and is formed on a top surface of the bottom spacer.

12. The vertical field effect transistor device according to claim 11, wherein the gate dielectric layer has a uniform thickness along the sidewall of the fin structure, except at the position where the high-k dielectric layer extends and is formed on the top surface of the bottom spacer.

13. A method for manufacturing a vertical field effect transistor device, the method comprising: providing a stack including a bottom source / drain region, a fin structure, a gate structure on a sidewall of the fin structure, a spacer layer on a sidewall of the gate structure, and a mask layer on the fin structure, the stack further including a bottom spacer on the bottom source / drain region and under the gate structure and the spacer layer, and the gate structure including a gate dielectric layer on the sidewall of the fin structure and a conductor layer on the gate dielectric layer; etching the stack from a top surface of the stack to remove the gate dielectric layer and the conductor layer from the top surface of the stack by different depths and remove the mask layer to leave an upper portion of the gate dielectric layer and the fin structure, such that the upper portion of the gate dielectric layer is positioned above a plane where a top surface of the conductor layer is located; and forming a top source / drain region on a top surface of the fin structure, a top surface of the gate structure, and a sidewall of the spacer layer.

14. The method according to claim 13, further comprising forming a top spacer at least on the conductor layer and between a sidewall of the upper portion of the gate dielectric layer and a sidewall of the spacer layer.

15. The method according to claim 14, wherein a top surface of the gate dielectric layer is positioned at the same height as a top surface of the top spacer or is positioned lower than the top surface of the top spacer.

16. The method according to claim 14, wherein the top spacer is formed of a material having a dielectric constant value less than 3.

5.

17. The method according to claim 14, wherein the top spacer is further formed on the top surface of the gate dielectric layer such that the top surface of the gate dielectric layer is positioned lower than the top surface of the top spacer and higher than the top surface of the conductor layer.

18. The method according to claim 14, wherein an upper portion of the gate dielectric layer on which the top spacer is formed is laterally thicker than a lower portion of the gate dielectric layer, and the lower portion of the gate dielectric layer has a uniform lateral thickness along a lower portion of the sidewall of the fin structure.

19. The method according to claim 18, wherein the greater lateral thickness at the upper portion of the gate dielectric layer is caused by at least oxidation or re-oxidation of the gate dielectric layer.

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