A device and method for low-loss coupling capacitor

Abstract

A low-loss coupling capacitor structure includes an n-type varactor (NVAR) structure (100) and a p-type varactor (PVAR) structure (200). The structure in the NVAR structure (100) includes a doped p-type semiconductor substrate (Psub) (106), a deeply doped n-type semiconductor well (DNW) (105) in the Psub (106), and a doped p-type semiconductor well (Pwell) (104) in the DNW. The circuit structure also includes a source terminal (102) of the doped p-type semiconductor material in the Pwell (104) and a drain terminal (101) of the doped p-type semiconductor material in the Pwell (104). In addition, the circuit structure includes an insulated gate (103) on the surface of the Pwell (104), a metal pattern including multiple layers of metal lines (107), and a plurality of through holes (108) passing through the metal lines (107). The through hole (108) is a contact point connecting the metal line (107) to the gate (103), the source terminal (102) and the drain terminal (101).

Description

[0001] Cross-application of related applications

[0002] This application claims priority to U.S. non-provisional patent application No. 14 / 687,549, filed on April 15, 2015, entitled “A device and method for a low-loss coupling capacitor,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to metal-oxide-semiconductor (MOS) capacitor design and, in a specific embodiment, to an apparatus and method for low-loss coupling capacitors that can be used in radio frequency (RF) or other applications. Background Art

[0004] A coupling capacitor is a capacitor that can be used to isolate the direct current (DC) bias of one circuit block from the DC bias of another circuit block. For example, in an analog circuit, a coupling capacitor is used to connect two circuits so that only the AC signal from the first circuit can pass to the next circuit, while the DC is blocked. This technique helps to isolate the DC bias settings of the two coupled circuits. In another example, coupling capacitors can be used for AC coupling in digital circuits to transmit digital signals with zero DC components, also known as DC balanced signals. DC balanced waveforms are very useful in communication systems because they can be used on AC coupled electrical connections to avoid voltage imbalance problems and charge accumulation between networked systems or components. Improved coupling capacitor design is needed to reduce losses and improve coupling efficiency, while also minimizing the design size of the capacitor structure. For example, this can be used in compact devices to reduce size and reduce power consumption. Summary of the invention

[0005] According to one embodiment, a circuit structure of a coupling capacitor includes a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P-well) in the DNW. The circuit structure also includes a first block of doped p-type semiconductor material extending from the surface of the P-well into the P-well, and a second block of doped p-type semiconductor material extending from the surface of the P-well into the P-well. The first block is a source terminal, and the second block is a drain terminal. In addition, the circuit structure includes an insulating layer on the P-well between the source and the drain, a conductive material on the surface of the insulating layer as the gate, a metal pattern including a multilayer metal line approximately parallel to the surface, and a plurality of through holes passing through the metal line and perpendicular to the metal line. The lowest level through hole is a contact connecting the metal line to the gate, the source terminal, and the drain terminal.

[0006] According to another embodiment, a circuit structure of a coupling capacitor includes a Psub and a doped n-type semiconductor well (N-well) in the Psub. The circuit structure also includes a first block of doped n-type semiconductor material extending from a surface of the N-well into the N-well, and a second block of the doped n-type semiconductor material extending from the surface of the N-well into the N-well. The first block serves as a source terminal, and the second block serves as a drain terminal. In addition, the circuit structure also includes an insulating layer on the surface of the N-well between the source and the drain, a conductive material on the surface of the insulating layer serving as the gate, a metal pattern including a multilayer metal line approximately parallel to the surface, and a plurality of through holes passing through the metal line and perpendicular to the metal line. Contacts connect the metal line to the gate, the source terminal, and the drain terminal.

[0007] According to another embodiment, a method for making a coupling capacitor structure in an n-type varactor (NVAR) configuration includes forming a DNW in a Psub, forming a doped p-type semiconductor well (P-well) in the DNW, placing an insulator on the surface of the P-well, and then placing a metal gate on the surface of the insulator. The method also includes forming a doped p-type semiconductor source terminal on one side of the insulator and the metal gate in the P-well within the surface of the P-well, and forming a doped p-type semiconductor drain terminal on the opposite side of the insulator and the metal gate. Multiple layers of metal wires cover the metal gate and the source / drain terminals. Further, multiple through holes are inserted perpendicular to the layers and connect the metal wires to the metal gate, the doped p-type semiconductor source terminal, and the doped p-type semiconductor drain terminal.

[0008] According to yet another embodiment, a method of making a coupling capacitor structure in a p-type varactor (PVAR) configuration includes forming an N-well in Psub, placing an insulator on the surface of the N-well, and then providing a metal gate, forming a doped n-type semiconductor source terminal on one side of the insulator / metal gate in the N-well within the surface of the P-well, and forming a doped n-type semiconductor drain terminal on the opposite side of the insulator and metal gate. The method also includes covering the metal gate and the source / drain terminals with multiple layers of metal wires. Further, multiple through holes are inserted perpendicular to the layers and connect the metal wires to the metal gate, the doped n-type semiconductor source terminal, and the doped n-type semiconductor drain terminal.

[0009] The above is a rather broad overview of the features of embodiments of the present invention in order to allow a better understanding of the detailed description of the present invention below. Additional features and advantages of embodiments of the present invention will be described below, which constitute the subject matter of the claims of the present invention. It should be appreciated by those skilled in the art that the disclosed concepts and specific embodiments may be readily used as a basis for modifying or designing other structures or processes for achieving the same purposes of the present invention. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a cross-sectional side view of an embodiment of a capacitor structure in an n-type varactor (NVAR) configuration;

[0012] Figure 2 is a cross-sectional side view of an embodiment of a capacitor structure in a p-type varactor (PVAR) configuration;

[0013] Figure 3 shows a top view of an embodiment of a metal pattern for a gate connection and a source / drain connection;

[0014] Figure 4 is a top view of an embodiment of a capacitor array layout;

[0015] Figure 5 An isometric view of an embodiment of a metal pattern for gate and source / drain connections is shown;

[0016] Figure 6 An embodiment of a method of making a low-loss coupling capacitor structure in a NVAR configuration is shown;

[0017] Figure 7 An embodiment of a method of making a low-loss coupling capacitor structure in a PVAR configuration is shown.

[0018] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0019] The making and use of the currently preferred embodiments will be discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use the present invention, and do not limit the scope of the present invention.

[0020] Embodiments for low-loss coupling capacitor structures are provided herein and can be constructed using metal-oxide-semiconductor (MOS) technology or other suitable integrated circuit manufacturing processes. Embodiments include n-type varactor (NVAR) and p-type varactor (PVAR) structures. The choice of structure depends on the circuit situation and the desired application. A varactor is a diode with a variable capacitance that varies as a function of the voltage applied across its terminals. Varactors can be used as voltage-controlled capacitors, such as in voltage-controlled oscillators, parametric amplifiers, and frequency multipliers, which can be used, for example, in wireless transmitters or signal modulators. In the NVAR and PVAR structures, multiple gate and source / drain connections are implemented by stacked layers of interlaced metal patterns for gate and source / drain connections, respectively. The structural design can reduce resistance and parasitic capacitance, thereby reducing capacitor losses. Parasitic capacitance can be reduced by reverse biasing the structural well capacitance. Further, the metal pattern is designed to enhance the required capacitance and reduce parasitic capacitance. This structure also allows multiple coupling capacitors in an array to be integrated on a compact chip, thereby achieving high capacitance per area. This structure can be used in radio frequency (RF) or wireless signal applications, such as providing a low loss RF differential signal path. Differential signals can be accommodated by placing the capacitors in an isolation well.

[0021] Figure 1One embodiment of a capacitor structure (circuit) in an NVAR configuration 100 is shown. The NVAR configuration 100 includes a suitable p-type semiconductor (P) block used as a drain 101 (P+drain) and another P block used as a source 102 (P+source) of the capacitor. For example, the drain 101 and the source 102 are doped p-type silicon wafers or other suitable semiconductor materials. The drain 101 and the source 102 are both placed in a p-type well 104 (P-well), for example, in doped p-type silicon. The p-well 104 is formed in a semiconductor substrate 106, such as a silicon substrate. Specifically, the substrate 106 (Psub) is doped p-type. For example, the substrate 106 is doped p-type silicon. The p-well 104 extends from the top of the surface to a properly determined depth in the DNW 105. An insulating layer 119 is formed on the surface of the p-well 104, and a conductor block is formed on the upper surface of the insulating layer 119, and the insulating layer 119 is approximately located in the middle of the p-well 104 below it. The conductor block serves as the gate 103 of the capacitor structure and can be made of polysilicon or other suitable metal / conductor materials. In other embodiments, semiconductor materials other than silicon or polysilicon can be used to form the above components. Examples of such materials include siliconized carbon (SiC), gallium arsenide (GaAs) and gallium nitride (GaN). Further, the P-well 104 is placed in a deep n-type well 105 in the substrate. The DNW 105 is formed in the Psub 106. The DNW 105 extends from the top of the surface to a properly determined depth in the substrate 106. As shown in the figure, the DNW 105 is relatively more doped, deeper and larger than the P-well 104, and surrounds the P-well 104. The DNW 105 is more doped than the P-well 104.

[0022] As shown, source 102 and drain 101 are located in a P-well 104 in substrate 106, at opposite ends of gate 103, gate 103 is located on the surface of substrate 106, and there is an insulating layer between the gate and P-well. The gate constitutes one terminal of the capacitor. As described below, source 102 and drain 101 constitute a second terminal, source 102 and drain 101 are electrically connected through the P-well, and are connected from the outside through metal connections. This arrangement of gate, source 102 / drain 101 and insulator constitutes a coupling capacitor, where the capacitance is generated between the gate 103 and the source 102 / drain 101 connection.

[0023] Figure 1The cross-sectional side view of the structure in shows a pair of source 102 / drain 101 and corresponding gate 103 in the P well 104. However, the NVAR structure 100 may include multiple capacitor elements configured in this manner, i.e., distributed and covering the source / drain and corresponding gate blocks through corresponding wells similar to Psub106. The capacitor elements can be connected to each other, for example in parallel, to increase the coupling capacitance, i.e., by stacking and interweaving metal lines (wires) in layers on the surface, and interconnecting the resulting metal pattern 107 to the corresponding gate and source / drain terminals at the surface level through metal / conductor vias 108. The metal pattern 107 is overlying the surface, and the vias 108 are vertical vias that connect the corresponding metal lines to the corresponding gate and source / drain terminals. The metal pattern 107 includes lines or wires connecting the gates, and also includes lines connecting the source / drain terminals. In one embodiment, as Figure 1 As shown, the metal lines connecting the source / drain side can be located next to or below the metal lines connecting the gate side. An example of a metal pattern design that can be used to interconnect capacitor elements is shown below.

[0024] In the NVAR configuration 100, the capacitor structure separates two circuit blocks to which different DC biases (different DC voltages) are applied. The DC bias of one circuit block is connected to the source 102 / drain 101, and the DC bias of the other circuit block is connected to the gate 103. Therefore, the two DC voltage bias capacitor structures result in a higher capacitance than when the source 102 / drain 101 and gate 103 are not biased. For NVAR, the gate is at a lower potential than the source 102 / drain 101. The voltage source 109 connected to the resistor 111 is set to a different voltage than the voltage applied to the source 102 / drain 101 or the gate 103. The purpose of the different voltages of the power supply 109 is to reverse bias the Pwell 104 / DNW 105 node and the DNW 105 / Psub 106 node. Reverse biasing these nodes can reduce unnecessary parasitic capacitance.

[0025] Figure 2An embodiment of a capacitor structure (circuit) in a PVAR structure 200 is shown. The PVAR structure 200 includes a suitable n-type semiconductor (N) block as a drain 201 (N+drain) and another N block as a source 202 (N+source) of the capacitor. The drain 201 and the source 202 are doped n-type silicon or other suitable semiconductor materials. The drain 201 and the source 202 can both be placed in an n-type well 210 (N well), for example, in doped n-type silicon. The N well 210 is less doped than the DNW 105 in the NVAR structure 100. In the PVAR structure 200, the N well 210 is formed in a semiconductor substrate 206, for example, a silicon substrate. Specifically, the substrate 206 (Psub) is doped p-type. For example, the substrate 206 is doped p-type silicon. The N well 210 extends from the top of the surface to a properly determined depth in the Psub 206. An insulating layer 219 is formed on the surface of the N-well 210, followed by a conductor block approximately located in the middle of the N-well 210 below it. The conductor block serves as the gate 203 of the capacitor structure and can be made of polysilicon or other suitable metal / conductor materials. In other embodiments, doped semiconductor materials other than silicon or polysilicon can be used to form the above components, such as siliconized carbon (SiC), gallium arsenide (GaAs) and gallium nitride (Gan).

[0026] As shown, source 202 and drain 201 are located in N-well 210 at opposite ends of insulator 219 / gate 203, which is placed on the surface of Psub 206. Gate 203 forms one terminal of the PVAR capacitor, and source 202 / drain 201 forms the second terminal of the PVAR capacitor. Source 202 and drain 201 are electrically connected through N-well 210 and are connected externally by metal lines as described below.

[0027] Similar to NVAR configuration 100, Figure 2The cross-sectional side view of the PVAR structure 200 in FIG. 1 shows a pair of source 202 / drain 201 and corresponding gate 203 in an N-well 210. However, the NVAR structure 200 may include multiple capacitor elements configured in this manner, namely by distributing and covering the source / drain and corresponding gate blocks in a well similar to the N-well 210. The capacitor elements may be interconnected, such as in parallel, to increase coupling capacitance, namely by stacking and interweaving metal lines (or wires) in layers on the surface, and interconnecting the resulting metal pattern 207 to the corresponding gate and source / drain terminals on the surface through metal / conductor vias 208. The metal pattern 207 is overlaid on the surface, and the vias 208 are vertical vias that connect the corresponding metal lines to the corresponding gate and source / drain terminals. The metal pattern 207 is similar to the metal pattern 107, including lines connecting the gate, and also including lines connecting the source / drain terminals. Similar to NVAR, PVAR separates two blocks with different DC biases. One block's DC bias is connected to the gate 203 and the other DC bias is connected to the source 202 / drain 210. Compared to NVAR, the gate bias is higher than the source / gate bias.

[0028] Figure 3A top view of an embodiment of a metal pattern 300 for gate connections and source / drain connections. For example, the metal pattern may correspond to the metal pattern 107 in the NVAR structure 100, and similarly to the metal pattern 207 in the PVAR structure 200. The metal pattern 300 connects multiple source / drain terminals to a source / drain terminal block. The same or similar metal settings connect multiple gate terminals to other gate terminal blocks on the capacitor structure (NVAR or PVAR structure), thereby forming a merged capacitor with a desired increased capacitance and lower losses (e.g., losses due to low parasitic capacitance and other parasitic parameters). The gate terminal constitutes one input terminal of the capacitor, and the source / drain terminal constitutes a second input terminal of the capacitor. The source / drain terminals and the gate block can be distributed in a two-dimensional array pattern in a corresponding well (P well in NVAR or N well in PVAR) in a structural substrate, for example. The metal pattern 300 includes stacked and staggered conductors / metal lines in a horizontal direction relative to the structural substrate, and vertical vias connecting the lines to their corresponding source / drain and gate blocks. The staggered lines of any layer are adjacent lines that have alternating connections (using vias) to the gate block and the source / drain terminals. Pattern 300 partially shows a top view of multiple layers of lines (stacked vertically with the substrate). In an actual structure, the metal lines are extended to fill a given area on the substrate. In this example, pattern 300 includes three layers of gate connections and also includes three layers of source / drain connections. The metal lines can be placed on the gate and aligned because the capacitance between the gate and the source / drain is desirable. However, the metal lines are not placed on the DNW or the substrate because coupling to these areas results in undesirable parasitic capacitance. Parasitic capacitance is reduced, thereby reducing the loss of the capacitor structure. The metal lines of each layer may be similar, and the metal lines of different layers may have different sizes, such as different widths, thicknesses and / or lengths.

[0029] Figure 4 An isometric view of an embodiment of a metal pattern for gate and source / drain (S / D) connections that can be used in NVAR configurations and similarly in PVAR configurations. The metal pattern includes multiple layers, such as in this example, four layers (M1 to M4) of metal line connections to gate elements and source / drain elements. The lines of each layer are parallel, and the lines of adjacent stacked layers are perpendicular. Each layer includes alternating lines of gate connection lines and source / drain connection lines. The gate connection lines of these layers are interconnected by vias perpendicular to these layers. Similarly, the source / drain connection lines of these layers are interconnected by a set of independent vias.

[0030] Figure 51 is a top view of an embodiment of a capacitor array layout. The capacitor array can be arranged on the NVAR structure 100 in this way, and similarly arranged on the PVAR structure 200. As shown, the array includes multiple similar units. The first metal top layer (metal layer 1) includes vertical parallel metal lines, which have contacts (through holes) connected to the source, drain and gate materials below the metal layer at the substrate surface. The second metal layer (metal layer 2) above the first metal layer includes horizontal parallel metal lines, also with through holes connected to the first metal layer. In each metal layer above the first layer, the through hole is connected to the adjacent metal layer. In the first metal layer, the contact is connected to the gate and source / gate, and the through hole is connected to the layer above the metal layer 1. Some metal lines or layers may not be directly connected to the gate and source / drain, but are connected to other metal lines through through holes, and these metal lines are directly connected to the gate and source / drain through other through holes. The layout may include additional metal line layers. The advanced metal layer (facing the top of the substrate) may have a larger width and larger spacing than the metal layer below. Stacking the metal connections in layers like this increases the effective capacitance of the overall structure and reduces losses due to lower parasitic capacitance.

[0031] Figure 6 An embodiment of a method 600 for making a low-loss coupling capacitor structure (circuit) by NVAR construction is shown. The steps of method 600 can be implemented by any suitable semiconductor process and circuit manufacturing technology (e.g., lithography and integrated chip manufacturing process). In step 610, a deep n-type well (DNW) such as n-type silicon is formed in a doped p-type semiconductor substrate (Psub) such as p-type silicon, for example, by doping. In step 620, a p-type well (P-well) array such as doped p-type silicon is formed in the DNW. In step 625, an insulating layer block array is formed on the P-well array. In step 630, a gate and source / drain block array is formed on the P-well array on the surface of the doped p-type substrate. The source and drain materials are doped p-type, such as p-type silicon wafers, and the gate material is a conductor / metal. The source and drain blocks are placed in the P-well on the opposite side of the insulating layer block. The gate is located between the source and drain blocks and on top of the insulating layer block. In step 640, a metal pattern including multiple layers of metal lines is formed on the substrate over the array of gate and source / drain materials. In step 645, the stacked metal lines are connected to the gate and source / drain arrays below the metal layer through vertical vias (called contacts). In step 650, the coupling capacitor structure is biased by connecting a DC bias to the gate connection (e.g., metal line) and the S / D connection. The DNW / Pwell node and the DNW / Psub node are connected in series with the power supply and the DNW portion of the structure by grounding Psub and connecting a DC voltage source to the DNW portion of the structure through a resistor (e.g., inserting a resistor).

[0032] Figure 7 An embodiment of a method 700 for making a low-loss coupling capacitor structure (circuit) by PVAR construction is shown. The steps of method 600 can be implemented by any suitable semiconductor process and circuit preparation technology (e.g., lithography and integrated chip preparation process). In step 710, an n-type well (N-well) array, such as doped n-type silicon, is formed in a doped p-type substrate (Psub) such as p-type silicon, for example, by doping. In step 715, an insulating layer block array is formed on the N-well array. In step 720, a gate and source / drain block array is formed on the N-well array on the surface of the doped p-type substrate. The source and drain materials are doped n-type, such as n-type silicon wafers, and the gate material is a conductor / metal. The source and drain blocks are placed in the N-well on the opposite side of the insulating layer block. The gate is located between the source and drain blocks and is located on the top of the insulating layer block. In step 730, a metal pattern containing multiple layers of metal lines is formed on the substrate on the gate and source / drain material array. In step 735, the stacked metal lines are connected to the gate and source / drain arrays below the metal layer through vertical vias (contacts). In step 740, the coupling capacitor structure is biased by connecting a DC bias to the gate, connecting a second DC bias to the S / D connection (e.g., metal line), and grounding Psub.

[0033] The present invention provides a coupling capacitor device and a method of making a coupling capacitor device in a varactor, wherein the varactor includes a deep well device (e.g., a doped p-type semiconductor well (P-well) in a doped p-type well (DNW)) having an oppositely doped device in a deep well device (e.g., a doped p-type semiconductor well (P-well) in a doped p-type well (DNW)). The coupling capacitor device also includes an insulator device on the surface of the oppositely doped (e.g., P-well) device and a metal gate device located on the insulator device. The coupling capacitor device also includes a doped semiconductor source terminal device (e.g., a doped p-type source terminal in one embodiment) located on one side of the insulator device and the metal gate device in the oppositely doped device and a semiconductor drain terminal device (e.g., doped p-type) located on the opposite side of the insulator device and the metal gate device. The coupling capacitor device also includes a capping metal layer covering the metal gate device, and an inserted through-hole device inserted into the layer and used to connect metal wires to the metal gate device, the semiconductor source terminal device, and the semiconductor drain terminal device through contacts.

[0034] Although several embodiments have been provided in the present invention, it should be understood that the systems and methods disclosed herein may be embodied in many other specific forms without departing from the spirit or scope of the present invention. The examples of the present invention should be considered illustrative rather than restrictive, and the present invention is not limited to the details given in this text. For example, various elements or components may be combined or merged in another system, or certain features may be omitted or not implemented.

[0035] In addition, without departing from the scope of the present invention, the techniques, systems, subsystems and methods described and illustrated as discrete or separate in the various embodiments may be combined or merged with other systems, modules, techniques or methods. Other items shown or discussed as coupled or directly coupled or communicating with each other may also be coupled or communicated indirectly through an interface, device or intermediate component, either electrically, mechanically or otherwise. Other variations, substitutions and altered examples may be determined by those skilled in the art without departing from the spirit and scope of the disclosure herein.

Claims

1. A circuit structure of a coupling capacitor, characterized in that: include: doped p-type semiconductor substrate Psub; A deeply doped n-type semiconductor well DNW in the Psub; A P-well in the DNW, wherein the P-well is a doped p-type semiconductor well; a first block of doped p-type semiconductor material extending from a surface of the P-well into the P-well, wherein the first block is a source terminal; a second mass of the doped p-type semiconductor material extending from the surface of the P-well into the P-well, wherein the second mass is a drain terminal; an insulator block on the P-well between the source terminal and the drain terminal; a conductive material on the insulator block between the source terminal and the drain terminal, wherein the conductive material is a gate; a metal pattern including a plurality of metal lines approximately parallel to the surface, and a plurality of vias passing through and perpendicular to the metal lines, wherein the vias connect the metal lines to the gate, the source terminal, and the drain terminal; The metal lines in the first layer of the metal pattern are substantially parallel to a first direction, and the metal lines in the second layer adjacent to the first layer are substantially parallel to a second direction, and the first direction is substantially perpendicular to the second direction.

2. The circuit structure according to claim 1, characterized in that: Also includes: at least one second P-well in the DNW; another piece of the doped p-type semiconductor material as a second source terminal, the second source terminal extending from a surface of the second P-well into the second P-well; another piece of the doped p-type semiconductor material as a second drain terminal, the second drain terminal extending from the surface of the second P-well into the second P-well; Another piece of the conductor material is a second gate located at the surface of the second P-well between the second source terminal and the second drain terminal, wherein the via also connects the metal line to the second gate, the second source terminal and the second drain terminal.

3. The circuit structure according to claim 1, characterized in that: The metal lines in each layer of the metal pattern are approximately parallel.

4. The circuit structure according to claim 1, characterized in that: The metal lines in each layer include alternating first lines connected to the gates through the vias and second lines connected to the source terminals and the drain terminals through the vias.

5. The circuit structure according to claim 1, characterized in that: The DNW is more heavily doped than the P-well.

6. The circuit structure according to claim 1, characterized in that: Opposite sidewalls of the gate are adjacent to sidewalls of the source terminal and the drain terminal.

7. The circuit structure according to claim 1, characterized in that: The metal lines in the multiple layers of the metal pattern have different dimensions, including at least one of different spacing, different width, different depth, and different length.

8. The circuit structure according to claim 1, characterized in that: The metal lines in high layers of the metal pattern from the surface have greater widths and greater spacing than the metal lines in lower metal layers.

9. The circuit structure according to claim 1, characterized in that: The gate and the source and drain terminals are connected to a DC via, the Psub is grounded, and the DNW is connected to a power source through a resistor.

10. A circuit structure of a coupling capacitor, characterized in that: include: doped p-type semiconductor substrate Psub; An N-well in the Psub, wherein the N-well is a doped n-type semiconductor well; a first block of doped n-type semiconductor material extending from a surface of the N-well into the N-well, wherein the first block serves as a source terminal; a second mass of doped n-type semiconductor material extending from the surface of the N-well into the N-well, wherein the second mass is a drain terminal; an insulator block on the N-well between the source terminal and the drain terminal; a conductive material on the insulator block between the source terminal and the drain terminal, wherein the conductive material is a gate; a metal pattern including a plurality of metal lines approximately parallel to the surface, and a plurality of vias passing through and perpendicular to the metal lines, wherein the vias connect the metal lines to the gate, the source terminal, and the drain terminal; The metal lines in the first layer of the metal pattern are substantially parallel to a first direction, and the metal lines in the second layer adjacent to the first layer are substantially parallel to a second direction, and the first direction is substantially perpendicular to the second direction.

11. The circuit structure according to claim 10, characterized in that: Also includes: at least one second N-well in said Psub; another block of doped n-type semiconductor material as a second source terminal, the second source terminal extending from the surface of the second N-well into the second N-well; another piece of the doped n-type semiconductor material as a second drain terminal, the second drain terminal extending from a surface of the second N-well into the second N-well; Another piece of the conductor material is a second gate located at a surface of the second N-well between the second source terminal and the second drain terminal, wherein the via also connects the metal line to the second gate, the source terminal and the second drain terminal.

12. The circuit structure according to claim 10, characterized in that: The metal lines in each layer of the metal pattern are approximately parallel.

13. The circuit structure according to claim 10, characterized in that: The metal lines of each layer include alternating first lines and second lines, the first lines being connected to the gates through vias, and the second lines being connected to the source terminals and the drain terminals through vias.

14. The circuit structure according to claim 10, characterized in that: The metal lines in the multiple layers of the metal pattern have different dimensions, including at least one of different spacing, different width, different depth, and different length.

15. The circuit structure according to claim 10, characterized in that: The metal lines in high layers of the metal pattern from the surface have greater widths and greater spacing than the metal lines in lower metal layers.

16. The circuit structure according to claim 10, characterized in that: The gate, source and drain terminals are connected to a DC bias, with Psub being connected to ground.

17. A method for making a coupling capacitor structure in an n-type varactor structure, characterized in that: The method comprises: A deeply doped n-type well DNW is formed in a p-type doped semiconductor substrate Psub; A P-well is formed in the DNW, wherein the P-well is a doped p-type semiconductor well; Placing an insulator on the surface of the P-well; placing a metal gate on the insulator; In the P-well, a doped p-type semiconductor source terminal is formed on one side of the insulator and the metal gate, and a doped p-type semiconductor drain terminal is formed on the opposite side of the insulator and the metal gate; Covering the metal gate with multiple layers of metal wires; inserting a via perpendicular to the layer and connecting the metal wire to the metal gate, the doped p-type semiconductor source terminal and the doped p-type semiconductor drain terminal through contacts; The metal lines in the first layer of the multilayer metal lines are substantially parallel to a first direction, and the metal lines in the second layer adjacent to the first layer are substantially parallel to a second direction, and the first direction is substantially perpendicular to the second direction.

18. The method according to claim 17, characterized in that Also includes: forming at least one second P-well in the DNW; placing a second insulator on the surface of the second P-well; placing a second metal gate on the second insulator; In the second P-well, a second doped p-type semiconductor source terminal is formed on one side of the second insulator and the second metal gate, and a second doped p-type semiconductor drain terminal is formed on the opposite side of the second insulator and the second metal gate; The metal line is connected to the second metal gate, the second doped p-type semiconductor source terminal, and the second doped p-type semiconductor drain terminal through the via and the contact.

19. The method according to claim 17, characterized in that Also includes: Covering the gate, the doped p-type semiconductor source terminal and the doped p-type semiconductor drain terminal with an additional metal wire layer; An additional via is inserted perpendicular to the additional metal line layer and connects the additional metal line to the metal line.

20. The method according to claim 17, characterized in that Also includes: connecting the metal gate and the doped p-type semiconductor source and drain terminals to a DC bias; Connect the Psub to ground; The DNW is connected to the power supply via a resistor placed in series between the power supply and the DNW.

21. A method for making a coupling capacitor structure in a p-type varactor structure, characterized in that: The method comprises: An N-well is formed in a p-type doped semiconductor substrate Psub, wherein the N-well is an n-type doped semiconductor well; Placing an insulator on the surface of the N-well; placing a metal gate on the insulator; In the N-well, a doped n-type semiconductor source terminal is formed on one side of the insulator and the metal gate, and a doped n-type semiconductor drain terminal is formed on the opposite side of the insulator and the metal gate; Covering the metal gate with multiple layers of metal wires; inserting a through hole perpendicular to the multi-layer metal line and connecting the metal line to the metal gate, the doped n-type semiconductor source terminal and the doped n-type semiconductor drain terminal through contacts; The metal lines in the first layer of the multilayer metal lines are substantially parallel to a first direction, and the metal lines in the second layer adjacent to the first layer are substantially parallel to a second direction, and the first direction is substantially perpendicular to the second direction.

22. The method according to claim 21, characterized in that Also includes: forming at least one second N-well in the Psub; placing a second insulator on the second N-well; placing a second metal gate on the second insulator; In the second N-well, a second doped n-type semiconductor source terminal is formed on one side of the second insulator and the second metal gate, and a second doped n-type semiconductor drain terminal is formed on the opposite side of the second insulator and the second metal gate; The metal line in the layer is connected to the second metal gate, the second doped n-type semiconductor source terminal, and the second doped n-type semiconductor second drain terminal through the vias and contacts.

23. The method according to claim 21, characterized in that Also includes: Covering the gate, the doped n-type semiconductor source terminal and the doped n-type semiconductor drain terminal with an additional metal wire layer; An additional via is inserted perpendicular to the layer and connects the additional metal line to the metal line.

24. The method according to claim 21, characterized in that Also includes: connecting the metal gate to a DC bias; connecting the doped n-type semiconductor source and drain terminals to a second DC bias; Connect the Psub to ground.

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