A high-reliability UVC LED chip and manufacturing method thereof

Abstract

The present invention discloses a high-reliability UVC LED chip and a manufacturing method thereof, wherein the chip comprises a substrate, an epitaxial layer arranged on the substrate, a transparent conductive layer arranged on the epitaxial layer, and a first electrode, and further comprises a second electrode, wherein the second electrode is arranged on the transparent conductive layer and the first electrode respectively; the first electrode comprises an N-contact layer, a first insulating layer, a first diffusion barrier layer, and a first pad layer. The present invention optimizes the ohmic contact, increases the current diffusivity, and uses the second electrode to level the bubbling electrode structure, so that the current conduction is smoother, thereby improving the overall life of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of light emitting diodes, and in particular to a high-reliability UVC LED chip and a manufacturing method thereof. Background Art

[0002] UV LED is a diode that emits ultraviolet light, mainly using GaN semiconductors. Generally refers to LEDs with a central wavelength of 400nm or less, but sometimes wavelengths greater than 380nm are called near-ultraviolet LEDs, and wavelengths shorter than 300nm are called deep-ultraviolet LEDs. Because short-wavelength light has a high bactericidal effect, UV LEDs are often used for sterilization and deodorization in refrigerators and home appliances.

[0003] Ultraviolet LEDs mainly destroy and change the DNA (deoxyribonucleic acid) structure of microorganisms, causing the bacteria to die immediately or be unable to reproduce, thus achieving the purpose of sterilization.

[0004] The effective wavelength range of ultraviolet sterilization can be divided into four different bands: UVA (400-315nm), UVB (315-280nm), UVC (280-200nm) and vacuum ultraviolet (200-100nm). The UVC ultraviolet rays have real sterilization effects.

[0005] Compared with UVA LED and UVB LED, UVC LED has a shorter wavelength and a high Al content in the epitaxial layer. Therefore, titanium and aluminum are needed to make ohmic contact between the electrode and the epitaxial layer. However, the alloy temperature must be very high (reaching 900°C). Excessive temperature will cause metal agglomeration of Al in the ohmic contact, causing electrode bubbling and cracking, and increasing chip voltage. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a high-reliability UVC LED chip with good ohmic contact, flat electrodes, high brightness and low voltage.

[0007] The technical problem that the present invention also solves is to provide a high-reliability UVC LED chip manufacturing method to form a good ohmic contact, flat electrode, high brightness and low voltage.

[0008] In order to solve the above technical problems, the present invention provides a high-reliability UVC LED chip, comprising a substrate, an epitaxial layer arranged on the substrate, a transparent conductive layer and a first electrode arranged on the epitaxial layer, and also comprising a second electrode, wherein the second electrode is arranged on the transparent conductive layer and the first electrode respectively;

[0009] The first electrode includes an N-contact layer, a first insulating layer, a first diffusion barrier layer and a first pad layer;

[0010] The N-contact layer is arranged on the epitaxial layer and is made of Ti;

[0011] The first barrier layer is disposed on the N-contact layer and wraps the sidewall of the N-contact layer, and is made of Al or Au;

[0012] The first diffusion barrier layer is disposed on the first barrier layer and wraps the sidewall of the first barrier layer, and is made of Ti, Ni or Pt;

[0013] The first pad layer is disposed on the first diffusion barrier layer and wraps the sidewall of the first diffusion barrier layer, and is made of Au.

[0014] As an improvement of the above solution, the thickness of the N-contact layer is 1000-2000 angstroms; the thickness of the first barrier layer is 3000-5000 angstroms; the thickness of the first diffusion barrier layer is 500-1000 angstroms; and the thickness of the first pad layer is 1-1.2 microns.

[0015] As an improvement of the above solution, the first electrode is subjected to high-temperature rapid annealing; wherein the annealing is performed at a temperature of 800 to 950° C. for 0.2 to 3 minutes.

[0016] As an improvement of the above solution, the second electrode includes a P-contact layer, a second insulating layer, a second diffusion barrier layer and a second pad layer;

[0017] The P-contact layer is respectively arranged on the transparent conductive layer and the first electrode, and is made of Ni;

[0018] The second barrier layer is disposed on the P-contact layer and is made of Pt;

[0019] The second diffusion barrier layer is disposed on the second barrier layer and is made of Ti;

[0020] The second pad layer is disposed on the second diffusion barrier layer and is made of Pt.

[0021] As an improvement of the above solution, the thickness of the P-contact layer is 800-1200 angstroms; the thickness of the second barrier layer is 600-800 angstroms; the thickness of the second diffusion barrier layer is 750-850 angstroms; and the thickness of the second pad layer is 2000-3000 angstroms.

[0022] As an improvement of the above solution, the structure of the transparent conductive layer is Ni / Au, Rh / Au or Pt / Au;

[0023] The transparent conductive layer is annealed at a temperature of 500-600° C. for 4-6 minutes.

[0024] As an improvement of the above solution, it also includes an equal-sized electrode and a protective layer, wherein the equal-sized electrode is arranged on the second electrode, and the structure of the equal-sized electrode is Ti / Au / Ni / Pt / Ni / AuSn;

[0025] The protection layer is filled between the first electrode, the second electrode and the epitaxial layer, and the protection layer is made of insulating material.

[0026] Accordingly, the present invention provides a method for manufacturing a high-reliability UVC LED chip, comprising the following steps:

[0027] 1. forming an epitaxial layer on the substrate, and etching the epitaxial layer to expose the first semiconductor layer;

[0028] 2. Forming a first electrode on the first semiconductor layer, the first electrode comprising an N-contact layer, a first insulating layer, a first diffusion barrier layer and a first pad layer; the N-contact layer is arranged on the first semiconductor layer of the epitaxial layer and is made of Ti; the first insulating layer is arranged on the N-contact layer and wraps the side wall of the N-contact layer and is made of Al or Au; the first diffusion barrier layer is arranged on the first insulating layer and wraps the side wall of the first barrier layer and is made of Ti, Ni or Pt; the first pad layer is arranged on the first diffusion barrier layer and wraps the side wall of the first diffusion barrier layer and is made of Au;

[0029] 3. Performing high temperature rapid annealing on the first electrode at a temperature of 800 to 950° C. and a pressure of 500 to 760 torr for 0.2 to 3 minutes;

[0030] 4. forming a transparent conductive layer on the second semiconductor layer;

[0031] 5. Form a second electrode on the first electrode and the transparent conductive layer respectively.

[0032] As an improvement to the above scheme, in step (iii), N 2 , the flow rate is 30-50slm, the annealing time is 0.5-2min under the conditions of temperature of 900℃ and pressure of 500-760torr.

[0033] As an improvement of the above solution, in step (iv), the structure of the transparent conductive layer is Ni / Au, Rh / Au or Pt / Au;

[0034] After forming the transparent conductive layer and before forming the second electrode, N 2 , anneal at a temperature of 500-600°C for 4-6 minutes.

[0035] The implementation of the present invention has the following beneficial effects:

[0036] The first electrode of the present invention forms a good ohmic contact with the first semiconductor layer with a high aluminum content by setting an N-contact layer made of Ti; further, the first barrier layer, the first diffusion barrier layer and the first pad layer in the first electrode layer of the present invention sequentially wrap the structure arranged thereunder, and adopt a sidewall wrapping structure to make the metals in different layers more compact, so as to protect the titanium and aluminum in the first electrode, avoid the migration of these two metals due to high temperature, and then offset the influence of high temperature annealing on the first electrode.

[0037] The present invention sets a second electrode on the first electrode, and uses the second electrode to fill and plate the first electrode to prevent the first electrode from bubbling and cracking after high-temperature annealing, which causes the chip voltage to increase; in addition, the present invention sets a second electrode on the first electrode and the transparent conductive layer respectively, so that the electrode on the first semiconductor layer is at the same height as the electrode on the transparent conductive layer, which is convenient for wire bonding or welding packaging.

[0038] The present invention optimizes ohmic contact to increase current diffusivity, and uses a second electrode to level the bubbling electrode structure, so that current conduction is smoother, thereby reducing the voltage of the UVC LED chip and increasing its brightness, thereby improving the sterilization effect of the UVC LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a schematic structural diagram of the high reliability UVC LED chip of the present invention. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0041] See also Figure 1 The present invention provides a high-reliability UVC LED chip, including a substrate 10, an epitaxial layer 20, a transparent conductive layer 30, a first electrode 40 and a second electrode 50.

[0042] The substrate 10 is a silicon substrate, a sapphire substrate or a silicon carbide substrate, but is not limited thereto.

[0043] The epitaxial layer 20 is disposed on the substrate 10 , and includes a first semiconductor layer 21 , an active layer 22 , and a second semiconductor layer 23 disposed in sequence. The epitaxial layer 20 of the present invention is preferably made of gallium nitride material.

[0044] Since the epitaxial layer 20 of the present invention is a UVC epitaxial layer emitting a wavelength of 280 to 200 nm, the aluminum content in the epitaxial layer 20 is very high, generally reaching 36.5% to 50%, especially the aluminum content in the first semiconductor layer 21, wherein the first semiconductor layer is N-AlGaN and the second semiconductor layer is P-AlGaN.

[0045] The transparent conductive layer 30 of the present invention is disposed on the second semiconductor layer 23 to improve the current expansion of the chip. In order to form a good match and ohmic contact with the second semiconductor layer 23, the first metal layer in the transparent conductive layer 30 of the present invention has a higher work function. Preferably, the structure of the transparent conductive layer 30 of the present invention is Ni / Au, Rh / Au or Pt / Au.

[0046] Preferably, the structure of the transparent conductive layer 30 is Ni / Au, and the thickness is 100nm / 1100nm.

[0047] In order to form a good ohmic contact, after forming the transparent conductive layer 30, annealing is required, wherein a furnace tube or RTA machine is used to pass N 2 , anneal at a temperature of 500-600°C for 4-6 minutes.

[0048] The first electrode 40 of the present invention is disposed on the first semiconductor layer 21. Specifically, the first electrode 40 includes an N-contact layer 41, a first insulating layer 42, a first diffusion barrier layer 43 and a first pad layer 44.

[0049] The N-contact layer 41 is arranged on the first semiconductor layer 21 and is made of Ti; the first barrier layer 42 is arranged on the N-contact layer 41 and wraps the side wall of the N-contact layer 41, and is made of Al or Au; the first diffusion barrier layer 43 is arranged on the first barrier layer 42 and wraps the side wall of the first barrier layer 42, and is made of Ti, Ni or Pt; the first pad layer 44 is arranged on the first diffusion barrier layer 43 and wraps the side wall of the first diffusion barrier layer 43, and is made of Au.

[0050] Among them, the invention adopts a sidewall wrapping structure to wrap the first barrier layer 42, the first diffusion barrier layer 43 and the first pad layer 44 in the first electrode 40 layer in sequence and arrange the structure thereunder, so that the metals in different layers are more compact. Specifically, the present invention adopts a large-angle yellow light and adjusts the inclination angle of evaporation at the same time. When coating, the stress of the film layer is used to increase the inclination angle of the yellow light, so that the metal can be plated thicker.

[0051] In the first electrode 40 of the present invention, the N-contact layer 41 is used to adhere to the first semiconductor layer 21 to prevent the first electrode 40 from falling off; in addition, the N-contact layer 41 must also meet the ohmic contact of the alloy half-junction; the first barrier layer 42 is used to prevent the metal migration of the N-contact layer 41 after the alloy is formed due to high temperature; the first diffusion barrier layer 43 is used to prevent the metal migration of the N-contact layer 41 and the first barrier layer 42, and form sufficient contact and filling with the N-contact layer 41 and the first barrier layer 42 to improve aging reliability; the first pad layer 44 is used for wire bonding or welding.

[0052] It should be noted that, since the aluminum content of the first semiconductor layer 21 in the UVC LED chip is very high and aluminum is easy to migrate and diffuse, highly stable Ti is required as a contact layer in the first electrode 40, and a very high annealing temperature is required to form an alloy between aluminum and titanium.

[0053] Specifically, after forming the first electrode 40 , high-temperature rapid annealing is performed to improve the ohmic contact between the first electrode 40 and the epitaxial layer 20 .

[0054] Preferably, a furnace tube or RTA machine is used to pass N 2 , the flow rate is 30-50slm, the annealing time is 0.2-3min under the conditions of temperature of 800-950℃ and pressure of 500-760torr.

[0055] Better yet, use a furnace or RTA machine to pass N 2 , the flow rate is 30-50slm, the annealing time is 0.5-2min under the conditions of temperature of 900℃ and pressure of 500-760torr.

[0056] Compared with conventional degradation processes, the annealing temperature of the present invention is high and the time is short. If the annealing time is less than 0.2 minutes, the time is too short to completely form an alloy; if the annealing time is greater than 3 minutes, the structure of the first electrode 40 will become porous, causing the voltage of the chip to increase.

[0057] It should be noted that the thickness of each layer in the first electrode 40 has an important influence on the optoelectronic performance of the chip. If the thickness of the N-contact layer 41 is too small, the first electrode 40 is easy to fall off, and if the thickness is too large, the chip voltage is too high; if the thickness of the first insulating layer 42 and the first diffusion barrier layer 43 is too small, they cannot play a role in blocking metal migration, and if the thickness of the first pad layer 44 is too small, it is easy to be broken down during wire bonding or welding.

[0058] Preferably, the thickness of the N-contact layer 41 is 1000-2000 angstroms; the thickness of the first barrier layer 42 is 3000-5000 angstroms; the thickness of the first diffusion barrier layer 43 is 500-1000 angstroms; and the thickness of the first pad layer 44 is 1-1.2 microns.

[0059] More preferably, the thickness of the N-contact layer 41 is 1300-1700 angstroms; the thickness of the first barrier layer 42 is 3500-4500 angstroms; the thickness of the first diffusion barrier layer 43 is 600-800 angstroms; and the thickness of the first pad layer 44 is 1-1.1 microns.

[0060] Since the first electrode 40 needs to be annealed at high temperature to form a good ohmic contact with the first semiconductor layer 21, metal agglomeration and migration will occur between the first electrode 40 and the first semiconductor layer 21 after high temperature, making the surface of the first electrode 40 uneven, the first electrode 40 bubbles and cracks, and causing the chip voltage to increase; in addition, the uneven surface of the first electrode 40 will easily cause contamination, affecting the formation of equal-sized electrodes. Therefore, the present invention sets a second electrode 50 on the first electrode 40, and uses the second electrode 50 to fill and plate the first electrode 40, and makes the electrode on the first semiconductor layer 21 and the electrode on the second semiconductor layer 23 equal in height to facilitate wire bonding or welding packaging.

[0061] In addition, the second electrode 50 of the present invention is also disposed on the transparent conductive layer 30 to form a conductive connection with the second semiconductor layer 23 .

[0062] Specifically, the second electrode 50 includes a P-contact layer 51, a second insulating layer 52, a second diffusion barrier layer 53 and a second pad layer 54;

[0063] The P-contact layer 51 is disposed on the transparent conductive layer 30 and the first electrode 40 respectively, and is made of Ni;

[0064] The second barrier layer 52 is disposed on the P-contact layer 51 and is made of Pt;

[0065] The second diffusion barrier layer 53 is disposed on the second barrier layer 52 and is made of Ti;

[0066] The second pad layer 54 is disposed on the second diffusion barrier layer 53 and is made of Pt.

[0067] In the second electrode 50 of the present invention, the P-contact layer 51 is used to adhere to the transparent conductive layer 30 to prevent the second electrode 50 from falling off; in addition, the P-contact layer 51 must also meet the ohmic contact of the alloy semi-junction; the second barrier layer 52 is used to prevent the metal migration of the P-contact layer 51 after the alloy is formed due to high temperature; the second diffusion barrier layer 53 is used to prevent the metal migration of the P-contact layer 51 and the second barrier layer 52, and form sufficient contact and filling with the P-contact layer 51 and the second barrier layer 52 to improve the aging reliability; the second pad layer 54 is used for wire bonding or welding.

[0068] It should be noted that the thickness of each layer in the second electrode 50 has an important influence on the optoelectronic performance of the chip. If the thickness of the P-contact layer 51 is too small, the second electrode 50 is easy to fall off, and if the thickness is too large, the chip voltage is too high; if the thickness of the second insulating layer 52 and the second diffusion barrier layer 53 is too small, they cannot play a role in blocking metal migration, and if the thickness of the second pad layer 54 is too small, it is easy to be broken down during wire bonding or welding.

[0069] Preferably, the thickness of the P-contact layer 51 is 800-1200 angstroms; the thickness of the second barrier layer 52 is 600-800 angstroms; the thickness of the second diffusion barrier layer 53 is 750-850 angstroms; and the thickness of the second pad layer 54 is 2000-3000 angstroms.

[0070] More preferably, the thickness of the P-contact layer 51 is 900-1100 angstroms; the thickness of the second barrier layer 52 is 650-750 angstroms; the thickness of the second diffusion barrier layer 53 is 750-850 angstroms; and the thickness of the second pad layer 54 is 2300-2800 angstroms.

[0071] It should be noted that the UVC LED chip of the present invention can be a face-up structure or a flip-down structure. If the UVC LED chip of the present invention is a flip-down structure, it also includes a reflective layer 60, which is arranged between the transparent conductive layer 30 and the second electrode 50 to reflect light to the side of the substrate 10.

[0072] Preferably, the reflective layer 60 is made of Ag and / or Al.

[0073] Preferably, the reflective layer 60 is a Bragg reflective layer.

[0074] In order to improve packaging efficiency and facilitate wire bonding and welding, the UVC LED chip of the present invention further includes an equal-sized electrode 70, which is disposed on the second electrode 50. After the equal-sized electrode 70 is disposed, the total electrode height and area of ​​the first semiconductor layer 21 and the second semiconductor layer 23 are respectively equal.

[0075] Preferably, the structure of the isomeric electrode 70 is Ti / Au / Ni / Pt / Ni / AuSn. The thickness of each layer of the isomeric electrode 70 is 400-600 angstroms / 2000-3500 angstroms / 1000-2000 angstroms / 800-1000 angstroms / 2500-3500 angstroms / 3-5 microns.

[0076] In order to protect the first electrode 40 and the second electrode 50, the UVC LED chip of the present invention further includes a protective layer 80, which is filled between the first electrode 40, the second electrode 50 and the epitaxial layer 20 to prevent water vapor, dust, etc. from entering the first electrode 40 and the second electrode 50. Specifically, the protective layer 80 is made of an insulating material. Preferably, the protective layer 80 is made of SiO 2 、Al 2 O 3 , SiNx, AlN, BN or more, with a thickness of 300 to 1000 nm.

[0077] The first electrode 40 of the present invention forms a good ohmic contact with the first semiconductor layer 21 with a high aluminum content by setting an N-contact layer 41 made of Ti; further, the first barrier layer 42, the first diffusion barrier layer 43 and the first pad layer 44 in the first electrode 40 layer of the present invention sequentially wrap the structure arranged thereunder to prevent the titanium and aluminum in the first electrode 40 from migrating due to high temperature, thereby preventing the influence of high temperature annealing on the first electrode 40.

[0078] Since the first electrode 40 needs to be annealed at high temperature to form a good ohmic contact with the first semiconductor layer 21, metal agglomeration and migration will occur between the first electrode 40 and the first semiconductor layer 21 after high temperature, making the surface of the first electrode 40 uneven, the first electrode 40 bubbles and cracks, and causing the chip voltage to increase; in addition, the uneven surface of the first electrode 40 is prone to contamination, affecting the formation of the equal-sized electrode 70, so the present invention sets a second electrode 50 on the first electrode 40, and uses the second electrode 50 to fill and plate the first electrode 40, and makes the electrode on the first semiconductor layer 21 and the electrode on the second semiconductor layer 23 the same height, so as to facilitate wire bonding or welding packaging.

[0079] Specifically, the present invention optimizes the ohmic contact to increase the current diffusivity, and at the same time, the second electrode 50 is used to level the bubbling electrode structure, so that the current conduction is smoother, thereby improving the overall life of the chip. The existing UVC LED chip has a brightness of only 0.6mw and a voltage of 24V; if the UVC LED chip of the present invention is not subjected to high-temperature rapid annealing (just conventional low-temperature annealing at a temperature of 500-600°C), the brightness is 1.86mw and the voltage is 9.6V; after high-temperature rapid annealing, the UVC LED chip of the present invention has a brightness of 4.5mw and a voltage of 5.5V.

[0080] Accordingly, the present invention also provides a method for manufacturing a high-reliability UVC LED chip, comprising the following steps:

[0081] 1. forming an epitaxial layer on the substrate, and etching the epitaxial layer to expose the first semiconductor layer;

[0082] The substrate is a silicon substrate, a sapphire substrate or a silicon carbide substrate, but is not limited thereto.

[0083] The epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer which are arranged in sequence. The epitaxial layer material of the present invention is preferably a gallium nitride material.

[0084] Since the epitaxial layer of the present invention is a UVC epitaxial layer emitting a wavelength of 280-200 nm, the aluminum content in the epitaxial layer is very high, especially the aluminum content in the first semiconductor layer.

[0085] It should be noted that, in order to form the first electrode, the epitaxial layer needs to be etched to expose the first semiconductor layer.

[0086] 2. forming a first electrode on the first semiconductor layer;

[0087] The first electrode includes an N-contact layer, a first insulating layer, a first diffusion barrier layer and a first pad layer;

[0088] The N-contact layer is arranged on the first semiconductor layer of the epitaxial layer and is made of Ti;

[0089] The first barrier layer is disposed on the N-contact layer and wraps the sidewall of the N-contact layer, and is made of Al or Au;

[0090] The first diffusion barrier layer is disposed on the first barrier layer and wraps the sidewall of the first barrier layer, and is made of Ti, Ni or Pt;

[0091] The first pad layer is disposed on the first diffusion barrier layer and wraps the sidewall of the first diffusion barrier layer, and is made of Au.

[0092] In the first electrode of the present invention, the N-contact layer is used to adhere to the first semiconductor layer to prevent the first electrode from falling off; in addition, the N-contact layer must also meet the ohmic contact of the alloy semi-junction; the first barrier layer is used to prevent the metal migration of the N-contact layer after the alloy is formed due to high temperature; the first diffusion barrier layer is used to prevent the metal migration of the N-contact layer and the first barrier layer, and forms sufficient contact and filling with the N-contact layer and the first barrier layer to improve aging reliability; the first pad layer is used for wire bonding or welding.

[0093] It should be noted that since the aluminum content of the first semiconductor layer in the UVC LED chip is very high and aluminum is easy to migrate and diffuse, highly stable Ti is needed as the contact layer in the first electrode. In order for aluminum and titanium to form an alloy, a very high annealing temperature is required.

[0094] It should be noted that the thickness of each layer in the first electrode has an important influence on the optoelectronic performance of the chip. If the thickness of the N-contact layer is too small, the first electrode is easy to fall off; if the thickness is too large, the chip voltage is too high; if the thickness of the first insulating layer and the first diffusion barrier layer is too small, they cannot prevent metal migration; if the thickness of the first pad layer is too small, it is easy to be broken down during wire bonding or welding.

[0095] Preferably, the thickness of the N-contact layer is 1000-2000 angstroms; the thickness of the first barrier layer is 3000-5000 angstroms; the thickness of the first diffusion barrier layer is 500-1000 angstroms; and the thickness of the first pad layer is 1-1.2 microns.

[0096] More preferably, the thickness of the N-contact layer is 1300-1700 angstroms; the thickness of the first barrier layer is 3500-4500 angstroms; the thickness of the first diffusion barrier layer is 600-800 angstroms; and the thickness of the first pad layer is 1-1.1 microns.

[0097] 3. performing high temperature rapid annealing on the first electrode;

[0098] Specifically, the annealing is performed at a temperature of 800 to 950° C. and a pressure of 500 to 760 torr for 0.2 to 3 minutes.

[0099] Preferably, a furnace tube or RTA machine is used to pass N 2 , the flow rate is 30-50slm, the annealing time is 0.2-3min under the conditions of temperature of 800-950℃ and pressure of 500-760torr.

[0100] Better yet, use a furnace or RTA machine to pass N 2 , the flow rate is 30-50slm, the annealing time is 0.5-2.5min under the conditions of temperature of 900℃ and pressure of 500-760torr.

[0101] Compared with conventional degradation processes, the present invention has high temperature and short time. If the annealing time is less than 0.2 minutes, the time is too short to completely form the alloy. If the annealing time is greater than 3 minutes, the structure of the first electrode will become porous, causing the voltage of the chip to increase.

[0102] In order to prevent the influence of high temperature annealing on the first electrode, the first barrier layer, the first diffusion barrier layer and the first pad layer in the first electrode layer of the present invention sequentially wrap the structure arranged thereunder, mainly to protect the titanium and aluminum in the first electrode and prevent the migration of these two metals due to high temperature.

[0103] Since the first electrode needs to be annealed at high temperature to form a good ohmic contact with the first semiconductor layer, metal agglomeration and migration will occur between the first electrode and the first semiconductor layer after the high temperature, making the surface of the first electrode uneven, the first electrode bubbling and cracking, and causing the chip voltage to increase; in addition, the uneven surface of the first electrode will easily cause contamination, affecting the formation of equal-sized electrodes. Therefore, the present invention arranges a second electrode on the first electrode, uses the second electrode to fill and plate the first electrode, and makes the electrode on the first semiconductor layer and the electrode on the second semiconductor layer the same height, so as to facilitate wire bonding or welding packaging.

[0104] 4. forming a transparent conductive layer on the second semiconductor layer;

[0105] The transparent conductive layer of the present invention is used to improve the current expansion of the chip. Since the aluminum content of the second semiconductor layer is also high, in order to form a good match and ohmic contact with the second semiconductor layer, the first metal layer in the transparent conductive layer of the present invention has a higher work function. Preferably, the structure of the transparent conductive layer of the present invention is Ni / Au, Rh / Au or Pt / Au.

[0106] Preferably, the structure of the transparent conductive layer is Ni / Au, and the thickness is 100nm / 1100nm.

[0107] 5. forming a second electrode on the first electrode and the transparent conductive layer respectively;

[0108] The second electrode includes a P-contact layer, a second insulating layer, a second diffusion barrier layer, and a second pad layer;

[0109] The P-contact layer is disposed on the transparent conductive layer and the first electrode and is made of Ni;

[0110] The second barrier layer is disposed on the P-contact layer and is made of Pt;

[0111] The second diffusion barrier layer is disposed on the second barrier layer and is made of Ti;

[0112] The second pad layer is disposed on the second diffusion barrier layer and is made of Pt.

[0113] In the second electrode of the present invention, the P-contact layer is used to adhere to the transparent conductive layer to prevent the second electrode from falling off; in addition, the P-contact layer must also meet the ohmic contact of the alloy semi-junction; the second barrier layer is used to prevent the metal migration of the P-contact layer after the alloy is formed due to high temperature; the second diffusion barrier layer is used to prevent the metal migration of the P-contact layer and the second barrier layer, and forms sufficient contact and filling with the P-contact layer and the second barrier layer to improve aging reliability; the second pad layer is used for wire bonding or welding.

[0114] It should be noted that the thickness of each layer in the second electrode has an important influence on the optoelectronic performance of the chip. If the thickness of the P-contact layer is too small, the second electrode is easy to fall off; if the thickness is too large, the chip voltage is too high; if the thickness of the second insulating layer and the second diffusion barrier layer is too small, it will not play a role in blocking metal migration; if the thickness of the second pad layer is too small, it is easy to be broken down during wire bonding or welding.

[0115] Preferably, the thickness of the P-contact layer is 800-1200 angstroms; the thickness of the second barrier layer is 600-800 angstroms; the thickness of the second diffusion barrier layer is 750-850 angstroms; and the thickness of the second pad layer is 2000-3000 angstroms.

[0116] More preferably, the thickness of the P-contact layer is 900-1100 angstroms; the thickness of the second barrier layer is 650-750 angstroms; the thickness of the second diffusion barrier layer is 750-850 angstroms; and the thickness of the second pad layer is 2300-2800 angstroms.

[0117] 6. forming an electrode of equal size on the second electrode;

[0118] The structure of the isomeric electrode is Ti / Au / Ni / Pt / Ni / AuSn. The thickness of each layer of the isomeric electrode is 400-600 angstroms / 2000-3500 angstroms / 1000-2000 angstroms / 800-1000 angstroms / 2500-3500 angstroms / 3-5 microns.

[0119] After the equal-sized electrodes are arranged, the total height and area of ​​the electrodes of the first semiconductor layer and the second semiconductor layer are respectively equal, so as to facilitate wire bonding and welding and improve packaging efficiency.

[0120] Preferably, the structure of the equal-sized electrode is Ti / Au / Ni / Pt / Ni / AuSn. The thickness of each layer of the equal-sized electrode is 400-600 angstroms / 2000-3500 angstroms / 1000-2000 angstroms / 800-1000 angstroms / 2500-3500 angstroms / 3-5 microns.

[0121] 7. forming a protective layer between the first electrode, the second electrode and the epitaxial layer;

[0122] The protective layer is filled between the first electrode, the second electrode and the epitaxial layer to prevent water vapor, dust, etc. from entering the first electrode and the second electrode. Specifically, the protective layer is made of an insulating material. Preferably, the protective layer is made of SiO 2 、Al 2 O 3 , SiNx, AlN, BN or more, with a thickness of 300 to 1000 nm.

[0123] The first electrode of the present invention forms a good ohmic contact with the first semiconductor layer with a high aluminum content by setting an N-contact layer made of Ti. In order to prevent the influence of high-temperature annealing on the first electrode, the first barrier layer, the first diffusion barrier layer and the first pad layer in the first electrode layer of the present invention sequentially wrap the structure arranged thereunder to prevent the titanium and aluminum in the first electrode from migrating due to high temperature.

[0124] Since the first electrode needs to be annealed at high temperature to form a good ohmic contact with the first semiconductor layer, metal agglomeration and migration will occur between the first electrode and the first semiconductor layer after the high temperature, making the surface of the first electrode uneven, the first electrode bubbling and cracking, and causing the chip voltage to increase; in addition, the uneven surface of the first electrode will easily cause contamination, affecting the formation of equal-sized electrodes. Therefore, the present invention arranges a second electrode on the first electrode, uses the second electrode to fill and plate the first electrode, and makes the electrode on the first semiconductor layer and the electrode on the second semiconductor layer the same height, so as to facilitate wire bonding or welding packaging.

[0125] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A high-reliability UVC LED chip, comprising a substrate, an epitaxial layer disposed on the substrate, a transparent conductive layer disposed on the epitaxial layer, and a first electrode, characterized in that: Also includes a second electrode, which is disposed on the transparent conductive layer and the first electrode respectively; The epitaxial layer comprises a first semiconductor layer, an active layer, and a second semiconductor layer which are arranged in sequence, and the transparent conductive layer is arranged on the second semiconductor layer; The first electrode includes an N-contact layer, a first insulating layer, a first diffusion barrier layer and a first pad layer; The N-contact layer is disposed on the first semiconductor layer and is made of Ti; The first barrier layer is disposed on the N-contact layer and wraps the sidewall of the N-contact layer, and is made of Al or Au; The first diffusion barrier layer is disposed on the first barrier layer and wraps the sidewall of the first barrier layer, and is made of Ti, Ni or Pt; The first pad layer is disposed on the first diffusion barrier layer and wraps the sidewall of the first diffusion barrier layer, and is made of Au; The first electrode is subjected to high temperature rapid annealing, wherein the annealing is performed at a temperature of 800-950° C. for 0.2-3 min.

2. The high reliability UVC LED chip according to claim 1, characterized in that: The thickness of the N-contact layer is 1000-2000 angstroms; the thickness of the first barrier layer is 3000-5000 angstroms; the thickness of the first diffusion barrier layer is 500-1000 angstroms; and the thickness of the first pad layer is 1-1.2 microns.

3. The high reliability UVC LED chip according to claim 1, characterized in that: The second electrode includes a P-contact layer, a second insulating layer, a second diffusion barrier layer, and a second pad layer; The P-contact layer is respectively disposed on the transparent conductive layer and the first electrode and is made of Ni; The second barrier layer is disposed on the P-contact layer and is made of Pt; The second diffusion barrier layer is disposed on the second barrier layer and is made of Ti; The second pad layer is disposed on the second diffusion barrier layer and is made of Pt.

4. The high reliability UVC LED chip according to claim 3, characterized in that: The thickness of the P-contact layer is 800-1200 angstroms; the thickness of the second barrier layer is 600-800 angstroms; the thickness of the second diffusion barrier layer is 750-850 angstroms; and the thickness of the second pad layer is 2000-3000 angstroms.

5. The high reliability UVC LED chip according to claim 1, characterized in that: The structure of the transparent conductive layer is Ni / Au, Rh / Au or Pt / Au; The transparent conductive layer is annealed at a temperature of 500-600° C. for 4-6 minutes.

6. The high reliability UVC LED chip according to claim 1, characterized in that: It also includes an equal-sized electrode and a protective layer, wherein the equal-sized electrode is arranged on the second electrode, and the structure of the equal-sized electrode is Ti / Au / Ni / Pt / Ni / AuSn; The protection layer is filled between the first electrode, the second electrode and the epitaxial layer, and the protection layer is made of insulating material.

7. A method for manufacturing a high-reliability UVC LED chip, characterized in that: The following steps are involved:

1. forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer arranged in sequence, and etching the epitaxial layer to expose the first semiconductor layer; 2. Forming a first electrode on the first semiconductor layer, the first electrode comprising an N-contact layer, a first insulating layer, a first diffusion barrier layer and a first pad layer; the N-contact layer is arranged on the first semiconductor layer of the epitaxial layer and is made of Ti; the first insulating layer is arranged on the N-contact layer and wraps the side wall of the N-contact layer and is made of Al or Au; the first diffusion barrier layer is arranged on the first barrier layer and wraps the side wall of the first barrier layer and is made of Ti, Ni or Pt; the first pad layer is arranged on the first diffusion barrier layer and wraps the side wall of the first diffusion barrier layer and is made of Au; 3. Perform high temperature rapid annealing on the first electrode at a temperature of 800-950°C and a pressure of 500-760 torr for 0.2-3 minutes; 4. forming a transparent conductive layer on the second semiconductor layer; 5. Form a second electrode on the first electrode and the transparent conductive layer respectively.

8. The method for manufacturing a high-reliability UVC LED chip according to claim 7, wherein: In step (iii), N2 is introduced at a flow rate of 30-50 slm, and the annealing time is 0.5-2 min at a temperature of 900°C and a pressure of 500-760 torr.

9. The method for manufacturing a high-reliability UVC LED chip according to claim 7, wherein: In step (iv), the structure of the transparent conductive layer is Ni / Au, Rh / Au or Pt / Au; After forming the transparent conductive layer and before forming the second electrode, N2 is introduced and annealing is performed at a temperature of 500-600° C. for 4-6 minutes.

Images