Capacitive coupled level shifter and related systems

Abstract

Embodiments of the present disclosure relate to a capacitively coupled level shifter and related systems. A capacitively coupled level shifter includes an input having a positive input terminal and a negative input terminal, the input configured to receive a modulated signal in a first voltage domain; a comparator circuit configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive voltage divider circuit including a first capacitive voltage divider leg coupling the positive input terminal of the input to a positive input terminal of the comparator circuit, and including a second capacitive voltage divider leg coupling the negative input terminal of the input to a negative input terminal of the comparator circuit. The first and second capacitive voltage divider legs are symmetric so as to cancel a common mode voltage of the modulated signal. A level shifter system including the capacitively coupled level shifter is also described.

Description

Background Technology

[0001] Level shifters are used in applications requiring interface between different voltage domains. Level shifters can be full-swing or floating, distinguished by whether the voltage domains share a common ground potential. Floating level shifters are used to shift the potential of control signals from a circuit powered by a low-voltage power rail to a circuit with a floating power supply and a ground rail. Floating level shifters are commonly used in gate drivers to drive power output stages in applications such as DC-DC converters, biomedical transducer drivers, Class D audio amplifiers, MEMS, LCD drivers, high-voltage charge pumps, and switched-capacitor power supplies.

[0002] While gate drivers are typically exposed to relatively low voltages, level shifters and potentially other components (such as bootstrap switches or diodes) must use high-voltage components—that is, components capable of withstanding the entire input voltage range. A cascading approach can also be used if the high voltage range exceeds the maximum permissible voltage of a single component, but is still within technical capabilities.

[0003] There are several ways to implement high-voltage level shifters, such as cascaded high-voltage devices, transformer-based level shifting, and capacitor-based level shifting. Cascading methods tend to be slower due to the stacking of devices, which are typically high-voltage, thus consuming layout area, reducing (speed) performance, and requiring accurate parasitic modeling and extraction. For high-speed gate driver applications such as full-bridge, half-bridge, and non-isolated buck topologies (where high common-mode rejection is critical to ensure reliable output signals), the main advantage of transformer- and capacitor-based level shifting solutions is that they are dynamically driven. Since inductors and capacitors block any DC component of the signal, the control signal is converted into a single-ended or differential pulse sequence that drives the transformer or capacitor. Thus, the static control input signal is converted into a continuous pulse sequence that refreshes the gate driver stage to prevent false triggering due to noise. The repetition rate is defined by application conditions such as switching frequency and duty cycle and can be converted to sub-nanosecond requirements. This, in turn, implies high current consumption.

[0004] Therefore, an improved level shifter design is needed. Summary of the Invention

[0005] According to one embodiment of a capacitively coupled level shifter, the capacitively coupled level shifter includes: an input having a positive input terminal and a negative input terminal, the input being configured to receive a modulated signal in a first voltage domain; a comparator circuit configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive voltage divider circuit including a first capacitive voltage divider branch coupling the positive input terminal of the input to the positive input terminal of the comparator circuit, and a second capacitive voltage divider branch coupling the negative input terminal of the input to the negative input terminal of the comparator circuit, the first and second capacitive voltage divider branches being symmetrical to cancel the common-mode voltage of the modulated signal.

[0006] In one embodiment, the first capacitive voltage divider branch includes: a first capacitor coupling a positive input terminal to a positive input terminal of a comparator circuit; a second capacitor coupling a voltage supply for the comparator circuit to a positive input terminal of the comparator circuit; and a third capacitor coupling a switching voltage node to a positive input terminal of the comparator circuit. The second capacitive voltage divider branch also includes: a fourth capacitor coupling a negative input terminal to a negative input terminal of the comparator circuit; a fifth capacitor coupling a voltage supply for the comparator circuit to a negative input terminal of the comparator circuit; and a sixth capacitor coupling a switching voltage node to a negative input terminal of the comparator circuit.

[0007] Individually or in combination, a capacitively coupled level shifter may further include a resistor ladder connected between a voltage supply for the comparator circuit and a switching voltage node. The resistor ladder may include a first resistor, a second resistor, and a third resistor connected in series. The first resistor may be electrically connected between the voltage supply for the comparator circuit and a first terminal of the second resistor. The third resistor may be electrically connected between the switching voltage node and a second terminal of the second resistor. The first terminal of the second resistor may be electrically connected to the negative input terminal of the comparator circuit, and the second terminal of the second resistor may be electrically connected to the positive input terminal of the comparator circuit. The first and third resistors may be approximately equal, and the second resistor may be smaller than both the first and third resistors.

[0008] Individually or in combination, the input may also have a reference terminal, and the capacitive voltage divider circuit may include a third capacitive voltage divider branch that couples the reference terminal of the input to the common-mode reference terminal of the comparator circuit. The modulation signal may be single-ended between the positive input terminal and the reference terminal of the input, and between the negative input terminal and the reference terminal of the input.

[0009] Individually or in combination, the capacitively coupled level shifter may further include: a first resistor ladder connected between the voltage supply for the comparator circuit and the switching voltage node; a second resistor ladder connected between the voltage supply for the comparator circuit and the switching voltage node; and a third resistor ladder connected between the voltage supply for the comparator circuit and the switching voltage node.

[0010] The first resistor ladder may include a first resistor, a second resistor, and a third resistor connected in series. The first resistor may be electrically connected between the voltage supply for the comparator circuit and the first terminal of the second resistor. The third resistor may be electrically connected between the switching voltage node and the second terminal of the second resistor. The second terminal of the second resistor may be electrically connected to the common-mode reference terminal of the comparator circuit.

[0011] The second resistor ladder may include a fourth resistor and a fifth resistor connected in series. The fourth resistor may be electrically connected between the voltage supply for the comparator circuit and the first terminal of the fifth resistor. The second terminal of the fifth resistor may be electrically connected to the switching voltage node. The first terminal of the fifth resistor may be electrically connected to the negative input terminal of the comparator circuit.

[0012] The third resistor ladder may include a sixth resistor and a seventh resistor connected in series. The sixth resistor may be electrically connected between the voltage supply for the comparator circuit and the first terminal of the seventh resistor. The second terminal of the seventh resistor may be electrically connected to the switching voltage node. The first terminal of the seventh resistor may be electrically connected to the positive input terminal of the comparator circuit.

[0013] Alone or in combination, the capacitively coupled level shifter of claim 1 may further include a resistor ladder configured to fix the DC bias points of the positive and negative inputs of the comparator circuit.

[0014] Individually or in combination, the comparator circuit may include: a differential transistor pair configured to output an amplified version of the modulated signal in a second voltage domain; and a converter circuit configured to convert the amplified version of the modulated signal into a rail-to-rail digital output signal, which is a copy of the digital control signal in the second voltage domain from which the modulated signal is generated in a first voltage domain.

[0015] Individually or in combination, the capacitively coupled level shifter may also include a speed booster circuit configured to increase the gain of the converter circuit. The speed booster circuit may include: a PMOS current source electrically connected in series with an NMOS switch between the voltage supply for the comparator circuit and the switching voltage node; and a PMOS switch configured to enable or disable the PMOS current source of the converter circuit based on the state of the rail-to-rail digital output signal provided by the converter circuit.

[0016] Individually or in combination, the voltage hysteresis of a capacitively coupled level shifter can be greater than the 6σ sigma equivalent input offset of the comparator circuit and less than the modulation signal input to the comparator circuit, wherein the common-mode voltage of the modulation signal is canceled.

[0017] Individually or in combination, a reference terminal may not be provided between the positive and negative input terminals, a common-mode reference terminal may not be provided between the positive and negative input terminals of the comparator circuit, and the modulation signal may be differential between the positive and negative input terminals.

[0018] Individually or in combination, the capacitively coupled level shifter may further include a speed booster circuit configured to increase the gain of the converter circuitry. The comparator circuitry may include: a differential transistor pair configured to output an amplified version of the modulated signal in a second voltage domain; and a first PMOS current source electrically connected to a first NMOS switch driven by the positive output of the differential transistor pair and electrically connected to a second NMOS switch driven by the negative output of the differential transistor pair. The speed booster circuitry may include: a second PMOS current source electrically connected in series with a third NMOS switch driven by the positive output of the differential transistor pair; and a PMOS switch configured to enable or disable the first PMOS current source based on the state of the rail-to-rail digital output signal provided by the converter circuitry.

[0019] Individually or in combination, a reference terminal may be provided between the positive and negative input terminals, a common-mode reference terminal may be provided between the positive and negative input terminals of the comparator circuit, and the modulation signal may be single-ended between the positive and negative input terminals and between the negative and negative input terminals.

[0020] Individually or in combination, the capacitively coupled level shifter may further include a first speed booster circuit and a second speed booster circuit configured to increase the gain of the converter circuit. The comparator circuit may include: a first differential transistor pair configured to output a first amplified version of a modulated signal applied between the positive input terminal and the common-mode reference terminal of the comparator circuit in a second voltage domain; a second differential transistor pair configured to output a second amplified version of a modulated signal applied between the negative input terminal and the common-mode reference terminal of the comparator circuit in a second voltage domain; a first PMOS current source electrically connected to a first NMOS switch driven by the positive output of the first differential transistor pair and electrically connected to a second NMOS switch driven by the common reference output of the first and second differential transistor pairs; and a second PMOS current source. An OS current source is electrically connected to a third NMOS switch driven by the negative output of a second differential transistor pair and electrically connected to a fourth NMOS switch driven by a common reference output. The first speed booster circuit may include: a third PMOS current source connected in series with a fifth NMOS switch driven by a common reference output; and a first PMOS switch configured to enable or disable the first PMOS current source based on the state of a rail-to-rail positive digital output signal provided by the converter circuit. The second speed booster circuit may include: a fourth PMOS current source connected in series with a sixth NMOS switch driven by a common reference output; and a second PMOS switch configured to enable or disable the second PMOS current source based on the state of a rail-to-rail negative digital output signal provided by the converter circuit.

[0021] According to one embodiment of a level shifter system, the level shifter system includes at least one capacitively coupled level shifter, comprising: an input having a positive input terminal and a negative input terminal, the input being configured to receive a modulated signal in a first voltage domain; a comparator circuit configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; and a capacitive voltage divider circuit including a first capacitive voltage divider branch coupling the positive input terminal of the input to the positive input terminal of the comparator circuit, and a second capacitive voltage divider branch coupling the negative input terminal of the input to the negative input terminal of the comparator circuit, the first and second capacitive voltage divider branches being symmetrical to cancel the common-mode voltage of the modulated signal. The level shifter system further includes: a modulator configured to modulate a carrier wave using a digital control signal to form a continuous pulse sequence, and to input the continuous pulse sequence as a modulated signal to the input of at least one capacitively coupled level shifter; and an SR latch having a set input electrically connected to a first output of at least one capacitively coupled level shifter, and a reset input electrically connected to a second output of at least one capacitively coupled level shifter, the SR latch being configured to output a level-shifted signal based on the states of the set input and the reset input.

[0022] Individually or in combination, a level shifter system may include a first capacitively coupled level shifter and a second capacitively coupled level shifter. For each capacitively coupled level shifter, a reference terminal may not be provided between the positive and negative input terminals, a common-mode reference terminal may not be provided between the positive and negative input terminals of the comparator circuit, and the modulation signal may be differential between the positive and negative input terminals. The modulator may be configured to apply a differential modulation signal to the first capacitively coupled level shifter when the digital control signal is in a first state, and to apply a differential modulation signal to the second capacitively coupled level shifter when the digital control signal is in a second state. The first capacitively coupled level shifter may be configured to apply a shifted modulation signal to the set input of an SR latch when the digital control signal is in the first state. The second capacitively coupled level shifter may be configured to apply a shifted modulation signal to the reset input of an SR latch when the digital control signal is in the second state.

[0023] Individually or in combination, a level shifter system may include a single capacitively coupled level shifter. The single capacitively coupled level shifter may include a reference terminal between the positive and negative input terminals of the input, and a common-mode reference terminal between the positive and negative input terminals of the comparator circuit. The modulation signal may be single-ended between the positive and reference terminals of the input, and between the negative and reference terminals of the input. The modulator may be configured to: apply the single-ended modulation signal between the positive and negative input terminals of the single capacitively coupled level shifter when the digital control signal is in a first state; and apply the single-ended modulation signal between the negative and positive input terminals of the single capacitively coupled level shifter when the digital control signal is in a second state. The single capacitively coupled level shifter may be configured to: apply the shifted modulation signal to the set input of the SR latch when the digital control signal is in the first state, and apply the shifted modulation signal to the reset input of the SR latch when the digital control signal is in the second state.

[0024] Alone or in combination, a level shifter system can be configured to apply a level-shifted signal to a high-side gate driver.

[0025] Additional features and advantages will become apparent to those skilled in the art upon reading the following detailed description and examining the accompanying drawings. Attached Figure Description

[0026] The elements in the figures need not be proportional to each other. The same reference numerals denote corresponding similar parts. Features of various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are depicted in the figures and described in detail below.

[0027] Figure 1 The diagram illustrates a block diagram of one embodiment of a level shifter system, which includes at least one capacitively coupled level shifter between an input / modulator and an output / SR latch.

[0028] Figure 2 The diagram illustrates a circuit schematic of one embodiment of a capacitively coupled level shifter.

[0029] Figure 3 The diagram illustrates a block diagram of an embodiment of a level shifter system that employs on-off keying modulation and two capacitively coupled level shifters to implement capacitively coupled level shifting.

[0030] Figure 4 and Figure 5 The diagrams show the diagrams respectively. Figure 3 The operating modes of the set and reset states of the level shifter system output / SR latch are shown.

[0031] Figure 6 The diagram illustrates a circuit schematic of another embodiment of a capacitively coupled level shifter.

[0032] Figure 7 The diagram illustrates a block diagram of an embodiment of a level shifter system that employs on-off keying modulation and a single fully differential capacitively coupled level shifter to implement capacitively coupled level shifting.

[0033] Figure 8 and Figure 9 The diagrams show the diagrams respectively. Figure 7 The operating modes of the set and reset states of the level shifter system output / SR latch are shown.

[0034] Figure 10 The diagram illustrates a circuit schematic of one embodiment of a fully differential capacitively coupled level shifter.

[0035] Figure 11 The diagram illustrates the first path of a fully differential capacitively coupled level shifter carrying a modulated signal over a time period.

[0036] Figure 12 The diagram illustrates the second path of a fully differential capacitively coupled level shifter carrying modulated signals at different time intervals.

[0037] Figure 13The diagram shows a simplified circuit diagram of a capacitively coupled level shifter. Detailed Implementation

[0038] The embodiments described herein provide a capacitively coupled level shifter. Capacitively coupled level shifters can be used in many types of applications, including those requiring operation at high voltages (even beyond the breakdown capability of devices available in the selected technology). For example, a capacitively coupled level shifter can be used in a high-side gate driver, where control signals are shifted from a low-voltage (e.g., digital) domain to the power supply domain of the gate driver. The power supply domain of the gate driver can be static or dynamic.

[0039] Capacitively coupled level shifters can be used in high-speed and high-power applications such as full-bridge, half-bridge, or non-isolated buck topologies, where high common-mode rejection is required to ensure a reliable output signal. Enhanced power supply rejection ratios may also be needed to address high power supply noise caused by overshoot and undershoot during operation.

[0040] Capacitively coupled level shifters can be used in applications where propagation delay, mismatch, and scattering at temperature and during processes are key parameters. For example, capacitively coupled level shifters can be used as floating level shifters for gate drivers to drive power output stages in applications such as DC-DC converters, biomedical transducer drivers, Class D audio amplifiers, MEMS, LCD drivers, high-voltage charge pumps, switched-capacitor power supplies, etc.

[0041] For high-speed gate driver applications such as full-bridge, half-bridge, and non-isolated buck topologies (where high common-mode rejection is required to ensure a reliable output signal), capacitively coupled level shifters offer the advantage of being dynamically driven. Because the capacitors included in the capacitively coupled level shifter block any DC component of the control signal, the control signal can be modulated into a single-ended or differential pulse sequence to drive the capacitively coupled level shifter. Therefore, a static control input signal can be converted into a continuous pulse sequence that refreshes the level shifter to prevent false triggering due to noise. The repetition rate can be defined by application conditions such as switching frequency and duty cycle, and can be converted to sub-nanosecond requirements.

[0042] Compared to other level shifter solutions, capacitively coupled level shifters offer higher speed performance, less dependence on temperature and process variations, and a smaller die area. The maximum permissible voltage swing of a capacitively coupled level shifter is determined by the maximum voltage that can be applied across the capacitor (i.e., the maximum oxide breakdown voltage of the coupling capacitor). Depending on the desired complexity and product constraints, the modulation and demodulation schemes can be digital or analog. Various embodiments of capacitively coupled level shifters and related systems are described below.

[0043] Figure 1 An embodiment of a level shifter system 100 is illustrated, which includes at least one capacitively coupled level shifter 102 between an input / modulator 104 and an output / SR latch 106. The input / modulator 104 is typically driven from a low-voltage domain (e.g., a digital domain) and has two inverted digital output signals INP and INN that form a modulation signal to drive each capacitively coupled level shifter 102 in the low-side voltage domain. The capacitively coupled level shifter 102 propagates the low-side modulation signal to the output / SR latch 106. The capacitively coupled level shifter 102 maintains and withstands the voltage difference between the power supply domain for the input / modulator 104 and the power supply domain for the output / SR latch 106.

[0044] The output / SR latch 106 is typically in the high-side voltage domain and provides an output signal (OUTPUT), which is a copy of the input signal (INPUT) shifted into the high-side voltage domain. The output signal can be used as a control signal for a gate driver, a charge pump, or generally as a control signal for any type of actuator. For example, the gate driver receiving the output signal from the level shifter system 100 can be a high-side gate driver for driving high-side power output stages in applications such as DC-DC converters, biomedical transducer drivers, Class D audio amplifiers, MEMS, LCD drivers, high-voltage charge pumps, switched-capacitor power supplies, etc. Typically, the level shifter system 100 can be used in any type of application requiring an interface between different voltage domains, such as, but not limited to, high-speed and high-power applications, such as full-bridge, half-bridge, or non-isolated buck topologies.

[0045] for Figure 1 The level shifter system 100 shown here experiences voltage stress across the coupling capacitors of each capacitively coupled level shifter 102. Different capacitor types (e.g., metallic (vertical or horizontal), polysilicon-polysilicon, etc.) can be used depending on the high-side voltage requirements. The input / modulator 104 and output / SR latch 106 of the level shifter system 100 are designed to withstand the dynamic current (AC) flowing through the capacitors of each capacitively coupled level shifter 102 during switching events (e.g., in bootstrap applications) to ensure signal integrity for reliable operation.

[0046] Figure 2 The diagram shows what is included Figure 1This is an embodiment of a capacitively coupled level shifter 102 in the level shifter system 100 shown. According to this embodiment, the capacitively coupled level shifter 102 has an input 200 with a positive input terminal INP and a negative input terminal INN. The input 200 of the capacitively coupled level shifter 102 receives a modulated signal from the input / modulator 104 of the level shifter system 100 in a first voltage domain. The capacitively coupled level shifter 102 also has a comparator circuit 202 that shifts the modulated signal at the input terminals INP and INN to a second voltage domain higher than the first voltage domain. A capacitive voltage divider circuit 204 capacitively couples the input terminals INP and INN to the comparator circuit 202 and ensures high-pass behavior of the modulated signal at the input terminals INP and INN.

[0047] The capacitive voltage divider circuit 204 includes a first capacitive voltage divider branch that couples the positive input terminal INP to the positive input terminal (A) of the comparator circuit 202, and a second capacitive voltage divider branch that couples the negative input terminal INN to the negative input terminal (B) of the comparator circuit 202. The first and second capacitive voltage divider branches are symmetrical to cancel the common-mode voltage of the modulation signal at the input terminals INP and INN of the capacitively coupled level shifter 102.

[0048] In one embodiment, the first capacitive voltage divider branch of the capacitive voltage divider circuit 204 includes a first capacitor C. B1_a Second capacitor C B1_b and the third capacitor C B1_c First capacitor C B1_a The positive input terminal INP is coupled to the positive input terminal A of comparator circuit 202, and the second capacitor C... B1_b The voltage for comparator circuit 202 is supplied to V. DD_CMP Coupled to the positive input terminal A of comparator circuit 202, and the third capacitor C B1_c Switching voltage node V SW Coupled to the positive input terminal A of comparator circuit 202. The second capacitive voltage divider branch similarly includes a fourth capacitor C. B2_a Fifth capacitor C B2_b and the sixth capacitor C B2_c The fourth capacitor C B2_a Couple the negative input terminal INN to the negative input terminal B of the comparator circuit, and the fifth capacitor C. B2_b The voltage for comparator circuit 202 is supplied to V. DD_CMP Coupled to the negative input terminal B of comparator circuit 202, and the sixth capacitor C B2_c Switching voltage node V SWCoupled to the negative input terminal B of comparator circuit 202.

[0049] In one embodiment, comparator circuit 202 includes a differential transistor pair MA, MB, such as for V DD_CMP The PMOS transistors output an amplified version (OUT_A, OUT_B) of the modulated signal in the voltage domain. Comparator circuit 202 also includes converter circuitry for converting the amplified version of the modulated signal into a rail-to-rail digital output signal (CMP_OUT), which is a digital control signal at V... DD_CMP A copy in the voltage domain, based on the digital control signal, is generated in the first voltage domain by the input / modulator 104 of the level shifter system 100. The converter circuit may include, for example, a PMOS current source 206 and corresponding NMOS transistors MC, MD for each branch of the PMOS current source 206.

[0050] The capacitively coupled level shifter 102 may also include a resistor ladder connected to the voltage supply V for the comparator circuit 202. DD_CMP With switching voltage node V SW Between. The resistor ladder fixes the DC bias points of the positive input A and negative input B of comparator circuit 202, while the differential transistor of comparator circuit 202 provides a high common-mode rejection ratio for MA and MB, thereby amplifying the input signal vab present across the positive input A and negative input B of comparator circuit 202. The voltage gain of comparator circuit 202 is given by the following formula:

[0051] |Av|=g mp ×R (1)

[0052] Where g mp R is the gain of the differential transistor pair MA and MB, and R is the resistance of the resistor included in each branch of the differential transistor pair MA and MB.

[0053] In one embodiment, the resistor ladder includes a first resistor R0, a second resistor R1, and a third resistor R2 connected in series. The first resistor R0 is electrically connected to the voltage supply V for the comparator circuit 202. DD_CMP The first terminal of the second resistor R1 is connected to the first terminal of the second resistor R1. The third resistor R2 is electrically connected to the switching voltage node V. SW Between the second terminal of the second resistor R1 and the second terminal of the second resistor R1. The first terminal of the second resistor R1 is electrically connected to the negative input terminal B of the comparator circuit 202, and the second terminal of the second resistor R1 is electrically connected to the positive input terminal A of the comparator circuit. In one embodiment, the first resistor R0 and the third resistor R2 of the resistor ladder are approximately equal, and the second resistor R1 is smaller than the first resistor R0 and the third resistor R2.

[0054] Because the resistor ladder fixes the DC bias points of the positive input A and negative input B of the comparator circuit 202, the capacitively coupled level shifter 102 provides reliable operation. The capacitively coupled level shifter 102 does not use high-voltage cascaded devices, resulting in better modeling and fewer parasitic bipolar devices to extract. The capacitively coupled level shifter 102 occupies less area than a transformer-based level shifter, and voltage stress is reduced because the input / modulator 104 and output / SR latch 106 of the level shifter system 100 are in different voltage domains with dedicated low-dropout linear regulators. The capacitively coupled level shifter 102 supports high-speed operation and fast propagation delay because it has smaller spread at the technology angle and temperature. Due to the high common-mode rejection achieved, the capacitively coupled level shifter 102 is suitable for various applications and switching behaviors, such as resonant ZVS (zero-voltage switching) or ZCS (zero-current switching) converters, hard-switching topologies, etc. The capacitively coupled level shifter 102 is stable and highly modular, and requires no additional pins / connections beyond those already available in the standard driver.

[0055] The following describes two different techniques for implementing capacitively coupled level shifting in a level shifter system. In the first technique, on-off keying (OOK) modulation and two capacitively coupled level shifters are used to implement capacitively coupled level shifting. In the second technique, a single fully differential capacitively coupled level shifter with OOK modulation is used to implement capacitively coupled level shifting.

[0056] Figure 3 The illustration shows an embodiment of a level shifter system 300 employing a first technique, in which capacitively coupled level shifting is implemented using OOK modulation and two capacitively coupled level shifters 102. For example... Figure 2 Implement as shown Figure 3 Each instance of the capacitively coupled level shifters 102', 102" shown is illustrated, and... Figure 3 The diagrams are presented with less detail. For example, the inputs 200 of each capacitively coupled level shifter 102', 102" are illustrated as a pair of inverter stages 302, and the capacitive voltage divider branches are illustrated as the corresponding capacitors C. B1 C B2 Furthermore, the comparator circuit 202 is illustrated as a simplified differential comparator module 304.

[0057] According to the first capacitively coupled level shifting technique, no reference terminal is provided between the positive input terminal INP and the negative input terminal INN of each capacitively coupled level shifter 102', 102" and no common-mode reference terminal is provided between the positive input terminal A and the negative input terminal B of the corresponding comparator circuit 202.

[0058] The input / modulator 104 of the level shifter system 300 uses a digital control signal 'HI' to modulate a carrier 'FOMHz' to form a continuous pulse sequence, and the multiplexer (MUX) 306, based on the state of the digital control signal, inputs the continuous pulse sequence as a modulation signal to the inputs of the corresponding capacitively coupled level shifters 102', 102" as a modulation signal, as will be described in more detail below. The output / SR latch 106 of the level shifter system has a set input electrically connected to the output 'CMP_OUT1' of the first capacitively coupled level shifter 102', and a reset input electrically connected to the output 'CMP_OUT2' of the second capacitively coupled level shifter 102" . The output / SR latch 106 outputs the level-shifted signal 'LVLSHFT_OUT' based on the state of the set and reset inputs of the output / SR latch 106.

[0059] According to this embodiment, the modulation signals input to the two capacitively coupled level shifters 102', 102" are differential between the positive input terminal INP and the negative input terminal INN of the corresponding level shifter input 200. Depending on the state of the modulation carrier, '1' or '0' is sent to the set or reset input of the output / SR latch 106 to ensure that the output LLVLSHFT_OUT in the level-shifted voltage domain follows the digital control signal HI.

[0060] Therefore, an on / off keying scheme is used to convert or modulate the static digital control signal HI into a continuous pulse sequence. This continuous pulse sequence refreshes the state of the output / SR latch 106 of the level shifter system 300 to prevent false triggering due to noise. The repetition rate is defined by application conditions such as switching frequency and duty cycle, and can be converted to sub-nanosecond requirements. Thus, the oscillator frequency representing the carrier FO is a design parameter selected based on current consumption budget and application constraints.

[0061] Figure 3 The level shifter system 300 shown has two paths for the set input and reset input of the output / SR latch 106. Figure 2The two symmetrical capacitively coupled level shifters 102' and 102" of the type shown complete this path. A high level of symmetry is used in the two capacitively coupled level shifters 102' and 102" to ensure that the propagation delays of the signal's rising and falling edges are the same or nearly the same during tracking processes and temperatures. A mismatch in propagation delays represents a quality factor for many power applications, which affects the minimum usable dead time and thus the overall system efficiency, and is preferably minimized.

[0062] Figure 4 and Figure 5 The diagrams illustrate the operation modes of the level shifter system output / SR latch 106 in the set and reset states, respectively. Figure 4 The operating modes of ON or Set state are shown. The ON or Set state corresponds to the state when the static digital control signal HI is high (such as logic '1'). Figure 5 The operating modes of OFF or reset state are shown. OFF or reset state corresponds to the state when the static digital control signal HI is low (such as logic '0'). When the static digital control signal HI is high, the first (upper) capacitively coupled level shifter 102' drives the set input of the output / SR latch 106, and when the static digital control signal HI is low, the second (lower) capacitively coupled level shifter 102” drives the reset input of the output / SR latch 106.

[0063] The input / modulator 104 of the level shifter system 300 uses a modulated signal to differentially drive symmetrical capacitively coupled level shifters 102', 102', as shown in the figure. Figure 4 and Figure 5 As shown. If If the power supply voltage is the input / modulator 104 of the level shifter system 300, then the total differential input signal (AC) used to drive the symmetrical capacitively coupled level shifters 102' and 102" can be represented as follows:

[0064]

[0065] Equation (2) represents the total differential input voltage signal of the input / modulator 104 of the level shifter system 300, and defines the SNR (signal-to-noise ratio) of the level shifter system 300. Thus, it should be... The choice is a trade-off between the optimal SNR at a given oscillator frequency and the available current budget.

[0066] In fact, the average current consumption on the input side of the level shifter system 300 is given by the following formula:

[0067]

[0068] Where C L This represents the total equivalent load capacitance of the inverter stage 302 of the symmetrically capacitively coupled level shifters 102' and 102" .

[0069] By the corresponding capacitive voltage divider branch ( Figure 2 The capacitors CB1_a to CB1_c and CB2_a to CB2_c in the capacitors form capacitive voltage dividers 204 for each capacitively coupled level shifter 102', 102" to implement a high-pass transfer function from the input side to the output side of the level shifter 102', 102" . The capacitive voltage divider 204 of each capacitively coupled level shifter 102', 102" blocks any DC component of the modulated input signal toward the input side of the comparator circuit 202, while allowing differential mode to pass through to the differential transistor pair MA, MB of the comparator circuit 202, which is the gain stage of the level shifter 102', 102" . Due to the symmetry of the capacitive voltage divider branches of each capacitively coupled level shifter 102', 102" , the positive input terminal A and negative input terminal B of the corresponding comparator circuit 202 are maintained The DC bias is defined by the corresponding resistor ladder formed by resistors R0, R1, and R2.

[0070] The common-mode variation at the positive input terminal A and negative input terminal B of each comparator circuit 202 is suppressed by the corresponding differential transistor pair MA and MB of the comparator circuit 202, which in turn amplifies the equivalent differential signal from the input side of the level shifters 102' and 102"

[0071] The attenuation factor α of capacitive voltage divider 204 C It can be defined as follows:

[0072] In C TX < <C RX In this case, Where C B1_a =C B2_a =C TX And C B1_b =C B1_c =C B2_b =C B2_c =C RX .

[0073] By appropriately selecting resistors R0, R1, and R2 in the resistor ladder, the equivalent input voltage signals at the positive input terminal A and negative input terminal B of comparator circuit 202 can be represented as follows:

[0074]

[0075]

[0076] The input signals at the positive input terminal A and negative input terminal B of comparator circuit 202 can be decomposed into common-mode V. cm Sum and difference modulus v d ,get:

[0077] v INP =v cm +v d / 2 (7)

[0078] v INN =v cm -v d / 2 (8)

[0079] Equations (7) and (8) can be substituted into equations (5) and (6) to obtain the equivalent differential input voltage on the input side of comparator circuit 202, as shown below:

[0080]

[0081] Equation (9) reveals that by including a capacitive voltage divider 204 in each capacitively coupled level shifter 102', 102"', the differential input voltage on the input side of the corresponding level shifter 102', 102"'' is only proportional to the differential output voltage on the output side of the level shifter 102', 102"''. This is because the capacitor C in each capacitive voltage divider 204... B1_a and C B2_a Due to the symmetry in the circuit, the common-mode voltage is canceled out. At the switching voltage node V with high voltage and high switching speed... SW In applications such as DC-DC converters with hard-switching topologies, this property is fundamental. Furthermore, the capacitor C of the capacitive voltage divider... B1_b C B1_c C B2_b and C B2_c The power supply rejection ratio of comparator circuit 202 is improved, thus enabling it to be used as a high-pass filter for power supply and ground noise.

[0082] A resistor ladder formed by resistors R0, R1, and R2 connected in series provides DC bias for comparator circuit 202, ensuring a stable output state when no modulation is applied at the input 200 of the corresponding capacitively coupled level shifters 102', 102"". Thus, appropriate voltage hysteresis should be guaranteed, as given by the following equation:

[0083]

[0084] In one embodiment, the hysteresis voltage is selected based on the ±6σ sigma equivalent input offset of comparator circuit 202 and based on the differential signal represented by equation (9), as given by:

[0085]

[0086] According to equation (11), the voltage hysteresis of each capacitively coupled level shifter 102', 102" can be greater than the 6σ sigma equivalent input offset of comparator circuit 202, and less than the modulation signal input to comparator circuit 202, wherein the common-mode voltage (V) of the modulation signal is... cm The input signal v across the positive input terminal A and negative input terminal B of comparator circuit 202 and expressed in equation (9) is canceled out. ab The differential transistors of the comparator circuit 202 amplify MA and MB, producing a voltage gain |Av| as expressed by equation (1).

[0087] Figure 6 The diagram shows that it can be used Figure 1 and Figure 3 Another embodiment of the symmetrically capacitively coupled level shifter 400 used in the level shifter systems 100 and 300 shown. Figure 6 The embodiments shown are similar to Figure 2 The embodiments illustrated in the figure are similar. However, the difference is that... Figure 6 The capacitively coupled level shifter 400 shown also includes a speed booster circuit for increasing the gain of the converter circuitry of the capacitively coupled level shifter 400. In one embodiment, the speed booster circuit includes a PMOS current source 402, which is connected in series with an NMOS switch MK to the voltage supply V for the comparator circuit 202. DD_CMP With switching voltage node V SW In between, and including a PMOS switch MOFF, which is configured to enable or disable the PMOS current source 206 of the converter circuit based on the state of the rail-to-rail digital output signal CMP_OUT provided by the converter circuit.

[0088] The comparator circuit 202 of the capacitively coupled level shifter 400 is actually a voltage amplifier, and with the help of transistors MC and MD, it converts the amplified differential voltage OUT_A-OUT_B into a rail-to-rail digital output signal OUT_D, which is a copy of the low-side input control signal HI in the level-shifted domain. Figure 6 The speed booster circuit shown increases the gain of comparator circuit 202, enhancing its speed performance while maintaining nearly the same current consumption. Using the proposed architecture, the propagation delay rises and falls in the sub-nanosecond range.

[0089] Figure 7 The illustration shows an embodiment of a level shifter system 500 employing a second type of OOK-modulated capacitively coupled level shifting technique. Figure 3 The embodiment illustrated in the figure differs from the one shown, using a single fully differential capacitively coupled level shifter 502. According to this embodiment, the input 302 of the fully differential capacitively coupled level shifter 502 also has a reference terminal INR, and the capacitive voltage divider circuit 504 has a corresponding third capacitive voltage divider branch. The third capacitive voltage divider branch couples the reference terminal INR to the common-mode reference terminal 'REF' of the comparator circuit 506 of the fully differential capacitively coupled level shifter 502. The third capacitive voltage divider branch in... Figure 7 The capacitor CB3 is shown in the diagram. The modulation signal input from the input / modulator 104 of the level shifter system 500 to the fully differential capacitively coupled level shifter 502 is single-ended between the positive input terminal INP and the reference terminal INR, and between the negative input terminal INN and the reference terminal INR.

[0090] The positive output O+ of the comparator circuit 506 of the fully differential capacitively coupled level shifter 502 is electrically connected to the set input S of the output / SR latch 106 of the level shifter system 500, and the negative output O- of the comparator circuit 506 is electrically connected to the reset input R of the output / SR latch 106. Based on the states of the set and reset inputs of the output / SR latch 106, the output / SR latch 106 outputs a level-shifted signal 'LVLSHFT_OUT', which in turn depends on whether the positive output O+ or the negative output O- of the comparator circuit 506 carries a level-shifted signal.

[0091] Figure 8 and Figure 9 The diagrams respectively illustrate the targets Figure 7 The operating modes of the set and reset states of the level shifter system output / SR latch 106 of the single fully differential capacitively coupled level shifter 502 shown. Figure 8 The operating modes for the ON or set state are shown. The ON or set state corresponds to the state when the static digital control signal HI is high (such as logic '1'). Figure 9 The operating modes for the OFF or reset state are shown. The OFF or reset state corresponds to the state when the static digital control signal HI is low (such as logic '0'). Based on the state of the static digital control signal HI, the multiplexer 306 of the input / modulator 104 of the level shifter system 500 controls whether the positive (upper) path or the negative (lower) path of the fully differential capacitively coupled level shifter 502 drives the output / SR latch 106 of the level shifter system 500.

[0092] When the static digital control signal HI is high, the set input of the output / SR latch 106 is driven by the positive path of the fully differential capacitively coupled level shifter 502 via a pulse received at the positive input terminal INP. The pulse, propagating along the positive path of the fully differential capacitively coupled level shifter 502, is referenced to the common-mode reference terminal REF of the comparator circuit 506 via the reference terminal INR, and is therefore single-ended, transitioning from a high voltage level VH to a low voltage level VL.

[0093] When the static digital control signal HI is low, the negative path of the fully differential capacitively coupled level shifter 502 drives the reset input of the output / SR latch 106 via a pulse received at the negative input terminal INN. The pulse, propagating along the negative path of the fully differential capacitively coupled level shifter 502, is referenced to the common-mode reference terminal REF of the comparator circuit 506 via the reference terminal INR, and is therefore single-ended; this pulse transitions from a high voltage level VH to a low voltage level VL.

[0094] Figures 7 to 9 The capacitively coupled level shifting technique illustrated in the diagram uses the same fully differential capacitively coupled level shifter 502 between the input / modulator 104 and the output / SR latch 106 of the level shifter system 500. As described above, in this case, OOK modulation is single-ended.

[0095] and Figures 3 to 5 Compared to the capacitively coupled level shifting technique illustrated in the diagram (which uses two symmetrically capacitively coupled level shifters 102', 102" between the input / modulator 104 and the output / SR latch 106 of the level shifter system 300), Figures 7 to 9 The capacitively coupled level shifting technique illustrated in the diagram reduces the signal path between the input / modulator 104 and the output / SR latch 106 to a single channel. Using a single fully differentially capacitively coupled level shifter 502 on the input side of the level shifter system 500 allows for reduced current consumption and layout area, but introduces increased complexity in the unit design.

[0096] Figure 10 The diagram shows... Figure 7 This is one embodiment of the unit design of the fully differential capacitively coupled level shifter 502 shown. The capacitive voltage divider circuit 508 of the fully differential capacitively coupled level shifter 502 is... Figure 2 and Figure 6 The capacitive voltage divider circuit 204 of the capacitively coupled level shifters 102 and 400 shown is similar. However, the difference is that... Figure 10The capacitive voltage divider circuit 508 of the fully differential capacitively coupled level shifter 502 illustrated in the diagram also has a third capacitive voltage divider branch, which couples the reference terminal INR of the level shifter input to the common-mode reference terminal REF of the comparator circuit 506. The third capacitive voltage divider branch includes a capacitor C. B3_a Capacitor C B3_b and capacitor C B3_c capacitor C B3_a The reference input terminal INR is coupled to the reference terminal REF of comparator circuit 506, and capacitor C... B3_b The voltage for comparator circuit 506 is supplied to V. DD_CMP Coupled to the reference terminal REF of comparator circuit 506, and capacitor C B3_c Switching voltage node V SW The reference terminal REF is coupled to comparator circuit 506.

[0097] In addition to the combinations mentioned above Figures 3 to 5 The capacitively coupled level shifting technique illustrated in the diagram describes a resistor ladder formed by resistors R0, R1, and R2. Figure 10 The fully differential capacitively coupled level shifter 502 shown in the diagram also includes a voltage supply V connected to the comparator circuit 506. DD_CMP With switching voltage node V SW The second resistor ladder between, and includes a voltage supply V connected to the comparator circuit 506. DD_CMP With switching voltage node V SW The third resistor ladder between.

[0098] The second resistor ladder includes two resistors R3_b and R4_b connected in series. Resistor R3_b is electrically connected to the voltage supply V used in comparator circuit 506. DD_CMP Between the first terminal of resistor R4_b and the second terminal of resistor R4_b. The second terminal of resistor R4_b is electrically connected to the switching voltage node V. SW The first terminal of resistor R4_b is electrically connected to the negative input terminal B of comparator circuit 506. The third resistor series also includes two resistors R3_a and R4_a connected in series. Resistor R3_a is electrically connected to the voltage supply V for comparator circuit 506. DD_CMP Between the first terminal of resistor R4_a and the second terminal of resistor R4_a. The second terminal of resistor R4_a is electrically connected to the switching voltage node V. SW The first terminal of resistor R4_a is electrically connected to the positive input terminal A of comparator circuit 506.

[0099] Figure 10 The basic operating principle of the fully differential capacitively coupled level shifter 502 shown in the figure is as follows: Figure 2and Figure 6 The capacitively coupled level shifters 102 and 400 shown are essentially the same. Therefore, for Figure 10 The equations and formulas described above are valid for the fully differential capacitively coupled level shifter 502 shown in the diagram.

[0100] Figure 10 The main difference of the fully differential capacitively coupled level shifter 502 shown in the diagram is that the comparator circuit 506 has three input paths: path A, which is the set path for the output / SR latch 106 of the level shifter system 500 when modulation is applied; path B, which is the reset path for the output / SR latch 106 when modulation is applied; and a reference path, which defines the dominant state of the comparator outputs OUT_A and OUT_B as low when neither path A nor path B is in modulation mode.

[0101] Path A of comparator circuit 506 includes a first differential transistor pair MA and MC, configured to output a first amplified version of the modulated signal applied between the positive input terminal A and the common-mode reference terminal REF of comparator circuit 506. Path B of comparator circuit 506 includes a second differential transistor pair MB and MC, configured to output a second amplified version of the modulated signal applied between the negative input terminal B and the common-mode reference terminal REF of comparator circuit 506.

[0102] The comparator circuit 506 further includes a first PMOS current source 510, which is electrically connected to a first NMOS switch ME driven by the positive output OUT_A of the first differential transistor pair MA / MC, and electrically connected to a second NMOS switch MF driven by the common reference output OUT_REF of the first and second differential transistor pairs MA / MC, MB / MC. The comparator circuit 506 also includes a second PMOS current source 512, which is electrically connected to a third NMOS switch MG driven by the negative output OUT_B of the second differential transistor pair MB / MC, and electrically connected to a fourth NMOS switch MH driven by the common reference output OUT_REF.

[0103] The modulation scheme can use, for example, on-off keying (OOK) and is single-ended, meaning that only path A or path B of comparator circuit 506 carries the modulated signal at a certain point in time, thereby reducing current draw. Therefore, by using differential OOK modulation, the differential signal v at the input side of comparator circuit 506... a-ref and v b-ref Both are reduced by half compared to equation (9), therefore, with Figure 2 and Figure 6 Compared to the capacitively coupled level shifter implementation shown, the SNR is reduced by -6dB.

[0104] The hysteresis voltage is still determined by the first resistor ladder formed by resistors R0, R1, and R2, and is determined according to equation (10). The resistors of the second and third resistor ladders satisfy the following conditions:

[0105] R3=R4and R0+R1+R2=R3+R4 (12)

[0106] R5 = R6 = R7 (13)

[0107] The fully differential capacitively coupled level shifter 502 may include two instances of the speed booster circuitry described earlier herein for increasing the gain of the converter circuitry. In one embodiment, the first speed booster circuitry includes a PMOS current source 514 electrically connected in series with an NMOS switch MK2 driven by the common reference output OUT_REF of the first and second differential transistor pairs MA / MC, MB / MC, and includes a PMOS switch MOFF2 configured to enable or disable the first PMOS current source 510 of the comparator circuitry 506 based on the state of a rail-to-rail positive digital output signal that forms the set input of the output / SR latch 106 of the level shifter system 500. The second speed booster circuit similarly includes a PMOS current source 516, which is connected in series with an NMOS switch MK1 driven by a common reference output OUT_REF; and includes a PMOS switch MOFF1, which is configured to enable or disable the second PMOS current source 512 of the comparator circuit 506 based on the state of a rail-to-rail negative digital output signal that forms the reset input of the output / SR latch 106 of the level shifter system 500.

[0108] Figure 11 The diagram illustrates path A of a fully differential capacitively coupled level shifter 502 that carries a modulated signal over a time period.

[0109] Figure 12 The diagram illustrates path B of a fully differential capacitively coupled level shifter 502 carrying modulated signals at different time intervals.

[0110] When the static digital control signal HI is high, the input / modulator 104 of the level shifter system 500 applies a modulation signal to the positive input terminal INP of the fully differential capacitively coupled level shifter 502, such as... Figure 11As shown in the diagram, the modulation signal is amplified by the first differential transistor pair MA and MC and converted into a rail-to-rail digital output signal SET_OUT. The rail-to-rail digital output signal SET_OUT is input to the set terminal S of the input / SR latch 106 of the level shifter system 500.

[0111] When the static digital control signal HI is low, the input / modulator 104 of the level shifter system 500 applies a modulation signal to the negative input terminal INN of the fully differential capacitively coupled level shifter 502, such as... Figure 12 As shown in the diagram, the modulation signal is amplified by the second differential transistor pair MB and MC, and converted into a rail-to-rail digital output signal RESET_OUT. The rail-to-rail digital output signal RESET_OUT is input to the reset terminal R of the input / SR latch 106 of the level shifter system 500.

[0112] Figure 13 A simplified schematic diagram of a level shifter 600 with capacitive coupling of differential transistors to MA and MB, consisting only of a capacitive voltage divider 602 and a comparator circuit 604, is shown. As described above and analyzed in equation (9), the equivalent differential input signal v on the input side of the differential transistors to MA and MB is... ab Depends only on the differential input signal v to the capacitively coupled level shifter 600 in_pn The common-mode voltage v of the modulation signal cm The symmetry of the capacitive voltage divider 602 cancels this out. In this way, even with rapid common-mode changes, the capacitively coupled level shifter 600 can always transmit control signals in different power domains. The proposed capacitively coupled level shifter described herein offers greater flexibility than conventional level shifters.

[0113] Terms such as "first," "second," etc., are used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout this description, the same terms refer to the same elements.

[0114] As used herein, the terms “having,” “comprising,” “including,” “containing,” etc., are open-ended terms that indicate the presence of the stated element or feature, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles “a,” “an,” and “the” are intended to include both plural and singular forms.

[0115] It should be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0116] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A capacitively coupled level shifter, comprising: The input has a positive input terminal and a negative input terminal, and the input is configured to receive a modulated signal in a first voltage domain; The comparator circuit is configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; A capacitive voltage divider circuit includes a first capacitive voltage divider branch coupling the positive input terminal of the input to the positive input terminal of the comparator circuit, and a second capacitive voltage divider branch coupling the negative input terminal of the input to the negative input terminal of the comparator circuit, the first and second capacitive voltage divider branches being symmetrical to cancel the common-mode voltage of the modulation signal; and A resistor ladder is connected between a voltage supply for the comparator circuit and a switching voltage node, wherein the resistor ladder includes a first resistor, a second resistor, and a third resistor connected in series, wherein the first resistor is electrically connected between the voltage supply for the comparator circuit and a first terminal of the second resistor, wherein the third resistor is electrically connected between the switching voltage node and a second terminal of the second resistor, wherein the first terminal of the second resistor is electrically connected to the negative input terminal of the comparator circuit, and wherein the second terminal of the second resistor is electrically connected to the positive input terminal of the comparator circuit.

2. The capacitively coupled level shifter according to claim 1, wherein the first capacitive voltage divider branch comprises: A first capacitor couples the positive input terminal of the input to the positive input terminal of the comparator circuit; The second capacitor couples the voltage supply for the comparator circuit to the positive input terminal of the comparator circuit; as well as The third capacitor couples the switching voltage node to the positive input terminal of the comparator circuit, and The second capacitive voltage divider branch includes: A fourth capacitor couples the negative input terminal of the input to the negative input terminal of the comparator circuit; A fifth capacitor couples the voltage supply for the comparator circuit to the negative input terminal of the comparator circuit; and A sixth capacitor couples the switching voltage node to the negative input terminal of the comparator circuit.

3. The capacitively coupled level shifter of claim 2, wherein the input further has a reference terminal, wherein the capacitive voltage divider circuit includes a third capacitive voltage divider branch that couples the reference terminal of the input to a common-mode reference terminal of the comparator circuit, and wherein the modulation signal is single-ended between the positive input terminal of the input and the reference terminal of the input, and between the negative input terminal of the input and the reference terminal of the input.

4. The capacitively coupled level shifter according to claim 3, wherein the resistor ladder is a first resistor ladder, and the capacitively coupled level shifter further comprises: A second resistor is connected between the voltage supply for the comparator circuit and the switching voltage node; as well as A third resistor ladder is connected between the voltage supply for the comparator circuit and the switching voltage node. The second resistor ladder includes a fourth resistor and a fifth resistor connected in series. The fourth resistor is electrically connected between the voltage supply for the comparator circuit and a first terminal of the fifth resistor. The second terminal of the fifth resistor is electrically connected to the switching voltage node, and the first terminal of the fifth resistor is electrically connected to the negative input terminal of the comparator circuit. The third resistor ladder includes a sixth resistor and a seventh resistor connected in series. The sixth resistor is electrically connected between the voltage supply for the comparator circuit and the first terminal of the seventh resistor. The second terminal of the seventh resistor is electrically connected to the switching voltage node, and the first terminal of the seventh resistor is electrically connected to the positive input terminal of the comparator circuit.

5. The capacitively coupled level shifter of claim 1, wherein the first resistor and the third resistor are approximately equal, and wherein the second resistor is smaller than the first resistor and the third resistor.

6. The capacitively coupled level shifter of claim 1, wherein the resistor ladder is configured to fix the DC bias point of the positive input terminal and the negative input terminal of the comparator circuit.

7. The capacitively coupled level shifter according to claim 1, wherein the comparator circuit comprises: A differential transistor pair is configured to output an amplified version of the modulated signal in the second voltage domain; as well as A converter circuit is configured to convert the amplified version of the modulated signal into a rail-to-rail digital output signal, the rail-to-rail digital output signal being a copy of a digital control signal in a second voltage domain, from which the modulated signal is generated in a first voltage domain.

8. The capacitively coupled level shifter of claim 7 further includes a speed booster circuit configured to increase the gain of the converter circuit.

9. The capacitively coupled level shifter according to claim 8, wherein the speed booster circuit comprises: A PMOS current source is connected in series with an NMOS switch between the voltage supply for the comparator circuit and the switch voltage node. as well as The PMOS switch is configured to enable or disable the PMOS current source of the converter circuit based on the state of the rail-to-rail digital output signal provided by the converter circuit.

10. The capacitively coupled level shifter of claim 1, wherein the voltage hysteresis of the capacitively coupled level shifter is greater than the 6σ sigma equivalent input offset of the comparator circuit and less than the modulation signal input to the comparator circuit, wherein the common-mode voltage of the modulation signal is canceled.

11. The capacitively coupled level shifter of claim 1, wherein no reference terminal is provided between the positive input terminal and the negative input terminal of the input, wherein no common-mode reference terminal is provided between the positive input terminal and the negative input terminal of the comparator circuit, and wherein the modulation signal is differential between the positive input terminal and the negative input terminal of the input.

12. The capacitively coupled level shifter of claim 11, wherein the comparator circuit comprises: A differential transistor pair is configured to output an amplified version of the modulated signal in the second voltage domain; A first PMOS current source is electrically connected to a first NMOS switch driven by the positive output of the differential transistor pair, and electrically connected to a second NMOS switch driven by the negative output of the differential transistor pair; as well as A converter circuit, including a first NMOS switch and a second NMOS switch, is configured to convert the amplified version of the modulated signal into a rail-to-rail digital output signal, the rail-to-rail digital output signal being a copy of a digital control signal in a second voltage domain, from which the modulated signal is generated in the first voltage domain. The capacitively coupled level shifter further includes a speed booster circuit configured to increase the gain of the converter circuit, wherein the speed booster circuit includes: The second PMOS current source is connected in series with the third NMOS switch driven by the positive output of the differential transistor pair; as well as The PMOS switch is configured to enable or disable the first PMOS current source based on the state of the rail-to-rail digital output signal provided by the converter circuit.

13. The capacitively coupled level shifter of claim 1, wherein a reference terminal is provided between the positive input terminal and the negative input terminal of the input, wherein a common-mode reference terminal is provided between the positive input terminal and the negative input terminal of the comparator circuit, and wherein the modulation signal is single-ended between the positive input terminal and the reference terminal of the input, and between the negative input terminal and the reference terminal of the input.

14. The capacitively coupled level shifter of claim 13, wherein the comparator circuit comprises: The first differential transistor pair is configured to output, in the second voltage domain, a first amplified version of the modulation signal applied between the positive input terminal and the common-mode reference terminal of the comparator circuit; The second differential transistor pair is configured to output a second amplified version of the modulation signal applied between the negative input terminal and the common-mode reference terminal of the comparator circuit in the second voltage domain. A first PMOS current source is electrically connected to a first NMOS switch driven by the positive output of the first differential transistor pair, and electrically connected to a second NMOS switch driven by the common reference output of the first differential transistor pair and the second differential transistor pair. The second PMOS current source is electrically connected to the third NMOS switch driven by the negative output of the second differential transistor pair, and electrically connected to the fourth NMOS switch driven by the common reference output. as well as A converter circuit, including a first NMOS switch, a second NMOS switch, a third NMOS switch, and a fourth NMOS switch, is configured to convert a first amplified version of the modulation signal and a second amplified version of the modulation signal into a rail-to-rail positive digital output signal and a rail-to-rail negative digital output signal, respectively. The rail-to-rail positive digital output signal and the rail-to-rail negative digital output signal are each copies of a digital control signal in a second voltage domain. The modulation signal is generated from the digital control signal in the first voltage domain. The capacitively coupled level shifter further includes a first speed booster circuit and a second speed booster circuit configured to increase the gain of the converter circuit, wherein the first speed booster circuit includes: The third PMOS current source is connected in series with the fifth NMOS switch driven by the common reference output; and The first PMOS switch is configured to enable or disable the first PMOS current source based on the state of the rail-to-rail positive digital output signal provided by the converter circuit. The second speed booster circuit includes: The fourth PMOS current source is connected in series with the sixth NMOS switch driven by the common reference output; and The second PMOS switch is configured to enable or disable the second PMOS current source based on the state of the rail-to-rail negative digital output signal provided by the converter circuit.

15. A level shifter system, comprising: At least one capacitively coupled level shifter, comprising: The input has a positive input terminal and a negative input terminal, and the input is configured to receive a modulated signal in a first voltage domain; The comparator circuit is configured to shift the modulated signal to a second voltage domain higher than the first voltage domain; A capacitive voltage divider circuit includes a first capacitive voltage divider branch coupling the positive input terminal of the input to the positive input terminal of the comparator circuit, and a second capacitive voltage divider branch coupling the negative input terminal of the input to the negative input terminal of the comparator circuit, the first and second capacitive voltage divider branches being symmetrical to cancel the common-mode voltage of the modulation signal; and A resistor ladder is connected between the voltage supply for the comparator circuit and a switching voltage node, wherein the resistor ladder includes a first resistor, a second resistor, and a third resistor connected in series, wherein the first resistor is electrically connected between the voltage supply for the comparator circuit and a first terminal of the second resistor, wherein the third resistor is electrically connected between the switching voltage node and a second terminal of the second resistor, wherein the first terminal of the second resistor is electrically connected to the negative input terminal of the comparator circuit, and wherein the second terminal of the second resistor is electrically connected to the positive input terminal of the comparator circuit. A modulator is configured to modulate a carrier wave using a digital control signal to form a continuous pulse sequence, and to input the continuous pulse sequence as the modulation signal to the input of the at least one capacitively coupled level shifter; and An SR latch has a set input electrically connected to a first output of the at least one capacitively coupled level shifter, and a reset input electrically connected to a second output of the at least one capacitively coupled level shifter, the SR latch being configured to output a level-shifted signal based on the states of the set input and the reset input.

16. The level shifter system of claim 15, wherein the level shifter system comprises a first capacitively coupled level shifter and a second capacitively coupled level shifter, wherein for each capacitively coupled level shifter, no reference terminal is provided between the positive input terminal and the negative input terminal of the input, no common-mode reference terminal is provided between the positive input terminal and the negative input terminal of the comparator circuit, and the modulation signal is differential between the positive input terminal and the negative input terminal of the input, wherein the modulator is configured to: when the digital control signal is in a first state The differential modulation signal is applied to the first capacitively coupled level shifter; and when the digital control signal is in the second state, the differential modulation signal is applied to the second capacitively coupled level shifter, wherein the first capacitively coupled level shifter is configured to apply the shifted modulation signal to the set input of the SR latch when the digital control signal is in the first state, and wherein the second capacitively coupled level shifter is configured to apply the shifted modulation signal to the reset input of the SR latch when the digital control signal is in the second state.

17. The level shifter system of claim 16, wherein the level shifter system comprises a single capacitively coupled level shifter, wherein the single capacitively coupled level shifter includes a reference terminal between the positive input terminal and the negative input terminal of the input, and a common-mode reference terminal between the positive input terminal and the negative input terminal of the comparator circuit, wherein the modulation signal is single-ended between the positive input terminal and the reference terminal of the input, and between the negative input terminal and the reference terminal of the input. The modulator is configured to apply the single-ended modulation signal between the positive input terminal and the negative input terminal of the input of the single capacitively coupled level shifter when the digital control signal is in a first state. The modulator is configured to apply a single-ended modulated signal between the negative input terminal and the negative input terminal of the input of the single capacitively coupled level shifter when the digital control signal is in the second state, wherein the single capacitively coupled level shifter is configured to apply the shifted modulated signal to the set input of the SR latch when the digital control signal is in the first state, and to apply the shifted modulated signal to the reset input of the SR latch when the digital control signal is in the second state.

18. The level shifter system of claim 15, wherein the level shifter system is configured to apply the level-shifted signal to a high-side gate driver.

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