Source contact structure for three-dimensional memory devices and methods of manufacturing the memory devices

Abstract

An embodiment of a three-dimensional (3D) memory device having a source contact structure in a memory stack is disclosed. The 3D memory device includes: a memory stack comprising a plurality of interleaved conductor layers and insulating layers extending over a substrate; a plurality of channel structures, each extending perpendicularly through the memory stack into the substrate; and a source contact structure extending perpendicularly through the memory stack and laterally to divide the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts, each electrically coupled to a common source of the plurality of channel structures.

Description

[0001] This application is a divisional application of the invention patent application filed on January 18, 2019, entitled "Source Contact Structure of Three-Dimensional Storage Device and Method for Manufacturing the Storage Device", with application number 201980000183.8. Technical Field

[0002] This disclosure relates to three-dimensional (3D) storage devices and methods for manufacturing the same. Background Technology

[0003] Through improvements in process technology, circuit design, programming algorithms, and manufacturing processes, planar memory cells have been scaled down to smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and expensive. As a result, the storage density of planar memory cells is approaching its upper limit.

[0004] 3D memory architecture can address the density limitations of planar memory cells. A 3D memory architecture comprises a memory array and peripheral devices for controlling signals to and from the memory array. Summary of the Invention

[0005] This invention discloses a 3D memory device and a method for manufacturing a 3D memory device.

[0006] In one example, a memory device includes: a memory stack having a plurality of interleaved conductor layers and insulating layers extending over a substrate; a plurality of channel structures, each extending perpendicularly through the memory stack into the substrate; and a source contact structure extending perpendicularly through the memory stack and laterally to divide the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts electrically coupled to a common source of the plurality of channel structures.

[0007] In another example, a memory device includes: a memory stack having a plurality of interleaved conductor layers and an insulating layer extending over a substrate; a plurality of channel structures, each extending perpendicularly through the memory stack into the substrate; and source contact structures extending perpendicularly through the memory stack and laterally to divide the memory stack into a first portion and a second portion. The source contact structures may include a plurality of source contacts in a dielectric layer and insulated from each other through the dielectric layer; and each of the plurality of source contacts is electrically coupled to a common source of the plurality of channel structures.

[0008] In yet another example, a method of forming a memory device includes: forming a plurality of channel structures, each extending vertically through a memory stack into a substrate; and forming source contact structures that extend vertically through the memory stack and laterally to divide the memory stack into a first portion and a second portion. Forming the source contact structures may include forming a plurality of source contact portions electrically coupled to a common source of the plurality of channel structures.

[0009] In yet another example, a method of forming a memory device includes: forming a plurality of channel structures, each extending vertically through a memory stack into a substrate; and forming source contact structures that extend vertically through the memory stack and laterally to divide the memory stack into a first portion and a second portion. The formation of the source contact structures may include forming a plurality of source contact portions on a source conductor. Each of the plurality of source contact portions may be electrically coupled to a common source of the plurality of channel structures. Attached Figure Description

[0010] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure and enable those skilled in the art to implement and use it.

[0011] Figure 1A A cross-sectional view of an exemplary 3D storage device according to some embodiments of the present disclosure is shown.

[0012] Figure 1B Examples of some embodiments according to this disclosure are provided. Figure 1A The top view of the 3D storage device is shown in the image.

[0013] Figures 2-5A Cross-sectional views of exemplary 3D storage devices according to some embodiments of the present disclosure at various stages of the manufacturing process are illustrated.

[0014] Figure 5B Examples of some embodiments according to this disclosure are provided. Figure 5A The top view of the 3D storage device is shown in the image.

[0015] Figure 6 Examples of exemplary process flows for forming 3D storage devices according to some embodiments of this disclosure.

[0016] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0017] While specific configurations and arrangements have been discussed, it should be understood that they are merely illustrative. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be adopted in various other applications.

[0018] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the application documents may describe embodiments that include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, this phrase does not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing that feature, structure, or characteristic in connection with other embodiments is within the knowledge of those skilled in the art.

[0019] Terminology is generally understood, at least in part, based on its use in context. For example, the term "one or more," as used herein, can be used, at least in part, depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can again be understood to convey either singular or plural usage, at least in part, depending on the context. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the existence of additional factors that are not necessarily clearly described, again, at least in part, depending on the context.

[0020] It will be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on,” but also includes “on,” with an intermediate feature or layer, and that “above” or “on top of” not only means “above,” but also includes “above,” without an intermediate feature or layer (i.e., directly on).

[0021] Furthermore, spatially relative terms such as "below," "under," "lower," "above," and "upper" are used to readily describe the relationship between one element or feature and other elements (single or multiple) or features (single or multiple) as exemplified in the figures. In addition to the orientations depicted in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein can be interpreted accordingly.

[0022] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can also be patterned, or the material added on top of the substrate can remain unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0023] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer may extend over the entirety of an undercoat or overcoat structure, or may have a width smaller than that of the undercoat or overcoat structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may lie between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers. For example, an interconnect layer may comprise one or more conductor and contact layers (where interconnects, and / or via contacts are formed) and one or more dielectric layers.

[0024] As used herein, the term "nominal" refers to the expected or target value of a characteristic or parameter for component or process operation set during the design phase of a product or process, together with a range of values ​​above and / or below the expected value. The range of values ​​can be attributed to tolerances or slight variations in the manufacturing process. As used herein, the term "approximately" indicates a given quantity value that can vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "approximately" can indicate that the value of a given quantity can vary within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0025] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (hereinafter referred to as "memory strings," such as NAND memory strings) on a laterally oriented substrate, such that the memory strings extend in a direction perpendicular to the substrate. As used herein, the term "vertical" means nominally orthogonal to the lateral surface of the substrate.

[0026] As used herein, the terms “step,” “staircase,” and “horizontal surface” may be used interchangeably. As used herein, a stepped structure refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. “Step” refers to a vertical displacement in height of a set of adjacent surfaces.

[0027] As used herein, the x-axis and y-axis (orthogonal to the xy-plane) extend horizontally to form a horizontal plane. This horizontal plane is substantially parallel to the top surface of the substrate. As used herein, the z-axis extends vertically, i.e., along a direction orthogonal to the horizontal plane. The terms "x-axis" and "y-axis" are interchangeable with "lateral direction," "horizontal direction," etc., the term "xy-plane" is interchangeable with "horizontal plane," etc., and the term "z-axis" is interchangeable with "vertical direction," etc.

[0028] In 3D memory devices, data operations such as reading, writing, and erasing involve the transfer of data through the source and drain electrodes of the memory cell. Memory cells, formed by the intersection of semiconductor channels and gate electrodes, share source contact structures (e.g., array common source or "ACS") distributed between adjacent semiconductor channels. The source contact structures are typically made of one or more conductive materials and extend perpendicularly from the surface of the substrate to which the source lines are to be connected, typically above the highest surface of the memory stack (single or multiple).

[0029] With the increasing demand for higher storage capacity for data storage, 3D storage devices employ a vertically arranged, increased number of memory cells to increase storage density. Obtaining more memory cells vertically typically involves increasing the number of vertically oriented memory cells within the storage stack. These approaches can introduce several problems with the source contact structure. For example, the increased height of the source contact structure vertically can lead to increased stress in the conductive material (e.g., tungsten) of the source contact structure, affecting the material quality. Furthermore, with the increased amount of conductive material used in the source contact structure, some conductive materials (e.g., polysilicon) can cause increased resistance in the source contact structure, impacting device performance. Therefore, improvements to the source contact structure are needed.

[0030] Various embodiments of this disclosure provide structures and methods for manufacturing 3D memory devices that address the aforementioned problems associated with stress and conductivity of source contact structures. For example, the source contact structure of a 3D memory device includes multiple metal source contacts (e.g., tungsten), each insulated from each other by a dielectric layer in a vertical direction. Separate source contacts in the dielectric layer (rather than a monolithic structure) reduce stress on the metal material. The stress of the dielectric layer can be flexibly controlled and adjusted to maintain low net stress and desired material quality in the source contact structure. Furthermore, a sufficiently low resistivity source conductor is formed at the bottom of the source contact structure. The source conductor contacts the multiple source contacts and the substrate and comprises a silicide material. The source conductor couples the common source of the channel structure of the 3D memory device to the source contact structure. In some embodiments, the multiple source contacts are formed using the same process as forming word line contacts that contact the gate electrode.

[0031] Figure 1A A cross-sectional view of a 3D storage device according to some embodiments is illustrated. Figure 1B Example Figure 1A The top view of the 3D storage device is shown in the image. Figures 2-5A Examples are shown in the formation Figure 1A and 1B The image shows different stages of the manufacturing process of a 3D memory device, and a cross-sectional view of the 3D memory device. Figure 5B Example Figure 5A The top view of the 3D storage device is shown in the image. Figure 6 Example of forming Figure 1- Figure 5B An exemplary manufacturing process 600 for a 3D memory device is shown. For ease of illustration, the memory stack, as an example, has a stepped structure. Multiple stacked stepped 3D memory devices can also be formed using the structures and methods of this disclosure in the same or similar manner.

[0032] like Figure 1AAs shown, a 3D memory device (or “memory structure”) 100 may include a memory stack on a substrate 102. The memory stack 124 may include a stepped structure having a plurality of interleaved conductor layers 120-1 (e.g., gate electrodes) and insulating layers 120-2 stacked vertically on the substrate 102. The memory stack 124 may be an insulating stack 125 and may include a plurality of channel structures 108 (e.g., semiconductor channels) extending vertically through the memory stack 124 into the substrate 102. The channel structure 108 may include a barrier layer 108-1, a memory layer 108-2, a tunneling layer 108-3, a semiconductor layer 108-4, and a dielectric core 108-5. The memory device 100 may include, for example, a doped semiconductor portion 110 at the bottom of the channel structure 108 in the substrate 102. The memory stack 124 may also include source contact structures 130, which include a plurality of source contacts 116 in the dielectric layer 118. The memory device 100 may also include source conductors 106 in contact with the plurality of source contacts 116 and the substrate. The memory device 100 may also include a first contact 112 on each source contact 116, a second contact 114-1 on each channel structure 108, and a third contact 114-2 on each second contact 114-1. The substrate 102 may also include a doped semiconductor region 104 under the memory stack 124 and a plurality of doped semiconductor portions 110 in the doped semiconductor region 104. Each doped semiconductor portion 110 may be under a corresponding channel structure 108. For ease of illustration, the memory stack 124 is divided into an array region 126-1 and a stepped region 126-2. A memory cell formed at the intersection of conductor layer 120-1 and channel structure 108 can be formed in array region 126-1. Word line contact portion 122 can be formed in step region 126-2. As described below. Figure 1A Details of each element are shown in the image.

[0033] The substrate 102 may comprise silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), and / or any other suitable material. In some embodiments, the substrate 102 comprises silicon.

[0034] In some embodiments, substrate 102 includes a doped semiconductor region 104 (e.g., a well layer). The doped semiconductor region 104 may be located beneath memory stack 124 (e.g., beneath channel structure 108 and source contact structure 130). The doped semiconductor region 104 may comprise elemental semiconductor materials such as single-crystal silicon, compound semiconductor materials, organic semiconductor materials, and / or other semiconductor materials. For example, the doped semiconductor region 104 can comprise doped single-crystal silicon formed by a suitable deposition process and / or ion implantation process.

[0035] The memory stack 124 may include a plurality of interleaved semiconductor layers 120-1 and insulating layers 120-2 stacked vertically on a substrate 120. The memory stack 124 may have: a stepped structure formed in stepped regions 126-2; and memory cells formed in array regions 126-1. In some embodiments, each conductor layer 120-1 and its corresponding / underlying insulating layer 120-2 form a step. The insulating layers 120-2 may insulate the conductor layers 120-1 from each other. The conductor layers 120-1 and the insulating layers 120-2 may both have the same thickness (e.g., vertically) or a different thickness than the other layers. The conductor layers 120-1 may contain conductive materials, including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicides, or any combination thereof. The insulating layer 120-2 may contain a dielectric material, including, but not limited to, silicon oxide (SiO), silicon nitride (SiN), and / or silicon oxynitride (SiON). In some embodiments, the conductor layer 120-1 contains a metal such as W, and the insulating layer 120-2 contains SiO.

[0036] In some embodiments, the storage stack 124 is formed by repeatedly etching a dielectric stack of multiple interleaved insulating and sacrificial material layers (e.g., multiple insulating / sacrificial material layer pairs) vertically stacked on substrate 102 to form multiple interleaved insulating and sacrificial layers, and replacing the sacrificial layers with a suitable conductive material. The dielectric stack can be formed by using any suitable deposition process, such as alternating deposition of multiple insulating and sacrificial material layers, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or low-pressure CVD (LPCVD). After the formation of the insulating and sacrificial layers, the sacrificial layer can be removed, and the desired conductive material can be deposited into the space created by the removal of the sacrificial layer to form conductor layer 120-1. The sacrificial layer can be removed by any suitable etching process, such as dry etching and / or wet etching. The deposition of conductor layer 120-1 can include any suitable deposition process, such as CVD, PVD, and / or ALD. The number of insulating / sacrificial layer pairs in the storage stack 124 can be any suitable number such as 32, 64, 96, or 128. The sacrificial layer can contain any suitable material different from the insulating layer. In some embodiments, the sacrificial layer contains SiN.

[0037] In some embodiments, the formation of the memory stack 124 can include: repeatedly etching / refining an etch mask (e.g., a photoresist layer) over the dielectric stack to expose portions of the insulating / sacrificial layer pair to be etched; and etching / removing the exposed portions using a suitable etching process. The etching of the etch mask and the insulating / sacrificial layer pair can be performed using any suitable etching process, such as wet etching and / or dry etching. In some embodiments, the etching includes dry etching, such as inductively coupled plasma (ICP) and / or reactive ion etching (RIE).

[0038] The channel structure 108 may include a barrier layer 108-1, a storage layer 108-2, a tunneling layer 108-3, a semiconductor layer 108-4, and a dielectric core 108-5. The channel structure 108 can be formed by forming channel vias through the storage stack 124 to expose the substrate 102. The location of each channel via corresponds to the location of the corresponding channel structure. The barrier layer 108-1 can reduce or prevent charge escape into the subsequently formed gate electrode. The barrier layer 108-1 can comprise a single-layer or multi-layer structure. For example, the barrier layer 108-1 can comprise a first barrier layer and a second barrier layer. The first barrier layer can be formed on the surface of the channel via using any suitable conformal deposition method. The first barrier layer can comprise a dielectric material (e.g., a dielectric metal oxide). For example, the first barrier layer can comprise a dielectric metal oxide having a sufficiently high dielectric constant (e.g., greater than 7.9). Examples of the first barrier layer include AlO, hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), their silicates, their nitrogen-doped compounds, and / or alloys thereof. The first barrier layer can be formed by suitable deposition methods such as CVD, ALD, pulsed laser deposition (PLD), and / or liquid-source atomized chemical deposition. In some embodiments, the first barrier layer comprises AlO.

[0039] The second barrier layer can be formed on top of the first barrier layer and can contain a different dielectric material than the first barrier layer. For example, the second barrier layer can contain SiO, SiON, and / or SiN. In some embodiments, the second barrier layer contains SiO, which can be formed by any suitable conformal deposition method such as LPCVD and / or ALD.

[0040] The storage layer 108-2 can contain a charge-trapping material and can be formed on top of the barrier layer 108-1. The storage layer 108-2 can have a single-layer or multi-layer structure. For example, the storage layer 108-2 can contain conductive materials and / or semiconductors, such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, their alloys, their nanoparticles, their silicides, and / or polycrystalline silicon or amorphous semiconductor materials (e.g., polycrystalline silicon and amorphous silicon). The storage layer 108-2 can also contain one or more insulating materials such as SiN and / or SiON. In some embodiments, the storage layer 108-2 contains a SiN layer sandwiched between SiON layers, which is further sandwiched between SiN layers. The storage layer 108-2 can be formed by any suitable deposition method such as CVD, ALD, and PVD.

[0041] The tunneling layer 108-3 may contain a dielectric material through which tunneling can occur under suitable bias. The tunneling layer 108-3 may be formed on the storage layer 108-2 and may contain a single-layer or multi-layer structure, and may contain SiO, SiN, SiON, dielectric metal oxides, dielectric metal nitrides, dielectric metal silicates, and / or alloys thereof. The tunneling layer 108-3 may be formed by a suitable deposition method such as CVD, ALD, and / or PVD. In some embodiments, the tunneling layer 108-3 comprises a plurality of SiON layers and SiO layers, wherein the plurality of SiON layers are located between the storage layer 108-2 and the SiO layers.

[0042] Semiconductor layer 108-4 facilitates charge transport and can be formed on top of tunneling layer 108-3. Semiconductor layer 108-4 can comprise one or more semiconductor materials, such as an elemental semiconductor material, III-V compound semiconductor material, II-VI compound semiconductor material, and / or organic semiconductor material. Semiconductor layer 108-4 can be formed by any suitable deposition method such as LPCVD, ALD, and / or metal-organic chemical vapor deposition (MOCVD). In some embodiments, semiconductor layer 108-4 comprises a polycrystalline silicon layer.

[0043] The dielectric core 108-5 can contain a suitable dielectric material and fill the space surrounded by the semiconductor layer 108-4. In some embodiments, the dielectric core 108-5 contains SiO (e.g., SiO of sufficiently high purity) and can be formed by any suitable deposition method such as CVD, LPCVD, ALD, and / or PVD.

[0044] The doped semiconductor portion 110 may include a doped semiconductor material (e.g., a doped semiconductor region 104) formed in the substrate 102 to promote electrical coupling between the source contact structure 130 and the common source of the channel structure 108. The doped semiconductor portion 110 may include a doped semiconductor material formed by epitaxial growth and / or ion implantation. For example, the doped semiconductor portion 110 may include doped single-crystal silicon formed by epitaxial growth.

[0045] Second contacts 114-1 may be formed on the channel structure 108, and third contacts 114-2 may be formed on the corresponding second contacts 114-1. In some embodiments, the dimension (e.g., diameter or width) of the second contact 114-1 along the horizontal plane is larger than the dimension of the corresponding third contact 114-2 and smaller than the dimension of the corresponding channel structure 108, so that the channel structure 108 can be coupled to the corresponding bit line in a subsequent process. In some embodiments, the second contact 114-1 comprises polysilicon, and the third contact 114-2 comprises a metallic material such as aluminum, copper, tungsten, and / or cobalt. First contacts 112 may comprise a suitable conductive material and may be formed on the corresponding source contacts 116 to facilitate electrical coupling between the source contacts 116 and the corresponding source line. In some embodiments, the dimension of the first contact 112 along the horizontal plane is smaller than the dimension of the source contacts 116 along the horizontal plane. In some embodiments, the first contact 112 and the third contact 114-2 comprise the same metallic material such as tungsten. In some embodiments, the first contact portion 112, the second contact portion 114-1, and the third contact portion 114-2 are formed by a suitable deposition process such as CVD, PVD, and / or ALD followed by a patterning process (e.g., photolithography).

[0046] In some embodiments, word line contacts 122 are formed in an insulating stack 125 and comprise a suitable conductive material, such as one or more of tungsten, copper, aluminum, cobalt, and polysilicon. Word line contacts 122 can be formed by filling openings in the insulating stack 125 with the desired conductive material (e.g., exposing the corresponding conductor layer 120-1). In some embodiments, word line contacts 122 are formed using the same manufacturing process as forming a plurality of source contacts 116 and can comprise the same conductive material as the plurality of source contacts 116. The insulating stack 125 can comprise any suitable dielectric material such as SiO.

[0047] In some embodiments, the source contact structure 130 extends vertically through the memory stack 124 into the substrate 102. The source contact structure 130 may also extend laterally, for example, along the y-direction (e.g., orthogonal to the xz plane). In some embodiments, the source contact structure 130 includes a plurality of source contacts 116 and a dielectric layer 118. The plurality of source contacts 116 may be arranged along the direction in which the source contact structure 130 extends. The plurality of source contacts 116 may be located within the dielectric layer 118, such that the dielectric layer 118 insulates each source contact 116 above the substrate 102 from each other. The source contacts 116 may have any suitable shape and may be arranged in any suitable pattern. For example, the source contacts 116 may be arranged in an array and may all have a pillar shape with nominally identical dimensions. The number of source contacts 116 arranged along the x-direction and / or y-direction may be determined based on, for example, the dimensions of the source contact structure 130, the dimensions of the source contacts 116, and / or design rule requirements. Figure 1B Example Figure 1A The top view of the storage structure is shown in the image.

[0048] like Figure 1B As shown, the source contact structure 130 can extend laterally (e.g., along the y-axis and parallel to the xy-plane) between the first portion 151-1 and the second portion 151-2 of the storage stack 124. The array region 126-1 can be surrounded by the stepped region 126-2. For illustrative purposes, Figure 1BFeatures in the stepped region 126-2 are not shown. The channel structure 108 may be located in the first portion 151-1 and the second portion 151-2 of the memory stack 124. A plurality of source contacts 116 may be arranged in an array within the dielectric layer 118 and may extend vertically through the memory stack 124 and laterally within the memory stack 124 to divide the memory stack 124 into the first portions 151-1 and 151-2. For example, the array may include at least one source contact 116 arranged along the x-axis and more than one source contact 116 arranged along the y-axis. In some embodiments, the distance D between the centers of two adjacent source contacts can be in the range of approximately 250 nm to approximately 1.4 μm, such as from 250 nm to 1.4 μm (e.g., 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, any range defined by the lower end of any of these values, or any range defined by any two of these values). In some embodiments, the size (e.g., diameter d) of each source contact 116 may be in the range of approximately 80 nm to approximately 150 nm, such as from 80 nm to 150 nm (e.g., 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, any range defined by the lower end of any of these values, or any range defined by any two of these values). In some embodiments, the diameter d of each source contact 116 is approximately 120 nm, such as 120 nm. It should be noted that the first portion 151-1 and the second portion 151-2 described herein are merely examples of the structure and / or location of the source contact structure 130. Other structures, such as other source contact structures 130, may also be formed in the first portion 151-1 and the second portion 151-2 of the memory stack 124, but for simplicity, such other structures are omitted herein.

[0049] The source contact 116 may comprise any suitable conductive material such as aluminum, tungsten, cobalt, and / or copper. In some embodiments, the source contact 116 comprises tungsten. The dielectric layer 118 may comprise any suitable dielectric material that insulates the source contacts 116 from each other and from the conductor layer 120-1. For example, the dielectric layer 118 may comprise SiO, SiN, and / or SiON. In some embodiments, the dielectric layer 118 comprises SiO.

[0050] The stress of the dielectric layer 118 (e.g., made of SiO) can be controlled and / or adjusted to ensure that the source contact structure 130 has low net stress and / or the source contact portion 116 has low stress. For example, the stress of the dielectric layer 118 can be controlled and / or adjusted by, for example, controlling the ratio of the total volume of the source contact portion 116 to the total volume of the source contact structure 130, controlling the composition of SiO (e.g., the ratio of the number of silicon atoms to the number of oxygen atoms in the SiO molecule), and / or controlling the formation / deposition conditions for forming SiO. In some embodiments, the ratio of the total volume of the plurality of source contacts 116 to the total volume of the source contact structure 130 is in the range of about 30% to about 70%, such as from 30% to 70% (e.g., 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, any range defined by the lower end of any of these values, or in any range defined by any two of these values).

[0051] Return to reference Figure 1A In some embodiments, the source contact structure 130 also includes a source conductor 106 at the bottom of the source contact structure 130. The source conductor 106 may contact a plurality of source contacts 116 and the substrate 102. In some embodiments, at least a portion of the source conductor 106 is located in the substrate 102. The source conductor 106 may have a sufficiently low resistivity and may facilitate electrical coupling between the source contact structure 130 (or source contacts 116) and the common source of the channel structure 108. In some embodiments, the substrate 102 comprises silicon, and the source conductor 106 comprises a silicide layer. For example, the source conductor 106 may comprise one or more of the following: tungsten silicide, titanium silicide, nickel silicide, sodium silicide, platinum silicide, magnesium silicide, and molybdenum silicide. The source conductor 106 may be formed by a self-aligned process. For example, one or more desired metals may be deposited between the first portion 151-1 and the second portion 151-2 to react with the substrate 102 (e.g., silicon) and form a silicide. The process for forming the source conductor 106 may include performing one or more of CVD, PVD, ALD, and sputtering of a desired metallic material on the substrate 102, followed by thermal reaction and / or annealing.

[0052] Based on Figure 2-6 The formation of the storage device 100 is described. (Refer to...) Figure 6 At the beginning of the manufacturing process, a gap opening is formed in the memory stack to expose a portion of the substrate beneath the memory stack (operation 602). Figure 2 A cross-sectional view of the corresponding structure 200 is shown as an example.

[0053] like Figure 2As shown, a gap opening 218 may be formed in the memory stack 224 to expose a portion of the substrate 202 beneath the memory stack 224. In some embodiments, the memory stack 224 includes a stepped structure within an initial insulating stack 225. The stepped structure may include a plurality of interleaved conductor layers 220-1 and an insulating layer 220-2 stacked on the substrate 202. The memory stack 224 may include a plurality of channel structures 208, each of which has a barrier layer 208-1, a memory layer 208-2, a tunneling layer 208-3, a semiconductor layer 208-4, and a dielectric core 208-5. The memory stack 224 may include a plurality of second contacts 214-1, each formed on a respective channel structure 208. The substrate 202 may include a doped semiconductor region 204 beneath the memory stack 224 and a plurality of doped semiconductor portions 210, each beneath a respective channel structure 208. The initial insulating stack 225 may comprise a suitable dielectric material such as SiO, SiN, and / or SiON, and may be formed by any suitable deposition process such as CVD, PVD, LPCVD, and / or ALD. In some embodiments, the initial insulating stack 225 comprises SiO formed by CVD. The storage stack 224 may be divided into array regions 226-1 and stepped regions 226-2. In some embodiments, the substrate 202, conductor layer 220-1, insulating layer 220-2, channel structure 208, array region 126-1, step region 126-2, first portion 151-1 and second portion 151-2 of the storage stack 124, and second contact portion 214-1 may be the same as or similar to the substrate 102, conductor layer 120-1, insulating layer 120-2, channel structure 108, array region 226-1, step region 226-2, first portion 251-1 and second portion 251-2 of the storage stack 124, and second contact portion 114-1. A detailed description of these elements can be found in [reference needed]. Figure 1A and Figure 1B The description is given, and will not be repeated here.

[0054] A slot opening 218 may be formed between a first portion 251-1 and a second portion 251-2 of the memory stack 224. The pattern and location of the slot opening 218 may correspond to the pattern and location of a subsequently formed source contact structure (e.g., source contact structure 130). The slot opening 218 may extend vertically through the memory stack 224 into the substrate 202 and laterally to divide the memory stack 224 into the first portion 251-1 and the second portion 251-2. A portion of the substrate 202 (or the doped semiconductor region 204) may be exposed at the bottom of the slot opening 218. In some embodiments, the slot opening 218 is a gate line slot of the memory stack 224.

[0055] The slot opening 218 can be formed by any suitable process, such as forming a patterned etch mask over the memory stack 224 to expose portions of the memory stack 224; and etching the exposed portions of the memory stack 224 to expose the substrate 202 to form the slot opening 218. Any suitable etching process can be employed. In some embodiments, dry etching (e.g., inductively coupled plasma (ICP) etching and / or reactive ion etching (RIE)) is performed to form the slot opening 218.

[0056] Return to reference Figure 6 After the slot opening is formed, a source conductor is formed on the substrate at the bottom of the slot opening (operation 604). Figure 3 A cross-sectional view of the corresponding structure 300 is shown as an example.

[0057] like Figure 3 As shown, a source conductor 306 can be formed on substrate 202 at the bottom of the slot opening 218. In some embodiments, the source conductor 306 comprises a self-aligned silicide layer and is similar to or the same as source conductor 106. A detailed description of the structure and formation of the source conductor 306 can be found in [reference needed]. Figure 1A The description is as described above and will not be repeated here.

[0058] Return to reference Figure 6 After the source conductor is formed, a dielectric material is deposited to fill the gap opening and form an initial dielectric layer (operation 606). Figure 4 The example corresponds to the cross-sectional view of structure 400.

[0059] like Figure 6 As shown, a dielectric material is deposited to fill the slot opening 218 and form an initial dielectric layer 418. The initial dielectric layer 418 may cover the source conductor 306. The initial dielectric layer 418 may contain the same dielectric material as the insulating stack 225 or may contain a different dielectric material than the insulating stack 225. In some embodiments, the initial dielectric layer 418 and the insulating stack 225 contain the same material, such as SiO. The initial dielectric layer 418 may be formed by any suitable deposition process such as CVD, PVD, LPCVD, and / or ALD. Optionally, after depositing the dielectric material, a planarization process (e.g., chemical mechanical polishing (CMP) and / or recess etching) is performed to remove any excess dielectric material on the initial dielectric layer 418.

[0060] Return to reference Figure 6After the initial dielectric layer is formed, multiple source contacts can be formed through the initial dielectric layer and multiple word line contacts can be formed through the initial insulating stack. The multiple source contacts are in contact with the source conductor (operation 608). Figure 5A The example corresponds to the cross-sectional view of structure 500.

[0061] like Figure 5A As shown, a plurality of source contacts 516 may be formed through the initial dielectric layer 418, and a plurality of word line contacts 522 may be formed through the initial insulating stack 225. A dielectric layer 518 and an insulating stack 525 may be formed. The plurality of source contacts 516 may contact the source conductor 306. In some embodiments, the plurality of source contacts 516 and the plurality of word line contacts 522 are the same as or similar to the plurality of source contacts 116 and the plurality of word line contacts 122, respectively. Detailed descriptions of the plurality of source contacts 516 and the plurality of word line contacts 522 can be found in the descriptions of the plurality of word line contacts 122 and the plurality of source contacts 116, respectively, and will not be repeated here. Similarly, detailed descriptions of the dielectric layer 518 and the insulating stack 525 can be found in the descriptions of the dielectric layer 118 and the insulating stack 125, respectively, and will not be repeated here.

[0062] In some embodiments, the initial dielectric layer 418 and the initial insulating stack 225 comprise the same dielectric material, such as SiO, and can be formed using the same fabrication process to create a plurality of source contacts 516 and a plurality of word line contacts 522. In some embodiments, a patterned etch mask can be formed over the memory stack 224 to expose portions of the initial dielectric layer 418 and portions of the initial insulating stack 225. Suitable etching processes (e.g., dry etching), such as ICP etching and / or RIE, can be performed to form openings (e.g., an array of openings) in the initial dielectric layer 418 and the initial insulating stack 225 to expose the source conductor 306 and the conductor layer 220-1, respectively. Suitable deposition processes, such as CVD, PVD, sputtering, and / or ALD, can then be performed to deposit the same conductive material into the openings and form the plurality of source contacts 516 and the plurality of word line contacts 522, respectively. Optionally, a planarization process (e.g., CMP and / or recessed etching) can be performed to remove any excess conductive material on top of the memory stack 224.

[0063] In some embodiments, the initial dielectric layer 418 and the initial insulating stack 225 comprise different dielectric materials. The patterning of the initial dielectric layer 418 and the initial insulating stack 225 can be performed separately, thereby enabling separate control of the etching of the different dielectric materials to obtain their optimized etching results. The plurality of source contacts 516 and the plurality of word line contacts 522 can also be filled with different conductive materials, for example, through separate deposition processes. The specific materials and manufacturing processes for forming the source contacts 516 and word line contacts 522 should be determined based on the different 3D memory devices and / or manufacturing requirements, and should not be limited to the embodiments of this disclosure.

[0064] Figure 5B Example Figure 5A The top view of structure 500 is shown. In some embodiments, a plurality of source contacts 516 are arranged in an array in a dielectric layer 518 between a first portion 551-1 and a second portion 551-2 of the memory stack 224. The plurality of source contacts 516 may extend laterally along the xy plane. The first portion 551-1 and the second portion 551-2 of the memory stack 224 are the same as or similar to the first portion 151-1 and the second portion 151-2 of the memory stack 124, respectively. A detailed description of the first portion 551-1 and the second portion 551-2 of the memory stack 224 can be referred to, respectively, the description of the first portion 151-1 and the second portion 151-2 of the memory stack 124, and will not be repeated here.

[0065] Return to reference Figure 6 After forming multiple source contacts and multiple word line contacts, a corresponding contact is formed on each channel structure and each source contact (operation 610). Figure 1A and Figure 1B Example storage device 100 (e.g., the final structure formed by process 600).

[0066] If you return to the reference Figure 1A and Figure 1B Contact portions (e.g., first contact portion 112 and third contact portion 114-2) may be formed on each contact portion 116 (e.g., the same as or similar to source contact portion 516) and each second contact portion 114-1 (e.g., the same as or similar to second contact portion 214-1), respectively. Detailed descriptions of the first contact portion 112 and the third contact portion 114-2 can be found in [reference needed]. Figure 1A The description is as described above and will not be repeated here.

[0067] It should be noted that in some embodiments, the order in which the channel structure, conductor layer, and source contact structure are formed can be varied. For example, the source contact structure may be formed, for instance, in a dielectric stack before the channel structure and / or conductor layer. Also, the second contact portion on the channel structure may be formed after the source contact structure and before the third contact portion. The specific order in which these structures are formed should be determined based on the manufacturing process and should not be limited to the embodiments of this disclosure.

[0068] In some embodiments, a memory device includes: a memory stack having a plurality of interleaved conductor layers and insulating layers extending over a substrate; a channel structure, each extending vertically through the memory stack into the substrate; and a source contact structure extending vertically through the memory stack and laterally to divide the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts electrically coupled to a common source of the plurality of channel structures.

[0069] In some embodiments, each of the plurality of source contacts comprises at least one of the following: aluminum, tungsten, cobalt, or copper.

[0070] In some embodiments, each of the plurality of source contacts contains tungsten.

[0071] In some embodiments, the source contact structure further includes a dielectric layer between the first portion and the second portion of the memory stack, and the dielectric layer insulates the plurality of source contacts from the first portion and the second portion of the memory stack.

[0072] In some embodiments, the dielectric layer comprises at least one of the following: silicon oxide, silicon nitride, or silicon oxynitride.

[0073] In some embodiments, the dielectric layer comprises silicon oxide.

[0074] In some embodiments, the source contact structure further includes a source conductor that contacts the plurality of source contacts and the substrate.

[0075] In some embodiments, the substrate comprises silicon, and the source conductor comprises a silicide layer.

[0076] In some embodiments, the plurality of source contacts are arranged in an array on the source conductor.

[0077] In some embodiments, the ratio of the total volume of the plurality of source contacts to the total volume of the source contact structure is in the range of about 30% to about 70%.

[0078] In some embodiments, the distance between the centers of two adjacent source contacts ranges from about 250 nm to about 1.4 μm.

[0079] In some embodiments, the diameter of each of the plurality of source contacts is in the range of approximately 80 nm to approximately 150 nm.

[0080] In some embodiments, the diameter of each of the plurality of source contacts is approximately 120 nm.

[0081] In some embodiments, the memory device further includes a doped semiconductor region in the substrate beneath the plurality of channel structures and the source conductor, and a doped semiconductor portion in the doped semiconductor region beneath each of the plurality of channel structures. The doped semiconductor portion may be electrically coupled to the source conductor via the doped semiconductor region.

[0082] In some embodiments, the storage device further includes a first contact portion on each of the plurality of source contacts.

[0083] In some embodiments, the storage device further includes a second contact portion on each of the plurality of channel structures and a third contact portion on the second contact portion.

[0084] In some embodiments, a memory device includes: a memory stack having a plurality of interleaved conductor layers and an insulating layer extending over a substrate; a plurality of channel structures, each extending perpendicularly through the memory stack into the substrate; and a source contact structure extending perpendicularly through the memory stack and laterally to divide the memory stack into a first portion and a second portion. The source contact structure may include a plurality of source contacts in a dielectric layer and insulated from each other through the dielectric layer; and each of the plurality of source contacts is electrically coupled to a common source of the plurality of channel structures.

[0085] In some embodiments, each of the plurality of source contacts comprises at least one of the following: aluminum, tungsten, cobalt, or copper.

[0086] In some embodiments, each of the plurality of source contacts contains tungsten.

[0087] In some embodiments, the dielectric layer comprises at least one of the following: silicon oxide, silicon nitride, or silicon oxynitride.

[0088] In some embodiments, the dielectric layer comprises silicon oxide.

[0089] In some embodiments, the source contact structure further includes a source conductor that contacts the plurality of source contacts and the substrate.

[0090] In some embodiments, the substrate comprises silicon, and the source conductor comprises a silicide layer.

[0091] In some embodiments, the ratio of the total volume of the plurality of source contacts to the total volume of the source contact structure is in the range of about 30% to about 70%.

[0092] In some embodiments, the distance between the centers of two adjacent source contacts ranges from about 250 nm to about 1.4 μm.

[0093] In some embodiments, the diameter of each of the plurality of source contacts is in the range of approximately 80 nm to approximately 150 nm.

[0094] In some embodiments, the diameter of each of the plurality of source contacts is approximately 120 nm.

[0095] In some embodiments, the memory device further includes a doped semiconductor region in the substrate beneath the plurality of channel structures and the source conductor, and a doped semiconductor portion in the doped semiconductor region beneath each of the plurality of channel structures. The doped semiconductor portion may be electrically coupled to the source conductor via the doped semiconductor region.

[0096] In some embodiments, the storage device further includes: a first contact portion on each of the plurality of source contacts; and a second contact portion on each of the plurality of channel structures and a third contact portion on the second contact portion.

[0097] In some embodiments, a method for forming a memory device includes: forming a plurality of channel structures, each of the plurality of channel structures extending vertically through a memory stack into a substrate; and forming a source contact structure, the source contact structure extending vertically through the memory stack and laterally extending to divide the memory stack into a first portion and a second portion. Forming the source contact structure may include forming a plurality of source contact portions electrically coupled to a common source of the plurality of channel structures.

[0098] In some embodiments, forming the plurality of source contacts includes forming a slot opening that extends vertically through the memory stack and laterally to divide the memory stack into a first portion and a second portion and expose the substrate between the first portion and the second portion of the memory stack. Forming the plurality of source contacts may also include filling the slot opening with an initial dielectric layer and forming the plurality of source contacts in the initial dielectric layer between the first portion and the second portion of the memory stack.

[0099] In some embodiments, the method further includes forming a source conductor that contacts the substrate at the bottom of the gap opening between the plurality of source contacts and the first and second portions of the storage stack.

[0100] In some embodiments, forming the source conductor includes forming a self-aligned silicide layer on the substrate.

[0101] In some embodiments, forming the self-aligned silicide layer includes performing one or more of the following to form the self-aligned silicide layer: chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, thermal reaction, and annealing.

[0102] In some embodiments, filling the gap opening with the initial dielectric layer comprises: depositing an insulating material to cover the source conductor and fill the gap opening; and planarizing the top surface of the insulating material.

[0103] In some embodiments, depositing the insulating material comprises depositing silicon oxide to fill the gap opening.

[0104] In some embodiments, forming the plurality of source contacts in the initial dielectric layer includes an array of source contacts formed on and in contact with the source conductor.

[0105] In some embodiments, the array forming the source contacts comprises: an array of openings formed in the initial dielectric layer to expose the source conductor; and an array of conductive materials deposited to fill the openings.

[0106] In some embodiments, the method further includes: forming an initial insulating stack on the substrate, such that the storage stack is located within the initial insulating stack; and forming a plurality of interleaved conductor layers and insulating layers within the storage stack. The plurality of interleaved conductor layers and insulating layers may extend on the substrate. The method may further include forming a plurality of word line contacts and the insulating stack using the same manufacturing process used to form the plurality of source contacts. The plurality of word line contacts may extend vertically within the initial insulating stack and contact the plurality of conductor layers.

[0107] In some embodiments, forming the plurality of word line contacts and the insulating stack comprises: forming a plurality of other openings extending vertically in the initial insulating stack by the same manufacturing process used to form the plurality of openings in the initial dielectric layer; and filling the plurality of other openings by the same deposition process used to fill the plurality of openings in the initial dielectric layer.

[0108] In some embodiments, the method further includes forming a first contact portion on each of the plurality of source contacts.

[0109] In some embodiments, the method further includes forming a second contact portion on each of the plurality of channel structures and forming a third contact portion on the second contact portion. The formation of the second contact portion may include forming a polysilicon portion on each of the plurality of channel structures. The formation of the third contact portion may include forming a conductive material using the same manufacturing process as that used to form the first contact portion.

[0110] In some embodiments, the method further includes forming a doped semiconductor region in the substrate. The doped semiconductor region may be located beneath the plurality of channel structures and the plurality of source contacts. The method further includes forming a doped semiconductor portion at the bottom of each of the plurality of channel structures in the doped semiconductor region, such that the plurality of channel structures are electrically connected to the plurality of source contacts.

[0111] In some embodiments, a method for forming a memory device includes: forming a plurality of channel structures extending vertically through a memory stack into a substrate; and forming source contact structures extending vertically through the memory stack and laterally to divide the memory stack into a first portion and a second portion. Forming the source contact structures may include forming a plurality of source contact portions on a source conductor. Each of the plurality of source contact portions may be electrically coupled to a common source of the plurality of channel structures.

[0112] In some embodiments, forming the plurality of source contacts over the source conductors includes: forming a slot opening that extends vertically through the memory stack and laterally to divide the memory stack into a first portion and a second portion and expose the substrate between the first and second portions of the memory stack; and forming the source conductor at the bottom of the slot opening. The source contacts may be at least partially in the substrate and electrically coupled to the plurality of channel structures. The forming further includes: filling the slot opening with an initial dielectric layer over the source conductors; and forming the plurality of source contacts in the initial dielectric layer that contact the source conductor between the first and second portions of the memory stack.

[0113] In some embodiments, forming the source conductor includes forming a self-aligned silicide layer on the substrate.

[0114] In some embodiments, forming the self-aligned silicide layer at the bottom of the slit opening comprises performing one or more of the following to form the self-aligned silicide layer: chemical vapor deposition, physical vapor deposition, sputtering, thermal reaction, and annealing.

[0115] In some embodiments, filling the gap opening with the initial dielectric layer comprises: depositing at least one of silicon oxide, silicon nitride, and silicon oxynitride to cover the source conductor and fill the gap opening; and planarizing the top surface of the at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0116] In some embodiments, forming the plurality of source contacts in the initial dielectric layer includes an array of source contacts formed on and in contact with the source conductor.

[0117] In some embodiments, the array forming the source contacts comprises: an array of openings formed in the initial dielectric layer to expose the source conductor; and an array of conductive materials deposited to fill the openings.

[0118] In some embodiments, the method further includes: forming an initial insulating stack on the substrate, such that the storage stack is located within the insulating stack; and forming a plurality of interleaved conductor layers and insulating layers within the storage stack. The plurality of interleaved conductor layers and insulating layers may extend on the substrate. The method further includes forming a plurality of word line contacts and the insulating stack using the same manufacturing process used to form the plurality of source contacts. The plurality of word line contacts may extend vertically within the initial insulating stack, and the plurality of word line contacts may contact the plurality of conductor layers.

[0119] In some embodiments, forming the plurality of word line contacts and the insulating stack comprises: forming a plurality of other openings extending vertically in the initial insulating stack by the same manufacturing process used to form the plurality of openings in the initial dielectric layer; and filling the plurality of other openings by the same deposition process used to fill the plurality of openings in the initial dielectric layer.

[0120] In some embodiments, the method further includes forming a first contact portion on each of the plurality of source contacts.

[0121] In some embodiments, the method further includes forming a second contact portion on each of the plurality of channel structures and forming a third contact portion on the second contact portion. The formation of the second contact portion may include forming a polysilicon portion on each of the plurality of channel structures. The formation of the third contact portion includes forming a conductive material using the same manufacturing process as that used to form the first contact portion.

[0122] In some embodiments, the method further includes: forming a doped semiconductor region in the substrate, the doped semiconductor region being below the plurality of channel structures and the plurality of source contacts; and forming a doped semiconductor portion at the bottom of each of the plurality of channel structures in the doped semiconductor region, such that the plurality of channel structures are electrically connected to the plurality of source contacts.

[0123] The foregoing description of specific embodiments will so fully disclose the overall characteristics of this disclosure that others, by applying the knowledge of those skilled in the art, can readily modify and / or adapt various applications of that specific embodiment without undue experimentation, without departing from the overall concept of this disclosure. Therefore, based on the teachings and guidance stated herein, it is intended that such adaptations and modifications be in the equivalent meaning and scope of the disclosed embodiments. It should be understood that the wording and terminology herein are for descriptive purposes and not for limitation, and that the terminology or terminology of this specification should be interpreted by those skilled in the art based on the teachings and guidance.

[0124] The embodiments of this disclosure have been described above with the aid of examples of functional building blocks that implement specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are suitably performed.

[0125] The summary and abstract section may set forth one or more, but not all, exemplary embodiments of this disclosure conceived by the inventors(s), and is not intended to limit this disclosure and the appended claims in any way.

[0126] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A storage device, comprising: Storage stack comprising multiple interleaved conductor layers and insulating layers extending over a substrate; Multiple channel structures extend vertically through the memory stack into the substrate, and each of the multiple channel structures includes a barrier layer, a memory layer, a tunneling layer, a semiconductor layer, and a dielectric core. as well as A source contact structure extends vertically through the memory stack and laterally to divide the memory stack into a first part and a second part. The source contact structure includes multiple source contact portions, each electrically coupled to a common source of the multiple channel structures. The source contact structure further includes a source conductor that contacts the plurality of source contact portions and the substrate. The source contact structure further includes a dielectric layer between the first portion and the second portion of the memory stack, and the dielectric layer insulates the plurality of source contacts from the first portion and the second portion of the memory stack. The ratio of the total volume of the plurality of source contacts to the total volume of the source contact structure is in the range of 30% to 70%, and The plurality of source contacts are arranged in an array consisting of multiple rows and multiple columns on the source conductor.

2. The storage device as claimed in claim 1, wherein, Each of the plurality of source contacts includes at least one of the following: aluminum, tungsten, cobalt, or copper.

3. The storage device as claimed in claim 2, wherein, Each of the plurality of source electrode contacts comprises tungsten.

4. The storage device as claimed in claim 1, wherein, The dielectric layer includes at least one of the following: silicon oxide, silicon nitride, or silicon oxynitride.

5. The storage device as claimed in claim 4, wherein, The dielectric layer comprises silicon oxide.

6. The storage device as claimed in claim 1, wherein, The substrate comprises silicon, and the source conductor comprises a silicide layer.

7. The storage device according to any one of claims 1-3, wherein, The distance between the centers of two adjacent source contacts ranges from 250 nm to 1.4 µm.

8. The storage device according to any one of claims 1-3, wherein, The diameter of each of the plurality of source contacts is in the range of 80 nm to 150 nm.

9. The storage device as claimed in claim 8, wherein, The diameter of each of the plurality of source contacts is 120 nm.

10. The memory device of claim 1, further comprising a doped semiconductor region in the substrate beneath the plurality of channel structures and the source conductor, and a doped semiconductor portion in the doped semiconductor region beneath each of the plurality of channel structures, the doped semiconductor portion being electrically coupled to the source conductor via the doped semiconductor region.

11. The storage device according to any one of claims 1-3, further comprising a first contact portion on each of the plurality of source contacts.

12. The storage device according to any one of claims 1-3, further comprising a second contact portion on each of the plurality of channel structures and a third contact portion on the second contact portion.

13. A storage device comprising: Storage stack comprising multiple interleaved conductor layers and insulating layers extending over a substrate; Multiple channel structures extend vertically through the memory stack into the substrate, and each of the multiple channel structures includes a barrier layer, a memory layer, a tunneling layer, a semiconductor layer, and a dielectric core. as well as A source contact structure extends vertically through the memory stack and laterally to divide the memory stack into a first part and a second part, wherein: The source contact structure includes a plurality of source contacts and a dielectric layer, wherein the plurality of source contacts are located in the dielectric layer and are insulated from each other by the dielectric layer; and Each of the plurality of source contacts is electrically coupled to the common source of the plurality of channel structures. The source contact structure further includes a source conductor that contacts the plurality of source contact portions and the substrate. The dielectric layer is located between the first and second portions of the memory stack, and insulates the plurality of source contacts from the first and second portions of the memory stack. The ratio of the total volume of the plurality of source contacts to the total volume of the source contact structure is in the range of 30% to 70%, and The plurality of source contacts are arranged in an array consisting of multiple rows and multiple columns on the source conductor.

14. The storage device of claim 13, wherein, Each of the plurality of source contacts includes at least one of the following: aluminum, tungsten, cobalt, or copper.

15. The storage device of claim 14, wherein, Each of the plurality of source electrode contacts comprises tungsten.

16. The storage device according to any one of claims 13-15, wherein, The dielectric layer includes at least one of the following: silicon oxide, silicon nitride, or silicon oxynitride.

17. The storage device of claim 16, wherein, The dielectric layer comprises silicon oxide.

18. The storage device of claim 13, wherein, The substrate comprises silicon, and the source conductor comprises a silicide layer.

19. The storage device according to any one of claims 13-15, wherein, The distance between the centers of two adjacent source contacts ranges from 250 nm to 1.4 µm.

20. The storage device according to any one of claims 13-15, wherein, The diameter of each of the plurality of source contacts is in the range of 80 nm to 150 nm.

21. The storage device of claim 20, wherein, The diameter of each of the plurality of source contacts is 120 nm.

22. The memory device of claim 13, further comprising a doped semiconductor region in the substrate beneath the plurality of channel structures and the source conductor, and a doped semiconductor portion in the doped semiconductor region beneath each of the plurality of channel structures, the doped semiconductor portion being electrically coupled to the source conductor via the doped semiconductor region.

23. The storage device according to any one of claims 13-15, further comprising: The first contact portion above each of the plurality of source contact portions; as well as The second contact portion and the third contact portion are located on each of the plurality of channel structures.

24. A method for forming a storage device, comprising: Multiple channel structures are formed, each of which extends vertically through the memory stack into the substrate. Each of the multiple channel structures includes a barrier layer, a memory layer, a tunneling layer, a semiconductor layer, and a dielectric core. A source contact structure is formed, the source contact structure extending vertically through the memory stack and laterally to divide the memory stack into a first part and a second part, wherein forming the source contact structure includes forming a plurality of source contact portions, each of the plurality of source contact portions being electrically coupled to a common source of the plurality of channel structures; and A source conductor is formed that contacts the substrate at the bottom of the gap opening between the first and second portions of the storage stack, and the plurality of source contacts. The plurality of source contact portions include: The slot opening is formed, extending vertically through the storage stack and laterally to divide the storage stack into a first portion and a second portion and expose the substrate between the first portion and the second portion of the storage stack; The gap opening is filled with an initial dielectric layer; and The plurality of source contacts are formed in the initial dielectric layer between the first portion and the second portion of the storage stack. The ratio of the total volume of the plurality of source contacts to the total volume of the source contact structure is in the range of 30% to 70%, and The plurality of source contacts are arranged in an array consisting of multiple rows and multiple columns on the source conductor.

25. The method of claim 24, wherein, Forming the source conductor includes forming a self-aligned silicide layer on the substrate.

26. The method of claim 25, wherein, Forming the self-aligned silicide layer includes performing one or more of the following to form the self-aligned silicide layer: chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, thermal reaction, and annealing.

27. The method of claim 26, wherein, Filling the gap opening with the initial dielectric layer includes: Deposit insulating material to cover the source conductor and fill the gap opening; and The top surface of the insulating material is planarized.

28. The method of claim 27, wherein, Depositing the insulating material includes depositing silicon oxide to fill the gap opening.

29. The method according to any one of claims 24-28, wherein, The formation of the plurality of source contacts in the initial dielectric layer includes an array of source contacts formed on and in contact with the source conductor.

30. The method of claim 29, wherein, The array forming the source contact portion includes: An array of openings is formed in the initial dielectric layer to expose the source conductor; and An array of conductive materials is deposited to fill the openings.

31. The method of claim 30, further comprising: An initial insulating stack is formed on the substrate, thereby the storage stack is located within the initial insulating stack; In the storage stack, a plurality of interleaved conductor layers and a plurality of insulating layers are formed, the plurality of interleaved conductor layers and the plurality of insulating layers extending over the substrate; as well as Multiple word line contacts and an insulating stack are formed using the same manufacturing process that forms the multiple source contacts. The multiple word line contacts extend vertically in the initial insulating stack and contact the multiple conductor layers.

32. The method of claim 31, wherein, The plurality of word line contacts and the insulating stack include: A plurality of other openings extending vertically in the initial insulating stack are formed using the same manufacturing process that forms the array of openings in the initial dielectric layer; and The plurality of other openings are filled using the same deposition process that fills the array of openings in the initial dielectric layer.

33. The method of any one of claims 24-28, further comprising forming a first contact portion on each of the plurality of source contacts.

34. The method of claim 33, further comprising forming a second contact portion on each of the plurality of channel structures and forming a third contact portion on the second contact portion, wherein: The formation of the second contact portion includes forming a polysilicon portion over each of the plurality of channel structures; as well as The formation of the third contact portion includes forming a conductive material using the same manufacturing process as that used to form the first contact portion.

35. The method of any one of claims 24-28, further comprising: A doped semiconductor region is formed in the substrate, the doped semiconductor region being beneath the plurality of channel structures and the plurality of source contacts; as well as A doped semiconductor portion is formed at the bottom of each of the plurality of channel structures in the doped semiconductor region, thereby electrically connecting the plurality of channel structures to the plurality of source contacts.

36. A method for forming a storage device, comprising: Multiple channel structures are formed, the multiple channel structures extending vertically through the memory stack into the substrate, each of the multiple channel structures including a barrier layer, a memory layer, a tunneling layer, a semiconductor layer, and a dielectric core; as well as A source contact structure is formed, the source contact structure extending vertically through the memory stack and laterally to divide the memory stack into a first part and a second part, wherein forming the source contact structure includes forming a plurality of source contact portions on the source conductor, each of the plurality of source contact portions being electrically coupled to a common source of the plurality of channel structures. The formation of the plurality of source contact portions on the source conductor includes: A slot opening is formed, which extends vertically through the storage stack and laterally to divide the storage stack into a first portion and a second portion and expose the substrate between the first portion and the second portion of the storage stack; The source conductor is formed at the bottom of the slot opening, and the source contact is at least partially in the substrate and electrically coupled to the plurality of channel structures; The gap opening is filled with an initial dielectric layer above the source conductor; and The plurality of source contacts are formed in the initial dielectric layer to contact the source conductor between the first portion and the second portion of the memory stack. The ratio of the total volume of the plurality of source contacts to the total volume of the source contact structure is in the range of 30% to 70%, and The plurality of source contacts are arranged in an array consisting of multiple rows and multiple columns on the source conductor.

37. The method of claim 36, wherein, Forming the source conductor includes forming a self-aligned silicide layer on the substrate.

38. The method of claim 37, wherein, Forming the self-aligned silicide layer at the bottom of the slit opening includes performing one or more of the following to form the self-aligned silicide layer: chemical vapor deposition, physical vapor deposition, sputtering, thermal reaction, and annealing.

39. The method of claim 38, wherein, Filling the gap opening with the initial dielectric layer includes: Depositing at least one of silicon oxide, silicon nitride, and silicon oxynitride to cover the source conductor and fill the gap opening; and The top surface of at least one of silicon oxide, silicon nitride, and silicon oxynitride is planarized.

40. The method of claim 36, wherein, The formation of the plurality of source contacts in the initial dielectric layer includes an array of source contacts formed on and in contact with the source conductor.

41. The method of claim 40, wherein, The array forming the source contact portion includes: An array of openings is formed in the initial dielectric layer to expose the source conductor; and An array of conductive materials is deposited to fill the openings.

42. The method of claim 41, further comprising: An initial insulating stack is formed on the substrate, such that the storage stack is located within the insulating stack; In the storage stack, a plurality of interleaved conductor layers and a plurality of insulating layers are formed, the plurality of interleaved conductor layers and the plurality of insulating layers extending over the substrate; as well as Multiple word line contacts and an insulating stack are formed using the same manufacturing process that forms the multiple source contacts. The multiple word line contacts extend vertically in the initial insulating stack and contact the multiple conductor layers.

43. The method of claim 42, wherein, The plurality of word line contacts and the insulating stack include: A plurality of other openings extending vertically in the initial insulating stack are formed using the same manufacturing process that forms the array of openings in the initial dielectric layer; and The plurality of other openings are filled using the same deposition process that fills the array of openings in the initial dielectric layer.

44. The method of any one of claims 36-43, further comprising forming a first contact portion on each of the plurality of source contacts.

45. The method of claim 44, further comprising forming a second contact portion on each of the plurality of channel structures and forming a third contact portion on the second contact portion, wherein: The formation of the second contact portion includes forming a polysilicon portion over each of the plurality of channel structures; as well as The formation of the third contact portion includes forming a conductive material using the same manufacturing process as that used to form the first contact portion.

46. ​​The method of any one of claims 36-43, further comprising: A doped semiconductor region is formed in the substrate, the doped semiconductor region being beneath the plurality of channel structures and the plurality of source contacts; as well as A doped semiconductor portion is formed at the bottom of each of the plurality of channel structures in the doped semiconductor region, thereby electrically connecting the plurality of channel structures to the plurality of source contacts.

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