Cache Dynamic Random Access Memory

Abstract

A dynamic random access memory having columns, data rows, tag rows and comparators is disclosed. Each comparator compares address bits with tag information bits from a tag row to determine a cache hit and generate address bits to access data information in a DRAM as a multi-way set associative cache.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to and claims priority to U.S. Provisional Application No. 62 / 680,738, entitled “CACHE DYNAMIC RANDOM ACCESS MEMORY,” filed on June 5, 2018, U.S. Provisional Application No. 62 / 777,639, entitled “CACHE DYNAMIC RANDOM ACCESS MEMORY,” filed on December 10, 2018, and U.S. Provisional Application No. 62 / 842,244, entitled “CACHE DYNAMIC RANDOM ACCESS MEMORY,” filed on May 2, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to a cache dynamic random access memory. Background Art

[0004] Dynamic random access memory (DRAM) is used as system memory in a variety of computers and computing devices. Now that DRAM scaling is slowing, storage class memory (SCM) and DRAM with reduced costs will be very useful to continue to increase memory system capacity. Hybrid memory systems that combine SCM with DRAM cache may be useful because SCM has longer latency and limited endurance compared to DRAM. Summary of the invention

[0005] The present application relates to a cache dynamic random access memory.

[0006] In a first aspect, an embodiment of the present application provides a dynamic random access memory DRAM, comprising: a plurality of columns, a plurality of data rows, and a plurality of tag rows; a communication interface for receiving a first set of address bits from a memory controller; a plurality of comparators, each of the plurality of comparators being used to: compare the first set of address bits with a first set of tag information bits from a plurality of tag rows to generate a cache hit indication and a plurality of set bits; and compare the plurality of set bits with the address bits based on a cache hit to generate a second set of address bits, the second set of address bits to be used to access cache data in the DRAM as a multi-way set associative cache in a plurality of storage bodies of the DRAM.

[0007] In a second aspect, an embodiment of the present application provides a set-associative cache dynamic random access memory DRAM, comprising: a plurality of memory bodies, each memory body comprising a plurality of boards, each board comprising a plurality of DRAM cells arranged in rows and columns; a majority of the rows comprising rows for data as data rows, and a minority of the rows comprising rows for tags as tag rows; a communication interface for receiving a first set of address bits from a memory controller; a plurality of comparators, each of the plurality of comparators being used to: compare the first set of address bits with a first set of tag information bits from a tag row to generate a cache hit indication and a plurality of set bits; and compare the plurality of set bits with the address bits based on a cache hit to generate a second set of address bits, the second set of address bits to be used to access cache data in the DRAM as one of a plurality of paths of a set-associative cache.

[0008] In a third aspect, an embodiment of the present application provides a method for operating a set-associative cache dynamic random access memory DRAM, comprising: presenting, by a memory controller, a plurality of address bits in a set in the DRAM to each of a plurality of comparators in a memory body of the DRAM, wherein each memory body has a data row and a tag row; comparing, in parallel, a plurality of address bits and a first group of tag information bits from the tag row in a plurality of comparators to generate a cache hit indication and a plurality of set bits; comparing, based on a cache hit, a plurality of set bits and address bits to generate a second group of address bits; and reading, by the memory controller, cache data from the data row based on the second group of address bits, wherein the DRAM and the plurality of comparators are arranged on a semiconductor substrate of a single chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0010] Figure 1A An embodiment of a DRAM having data rows and tag rows is shown, which can be used as a multi-way set associative cache or a multi-way set associative cache.

[0011] Figure 1B Shown suitable for Figure 1A The DRAM embodiment version in the separate label sheet (mat) labels.

[0012] Figure 2A Another embodiment of a DRAM having a set of cache data distributed among multiple memory banks is shown.

[0013] Figure 2B Shown suitable for Figure 2A The DRAM embodiment version has data rows and tag rows.

[0014] Figure 2C Shown suitable for Figure 2A A version of the DRAM embodiment in which distributed tags are used.

[0015] Figure 3A Circuitry and addressing for cache hits and accesses to data of a set that has been cached in a way of a multi-way set associative cache in one embodiment is shown.

[0016] Figure 3B The use of set bits from tag data in column decode to access cache data pointed to by a matching tag is shown.

[0017] Figure 3C The address space in the SCM and DRAM for accessing the data of the SCM cached in a multi-way set associative cache DRAM is shown according to one embodiment.

[0018] Figure 4A is a diagram showing read timing details for normal access to data and modified access to cached data in one embodiment.

[0019] Figure 4B Shows the use of Figure 4A The read timing shown reads cache data from one of the memory banks of the multi-way set associative cache DRAM, while more cache data is read from the other memory banks in parallel.

[0020] Figure 5A is a write timing detail showing normal access to data and modified access to cached data in one embodiment.

[0021] Figure 5B Shows the use of Figure 5A The write timing shown writes cache data to one of the banks of the multi-way set associative cache DRAM, while more cache data is written to the other banks in parallel.

[0022] Figure 6 Shown are DRAM cells and sense amplifiers in a board that may be used in embodiments of a DRAM.

[0023] Figure 7 A mode register is shown for selecting standard DRAM mode or multi-way set associative cache mode, where the bit lengths of tags and comparators are adjustable.

[0024] Fig. 8A is a flow chart of a method of operating a multi-way set associative DRAM cache, which may be practiced by various embodiments described herein.

[0025] Figure 8B is a flow chart for selecting an operating mode, which may be practiced by various embodiments described herein.

[0026] Fig. 9 An embodiment of a multi-way set associative DRAM cache is depicted.

[0027] Fig.10 Another embodiment of a multi-way set associative DRAM cache is depicted.

[0028] Fig.11 A DRAM according to the present embodiment and a memory controller that can use the DRAM as a multi-way set associative DRAM cache are depicted.

[0029] Fig.12 Depicted is a stack of dies connected by through silicon vias for a multi-chip package of a DRAM device having independently selectable layers of DRAM and DRAM cache in accordance with the present embodiment.

[0030] Fig.13 Depicted Fig.12 A version of the die stack with a cache layer, DRAM layer, and mixed-mode logic on the base layer.

[0031] Fig.14 Describes the embodiment according to the present invention Fig. 9 A multi-way set-associative DRAM cache version in which Fig.12 and Fig.13 Circuit systems are arranged on the DRAM layer and the base layer of the die stack. DETAILED DESCRIPTION

[0032] In the following description, various aspects of the illustrative embodiments will be described using terms commonly used by those skilled in the art to convey the essence of their work to other persons skilled in the art. For illustrative purposes, specific numbers, materials, and configurations are set forth to provide a thorough understanding of the illustrative embodiments. However, it will be clear to those skilled in the art that the present disclosure may be practiced using only some of the described aspects or without specific details. In other cases, well-known features have been omitted or simplified so as not to make the illustrative embodiments unclear.

[0033] The DRAM architecture modifications described herein enable tag storage and comparison, as well as access to cached data, to be performed on DRAM. In some versions, DRAM can be used as a multi-way set associative cache, and can also be used as standard DRAM, for example, if not part of a hybrid system with storage class memory or other memory. Data sets from storage class memory or other memory can be cached in the DRAM cache through some path, and accessed when the tag comparison indicates a cache hit.

[0034] In a typical system, circuitry external to the DRAM die performs tag matching. Using standard DRAM components as cache in a hybrid memory system includes transferring the tag information bits from the DRAM to the chip that does the tag matching before the data information on the DRAM can be accessed. This creates both latency and power overheads compared to modifying the DRAM to implement tag matching on the DRAM, as described herein.

[0035] Various embodiments of DRAM caches have some or all of the following features.

[0036] Transfers to and from storage class memory (SCM) are typically done using very large block sizes. This results in a much smaller tag to data ratio than conventional caches, allowing DRAM modifications to be made to the cache with little overhead. Various embodiments of DRAMs having data rows and tag rows and data plane rows and tag plane rows are described in detail below. Figures 1A to 4B , and other embodiments with other arrangements of data rows, label rows, data plate rows, and label plate rows are readily contemplated for various ratios of labels to data.

[0037] DRAM caches are organized as set associative caches. In a set associative cache, data sets from storage class memory can be cached in sets and cached in cache memory in any of a number of ways or locations within the set. Multiplying the total number of statistics by the total number of paths in each set gives the total number of lines in the cache memory. Each path and each set maps to a line. When a data set is cached, a tag is matched to a portion of the address of the data set and points to the set and the path or location in the cache so that the tagged cached data set can be read from the cache. The tags associate the data set with the set and the path or location in the cache memory, hence the name of this type of cache. The amount of data that can be cached for the data set, the number of sets, and the number of ways or locations that can cache that number (usually denoted as N) determine the amount of cache memory for an N-way set associative cache and the number of address bits used in total and per tag.

[0038] Tag storage in DRAM is accomplished by adding additional rows of cells distributed across an existing board or by adding boards. A board (whether a data board with data rows, a tag board with tag rows, or a board with both data and tag rows) is a group of DRAM cells with a defined height (number of cells or rows) and width (number of cells or columns). Each DRAM cell has a transistor (usually NMOS or N-type metal oxide semiconductor) and a capacitor. Various embodiments of boards refer to Figures 1A to 6 , and other arrangements of DRAM cells and boards are readily contemplated.

[0039] Associating the tag rows with data rows that do not share a main sense amplifier avoids the need to double the sense amplifier stripes and saves area. In some embodiments, a tag row in a plate with one sense amplifier is associated with and points to a data location elsewhere in the DRAM with another sense amplifier. This supports timing overlap of tag reads by the sense amplifiers for the tag rows, and timing overlap of data reads by the sense amplifiers for the data locations associated with the tag rows, as shown in the timing details of Figures 4 and 5. If the tag rows and associated data locations were in the same plate, such timing overlap would require doubling the sense amplifiers.

[0040] The labels of different paths in the set are in one row. The label hit activation matches the label of a path in this row, as shown in the reference Figure 3A This feature supports comparison blocks, one for each tag and tag match, to be combined together in a logical "OR" configuration for use Figure 3A Compact circuitry in the comparison block shown.

[0041] Tag comparison is done only with column accesses. The tags for all paths for a particular set are in the same row and are compared with the address bits in parallel between column accesses of the tag data for that row, as Figure 3A and Figure 3B shown.

[0042] Parallel access at the memory bank edges is used to maximize parallel tag comparisons. Tags are compared at the edge of each memory bank so that multiple tag comparisons can be performed in parallel across multiple memory banks. Then, in some embodiments, for example, Figures 1A to 2C As shown, cache data is accessed in parallel in multiple memory banks.

[0043] Addressing a set uses device, bank, and row addresses. Data from a storage class memory can be cached in one of N ways or locations, in one of a set, in an N-way associative cache. The address of the set includes the device address, bank address, and row address decoded by address decoding.

[0044] The internal address bus is used to allocate the set address, the comparison value, and the address determined by the tag match in DRAM. See for example Fig. 9 , Fig. 9 The cache logic and multiplexing for row decoding and column decoding used to assign addresses to memory banks in DRAM are shown.

[0045] The internal data bus outside the array and the DQ pins are for data only. See e.g. Fig. 9 , Fig. 9 Internal data from the memory banks in the DRAM to the data logic is shown. Addresses and data are not mixed or multiplexed on the data bus.

[0046] Figure 1A An embodiment of a DRAM having data plane rows 104 (each having multiple data lines) and tag plane rows 106 (each having multiple tag lines for tag information bits) that can be used as a multi-way set associative cache is shown. In this example, each bank 102 of the DRAM is an array of 32 planes 108 by 64 planes 108 of DRAM, and each plane 108 is an array or subarray of 512 bits by 512 bits (see Figure 6 ), for a total of 256 kilobits (kb) per plate 108. There are 8 banks 102 in each channel A and B of DRAM 0, and 8 banks 102 in each channel C and D of DRAM 1, for a total of 32 banks 102. The DRAM can perform 64-byte read or write accesses to a 4-kilobit (kB) DRAM block (cache line). In this example, the tags in the tag row of 32 plates 108 forming the tag plate row 106 at the bottom (or at the top in other embodiments) of the bank 102 occupy approximately 1.6% additional memory cell area.

[0047] DRAM bank 102 consists of a matrix block array (sub-array) containing memory cells and row / column peripheral logic. Data lines connect bank 102 to the interface block. One row of unmodified boards provides enough capacity and bandwidth (BW) for a tag.

[0048] Figure 1B Shown suitable for Figure 1AThe DRAM embodiment of the embodiment of the present invention is shown in FIG. 1 . The tag read bit determines whether cache data or tag data is read during a read operation. If the tag read bit is 1, the data of the tag in the tag plate 112 is read. If the tag read bit is 0, the cache data is read from the data plate 110.

[0049] In various embodiments, including for example Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 2C The tags shown can be read using accesses similar to normal accesses (no tag matching, direct access from the memory controller to the row address to be activated). In some embodiments, there needs to be additional address space to signal tag accesses instead of normal accesses. Internally, this can be set by the tag read bit, such as Figure 1B As shown for the labels in individual panels 112, or distributed among the panels, such as Figure 2B and Figure 2C There are several options for doing this:

[0050] 1. When the DRAM is in cache mode, the bit assignments that decode the series of bits sent over the CA bus are modified to have an additional state that signals a tag access.

[0051] 2. When the DRAM is in cache mode and there is a bidirectional signal (such as DMI) for transferring additional information, this signal can be used to switch between cache access and tag read.

[0052] 3. The Mode Register Set (MRS) switches between cache access and tag read.

[0053] Figure 2A Another embodiment of a DRAM having cache data of a set distributed among multiple banks 202 is shown. In this example, the set is distributed among four banks 202 at 32 kB per bank 202, and each path of the set is allocated 16 bytes per bank 202 in each of the four identical banks 202. Each of the four identical banks 202 has 32 tags. Other sets are distributed among the other banks 202 of the DRAM, four banks 202 per set. The tags in the tags in each of the four banks 202 occupied by the set match the cache data of the paths pointing to the set in each of the four banks 202.

[0054] Figure 2B Shown suitable for Figure 2A204 and tag rows 206 of a version of a DRAM embodiment in FIG. This number and other numbers and arrangements of data rows and tag rows in a DRAM that are readily contemplated by the teachings herein can be used as a multi-way set associative cache. In this example, each bank 202 of the DRAM is an array of 8 plates 208 by 64 plates 208, and each plate 208 is an array or subarray of 512 bits by 1024 bits (see FIG. Figure 6 ), 512kb total per board 208. In this example, each board 208 includes redundant rows at the top and bottom, tag rows next to the upper redundant rows or alternatively next to the lower redundant rows, and normal rows (i.e., data rows), and each set uses 32 rows of data. In various embodiments, the tag row 206 can be at the top, bottom, or elsewhere on the board 208. Various arrangements for tags, redundant, and normal data rows are possible. In some embodiments, tags in the lower half of a segment (or memory bank 202) are assigned to data in the upper half of a segment (or memory bank 202). Tags in the upper half of a segment (or memory bank 202) are assigned to data in the lower half of a segment (or memory bank 202). There are 16 memory banks 202 in each channel A and B of DRAM 0, and 16 memory banks 202 in each channel A and B of DRAM 1. 32 tags in each of the four banks 202 in DRAM 0 can cache 4 times 32 kB sets, with hit data being 4 times 16 bytes.

[0055] Figure 2C Shown suitable for Figure 2A 2. Distributed tags for a version of a DRAM embodiment in FIG. 2. There are normal word lines (shown as solid lines) and tag word lines (shown as dashed lines) in board 210. When the tag read bit is 0, the data of the normal word line can be read. When the tag read bit is 1, the data of the tag word line can be read. In this embodiment, in a given board 210, there can be multiple normal word lines for cache data and a single tag word line for tag data.

[0056] refer to Figure 1A , Figure 1B and FIG. 2A to FIG. 2C , various embodiments have some or all of the following architectural details.

[0057] Optimizing the distribution of data cells corresponding to one way in a multi-way cache (e.g., 64B transactions within a 4kB way) can be based on the trade-off between access speed of tag matching, random data access to a single cell, and access to the entire 4kB block and bank utilization to achieve continuous data flow. For example, Figure 1A A multi-way set associative cache DRAM embodiment in distributes cache data for these ways across all memory banks. Figure 2A A multi-way set associative cache DRAM embodiment in distributes cache data for a given way across only a few memory banks. Figure 1A A version or variant of it may have simultaneous row activations for labels and data, Figure 2A Another version in or a variant thereof may wait until the compare has a match to activate the line for cache data access. Figure 1A A version of the Figure 2A Another version in favors memory bank utilization and continuous flow.

[0058] Associating the way address with the column address allows full overlap of tag row activations and data row activations, but requires accessing more banks or multiple row accesses in the same bank when accessing the full way for fill, e.g., fetch and evict. Fill involves placing data into cache and then finally flushing the dirty data.

[0059] Tags are replicated as needed so that tag matching can be done locally if matching information is needed. Multiple banks each have a copy of the tags for the path to cache data in that bank so that virtually any bank(s) with a tag match can produce the data. See e.g. Figure 2A , Figure 2A Figure 1 shows tag hits in four banks of a multi-way set associative cache DRAM. Each bank has a tag match for a particular way, and the cache data for that way in all four banks is read in parallel. Each bank has data for all the paths of the set, but not the complete data for each path. Figure 1A In , the tags are replicated 32 times (each of the 32 banks has a complete set of duplicate tags), and all cache data for one way is available at one time by accessing the data for one set of ways in all 32 banks in parallel. Figure 2A In , the tags are replicated four times (each of the four banks has a duplicate set of tags, each other set of four banks has a duplicate set of tags, and so on), and these four banks are accessed multiple times to get all the cache data for this way.

[0060] The comparison logic is located near the edge of the array. For example, the comparator and comparison block (see Figure 3) are located along the edge of the array of the board of DRAM cells in the memory bank. Such a location shortens the signal path, thereby keeping the parasitic signal line loading low, for example, reducing resistance and capacitance, and may also reduce the incidence of signal reflections.

[0061] Feedback to the controller (e.g., hit or miss) is done using the available feedback pins (alert (ALERT_n), data mask inversion (DMI), etc.). For example, feedback to the controller can be done using the available pins with DRAM to controller direction and is not required in the case of using the DRAM in its cache mode. An example is the use of the DMI pins in the case of modifying an LPDDR4 DRAM as a cache DRAM (see Fig.11 ), or using the ALERT_n pin in the case of modifying DDR4 DRAM. Another example is using the Error Detection Code (EDC) pin in the case of modifying GDDR5 or GDDR6 DRAM.

[0062] Writing the dirty bit and writing the data can start at the same time. The dirty bit is written along with the tag data, and the data to be cached is written to the location (or path) in the cache memory associated with the tag. If the same bank in DRAM is used for both tag data and cache data, it may take two column cycles to push out the closing of the tag row with one column cycle.

[0063] Redundancy: tag lines can get priority replacement or always be doubled.

[0064] The DRAM is dual-purpose and can be set to a mode in which it is used as a cache DRAM (e.g., a multi-way set associative cache mode) or another mode in which it is used as a standard DRAM (e.g., a standard DRAM mode). An embodiment of a mode register for selecting the standard DRAM mode and the cache DRAM mode is shown in FIG. Figure 7 The mode select controls address multiplexing and data multiplexing, which differ between the two modes.

[0065] If one redundant row per board is assigned as a tag row, it is possible to change the implementation of the peripheral logic only from the standard DRAM design layout. The standard DRAM design layout has multiple redundant rows, and one of the redundant rows can be designated as a tag row without changing the design layout of the board or row arrangement. The peripheral logic can then implement changes to address decoding and data multiplexing, and add comparators and comparison blocks for N-way set associative cache operation for the tag row and the rest of the DRAM.

[0066] In one embodiment, the latest tag match information can be stored on DRAM to allow subsequent accesses in the same path without another comparison. If the cache DRAM is used according to a closed page policy, both the tag and data rows (paths) will be closed after one access. The cache DRAM can also be used according to an open page policy, where the data row (path) remains open after the initial cache hit occurs. In this case, consecutive column commands can be used to access other columns of the open row. An explicit precharge command will close the data row, and the next access will start the tag comparison again.

[0067] The size of the tag and the bits allocated to the address and metadata are configurable. Embodiments of a mode register for selecting the bit length of tags and comparators corresponding to a configurable number of ways of a multi-way set associative cache ... Figure 7 Show and describe.

[0068] One embodiment is a DRAM device supporting cache operations in which cache row tags are maintained in dedicated row storage elements adjacent to associated data row storage elements on separate physical word lines that are accessed by two associated operations. The first operation accesses the data of the tag in the tag match and accesses the data row storage element. The second operation obtains the data of the tag, uses the data to point to the column of data, and then accesses the cache data. These two operations are described in reference to Figure 4A and Figure 5A The timing shown and described overlap. Therefore, for one of the two related operations, the data and cache accesses overlap. See, e.g. Figure 1A In the design, tag and data rows are accessed concurrently, and tag matching activates column decoding for cache data access.

[0069] For the other of the two associated operations, data and cache accesses are non-overlapping. See e.g. Figure 2A This causes the tag match to occur before another line is opened for cache data access.

[0070] One embodiment of a multi-way set associative cache has the following features.

[0071] 2GB cache size. This is the amount of DRAM that can be used to cache data from the storage class memory. Other sizes of cache are readily contemplated for other embodiments.

[0072] Two 8Gb LPDDR4 DRAM dies. In one embodiment, this is the number of dies that can be used for a multi-way set associative cache. Other numbers of dies are readily used for other embodiments.

[0073] 32 ways. This is the number of ways or addressing locations in each set in the cache memory where data from the storage class memory can be cached in a multi-way (now 32 ways for this embodiment) set associative cache. Other numbers of ways are readily used for other embodiments.

[0074] 4kB per way. This is the amount of data that can be cached in each way or each row according to a 32-way or N-way set associative cache. Other amounts of data per way are easily used for other embodiments.

[0075] 64B transaction. This is the amount of data that can be read from or written to each cache memory in each (read or write) transaction. Other amounts of data per transaction are readily available for other embodiments.

[0076] Operation compatible with Low Power Double Data Rate Version 4 (LPDDR4) signaling and timing: one burst with 16b burst length on two 16b channels (32B per channel). In one embodiment, when enabled, standard timing and signaling for LPDDR4 DRAM is used for standard DRAM operation and N-way set associative cache operation. In another embodiment, the DRAM operates as an N-way set associative cache using standard timing and signaling for LPDDR4 DRAM, but is not selectable for standard DRAM operation without N-way set associative cache operation. As will be readily appreciated, other embodiments may use standard timing and signaling for other types of DRAM.

[0077] Addressing including address decoding and address line multiplexing is readily contemplated for the following configuration in one embodiment and other variations in other embodiments.

[0078] 2GB of cache memory is 2 31 Byte = (divided into) 2 5 paths, 2 per path 12 bytes of cache memory and 2 14 Therefore, the 14b set address identifies the set, and the size of the set is 128kB. In a 4kB path, there are 64=2 6 A possible 64B transaction. The 6b offset address identifies the transaction in case of a cache hit.

[0079] For a 1TB SCM size, there are 40b of addresses in the SCM. The matching address in the tag is 40b-14b (number of sets)-12b (way size) = 14b. Adding two status bits will make tag 2B = 16b. The tag storage overhead of 2B for each 4kB of data (each way of a 32-way set associative cache in this example) is very small. Even if the tags are stored in multiple locations in DRAM to facilitate parallel access, the overhead will be well below 1%.

[0080] In one embodiment, addressing including address decoding and address line multiplexing is readily contemplated for the following configurations and variations in other embodiments. 1b addressing of the device, 3b addressing of the bank, and 10b addressing of the row blocks belonging to a set identify a region of 32 1kB rows for each sub-bank. In this embodiment, four sub-banks are used simultaneously.

[0081] There are various possible timings to access cached data depending on how and where the data is cached and design decisions for address multiplexing, bank selection, row decoding and row enabling, column decoding and column enabling. Multiple embodiments can be combined to perform timing in one device. In one embodiment, there is no overlap between tag comparison and access to cached data in DRAM. The address of a set of data that can be cached from main memory (e.g., SCM) is divided into bit fields, and one field (the tag field of the address) is provided to the comparator for tag matching. The tag is read and compared to the tag field. Tag matching generates part of the address for the cached data in DRAM, while the other part of the address of the cache DRAM comes from the address of the data set in main memory. Only after all address bits are available can access be performed in DRAM.

[0082] In other embodiments, for tag matching, there is a full or partial overlap in access to the tag (i.e., the tag row) and access to the cache data in DRAM. Certain address bits of the data set in main memory are used to access the bank select and row enable in the data row of DRAM, in parallel with or immediately after accessing the tag row. The tag match generates a portion of the address for the cache data in DRAM, and a portion of the address is used for column decoding to access the cache data.

[0083] Various embodiments are presented herein with various numbers of tag address bits for comparison, number of paths in a set, number of flag bits, arrangement of address bits for column and row decoding, design and functionality for sense amplifiers, etc. It should be understood that these are examples and other embodiments are readily conceivable therefrom.

[0084] Figure 3A1 shows the circuitry and addressing for cache hits and accesses to data from a set already cached in a way of a multi-way set associative cache in one embodiment. The tag plates are identical to the normal data plates of a memory bank. For example, in the embodiment shown, each plate 108 is an array or subarray of 512 bits by 512 bits (see Figure 6 ), with a total of 256 kilobits (kb) per board. The tag array allows access to a 16kb row from the bank, and to a 256b column from the row. The 256b column contains 16 16b tags 106, each of which can be the physical address A being accessed. P [39:27] field. The tag is accessed using 9 address bits AR[14:6] for row decoding and 6 bits AR[5:0] for column decoding 306. The tags are read and compared in parallel, with each tag access providing 16 bits, 13 of which are presented to comparator 304 in compare block 302 to compare with A. P [39:27] Address field comparison, where the other 3 bits are flag bits (e.g., dirty, valid, parity). Another embodiment may use 14 bits for address comparison, leaving two flag bits. Other numbers of tag bits, address comparison bits, and flag bits are readily contemplated.

[0085] Figure 3B The use of set bits from the tag data in the column decode to access the cache data pointed to by the matching tag is shown. The matching tag 106 is a HIT, and the set number (from 0 to 15) Set[3:0] is passed by the compare block 302 to the column access path of the memory bank, i.e., the column decode 306. In the circuit shown, each compare block 302 is hardwired with the set number N, which is enabled by a hit in that compare block 302 onto the set number bits Set[3:0]. The matching data is then accessed. In various embodiments (e.g., see Figure 1A , Figure 2A , Fig. 9 and Fig.10 ), comparison and data access can occur in multiple memory banks 102 in parallel.

[0086] Figure 3C FIG. 1 shows the address space in the SCM and DRAM for accessing the data of the SCM cached in the multi-way set associative cache DRAM according to one embodiment. In one embodiment, the SCM physical address is a 40-bit A P [39:0], to address SCM 2 40 To access cache data, the 13 most significant bits A P [39:27] is used as a tag field, which generates Set[3:0], which is used for the column address bit A of the cache dataC [5:2]. Block address (15 bits of SCM physical address) A P [26:12] Row address A for cache data R [14:0]. The five most significant bits of the sub-block address of the SCM physical address A P [11:6] is the device address A D [1:0] provides two bits, which are the memory bank address A of the cache data B [2:0] provides 3 bits. The next two bits of the sub-block address of the SCM physical address are the column address A of the cache data. C [1:0] provides the other two bits. Column decode 306 uses address bits A C [5:2] and A C [1:0]. After tag comparison, all sets are available in DRAM cache.

[0087] Figure 4A 4 is a read timing detail showing normal access 402 of data and modified access 404 of cached data in one embodiment. Copies of 4kB blocks in DRAM (cache) are distributed among 32 banks 102 for better performance. In the embodiment shown, the 4kB blocks are composed of plates, and each plate 108 is an array or sub-array of 512 bits by 512 bits (see Figure 6 ), with a total of 256 kilobits (kb) per plane. Other arrangements of banks, blocks, and planes are readily contemplated. Column decoding 306 is described above with reference to Figure 3A The labels in label panel row 106 are as described above with reference to Figure 1A Variations for other embodiments are readily conceivable.

[0088] Figure 4AThe clock signal CK is shown, which is grouped into command / address CA as clock, command and address (controller for DRAM), data bus DQ as data (DRAM used in normal mode), and bank control Bank as internal activity of DRAM (DRAM used in normal mode) for normal (direct) access 402 to read data. Below these are tag activities Tag, which are grouped into bank control Bank as internal activity of DRAM (DRAM used in cache mode), and data bus DQ as data (DRAM used in cache mode) for modified (cached) access 404 to read cache data. According to the bank control, for normal (direct) access 402, there is first activation and readout of the bank, followed by reading and transmission to interface Xface. The Xface in the timing diagram represents the time from when data comes out of the array inside the DRAM to when it appears on the external DQ (read) (for example, Figure 4A ) or from entering the external DQ to appearing in the array (write) (e.g., Figure 5A ) time spent at the location.

[0089] The timing of a normal (direct) read access 402 transfers two columns of data in 41ns, with activation and readout of the memory bank 102 taking 36 clock cycles or 18ns, reading taking 8 clock cycles or 4ns, and then transferring to the interface (xface) taking 8 clock cycles or 4ns. Figure 4A and Figure 5A CA[5:0] is shown as an example of command and address transmission from the controller to the DRAM following the LPDDR4 protocol. If a DRAM of another protocol is modified to be usable as a cache DRAM, these functions can be accomplished using explicit address pins and separate command pins such as RAS, CAS, and WE.

[0090] According to the tag activity, for the modified (cached) access 404, there is first an activation and readout of the tag, followed by a read and comparison of the tag data, where a tag hit or miss is determined. The CA input packet is the same as the modified (cached) access 404 for the normal (direct) access 402. According to the memory bank control, overlapping with this activity, there is an activation and readout of the memory bank, where a tag hit provides the set bits Set[3:0], followed by a data read of the cache data and transmission to the interface Xface. The timing of the modified (cached) read access 404 is 51ns, where the activation and readout of the tag takes the same 36 clock cycles or 18ns as the data read in the normal access 402, followed by a tag comparison taking 12 clock cycles or 6ns. For cache data access, the timing overlaps, where the activation and readout of the bank 102 takes the same 36 clock cycles or 18ns, but the activation and readout of the tag overlaps, followed by the same 8 clock cycles or 4ns for the read, and the same 8 clock cycles or 4ns for the transfer to the interface (Xface). The additional 10ns (total time for access to read cache data) includes 4ns (for column access) and 6ns (for 16b comparison).

[0091] Figure 4B Shows the use of Figure 4A The read timing shown reads cache data from one of the banks of a multi-way set associative cache DRAM, while more cache data is read in parallel from other banks. In one embodiment, to achieve better performance, copies of 4kB data blocks from the SCM are distributed among 32 banks in the DRAM (cache) memory (see, e.g. Figure 1A ). 256 bits of tag data are read in parallel from the memory bank using the selected address bits for plane (and tag row) selection and column decoding 306. In one embodiment, for one of the tags 106, a tag match generates a hit indication (i.e., a cache hit, tag match, or tag hit, see Figure 3A ) and set bits Set[3:0], as well as dirty bits, valid bits, and parity bits. The set bits are combined with the specified address bits to perform column decoding 306, and 256 bits of cache data are read from the memory bank. Similar activities occur between the 32 memory banks of the DRAM, thereby reading 4kB blocks of cache data in parallel. For other embodiments of a multi-way set associative DRAM cache, including Figure 2A The embodiment shown can be easily developed into variants with different number of bits and different addressing and timing schemes.

[0092] Figure 5A5 is a write timing detail showing normal access 502 of data and modified access 504 of cached data in one embodiment. The copies of the 4kB blocks in DRAM (cache) are distributed among 32 banks 102 for better performance. In the embodiment shown, the 4kB blocks are composed of plates, and each plate 108 is an array or subarray of 512 bits by 512 bits (see Figure 6 ), with a total of 256 kilobits (kb) per board. Other arrangements of banks, blocks, and boards are readily contemplated. Other arrangements of banks, blocks, and boards are readily contemplated. Column decoding 306 is as described above with reference to Figure 3A The labels in label panel row 106 are as described above with reference to Figure 1A Variations for other embodiments are readily conceivable.

[0093] Figure 5A The clock signal CK is shown, which is grouped into command / address CA as clock, command and address (controller for DRAM), data bus DQ as data (DRAM used in normal mode), and bank control Bank as internal activity of DRAM (DRAM used in normal mode) for normal (direct) access 502 to write data. Below these are tag activities Tag, which are grouped into bank control Bank as internal activity of DRAM (DRAM used in cache mode), and data bus DQ as data (DRAM used in cache mode) for modified (cached) access 504 to write cache data. According to bank control, for normal (direct) access 502, there is first activation and reading of the bank, followed by transfer to interface Xface, writing, and column access. The timing of normal (direct) write access 502 stores two columns of data within 34ns, the activation and reading of the storage body 102 takes 36 clock cycles or 18ns, one wait cycle, the transfer to the interface (Xface) takes 8 clock cycles or 4ns, the write WR takes 8 clock cycles or 4ns, and the column COL takes 8 clock cycles or 4ns.

[0094] In terms of tag activity, for a modified (cached) access 504, there is first an activation and readout of the tag, followed by a read and comparison of the tag data, where a tag hit or miss is determined. The CA input packet is the same for a normal (direct) access 502 as for a modified (cached) access 504. In terms of bank control, overlapping with this activity, there is an activation and readout of the bank, where a tag hit provides the set bits Set[3:0], followed by a transfer to the interface (Xface), and 2 write cycles for writing the cached data. The Xface in the timing diagram represents the time between when data comes out of the array inside the DRAM and when it appears on the external DQ (read) (e.g., Figure 4A ) or from entering the external DQ to appearing in the array (write) (e.g., Figure 5A ). The second WR in "Bank" of Modified (Cached) Access 504 is for Tag Write WR. There is a difference between the row labeled "Tag" and the row labeled "Bank" above. The "Tag" row shows what happens in the tag logic, i.e., for a WR, the tag needs to be read, compared, and a new tag needs to be prepared with dirty bit etc. The "Bank" row shows what happens in the array. Figure 4A and Figure 5A Both read the tags, but Figure 4A and Figure 5A The "Bank" row does not show a tag that has been read (when reading a tag, this bank is located below the "Activate / Read Bank" block, and the data row is activated and read out at the same time).

[0095] The timing for a modified (cached) write access 504 is 44ns, with the activation and readout of the tag taking the same 36 clock cycles or 18ns as the data read in the normal access 502, followed by a tag read taking 8 clock cycles or 4ns and a tag compare taking 12 clock cycles or 6ns. This is followed immediately by a write wr, which takes 8 clock cycles or 4ns. The tag is read (rd) and (if hit) written back (wr), with the dirty bit set and parity adjusted. The hit or miss status is returned to the controller. If a miss, the 64-byte write and tag write dirty operations are canceled. In some embodiments, the additional 10ns (total time for access to write cache data) includes 4ns for the column access and 6ns for the 16b compare. The 16b tag is written back with its "dirty" flag set - this may increase the tRC of the tag access.

[0096] Figure 5B Shows the use of Figure 5A The write timing shown writes cache data to one of the banks of the multi-way set associative cache DRAM, while more cache data is written to the other banks in parallel. In one embodiment, to achieve better performance, copies of 4kB data blocks from the SCM are distributed among 32 banks in the DRAM (cache) memory (see, e.g. Figure 1A ). 256 bits of tag data are read in parallel from the memory bank using the selected address bits for plane (and tag row) selection and column decoding 306. In one embodiment, for one of the tags 106, a tag match generates a hit indication (i.e., a cache hit, tag match, or tag hit, see Figure 3A) and set bits Set[3:0], as well as dirty bits, valid bits, and parity bits. The set bits are combined with the specified address bits for column decoding 306, and the 256 bits of cache data are written to the memory bank. If a hit is suitable, the newly prepared tag with dirty bits and adjusted parity, etc. will also be written back to the memory bank. Similar activities occur between the 32 memory banks of the DRAM, thereby writing 4kB blocks of cache data in parallel. For other embodiments of multi-way set associative DRAM caches, including Figure 2A The embodiment shown can be easily developed into variants with different number of bits and different addressing and timing schemes.

[0097] Figure 6 DRAM cells 604 and sense amplifiers 608 in a board 602 are shown, which can be used in an embodiment of a DRAM. DRAM cells 604 are arranged in rows 612 and columns 610. Each DRAM cell 604 has a MOSFET and a capacitor that can store charge. The DRAM cell 604 in a given row 612 is activated by the word line 614 used for the row 612, and is read out to the bit line 616 of the column 610 of the DRAM cell 604. All bit lines 616 read out bit line precharge 606 are precharged, and the selected DRAM cell 604 is read out through the sense amplifier 608. The sense amplifier 608 can have other circuit systems. Generally, the sense amplifier will have three functions, namely precharge, readout, and connection with the array data line, and various sense amplifier designs are easily used in various embodiments. It is worth noting that in this design, each board 602 has a sense amplifier 608 specific to the DRAM cell 604 of the board 602. Thus, tag plane rows 106 can be arranged with a set of tags 602 and data rows 104 associated with the tags (i.e., as tag rows) can be arranged with other sets of plates 602 such that each tag and tag plane row 106 is coupled to a read amplifier (i.e., a read amplifier 608 for the set of plates 602 that constitute the tag plane row 106) and the associated data rows are coupled to different read amplifiers (i.e., a read amplifier 608 for the set of plates 602 that constitute the data plane row 104), and access to the tags can overlap with access to the cache data pointed to by the tags.

[0098] In various embodiments, the presence of different paths may avoid sense amplifier conflicts. Figure 1A and Figure 1BIt is possible to have tag and data planes adjacent to each other, so they may only need to have doubled sense amplifier stripes at that boundary, anywhere else in the bank. Figure 2 and other possible embodiments do not require doubling of the usual interleaved sense amplifiers, because they are constructed in a way that tags are never adjacent to associated data. Having adjacent planes operating simultaneously in a 6F2 open bitline architecture requires the overhead of a dummy array to provide the supplemental bitlines, and so the overhead is considerable.

[0099] Figure 7 A mode register 702 is shown for selecting a standard DRAM mode or a multiplexed set associative cache mode, wherein the bit length of the tag and comparator is adjustable. One or more mode registers 702 control the address multiplexer (mux) 704, the data multiplexer (mux) 706, and the comparator 304. The address bits used for row decoding and row enabling and column decoding and column enabling in tag access and cache data access, and the number and position of data bits used for tag comparison are selected (see FIG. 3A to FIG. 5B ) is therefore controlled by the address multiplexer 704 and / or the data multiplexer 706 according to the mode selection. In various embodiments, the tag and comparator 304 can have a specified range of bit lengths corresponding to the range of the number of paths of the multi-way set associative cache. The mode register 702 can select the number of bits used for tag comparison or the number of paths in the set. For example, a higher performance solution can be converted from 32-way to 16-way, where the number of sets is twice. The same DRAM can be used as a standard DRAM, compatible with the specified DRAM timing and signaling, and the comparator is disabled, or as a multi-way set associative cache with the comparator enabled, and can even switch back and forth between the two modes. In another embodiment, fuse logic can be used instead of the mode register 702 to enable or select some or all of these features.

[0100] Fig. 8A 1 is a flow chart of a method of operating a multi-way set associative DRAM cache, which can be practiced by various embodiments described herein. For example, hardware, software executed on a processor, firmware, or a combination thereof can be used as shown in FIG. Figure 3A , 4A or the timing and circuit shown in 5A or its variants to perform the Figures 1A to 7 These various actions are performed by accessing cache data in the DRAM as shown in Figure 8 or its variants. In action 802, the tag row of the DRAM is read. The tag rows are read in parallel and can be as shown in Figure 8. Figure 1A and Figure 2A or variations thereof are positioned as shown. Figure 4AAn example of read timing for action 802 for a modified (cached) access 404 is shown in , where the tag activity shows an activate / readout tag followed by a read (rd).

[0101] In act 804, address bits of a set that may be cached in DRAM (e.g., from main memory or SCM) are presented to a comparator. The selection of address bits may be as follows: Figure 7 or Figure 8B or variations thereof. Figure 4A An example of read timing for action 804 for a modified (cached) access 404 is shown in , where the tag activity shows a read (rd) followed by a compare.

[0102] In action 806, the address bits of the set are compared to the data bits (i.e., tag information bits) from the tag row of the DRAM. FIG. 3A to FIG. 5B The comparators shown perform comparisons in parallel between the memory banks of the DRAM. Figure 4A An example of read timing for action 806 for a modified (cached) access 404 is shown in , where the tag activity shows a comparison where a tag hit provides set bits Set[3:0].

[0103] In decision action 808 , it is determined whether there is a cache hit. A cache hit is determined based on the comparison result in action 806 . Figure 4A An example of this timing for a modified (cached) access 404 is shown in , where a comparison is performed to determine whether there is a cache hit or a cache miss. If the answer is no, there is no cache hit and the flow proceeds to action 810 to report a cache miss. If the answer is yes, there is a cache hit and the flow proceeds to action 812.

[0104] In act 812, address bits are generated for a multi-way set associative cache hit. FIG. 3A to FIG. 5B An example is shown showing set bits Set[3:0] showing which way in a multi-way set associative cache has a cache data set.

[0105] In act 814, based on the cache hit, data is read from the data line using the address bits. FIG. 3A to FIG. 5B An example of column decoding for reading cache data is shown. An example of this timing for a modified (cached) access 404 is shown in Figure 4, where after a cache hit, the DQ bits are read onto the DQ bus.

[0106] Figure 8Bis a flow chart for selecting an operating mode, which may be practiced by various embodiments described herein. In act 820, a mode register is written to select either standard DRAM mode or multi-way set associative cache mode, with tags and comparators having selected bit lengths.

[0107] In act 822, address multiplexing, data multiplexing, the bit length of the tag, and the bit length of the comparator are controlled based on the contents of the mode register. Figure 7 An example of a mode register that controls these aspects is shown.

[0108] Fig. 9 An embodiment of a multi-way set associative DRAM cache is depicted. Four banks 902 are shown, each with a row decoder 904. Each bank 902 has a column decoder 906 and a secondary sense amplifier (SA) 908. Each bank 902 also has cache logic 914. This example shows one multiplexer 920 for every two banks 902, but in other embodiments there may be one multiplexer 920 for each bank or any number of banks 902. Internal command and address lines from command / address logic / redriver 916 connect to logic at the edge of the array (for bank control, decoders, and row decoders) from the cache logic or from global command and address logic and redriver 916. Internal data lines 910 connect the secondary sense amplifier 908 to the global data logic and data logic / redriver 918 without connecting to the cache logic 914.

[0109] Fig.10 Another embodiment of a multi-way set associative DRAM cache is depicted. Sense amplifiers 1008 are shared between adjacent plates 1004. Load plates 1002 are required at the edge of the bank. Activating a word line (WL) blocks the word lines that access the shared sense amplifier 1008, for example, WL b blocks both WL a and WL c.

[0110] Options for embodiments of multi-way set associative DRAM caches (see Fig.10 The left side of ) includes the following. Option A) Plate 1 and plate n store tags, plate 1 stores tags for data in plates 2 to n / 2, and plate n stores tags for data in plates n / 2+1 to n-1. Option B) Only plate 1 stores tags, plate 2 is a load plate shared between plates 1 and 3, and data is stored in plates 3 to n. Option C) Tags are distributed as extra rows in all tags, with tags for data in plates 1 to n / 2 located in plates n / 2+1 to n, and tags for data in plates n / 2+1 to n located in plates 1 to n / 2.

[0111] Options for embodiments of multi-way set associative DRAM caches (see Fig.10 Option D) Plane 1 1006 stores tags (i.e., tag plane), Plane 1 1006 has a different wordline count than Planes 1 through n, Plane 1 1006 needs its own load plane with the same wordline count to balance the load (cutting load bitlines and sharing load planes may cause process issues), and data is stored in Planes 1 through n.

[0112] Fig.11 Depicted is a DRAM 1102 and a memory controller 1104 that can operate the DRAM 1102 as a multi-way set associative DRAM cache in accordance with the present embodiment. In some versions, the DRAM 1102 is used as a multi-way set associative DRAM, while in other versions, the DRAM 1102 can be selectively used as a standard DRAM or a multi-way set associative DRAM (e.g., see Figure 7 1104). The signal lines connecting corresponding pins on both DRAM 1102 and memory controller 1104 include CK, CKE, CS, CA, DQ, DQS, and DMI (see DRAM Standards below). In this embodiment, the DMI signal and pin are re-designated for conveying cache information and are labeled DMI / CACHE_INFO.

[0113] One example DRAM standard suitable for embodiments of DRAM 1102 is JEDEC Standard No. 209-4B for LPDDR4 (Low Power Double Data Rate version 4) DRAM, as summarized below. More information may be obtained from the published standard.

[0114] Clock, Input, Symbols CK_t_A, CK_c_A, CK_t_B, CK_c_B. Differential clock input, each channel (A and B) has its own clock pair.

[0115] Clock Enable, input, symbol CKE_A, CKE_B. Each channel (A and B)

[0116] Each has its own clock enable signal.

[0117] Chip select, input, symbol CS_A, CS_B. Each channel (A and B) has its own chip select signal.

[0118] Command / address input, input, symbol CA[5:0]_A, CB[5:0]_B. Each channel (A and B) has its own command / address signal.

[0119] Command / Address On-die Termination Control, Input, Symbols ODT_CA_A, ODT_CA_B. Turns on or off on-die termination of the CA pin.

[0120] Data input / output, EO, symbol DQ[15:0]_A, DQ[15:0]_B. Bidirectional data bus. Each channel (A and B) has its own bus.

[0121] Data strobe, EO, symbol DQS[1:0]_t_A, DQS[1:0]_c_A, DQS[1:

[0122] DQS[0]_t_B, DQS[1:0]_c_B. Bidirectional differential output clock signal used to strobe data during read or write. Each channel (A and B) has its own DQS strobe.

[0123] Data Mask Inversion, EO, symbol DMI[1:0]_A, DMI[1:0]_B. Bidirectional signal indicates when the data on the data bus is inverted or in normal state, or provides write data mask information to the DRAM, depending on the mode register setting for data inversion or data masking. Each channel (A and B) has its own DMI signal.

[0124] Calibrate reference, reference, symbol ZQ. Calibrate output drive strength and termination resistor.

[0125] Power supply, power supply, symbol VDDQ, VDD1, VDD2.

[0126] Ground reference, GND, symbol VSS, VSSQ.

[0127] Reset, input, symbol RESET_n. Active low reset signal.

[0128] Another example DRAM standard suitable for embodiments of DRAM 1102 is JEDEC Standard No. 79-4 for DDR4 (Double Data Rate Version 4) DRAM, which is summarized below. Similar or identically named pins or signals in the LPDDR4 and DDR4 standards perform similar or identical functions. More information can be obtained from the published standards.

[0129] Clock, input, symbols CK_t, CK_c. Differential clock input.

[0130] Clock Enable, Input, Symbol CKE (CKE1). Activates and disables the internal clock signal, device input buffers, and output drivers.

[0131] Chip select, input, symbol CS_n(CS1_n).

[0132] Chip ID, Input, Symbols C0, C1, C2. Select each slice of the stacked assembly. On-die Termination, Input, Symbols ODT (ODT1). Applies to the selected pins for the selected configuration.

[0133] Activation command input, input, symbol ACT_n). Defines the activation command input together with CS_n.

[0134] Command input, input, symbol RAS_n / A16, CAS_n / A15, WE_n / A14. Multi-function pin defines the input command.

[0135] Input Data Mask and Data Bus Inversion, EO, Symbol DM_n / DBI_n / TDQS_t, (DMU_n / DBIU_n), (DML_n / DBIL_n). Input mask signal, or indicator of true or inverted data.

[0136] Bank Group Input, Input, Symbol BG0-BG1. Defines to which bank group an Activate, Read, Write, or Precharge command is applied.

[0137] Bank address input, input, notation BA0-BA1. Defines to which bank an Activate, Read, Write or Precharge command is applied.

[0138] Address Input, Input, Symbols A0-A17. Provides row address for "Activate" command and column address for "Read / Write" command.

[0139] Auto-Precharge, Input, Symbol A10 / AP. Address A10 is sampled during read and write commands to determine auto-precharge.

[0140] Burst Chop, Input, Symbol A12 / BC_n. Address A12 is sampled during a read / write command to determine the burst chop.

[0141] Active low asynchronous reset, input, symbol RESET_n.

[0142] Data In / Out, EO, Symbol DQ. Bidirectional data bus.

[0143] Data strobe, EO, symbol DQS_t, DQS_c, DQSU_t, DQSU_c, DQSL_t, DQSL_c. Output read data, input write data.

[0144] Termination Data Strobe, Output, Symbol TDQS_t, TDQS_c. Enables termination resistor function, data mask function, or data mask inversion, depending on the mode register. Command and Address Parity Input, Input, Symbol PAR. Supports even parity.

[0145] Alert, EO, symbol ALERT_n. Multi-function alert for CRC error, command and address parity error, connection test.

[0146] Connection Test Mode Enable, Input, Symbol TEN. Enables connection test mode operation. Not connected, Symbol NC.

[0147] DQ power supply, power supply, symbol VDDQ.

[0148] DQ ground, power supply, symbol VSSQ.

[0149] Power supply, power supply, symbol VDD.

[0150] Ground, power supply, symbol VSS.

[0151] DRAM activation power supply, power supply, symbol VPP.

[0152] CA reference voltage, power supply, symbol VREFCA.

[0153] Reference pin for ZQ calibration, power supply, symbol ZQ.

[0154] Fig.12 A die stack connected with through silicon vias 1210 of a multi-chip package for a DRAM device having independently selectable layers of DRAM and DRAM cache memory according to the present embodiment is depicted. In various embodiments, each DRAM layer 1202, 1204, 1206 of the multi-die stack has a memory bank of DRAM that is selectable to be used as normal DRAM, such as compatible with DDR4, LPDDR4, HBM (high bandwidth memory), or other DRAM standards, and is also selectable to be used as a DRAM cache, as described herein. The base layer 1208 (which is one of the dies in the stack) controls the DRAM and the cache. For example, the base layer 1208 may select multiple layers, including DRAM layer 1202 to DRAM layer 1204 to be used as DRAM, i.e., the selected (multiple) DRAM layer 1304 (see Fig.13 ), and selects DRAM layer 1206 (and possibly one or more other DRAM layers) to be used as DRAM cache, i.e., selected cache layer(s) 1302 (see Fig.13 ). The packaging details of the die stack are not shown, but are easy to imagine.

[0155] It may be optimal to have base layer 1208 be the lowest die in a die stack in a multi-chip package, but other embodiments may have base layer 1208 at the top or in the middle of a die stack. Other embodiments may have multiple dies attached to and interconnected by a multi-layer substrate in a multi-chip package. Still further, embodiments may have all DRAM layers, base layer circuitry, and interconnects on one die.

[0156] Fig.13 Depicted Fig.12 A version of a die stack with a cache layer 1302, a DRAM layer 1304, and mixed mode logic on a base layer 1208. External data and controls 1310 are connected to the base layer 1208 to read and write (multiple) mode registers 1308, read and write DRAM layers 1304, and read and write cache operations of the cache layer 1302. Internal data and controls 1312 are passed between the base layer 1208 and the selected (multiple) cache layers 1302 and the selected (multiple) DRAM layers 1304. (Multiple) mode registers 1308 select whether a given DRAM layer 1202, 1204, 1206 is used as the selected DRAM layer 1304 or the selected cache layer 1302. These mode registers 1308 can be implemented similarly to other registers and can have control bits and / or flag bits. In another embodiment, the mode registers 1308 are implemented with fuses or are mask programmable during chip manufacturing.

[0157] Fig.14 Describes the embodiment according to the present invention Fig. 9 A multi-way set-associative DRAM cache version in which Fig.12 and Fig.13 Circuitry is arranged on the DRAM layers 1202, 1204, 1206 and base layer 1208 of the die stack. Each DRAM layer 1202, 1204, 1206, which can be used as a selected cache layer 1302 or a selected DRAM layer 1304, has a memory bank 902, a row decoder 904, a column decoder 906, and a secondary sense amplifier 908. The base layer 1208 of the chip stack has a command / address logic / redriver 916, a data logic / redriver 918, a cache logic 914, and a multiplexer 920. The internal command and address lines are connected between the base layer 1208 and the DRAM layers 1202, 1204, 1206 through a set of TSVs 1210 (i.e., through silicon vias 1402). Internal data lines 910 are connected between the base layer 1208 and the DRAM layers 1202 , 1204 , 1206 through another set of TSVs 1210 (ie, through silicon vias 1402 ).

[0158] The above methods, systems and devices can be implemented in a computer system or stored by a computer system. The above methods can also be stored on a non-transitory computer-readable medium. The devices, circuits and systems described herein can be implemented using computer-aided design tools available in the art and can be embodied by computer-readable files containing software descriptions of such circuits. This includes but is not limited to one or more elements of DRAM and its components. These software descriptions can be: behavior, register transfer, logic component, transistor and layout geometry level descriptions. In addition, the software description can be stored on a storage medium or transmitted via a carrier wave.

[0159] Data formats that can implement such descriptions include, but are not limited to, formats that support behavioral languages ​​(such as C), formats that support register transfer level (RTL) languages ​​(such as Verilog and VHDL), formats that support geometric description languages ​​(such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transmission of such files on machine-readable media can be performed electronically over the Internet through various media or, for example, via email. Note that physical files can be implemented on machine-readable media, such as: 4mm tape, 8mm tape, 3-1 / 2 inch floppy disk media, CD, DVD, hard drive, solid state drive (SSD), etc.

[0160] The above description of exemplary embodiments of the present disclosure, including the contents described in the Abstract, is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications may be made within the scope of the present disclosure as will be appreciated by those skilled in the relevant art. Other embodiments may have layers in a different order than the illustrated embodiments, more layers, or fewer layers.

[0161] Furthermore, various operations are described as multiple discrete operations in a manner that is most helpful to understanding the present disclosure, but the order of description should not be construed as implying that these operations are necessarily order-dependent. In particular, these operations do not need to be performed in the order presented.

[0162] As used herein, the terms "above," "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer deposited above, above, or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Also, a layer deposited between two layers may be in direct contact with the two layers, or may have one or more intervening layers. Conversely, a first layer "above" a second layer is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature deposited between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0163] The words "example" or "exemplary" are used herein to mean used as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be interpreted as being more preferred or advantageous than other aspects or designs. On the contrary, the use of the words "example" or "exemplary" is intended to present concepts in a specific way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clearly seen from the context, "X includes A or B" is intended to mean any natural inclusive arrangement. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied in any of the foregoing cases. In addition, the articles "a" and "an" used in this application and the appended claims can generally be interpreted as meaning "one or more", unless otherwise specified or clearly pointed to the singular form from the context. Moreover, unless so described, the use of the terms "embodiment" or "one embodiment" or "embodiment" or "one embodiment" throughout the text is not intended to mean the same embodiment. As used herein, the terms “first,” “second,” “third,” “fourth,” etc. refer to labels for distinguishing between different elements and do not necessarily have ordinal meanings according to their numerical names.

Claims

1. A dynamic random access memory DRAM, the DRAM comprising: Multiple columns, multiple data rows, and multiple label rows; a communication interface for receiving a first set of address bits from a memory controller; A plurality of comparators, each of the plurality of comparators being configured to: comparing the first set of address bits to a first set of tag information bits from the plurality of tag lines to generate a cache hit indication and a plurality of set bits; and The plurality of set bits and address bits are combined based on the cache hit to generate a second set of address bits to be used to access cache data in the DRAM as a multi-way set associative cache in multiple banks of the DRAM. 2 . The DRAM of claim 1 , wherein each of the plurality of boards in each of the plurality of banks has one tag row among the plurality of tag rows. 3 . The DRAM of claim 1 , wherein each of the plurality of memory banks comprises a plurality of data planes and one or more tag planes, each of the one or more tag planes having a tag row to contain the tag information.

4. The DRAM according to claim 1, wherein: The segment of the DRAM has a first tag row in an upper half of the segment, the first tag row being assigned to data in a lower half of the segment; and The segment has a second tag row in the lower half of the segment, the second tag row being assigned to data in the upper half of the segment.

5. The DRAM of claim 1, wherein each tag row of the plurality of tag rows is associated with a specific data row as a way of the multi-way set associative cache and does not share a sense amplifier with the associated specific data row.

6. The DRAM according to claim 1, further comprising: The plurality of memory banks are operable in a standard DRAM mode and in a set associative cache mode.

7. The DRAM of claim 1, wherein the second group of address bits comprises column address bits for column access.

8. The DRAM of claim 1 further comprising each tag and each comparator of the plurality of comparators, the tag and each comparator of the comparators being configurable with respect to a bit length or how many paths are in a set.

9. A set associative cache dynamic random access memory DRAM, comprising: a plurality of memory banks, each memory bank comprising a plurality of plates, each plate comprising a plurality of DRAM cells in rows and columns; A majority of the rows include rows for data as data rows, and a minority of the rows include rows for labels as label rows; a communication interface for receiving a first set of address bits from a memory controller; A plurality of comparators, each of the plurality of comparators being configured to: comparing the first set of address bits to a first set of tag information bits from the tag row to generate a cache hit indication and a plurality of set bits; and The plurality of set bits and address bits are combined based on the cache hit to generate a second set of address bits to be used to access cache data in the DRAM as one of a plurality of ways of the set associative cache.

10. The set-associative cache dynamic random access memory of claim 9, wherein the tag row comprises a tag row in each of the plurality of boards of each memory bank, such that a tag row of one board is associated with data rows of different boards in the same memory bank for concurrent access of the memory bank.

11. The set associative cache dynamic random access memory according to claim 9, wherein the tag line comprises: The first label row in the upper half of each segment is assigned to the data in the lower half of the segment; as well as The second label row in the lower half of each segment is assigned to the data in the upper half of the segment.

12. The set associative cache dynamic random access memory according to claim 9, wherein: Each tag row is associated with a plurality of said data rows; Each tag row is coupled to a first sense amplifier; and Associated ones of the plurality of data rows are coupled to different second sense amplifiers.

13. The set associative cache dynamic random access memory according to claim 9, further comprising: A mode register for selecting between operating the plurality of memory banks in a standard DRAM mode with the plurality of comparators disabled and operating the plurality of memory banks in a set associative cache mode with the plurality of comparators operating in parallel across the tag rows.

14. The set associative cache dynamic random access memory of claim 9, wherein the second set of address bits will also be used for column access of the cache data in the DRAM.

15. The set associative cache dynamic random access memory according to claim 9, further comprising a mode register, the mode register being used to set the bit length of each of the tags and each of the plurality of comparators, or to select how many paths there are in a set.

16. A method for operating a set associative cache dynamic random access memory DRAM, comprising: presenting, by a memory controller, a plurality of address bits from a set in the DRAM to each of a plurality of comparators in a memory bank of the DRAM, wherein each memory bank has a data row and a tag row; comparing the plurality of address bits and a first set of tag information bits from the tag row in parallel in the plurality of comparators to generate a cache hit indication and a plurality of set bits; combining the plurality of set bits and address bits based on the cache hit to generate a second set of address bits; as well as Cache data is read from the data line by the memory controller based on the second set of address bits, wherein the DRAM and the plurality of comparators are arranged on a semiconductor substrate of a single chip.

17. The method according to claim 16, further comprising: reading a first tag row in the upper half of each segment, the first tag row being assigned to data in the lower half of the segment; as well as A second tag row in the lower half of each segment is read, the second tag row being assigned to the data in the upper half of the segment.

18. The method according to claim 16, further comprising: Operating the DRAM in the set associative cache mode is selected based on a selection between the set associative cache mode and a standard DRAM mode.

19. The method according to claim 16, further comprising: A plurality of paths in the set are set according to a path range, or a bit length of each tag and each comparator in the plurality of comparators is set according to a bit length range.

20. The method of claim 16, wherein determining the second set of address bits comprises determining column address bits.

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