Integrated devices for protection against electrostatic discharge

Abstract

Embodiments of the present disclosure relate to integrated devices for protecting against electrostatic discharge. A first power rail is provided as a power tree configured with a coupling to distribute a power supply voltage to active elements of a circuit. A second power rail is provided as an electrostatic discharge path and is not configured with a distribution tree coupling to active elements of the circuit. A first electrostatic discharge circuit is directly electrically connected between one end of the second power rail and a ground rail. A second electrostatic discharge circuit is directly electrically connected between an interconnect node and the ground rail. The interconnect node electrically interconnects the other end of the second power rail to the first power rail at the second electrostatic discharge circuit.

Description

[0001] Priority claim

[0002] This application claims the priority of French Patent Application No. 1905367, filed on May 22, 2019, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments relate to integrated circuits, and more particularly to devices for protection from electrostatic discharge in integrated circuits. Background Art

[0004] Circuitry for electrostatic discharge (ESD) protection of integrated circuits is subject to large currents (typically several amperes) within the circuits.

[0005] These large currents must flow through the interior of the chip via specific pathways between the terminals that receive the discharge.

[0006] As a general rule, these paths include dedicated protection components connected to the power rails and are configured to limit the electrostatic discharge and discharge current that will flow through the path.

[0007] In the integrated circuit interconnect layers (BEOL, for Back End of Line), power rails are typically made of metal tracks and distribute supply and reference voltages to active components at various points on the integrated circuit.

[0008] Typically, active components can be connected at any point on the supply rail and can withstand a specified maximum voltage before breakdown. Active components are particularly sensitive to overvoltages in the supply voltage.

[0009] Due to the ohmic voltage drop, during an electrostatic discharge the voltage on the power rail is equal to the voltage across the terminals of the dedicated protection component plus the voltage generated by the flow of the discharge current against the resistance of the power rail.

[0010] Therefore, the voltage at one end of the power rail is usually higher than the maximum breakdown voltage, and the voltage at the point on the power rail to which the active component is connected (equivalent to the voltage divider bridge) is likely to be higher than the maximum breakdown voltage as well.

[0011] It has been proposed to reduce the resistance of the track by increasing its width, but this results in detrimental bulk.

[0012] Scaling the protection components to reduce the voltage across the terminals, besides being technically difficult and expensive, is also limited by the trade-off between the supply voltage and the maximum breakdown voltage.

[0013] Increasing the number of protected components often results in random and uncontrollable behavior.

[0014] Therefore, there is a need to reduce the risk of failures in the electrostatic discharge (ESD) protection process of integrated circuits. Summary of the invention

[0015] According to an embodiment, proposed is a simple and inexpensive device making it possible to completely eliminate the risk of failure in the protection of integrated circuits from electrostatic discharges, the device exhibiting reduced size and improved performance, in particular in terms of predictability.

[0016] According to one aspect, an integrated circuit includes a first power rail configured to distribute a supply voltage to active elements of the integrated circuit, and a device for protecting against electrostatic discharge, the device including a second power rail configured to conduct an electrostatic discharge current between a power pin and a ground pin, the second power rail not being connected to any active element of the circuit.

[0017] Therefore, in the event of an electrostatic discharge, the discharge current flows through the second power rail. Since the second power rail is not connected to any active element of the circuit, the ohmic voltage drop does not introduce a voltage higher than the maximum breakdown voltage into any active element of the circuit.

[0018] The device for protecting against electrostatic discharge according to this aspect does not require the second power rail to exhibit a very low resistivity and can therefore use a smaller area than conventional devices.

[0019] Since the protection device has a simple structure, the behavior of the device is easy to predict and can be easily optimized.

[0020] According to one embodiment, a device for protecting against electrostatic discharge includes a first electrostatic discharge limiter device having terminals directly connected to a ground terminal and an input terminal, and a second power rail is connected to a power pin and to the input terminal of the first electrostatic discharge limiter device.

[0021] Advantageously, the first power rail is connected to the power pin on said input terminal of the first ESD limiter device via the second power rail.

[0022] Thus, during an ESD, the voltage in the power distribution tree is determined by the voltage at the input terminal and this voltage is characterized by the first ESD limiter device. For example, the ESD limiter device is provided with thyristors and transistors using reliable and mature technology.

[0023] According to one embodiment, the integrated circuit includes a ground distribution tree connected to a ground pin, the ground distribution tree being configured to distribute a ground voltage to active elements of the circuit, and the device for protecting against electrostatic discharge includes a second electrostatic discharge limiting device directly connected to the power pin and directly connected to a point on the ground distribution tree.

[0024] The second limiting device is advantageously connected to a point on the ground distribution tree closest to the power supply pin.

[0025] In particular, the second limiting device makes it possible to distribute the discharge current from the power pin to the ground pin by guiding the discharge current through the second power rail and the ground distribution tree at the same time. This makes it possible to reduce the width of the second power rail and avoid the risk of fuse breaking caused by the entire discharge current flowing through the second power rail.

[0026] According to one embodiment, the integrated circuit further includes at least one input-output pin, and the device for protecting against electrostatic discharge includes at least one third electrostatic discharge limiting device, which is directly connected to each input-output pin and directly connected to various points on the ground distribution tree.

[0027] In particular, this embodiment makes it possible to avoid a voltage increase in the first power rail in the event of a positive electrostatic discharge from the power pin to the input-output pin. In particular, the voltage increase caused by the ohmic voltage drop on the ground distribution tree (after flowing through the second power rail, the discharge current flows through the ground distribution tree to the input-output pin) will be transferred to the ground pin as well as the first power rail.

[0028] However, the at least one third discharge limiting device allows the discharge current to flow through a more direct resistance path between the power pin and the input-output pin, thereby avoiding a harmful increase in voltage caused by an ohmic voltage drop.

[0029] This embodiment is advantageously applicable to input-output terminals that are closer to the power pins than the ground pins.

[0030] For example, the integrated circuit comprises a chip produced on a semiconductor substrate and containing active elements of the circuit, and interconnect portions including metal layers including said power rails, said pins and a ground distribution tree. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other advantages and features will become apparent by examining the detailed description of entirely non-limiting embodiments and the accompanying drawings, in which:

[0032] Figure 1 An example of metal tracks of a metal layer in a back end of line BEOL interconnect layer of an integrated circuit is shown; and

[0033] Figure 2 shows a reference in the form of a circuit diagram Figure 1 The metal track. DETAILED DESCRIPTION

[0034] Figure 1 An example of metal tracks of a metal layer in a BEOL interconnect layer of an integrated circuit CI is shown. The abbreviation BEOL stands for Back End of Line.

[0035] The integrated circuit CI also comprises a chip (not shown) produced on the basis of a semiconductor substrate and containing the active elements of the circuit CI in an area generally denoted as the front end of the line using the abbreviation FEOL.

[0036] The interconnection part of the integrated circuit CI comprises pins for external contacts of the integrated circuit, in particular a power pin VDD for receiving a power voltage (eg 5V) and a ground pin GND for receiving a reference voltage.

[0037] The integrated circuit CI comprises a first power rail VDDTR configured as a distribution tree for distributing the supply voltage to active components located at various points in the chip through various tree couplings. The first power rail VDDTR is formed by metal tracks in one or more metal layers of the interconnection part of the integrated circuit CI.

[0038] Similarly, the ground distribution tree GNDTR is coupled to the active elements at various points Gi in the chip and is formed by metal tracks in one or more metal layers of the interconnection part of the integrated circuit CI, and is configured as a distribution tree for distributing the ground voltage to the active components located at various points in the chip through various tree-shaped couplings.

[0039] In this example, the integrated circuit CI further comprises two input-output pins I / O for routing input and / or output signals.

[0040] In this specification, the pins VDD, GND, and I / O are shown as pads in the metal layer. After packaging, these pads will be electrically connected to actual external pins, which are usually used to connect external devices.

[0041] The external pins may come into contact with components carrying an electrostatic charge, such as the fingers of an operator handling the integrated circuit CI. The electrostatic charge may be higher than the maximum breakdown voltage, beyond which the active components of the integrated circuit CI will be destroyed.

[0042] The integrated circuit CI comprises a device ESD for protection against electrostatic discharge, which is configured to present as low a voltage as possible between two pins receiving the electrostatic discharge, so that the energy of the discharge is dissipated by the electrostatic discharge source.

[0043] Usually, the Human Body Model (HBM), which is conventional and known per se, is used as a reference impedance which must be able to dissipate the discharge energy.

[0044] To this end, the device ESD for protecting against electrostatic discharge includes electrostatic discharge limiting devices ESD1, ESD2, ESD3, ESD4 ("ESDi") associated with each pin VDD, GND, I / O.

[0045] The electrostatic discharge limiting device ESDi is connected directly to the respective pins, ie as close as possible and without any other components coupled between them.

[0046] According to arbitrary numbering, the first electrostatic discharge limiting device ESD1 is a device directly connected to the ground pin GND.

[0047] An electrostatic discharge limiting device ESDi typically comprises a semiconductor component, such as a thyristor, which is configured to exhibit a high impedance ("open circuit") when the voltage between the two terminals is below a trigger voltage (also called a discharge voltage), and to exhibit a negligible impedance ("short circuit") if the voltage between the two terminals exceeds the trigger voltage. The term "negligible impedance" is understood to mean an impedance that is negligible relative to the impedance of the human body model (HBM).

[0048] The device ESD for protecting against electrostatic discharge further comprises a second power rail VDDBUS connecting the power supply pin VDD to terminals of the first electrostatic discharge limiting device ESD1.

[0049] The second power supply rail VDDBUS is for example formed by metal tracks in one or more metal layers of an interconnection part of the integrated circuit CI.

[0050] The second power supply rail VDDBUS is not connected to any active element of the chip of the integrated circuit CI between the power supply pin VDD and said input terminal of the first discharge limiter device ESD1 (i.e., the bus is not configured as a distribution tree and therefore does not include any tree coupling for distributing the power supply voltage to active components located at various points in the chip).

[0051] Furthermore, in order to distribute the power supply voltage to the active elements of the chip, the first power supply rail VDDTR is connected to the power supply pin VDD receiving the power supply voltage via the second power supply rail VDDBUS.Therefore, the first power supply rail VDDTR is connected to the input terminal NE of the first electrostatic discharge limiter device ESD1.

[0052] The metal track of the first power rail VDDTR is configured to route the supply voltage from the input terminal NE to the active elements located at various points Vi in the chip.

[0053] Furthermore, the device ESD for protecting against electrostatic discharge comprises a second electrostatic discharge limiting device ESD2 directly connected to the power supply pin VDD and a point on the ground distribution tree GNDTR. Advantageously, the point on the ground distribution tree GNDTR is selected as close as possible to the power supply pin VDD.

[0054] The third electrostatic discharge limiting devices ESD3, ESD4 are directly connected to each input / output pin I / O and corresponding points on the ground distribution tree GNDTR.

[0055] Reference now Figure 2 .

[0056] Figure 2 The circuit diagram is shown in the form of a reference Figure 1 The metal track.

[0057] The resistance RVi (where 0≤i≤n-1) represents the inherent resistance of the metal track of the distribution tree of the first power rail VDDTR between two points Vi and Vi+1 (where 0≤i≤n-1), to which the active components of the chip are coupled.

[0058] The resistance RGi (where 0≤i≤n-1) represents the inherent resistance of the metal track of the ground distribution tree GNDTR between two points Gi and Gi+1 (where 0≤i≤n-1), to which the active components of the chip are coupled.

[0059] The resistances RG′ and RG″ respectively represent the inherent resistance of the metal track of the ground distribution tree GNDTR between the power pin VDD and the adjacent input / output pin I / O and the inherent resistance between the ground pin GND and the adjacent input / output pin I / O.

[0060] The resistance Rbus represents the inherent resistance of a metal track connecting the power supply pin VDD and the second power supply rail VDDBUS of the input terminal NE of the first electrostatic discharge limiter device ESD1 .

[0061] Therefore, in the event of electrostatic discharge between the power pin VDD and the ground pin GND, the discharge current IESDbus flows through the second power rail VDDBUS. In addition, since the second power rail VDDBUS is not connected to any active element of the chip at point Vi, the ohmic voltage drop in the second rail VDDBUS does not introduce a voltage higher than the maximum breakdown voltage into the active elements of the chip.

[0062] In contrast, during an electrostatic discharge, the voltage in the power distribution tree VDDTR is determined by the voltage on the input terminal NE, and this voltage is determined by the design of the first electrostatic discharge limiter device ESD1.

[0063] The technology, conventional and known per se, allows configuring the first electrostatic discharge limiting device ESD1 such that, in the switched-on state, the voltage at the input terminal NE is lower than the maximum breakdown voltage specified for the active element.

[0064] The parallel discharge current IESDg flows through the ground distribution tree GNDTR via the second discharge limiter device ESD2 and the first discharge clamp device ESD1.

[0065] Due to the ohmic voltage drop across resistor RGi, the voltage level at point Gi increases without causing any harm to the active components of the chip.

[0066] However, if electrostatic discharge occurs between the power pin VDD and the input / output pin I / O, for example, near the power pin VDD ( Figure 2 Instead of flowing through the direct metal line VDDBUS to reach the ground pin GND, and then flowing through the ground distribution tree GNDTR via the third electrostatic discharge limiter device ESD3 to reach the input / output pin I / O, the discharge current flows directly through the ground distribution tree between the power pin VDD and the input / output pin I / O via the second discharge limiter device ESD2 and the third discharge limiter device ESD3.

[0067] This avoids combining the resistances Rbus, RGi (0≤i≤n-1) and Rg' of the metal track through which the discharge current flows, thereby avoiding excessive increase in the voltage level on the power pin due to the ohmic voltage drop caused by the combination of resistances Rbus, RGi (0≤i≤n-1) and Rg'.

[0068] In particular, in the absence of the second limiting device ESD2, the voltage increase caused by the ohmic voltage drop across the resistors Rbus, RGi (0≤i≤n-1) and Rg' will be transmitted to the ground pin GND and transmitted to the input terminal NE connected to the power distribution tree VDDTR through the first discharge limiting device ESD1.

[0069] However, the second discharge limiter device ESD2 and the at least one third discharge limiter device ESD3 allow the discharge current to flow through a more direct resistive path between the power pin VDD and the input-output pin I / O, namely only through Rg', so that no voltage increase is caused by the ohmic voltage drop in the power distribution tree VDDTR.

[0070] Devices used to protect against electrostatic discharge (ESD) do not require the metal lines of the second power rail VDDBUS to exhibit very low resistivity, and the metal lines can be as small as the design rules allow, especially considering the maximum allowable current density limits during discharge and normal operation.

[0071] Since the structure of the ESD protection device is simple, the behavior of the device is easy to predict and can be easily optimized.

[0072] In other words, what is proposed is a dual power rail structure, where one rail acts as a standard power tree and the other rail only carries ESD current and is not connected to any active components.

[0073] This structure makes it possible to foreseeably avoid the risk of poor performance in protecting the integrated circuit from electrostatic discharges, resulting in malfunctions due to the local introduction of overvoltages in the active components by the resistivity of the power supply rails.

[0074] This structure allows the size of the power rails to be based only on the normal operating requirements of the integrated circuit, rather than on minimizing the voltage drop during ESD. This makes it possible to avoid wasting silicon area or implementing more expensive processes for protection from ESD.

Claims

1. An integrated circuit, comprising: a first power rail configured to distribute a supply voltage to active components of the integrated circuit; as well as A device for protecting against electrostatic discharge, the device comprising: a second power rail configured to conduct electrostatic discharge current between a power pin and an input terminal, the second power rail being not connected to any active element of the circuit along its length between the power pin and the input terminal; and A first electrostatic discharge limiting device has: a first node connected to the input terminal; and a second node connected to a ground pin; Wherein the first power rail is directly electrically connected to the second power rail at the input terminal. 2 . The integrated circuit of claim 1 , wherein the first ESD limiter device further has a reference terminal at the second node that is directly electrically connected to the ground pin.

3. The integrated circuit of claim 1, wherein the second power rail is connected to the power supply pin at a first end and to the input terminal at a second end.

4. The integrated circuit of claim 1 , further comprising a ground distribution tree connected to the ground pin, the ground distribution tree being configured to distribute ground voltage to active elements of the integrated circuit, wherein the device for protecting against electrostatic discharge comprises a second electrostatic discharge limiting device connected directly to the power pin and directly to a point on the ground distribution tree.

5. The integrated circuit according to claim 4 further includes at least one input-output pin, wherein the device for protecting against electrostatic discharge includes at least one third electrostatic discharge limiting device, and the third electrostatic discharge limiting device is directly connected to each input-output pin and directly connected to another corresponding point on the ground distribution tree.

6. The integrated circuit of claim 1 , further comprising: Integrated circuit chips, produced on semiconductor substrates and containing the active elements of said circuits; as well as The interconnection portion includes a metal layer including the power rail and the power pins and ground pins.

7. An integrated circuit comprising: Active circuit components; Power supply pin; Ground pin; a first power rail having a first end and a second end, the first end being directly electrically connected to the power pin, wherein the first power rail has no distribution tree coupling for connecting power to any active circuit components; a second power rail having a first end electrically connected directly to a second end of the first power rail at a node, wherein the second power rail has a distribution tree coupling for connecting power to active circuit components; a ground rail directly connected to the ground pin, wherein the ground rail has a distribution tree coupling for connecting power to active circuit components; a first electrostatic discharge limiting device having a first terminal directly electrically connected to the node and a second terminal directly electrically connected to the ground rail; as well as A second electrostatic discharge limiter device has a first terminal directly electrically connected to the power pin and a second terminal directly electrically connected to the ground rail.

8. The integrated circuit of claim 7, further comprising: Input / output pins; as well as A third ESD limiter device has a first terminal directly connected to the input / output pin and a second terminal directly connected to the ground rail.

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