Three-dimensional semiconductor device and manufacturing method thereof

Abstract

A three-dimensional semiconductor device and a method for manufacturing the same are provided. The three-dimensional semiconductor device includes a plurality of first gate electrodes sequentially stacked on a substrate, a second gate electrode located on the plurality of first gate electrodes, a first channel structure extending through a portion of the second gate electrode and the plurality of first gate electrodes, a buried insulating pattern located on the sidewall of the first channel structure with its upper surface at a level higher than the top of the first channel structure, a second channel structure extending through the remaining portion of the second gate electrode, and a buried conductive pattern located on the sidewall of the second channel structure, the second channel structure being connected to the first channel structure.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0064724, filed on May 31, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The exemplary embodiments disclosed herein relate to three-dimensional semiconductor devices and methods of manufacturing the same. Background Technology

[0003] Although electronic devices are becoming increasingly smaller, they still require extensive data processing. The semiconductor devices used in such devices must be highly integrated. To provide highly integrated semiconductor devices, it may be desirable to have three-dimensional (e.g., vertical) transistors instead of planar transistors. Summary of the Invention

[0004] According to some exemplary embodiments of the inventive concept, a three-dimensional semiconductor device may include: a substrate; a plurality of first gate electrodes stacked sequentially on the substrate; a second gate electrode located on the plurality of first gate electrodes; a first channel structure extending through a portion of the second gate electrode and the plurality of first gate electrodes; a buried insulating pattern disposed on the sidewall of the first channel structure and having an upper surface at a level higher than the top of the first channel structure; a second channel structure extending through the remainder of the second gate electrode and connected to the first channel structure; and a buried conductive pattern located on the sidewall of the second channel structure.

[0005] According to some exemplary embodiments of the inventive concept, a three-dimensional semiconductor device may include: a substrate; a plurality of first gate electrodes sequentially stacked on the substrate; a second gate electrode including a lower gate electrode and an upper gate electrode sequentially stacked on the plurality of first gate electrodes; a first channel structure extending through a portion of the lower gate electrode and the plurality of first gate electrodes; a buried insulating pattern disposed on a sidewall of the first channel structure and having an upper surface at a level higher than the top of the first channel structure; a second channel structure extending through the remainder of the second gate electrode and connected to the first channel structure; and a buried conductive pattern disposed on a sidewall of the second channel structure, the buried conductive pattern being separated from the buried insulating pattern.

[0006] According to some exemplary embodiments of the inventive concept, a three-dimensional semiconductor device may include: a substrate; a stacked structure including a plurality of first gate electrodes stacked on the substrate, at least one second gate electrode located on the plurality of first gate electrodes, and a channel via passing through the plurality of first gate electrodes and at least one second gate electrode; a first channel structure disposed on the inner sidewall of the channel via and stacked with a first portion of at least one second gate electrode and the plurality of first gate electrodes in a horizontal direction parallel to the upper surface of the substrate; and a first buried insulating pattern located in the channel via and on the sidewall of the first channel structure. The device has an upper surface at a level higher than the top of the first channel structure; a second channel structure disposed on the inner sidewall of the channel hole and located on the top of the first channel structure, and including a channel layer superimposed on a second portion of at least one second gate electrode in a horizontal direction and an intermediate horizontal layer located on the upper surface of the first buried insulating pattern; a second buried insulating pattern located in the channel hole and located on the sidewall of the intermediate horizontal layer of the second channel structure and the channel layer of the second channel structure; and a buried conductive pattern located in the channel hole and located on the sidewall of the second buried insulating pattern and the channel layer of the second channel structure.

[0007] According to some exemplary embodiments of the inventive concept, a method of manufacturing a three-dimensional semiconductor device may include: forming a structure comprising an insulating layer and a sacrificial layer alternately stacked on a substrate; forming a channel via through the structure; forming a first channel structure on the inner sidewall of the channel via; forming a buried insulating pattern in the channel via and on the first channel structure; recessing the upper surface of the buried insulating pattern; removing a portion of the first channel structure such that the top of the first channel structure is recessed lower than the recessed upper surface of the buried insulating pattern; forming a second channel structure on the inner sidewall of the channel via and on the recessed top of the first channel structure and the recessed upper surface of the buried insulating pattern; and forming a buried conductive pattern in the channel via and on the second channel structure. Attached Figure Description

[0008] Figure 1 This is an equivalent circuit diagram of a memory cell array of a three-dimensional semiconductor device according to an exemplary embodiment of the inventive concept.

[0009] Figure 2 This is a schematic perspective view illustrating a three-dimensional semiconductor device according to an example embodiment of the inventive concept.

[0010] Figure 3A yes Figure 2 An enlarged sectional view of part "A".

[0011] Figure 3B It is shown Figure 3A A transparent perspective view of a vertical structure.

[0012] Figure 4 , Figure 5 , Figure 6 and Figure 7 This is a cross-sectional view showing an example embodiment of a three-dimensional semiconductor device according to an inventive concept.

[0013] Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a cross-sectional view illustrating steps in a method for manufacturing a three-dimensional semiconductor device according to an exemplary embodiment of the inventive concept.

[0014] Figure 12A , Figure 12B , Figure 12C and Figure 12D This is a cross-sectional view illustrating a process (to form a second channel structure) in a method of manufacturing a three-dimensional semiconductor device according to an exemplary embodiment of the inventive concept.

[0015] Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 This is a cross-sectional view illustrating steps in a method for manufacturing a three-dimensional semiconductor device according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0016] Various exemplary embodiments will now be described more fully below with reference to the accompanying drawings. Throughout this application, the same reference numerals may refer to the same elements.

[0017] Figure 1 This is an equivalent circuit diagram of a memory cell array of a three-dimensional (3D) semiconductor device according to an exemplary embodiment of the inventive concept, and can be understood to include... Figure 2 Equivalent circuit diagram of memory cell array in a 3D semiconductor device.

[0018] Reference Figure 1 The memory cell array of a 3D semiconductor device may include a common source line (CSL), multiple bit lines (BL), and / or multiple cell strings (CSTR) between the common source line (CSL) and the bit lines (BL).

[0019] The common-source line (CSL) can be a conductive layer on a substrate or an impurity region within the substrate. The bit line (BL) can be a conductive pattern (e.g., a metal line) on the substrate. The bit line (BL) can be arranged in two dimensions. Multiple cell strings (CSTRs) can be connected in parallel to each of the bit lines (BL). Multiple cell strings (CSTRs) can be collectively connected to the common-source line (CSL). Multiple cell strings (CSTRs) can be positioned between the common-source line (CSL) and multiple bit lines (BL). In some example embodiments, the common-source line (CSL) can include multiple common-source lines arranged in two dimensions. Here, the same voltage can be applied to the common-source line (CSL), or each common-source line (CSL) can be electrically controlled individually.

[0020] Each cell string (CSTR) may include a ground select transistor (GST) connected to the common-source line (CSL), a string select transistor (SST) connected to the bit line (BL), and multiple memory cell transistors (MCTs) between the ground select transistor (GST) and the string select transistor (SST). The ground select transistor (GST), the multiple memory cell transistors (MCTs), and / or the string select transistors (SSTs) may be connected in series. The common-source line (CSL) may be commonly connected to the source of the ground select transistor (GST). The ground select line (GSL), multiple word lines (WL1 to WLn), and multiple string select lines (SSL) disposed between the common-source line (CSL) and the bit line (BL) may be used as the gate electrodes of the ground select transistor (GST), the memory cell transistors (MCTs), and the string select transistors (SSTs), respectively. Each memory cell transistor (MCT) may include a data storage element.

[0021] The memory cell array according to some exemplary embodiments of the inventive concept may include a GIDL transistor GIDLT for performing erase operations on the memory cell array using a gate-induced drain (GIDL) method. The GIDL transistor GIDLT may be disposed between the string select line SSL and the bit line BL, and thus may refer to an "upper GIDL transistor". In some exemplary embodiments, a "lower GIDL transistor" may also be disposed between the ground select line GSL and the common source line CSL. The GIDL gate line GIDLGL, which serves as the gate electrode of the GIDL transistor GIDLT, may be disposed between the string select line SSL and the bit line BL.

[0022] To realize a GIDL transistor GIDLT (e.g., an upper GIDL transistor), the portion of the transistor's channel region adjacent to the drain region can be doped with a high concentration of dopant. Typically, an abrupt junction can be formed by implanting dopant into this portion of the transistor's channel region using an implantation process and performing subsequent thermal treatments to diffuse and activate the dopant. For example, the high-dose implantation process can be repeated several times to obtain sufficient GIDL current. The upper insulating layer (e.g., oxide layer) may be damaged due to the high-dose implantation process. Damaged portions of the upper insulating layer are etched in subsequent etching processes, thus creating defects such as the formation of parasitic word lines. GIDL transistor GIDLTs according to some exemplary embodiments of the inventive concept can be implemented without using a high-dose implantation process.

[0023] Figure 2 This is a schematic perspective view illustrating a memory cell array of a three-dimensional semiconductor device according to an exemplary embodiment of the inventive concept. Figure 3A yes Figure 2 An enlarged sectional view of part "A". Figure 3B It is shown Figure 3A A transparent perspective view of a vertical structure.

[0024] Reference Figure 2 The 3D semiconductor device 100 may include a substrate 101 and a stacked structure SS including an insulating layer 120, a plurality of first gate electrodes 131 and / or a plurality of second gate electrodes 132. Some of the insulating layers 120 and the plurality of first gate electrodes 131 may be stacked alternately on the substrate 101. The remaining portion of the insulating layers 120 and the second gate electrodes 132 may be stacked alternately on the plurality of first gate electrodes 131.

[0025] The substrate 101 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0026] The plurality of first gate electrodes 131 may include a lowermost gate electrode 131G, an uppermost gate electrode 131S, and unit gate electrodes 131-1, 131-2, ..., 131-n vertically stacked between the lowermost gate electrode 131G and the uppermost gate electrode 131S. The lowermost gate electrode 131G and the uppermost gate electrode 131S may be respectively connected to a ground selection transistor (see...). Figure 1 The gate electrode and series select transistor of the GST (see GST) Figure 1 The gate electrode of the SST corresponds to this.

[0027] The gate electrodes 131-1, 131-2, ... and 131-n can be connected to the memory cell transistor (see...). Figure 1The gate electrode of the MCT corresponds to this. In other words, the bottommost gate electrode 131G and the topmost gate electrode 131S can be used as ground selection lines respectively (see [reference]). Figure 1 GSL) and serial select line (see GSL) and serial select line (see GSL) Figure 1 (SSL), and the cell gate electrodes 131-1, 131-2, ... and 131-n can be used as word lines (see SSL). Figure 1 (WL1 to WLn).

[0028] The number of unit gate electrodes 131-1, 131-2, ... and 131-n can be determined according to the integration density of the 3D semiconductor device 100. For example, the number of unit gate electrodes 131-1, 131-2, ... and 131-n can be 30 or more.

[0029] The second gate electrode 132 may include a lower gate electrode 132a and an upper gate electrode 132b sequentially stacked on a plurality of first gate electrodes 131. The second gate electrode 132 may be associated with a GIDL transistor (see...). Figure 1 The gate electrode of the GIDLT corresponds to the second gate electrode 132. Figure 2 The illustration includes two gate electrodes 132a and 132b, but the inventive concept is not limited thereto. For example, the second gate electrode 132 may include one, three or more gate electrodes.

[0030] In the plan view, the stacked structure SS can extend in an XY plane having a first direction X and a second direction Y intersecting the first direction X. A plurality of first gate electrodes 131 and a plurality of second gate electrodes 132 can be sequentially stacked in a third direction Z perpendicular to the first direction X and the second direction Y. The first direction X and the second direction Y can be parallel to the upper surface of the substrate 101. The third direction Z can be perpendicular to the upper surface of the substrate 101. The plurality of first gate electrodes 131 and the plurality of second gate electrodes 132 can be separated from each other by an insulating layer 120 disposed between the respective gate electrodes of the plurality of first gate electrodes 131 and the plurality of second gate electrodes 132.

[0031] For example, each of the insulating layers 120 may include a silicon layer, a silicon oxide layer, a silicon carbide layer, a silicon oxynitride layer, and / or a silicon nitride layer. For example, each of the plurality of first gate electrodes 131 and the plurality of second gate electrodes 132 may include polysilicon and / or a metal such as tungsten and / or a conductive metal nitride.

[0032] A lower insulating layer 102 may be disposed between the substrate 101 and the stacked structure SS. The lower insulating layer 102 may include, for example, silicon oxide, silicon nitride, a high-k dielectric material (e.g., aluminum oxide, hafnium oxide, etc.) and / or combinations thereof. The lower insulating layer 102 may be thinner than each of the insulating layers 120. The thickness of the lower insulating layer 102 and the thickness of the insulating layers 120 may be measured in a third direction Z.

[0033] The stacked structure SS may include a channel hole CH extending through it in the third direction Z. A vertical structure VS may be provided in each of the channel holes CH. Figure 2 As shown, the vertical structures VS (or each of the channel holes CH) may have the same or substantially the same width along the third direction Z, but the inventive concept is not limited thereto. In some example embodiments, the vertical structures VS (or each of the channel holes CH) may gradually narrow as they approach the substrate 101.

[0034] The vertical structure VS may include vertical insulators 160 arranged in sequence near the first gate electrode 131 and the second gate electrode 132, a first channel structure 151 and a second channel structure 152 connected to each other in the vertical direction, and a buried insulating pattern (hereinafter also referred to as the first buried insulating pattern) 181. The vertical structure VS may pass through the stacked structure SS and may be electrically connected to the substrate 101. The vertical structure VS may include multiple vertical structures disposed in the stacked structure SS. In a plan view, the multiple vertical structures VS may be arranged in a first direction X and a second direction Y. The multiple vertical structures VS may be arranged in a zigzag pattern in the first direction X.

[0035] Reference Figure 2 and Figure 3A The channel structure may include a first channel structure 151 and a second channel structure 152 connected to each other in a third direction Z. The bottom end of the second channel structure 152 may be connected to the top end 151T of the first channel structure 151. The first channel structure 151 may pass through a portion of the second gate electrode 132 and a plurality of first gate electrodes 131. The second channel structure 152 may pass through the remaining portion of the second gate electrode 132.

[0036] For example, the first channel structure 151 can pass through multiple first gate electrodes 131 and lower gate electrode 132a, and the second channel structure 152 can pass through the upper gate electrode 132b.

[0037] The first channel structure 151 may include undoped semiconductor material, such as undoped polysilicon. The second channel structure 152 may include doped semiconductor material and / or semiconductor material having a band gap smaller than that of the first channel structure 151. For example, the second channel structure 152 may include doped polysilicon. Based on X-ray fluorescence (XRF) analysis, the doping concentration of the doped polysilicon in the second channel structure 152 can be as high as 2 count / cm³. 3 (number of atoms / cm 3 Up to 10 count / cm 3Within the range of [specific parameters]. Including a semiconductor material with a relatively small bandgap in the second channel structure 152 can increase GIDL efficiency, and may include, for example, silicon-germanium (SiGe) and / or germanium (Ge). In some example embodiments, a semiconductor material with a relatively small bandgap may be doped. In some example embodiments, the second channel structure 152 can be formed by depositing a doped semiconductor material. In some example embodiments, the second channel structure 152 can be formed by depositing a semiconductor material and then doping the semiconductor material to a desired doping concentration using subsequent processes.

[0038] The buried insulating pattern 181 can be disposed on the sidewall of the first channel structure 151, and the buried insulating pattern 181 can be surrounded by the first channel structure 151 in a plan view (or the sidewall of the buried insulating pattern 181 can be covered by the first channel structure 151). The upper surface 181T of the buried insulating pattern 181 can be positioned at a level higher than the top 151T of the first channel structure 151 relative to the upper surface of the substrate 101.

[0039] like Figure 3A As shown, the horizontal level Lb of the top end 151T of the first channel structure 151 can be positioned higher than the horizontal level of the upper surface of the lower gate electrode 132a and lower than the horizontal level of the lower surface of the upper gate electrode 132b. However, the inventive concept is not limited thereto. For example, the horizontal level Lb of the top end 151T of the first channel structure 151 can be varied depending on the thickness and number of gate electrodes. In some exemplary embodiments, refer to... Figure 5 , Figure 6 and Figure 7 The horizontal Lb of the top end 151T of the first channel structure 151 can be selected within a range that is higher than the lower surface of the lower gate electrode 132a and lower than the upper surface of the upper gate electrode 132b.

[0040] The upper surface 181T of the buried insulating pattern 181 can be positioned at a horizontal level parallel to the upper surface of the substrate 101 (or in the first direction X or the second direction Y), overlapping the upper gate electrode 132b. In other words, the horizontal level La of the upper surface 181T of the buried insulating pattern 181 can be positioned above the horizontal level Lb of the top end 151T of the first channel structure 151. The buried insulating pattern 181 may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0041] Reference Figure 3B Each of the first channel structure 151 and the second channel structure 152 (e.g., channel layer 152a) may have a hollow tube shape or a through shape. The bottom end of the first channel structure 151 may be closed.

[0042] Reference Figure 3AThe second channel structure 152 may include a channel layer 152a adjacent to the upper gate electrode 132b and an intermediate horizontal layer 152b on the upper surface 181T of the buried insulating pattern 181. The channel layer 152a may include an extension 152R extending into a recessed region (hereinafter referred to as the recessed region) Rp around the buried insulating pattern 181 to connect to the top end 151T of the first channel structure 151. The length of the extension 152R extending through the recessed region Rp can be suitably set such that it is used for GIDL transistors (see [link to GIDL generation]). Figure 1 The channel length of the GIDLT can be precisely designed. The thickness of the second channel structure 152 (e.g., the thickness of the channel layer 152a) can be, for example... to Within the scope or in the approximate to approximately Within the range.

[0043] In a plan view, the buried conductive pattern 192 may be disposed on the sidewall of the second channel structure 152 and may be surrounded by the second channel structure 152. The buried conductive pattern 192 may be disposed within the space defined by the second channel structure 152. The buried conductive pattern 192 may have a flat upper surface coplanar with the upper surface of the stacked structure SS and may include doped semiconductor material. The buried conductive pattern 192 may be configured as a pad region. In some example embodiments, since the buried conductive pattern 192 is doped from its top, the buried conductive pattern 192 may include a first portion 192H and a second portion 192L, the first portion 192H including semiconductor material with a high concentration of doping, and the second portion 192L including semiconductor material with a low concentration of doping or undoped semiconductor material.

[0044] Reference Figure 2 and Figure 3A A vertical insulating member 160 may be disposed between the stacked structure SS and the first channel structure 151 and the second channel structure 152. The vertical insulating member 160 may be positioned between each of the first gate electrode 131 and the second gate electrode 132 and each of the first channel structure 151 and the second channel structure 152. In some example embodiments, the vertical insulating member 160 may extend between each of the insulating layers 120 and each of the first channel structure 151 and the second channel structure 152. The vertical insulating member 160 may have a tubular shape or a through-shaped shape with openings at the top and bottom.

[0045] The vertical insulator 160 may include memory elements of a flash memory device. For example, the vertical insulator 160 may include a charge storage layer 164 of the flash memory device. Data stored in the vertical insulator 160 may be altered using Fowler-Nordheim tunneling caused by the voltage difference between the first channel structure 151 and the adjacent first gate electrode 131. In some example embodiments, the vertical insulator 160 may include a thin layer capable of storing information based on another operating principle, such as a thin layer for a phase-change memory or a variable resistance memory.

[0046] The vertical insulator 160 may further include a tunnel insulating layer 162 between the charge storage layer 164 and each of the first channel structure 151 and the second channel structure 152. The tunnel insulating layer 162 may directly contact the first channel structure 151 and the second channel structure 152. In some example embodiments, the vertical insulator 160 may further include a barrier layer 166 between the charge storage layer 164 and the first gate electrode 131 and the second gate electrode 132. The charge storage layer 164 may include at least one of, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, and a stacked trapping layer. The tunnel insulating layer 162 may include a material having a band gap larger than that of the charge storage layer 164. For example, the tunnel insulating layer 162 may be a silicon oxide layer. The barrier layer 166 may include a material having a band gap larger than that of the charge storage layer 164. The barrier layer 166 may include a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer.

[0047] The vertical insulating element 160 may further include a capping layer (not shown) between each of the insulating layers 120 and each of the first gate electrode 131 and the second gate electrode 132. The capping layer may directly contact the insulating layer 120 and may be disposed separately from the first gate electrode 131 and the second gate electrode 132. In some example embodiments, the capping layer may extend vertically between adjacent gate electrodes in the first gate electrode 131 and the second gate electrode 132. The capping layer may have etch selectivity relative to the charge storage layer 164 and may comprise a material different from the insulating layer 120. For example, the capping layer may comprise at least one of a silicon oxide layer, a polysilicon layer, a silicon carbide layer, and / or a silicon nitride layer that is different from the insulating layer 120.

[0048] Horizontal insulating members 170 may each be disposed on the upper and lower surfaces of each of the first gate electrode 131 and the second gate electrode 132. Each of the horizontal insulating members 170 may extend between each of the first gate electrode 131 and the second gate electrode 132 and the vertical insulating member 160. Each of the horizontal insulating members 170 may include one or more thin layers. In some example embodiments, each of the horizontal insulating members 170 may include a barrier insulating layer of a charge-trapping flash memory transistor.

[0049] An epitaxial layer 140 may be disposed between the first channel structure 151 and the substrate 101, and may contact the first channel structure 151 and the substrate 101. The first channel structure 151 may be electrically connected to the substrate 101 via the epitaxial layer 140. The epitaxial layer 140 may be disposed in a recessed region R of the substrate 101. The epitaxial layer 140 may fill the recessed region R and may protrude above the upper surface of the substrate 101. For example, relative to the upper surface of the substrate 101, the height of the upper surface of the epitaxial layer 140 may be higher than the height of the upper surface of the lowermost gate electrode 131G and lower than the height of the upper surface of the second lowest gate electrode 131-1. The upper surface of the epitaxial layer 140 may have an upwardly tapered shape (e.g., it may slope downward from the center of its upper surface towards its side edges). The epitaxial layer 140 may be a semiconductor material layer formed by a selective epitaxial growth (SEG) process. The epitaxial layer 140 may include doped or undoped silicon (Si), germanium (Ge), and / or silicon-germanium (SiGe). In some example embodiments, the epitaxial layer 140 may be omitted, so the lower portion of the first channel structure 151 can be inserted into the substrate 101. Therefore, the bottom end of the first channel structure 151 can contact the substrate 101. The lower surface of the vertical insulator 160 can contact the substrate 101.

[0050] like Figure 2 As shown, electrode separation pattern 107 can be disposed at each of the opposing sidewalls of the stacked structure SS. Electrode separation pattern 107 can cover common source region 105 disposed in substrate 101. Electrode separation pattern 107 can include at least one of, for example, silicon oxide layer, silicon nitride layer, and silicon oxynitride layer. Common source region 105 can be used as common source line (see...). Figure 1 The SSL (Secure Layer) can be an impurity-doped region. A spacer insulating layer 184 can be disposed between the sidewall of the stacked structure SS and the electrode separation pattern 107. Wiring (e.g., bit line 195) can be disposed on the stacked structure SS and can traverse the stacked structure SS. Bit line 195 can be connected to a buried conductive pattern 192, which is a pad region, via a contact plug 194. An interlayer insulating layer (not shown) can be disposed between bit line 195 and the stacked structure SS. Contact plug 194 can pass through the interlayer insulating layer.

[0051] The 3D semiconductor device 100 according to some example embodiments of the inventive concept can be modified in various ways. The pad region connected to each of the bit lines 195 can be modified to effectively prevent dopant diffusion from the second channel structure 152. Figure 4 The image shows a 3D semiconductor device with such a structure. (Compared to...) Figure 3A resemblance, Figure 4 yes Figure 2 A magnified view of part of the letter "A".

[0052] Reference Figure 4 In addition to the second buried insulating pattern 182 being additionally disposed between the buried conductive pattern 192' and the buried insulating pattern 181, the 3D semiconductor device according to the exemplary embodiment of the inventive concept can be used with... Figures 1 to 3B The 3D semiconductor device 100 shown is the same as or similar to that illustrated. The same reference numerals are used to indicate the same... Figures 1 to 3B The same element shown.

[0053] The 3D semiconductor device according to some exemplary embodiments of the inventive concept may further include a second buried insulating pattern 182 between the buried conductive pattern 192' and the first buried insulating pattern 181. The second channel structure 152 may include an intermediate horizontal layer 152b on the upper surface 181T of the first buried insulating pattern 181. The second buried insulating pattern 182 may be surrounded by the channel layer 152a of the second channel structure 152 (e.g., the sidewalls of the second buried insulating pattern 182 may be covered by the channel layer 152a of the second channel structure 152) and may be disposed between the intermediate horizontal layer 152b and the buried conductive pattern 192'. For example, the buried conductive pattern 192' may be configured as a pad region and / or may include a semiconductor material with a high concentration of doping. For example, the second buried insulating pattern 182 may include silicon oxide, silicon nitride, and / or silicon oxynitride. The second buried insulating pattern 182 may include the same material as the first buried insulating pattern 181.

[0054] exist Figure 3A In the cross-section shown, when the buried conductive pattern 192 is doped from its top according to the burial depth and doping conditions of the buried conductive pattern 192, the first portion 192H is doped at a high concentration, but the second portion 192L may be doped at a low concentration or may be undoped. In some example embodiments, the dopant may diffuse from the second channel structure 152, which is doped at a desired concentration, into the second portion 192L. However, in some example embodiments of the inventive concept, since the region corresponding to the second portion 192L of the buried conductive pattern 192 is formed of an insulating material, changes in the threshold voltage due to dopant diffusion can be reduced or prevented.

[0055] The 3D semiconductor device according to some example embodiments can be modified in various ways. For example, the horizontal Lb at the top of the first channel structure 151 and the horizontal La on the upper surface of the first buried insulating pattern 181 can be modified in various ways when the following conditions are met.

[0056] 1) The top of the first trench structure 151 is recessed lower than the upper surface of the first buried insulating pattern 181.

[0057] 2) At least a portion of the second gate electrode 132 (e.g., a portion of one or more second gate electrodes 132) is stacked with the first channel structure 151 in the horizontal direction, and

[0058] 3) At least one other portion of the second gate electrode 132 is stacked with the second channel structure 152 in the horizontal direction.

[0059] Figure 5 and Figure 6 This is a cross-sectional view illustrating an example embodiment of a three-dimensional semiconductor device according to the inventive concept, and is... Figure 2 A magnified view of part of the letter "A".

[0060] Reference Figure 5 Except that the horizontal Lb' of the top end 151T' of the first channel structure 151 and the horizontal La' of the upper surface 181T' of the buried insulating pattern 181 differ from the horizontal Lb and La of some of the foregoing example embodiments, the 3D semiconductor device according to some example embodiments of the inventive concept can be compared with... Figures 1 to 3B The 3D semiconductor device 100 shown is the same as or similar to that illustrated. The same reference numerals are used to indicate the same... Figures 1 to 3B The same elements shown in the figure.

[0061] The horizontal level La' of the upper surface 181T' of the buried insulating pattern 181 can be higher than the horizontal level La of the upper surface 181T' of the buried insulating pattern 181 in some of the foregoing example embodiments. In other words, the upper surface 181T' of the buried insulating pattern 181 can be positioned at the same, substantially the same, or higher level than the upper surface of the upper gate electrode 132b. Figure 5 As shown, the second channel structure 152 can extend almost through the upper gate electrode 132b. However, the horizontal Lb' of the top end 151T' of the first channel structure 151 can be positioned lower than the upper surface of the upper gate electrode 132b.

[0062] Reference Figure 6 Except that the horizontal Lb” of the top end 151T” of the first channel structure 151 and the horizontal La” of the upper surface 181T” of the first buried insulating pattern 181 are different from those of some of the foregoing example embodiments, and a second buried insulating pattern 182 is additionally disposed between the buried conductive pattern 192' and the first buried insulating pattern 181, the 3D semiconductor device according to some example embodiments of the inventive concept can be connected to… Figures 1 to 3B The 3D semiconductor device 100 shown is the same as or similar to that illustrated. The same reference numerals are used to indicate the same... Figures 1 to 3B The same elements shown in the figure.

[0063] The horizontal level "La" of the upper surface 181T” of the first buried insulating pattern 181 may be lower than the horizontal level "La" of the upper surface 181T” of the first buried insulating pattern 181 in some of the foregoing example embodiments. The horizontal level "La" of the upper surface 181T” of the first buried insulating pattern 181 may be positioned lower than the lower surface of the upper gate electrode 132b and higher than the upper surface of the lower gate electrode 132a. In some example embodiments of the inventive concept, the horizontal level "Lb" of the top end 151T” of the first channel structure 151 may be lower than the level of the upper surface of the lower gate electrode 132a and higher than the level of the lower surface of the lower gate electrode 132a.

[0064] and Figure 4 Similar to the case shown, the second buried insulating pattern 182 may be surrounded by the channel layer 152a of the second channel structure 152 (e.g., the sidewalls of the second buried insulating pattern 182 may be covered by the channel layer 152a of the second channel structure 152) and / or may be disposed between the buried conductive pattern 192' and the intermediate horizontal layer 152b. For example, since the buried conductive pattern 192' is configured as a pad region, the buried conductive pattern 192' may include a semiconductor material with a high concentration of doping. For example, the second buried insulating pattern 182 may include silicon oxide, silicon nitride, and / or silicon oxynitride. Because the upper surface 181T” of the first buried insulating pattern 181 is positioned at a lower level than the upper surface 181T of the first buried insulating pattern 181 in some of the foregoing example embodiments, the channel layer 152a of the second channel structure 152 can extend relatively longitudinally. The diffusion of dopants from the channel layer 152a can be effectively reduced or prevented by the second buried insulating pattern 182. Therefore, in order to achieve the above effects, the second buried insulating pattern 182 can be formed to protrude above the upper surface of the upper gate electrode 132b.

[0065] In some of the foregoing embodiments, the second gate electrode 132 for generating the GIDL may include two gate electrodes disposed on the stacked structure SS. However, the second gate electrode 132 for generating the GIDL may include one or three or more gate electrodes disposed on the stacked structure SS. In some example embodiments, as described above, 1) the top end of the first channel structure 151 is recessed lower than the upper surface of the first buried insulating pattern 181, 2) at least a portion of the second gate electrode 132 (e.g., a portion of a second gate electrode 132 or some second gate electrodes 132) is horizontally stacked with the first channel structure 151, and 3) at least another portion of the second gate electrode 132 is horizontally stacked with the second channel structure 152.

[0066] Figure 7A 3D semiconductor device according to an example embodiment of the inventive concept is shown, and a gate electrode for generating GIDL is shown disposed on the upper layer of the stacked structure.

[0067] Reference Figure 7 Except that the horizontal Lb of the top end 151T of the first channel structure 151 and the horizontal La of the upper surface 181T of the buried insulating pattern 181 are altered and the second gate electrode 132 includes a gate electrode, the 3D semiconductor device according to some exemplary embodiments of the inventive concept can be used with Figures 1 to 3B The 3D semiconductor device 100 shown is the same as or similar to that illustrated. The same reference numerals are used to indicate the same... Figures 1 to 3B The same elements shown in the figure.

[0068] The second gate electrode 132 may include a gate electrode. The second gate electrode 132 (e.g., the lower portion of the second gate electrode 132) may be horizontally stacked with the first channel structure 151. Other portions of the second gate electrode 132 adjacent to the channel for inducing GIDL (e.g., the upper portion of the second gate electrode 132) may be horizontally stacked with the second channel structure 152. However, the inventive concept is not limited thereto. For example, to form the second channel structure 152, the upper surface 181T of the buried insulating pattern 181 may be positioned at the same, substantially the same, or higher level than the upper surface of the second gate electrode 132.

[0069] In some example embodiments, the second gate electrode 132 may include a plurality of gate electrodes (e.g., three or more gate electrodes) sequentially stacked on a plurality of first gate electrodes 131.

[0070] In some example embodiments, the top of the first channel structure 151 may be positioned at a level that is higher than the lower surface of the lowermost second gate electrode 132 among the plurality of second gate electrodes 132 and lower than the upper surface of the uppermost second gate electrode 132 among the plurality of second gate electrodes 132.

[0071] Specifically, the first channel structure 151 may extend vertically through some of the plurality of second gate electrodes 132 adjacent to the first gate electrode 131, and the second channel structure 152 may extend vertically through the remaining portion of the plurality of second gate electrodes 132.

[0072] In the case of three or more second gate electrodes 132, since a relatively long channel region can generate GIDL, the upper surface of the buried insulating pattern 181 can be positioned at a lower level than the upper surface of the uppermost second gate electrode 132 among the second gate electrodes 132.

[0073] Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a cross-sectional view illustrating steps in a method of manufacturing a three-dimensional semiconductor device according to an exemplary embodiment of the inventive concept, and is along... Figure 2 A cross-sectional view of the 3D semiconductor device 100 taken from the XZ plane.

[0074] Reference Figure 8 A lower insulating layer 102 can be formed on the substrate 101. Sacrificial layers 110 and insulating layers 120 can be alternately stacked on the lower insulating layer 102.

[0075] The substrate 101 may be, for example, a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The lower insulating layer 102 may be, for example, a silicon oxide layer formed by an oxidation process or a deposition process.

[0076] The sacrificial layer 110 may be formed of a material that has etch selectivity relative to the insulating layer 120. For example, each of the insulating layers 120 may include silicon oxide and / or silicon nitride. Each of the sacrificial layers 110 may include, for example, a material different from the insulating layer 120, of silicon, silicon oxide, silicon carbide, and / or silicon nitride.

[0077] The thickness of the lower insulating layer 102 can differ from the thickness of each of the insulating layers 120. The thickness of the lower insulating layer 102 can be less than the thickness of each of the insulating layers 120. The uppermost insulating layer 120 of the insulating layers 120 can be thicker than the other insulating layers 120. The insulating layers 120 positioned above and below the word line regions (including the word lines to be formed in subsequent processes) can be formed to be relatively thicker than the insulating layers 120 between the word lines. However, the inventive concept is not limited thereto. The thickness and number of the insulating layers 120 and the sacrificial layers 110 can be varied in various ways.

[0078] Reference Figure 9 The channel holes CH can be formed through the sacrificial layer 110 and the insulating layer 120. An epitaxial layer 140 can be formed in the recessed region R below each channel hole CH.

[0079] The via CH can extend into the substrate 101 in a vertical direction (in the third direction Z) substantially perpendicular to the upper surface of the substrate 101, thereby forming a recessed region R in the substrate 101. The via CH can be formed by anisotropically etching the sacrificial layer 110 and the insulating layer 120. In some example embodiments, the inner sidewalls of the via CH may not be substantially perpendicular to the upper surface of the substrate 101. For example, the width of each of the vias CH may increase as it approaches the upper surface of the substrate 101.

[0080] The epitaxial layer 140 can be formed by performing a selective epitaxial growth process using the substrate 101 exposed in the recessed region R as a seed. The epitaxial layer 140 can comprise a single layer or multiple layers grown under different growth conditions or with different compositions. The epitaxial layer 140 can be doped with dopants. For example, the epitaxial layer 140 can be doped with dopants of the same conductivity type as the substrate 101 or of the opposite conductivity type. The upper surface of the epitaxial layer 140 can be higher than the upper surface of the sacrificial layer 110 adjacent to the substrate 101, relative to the upper surface of the substrate 101.

[0081] Reference Figure 10 Vertical insulating elements 160 and first channel structures 151 can be sequentially formed on the inner sidewall of each channel hole CH in the channel hole CH.

[0082] Vertical insulating elements 160 can be conformally formed on the inner wall of each channel hole CH, the upper surface of the epitaxial layer 140, and the uppermost insulating layer 120. Then, a portion of the vertical insulating elements 160 on the upper surfaces of the epitaxial layer 140 and the uppermost insulating layer 120 can be removed using an anisotropic etching process, leaving the vertical insulating elements 160 on the inner wall of each channel hole CH. Therefore, the upper surface of the epitaxial layer 140 can be exposed.

[0083] The vertical insulator 160 can be formed by sequentially depositing a barrier layer 166, a charge storage layer 164, and a tunnel insulating layer 162. The vertical insulator 160 can be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0084] Subsequently, a first channel structure 151 can be formed by ALD or CVD. The first channel structure 151 can be formed on the vertical insulating member 160 and can contact the upper surface of the epitaxial layer 140. The first channel structure 151 can be formed on the upper surface of the uppermost insulating layer 120.

[0085] Reference Figure 11 A buried insulating layer 181' can be formed to fill each of the channel holes CH having a first channel structure 151.

[0086] A buried insulating layer 181' may be provided on the topmost insulating layer 120. For example, the buried insulating layer 181' may include silicon oxide, silicon nitride, and / or silicon oxynitride. In some example embodiments, the buried insulating layer 181' may be formed from spin-coated glass (SOG) material.

[0087] After that, the process of forming a second channel structure to realize a GIDL transistor can be performed. Figure 12A , Figure 12B , Figure 12C and Figure 12D This is a cross-sectional view illustrating the process of forming a second channel structure according to an exemplary embodiment of the inventive concept, and is... Figure 11 A magnified view of part "B".

[0088] Reference Figure 12A A portion of the buried insulation layer 181' can be removed to form a buried insulation pattern 181. The upper surface 181T of the buried insulation pattern 181 can be lowered to the horizontal level La by removing said portion of the buried insulation layer 181'.

[0089] The removal of the portion of the buried insulating layer 181' can be performed using an etch-back process. At this time, the portion of the buried insulating layer 181' on the uppermost insulating layer 120 can be removed. The horizontal La of the upper surface 181T of the buried insulating pattern 181 can be horizontally superimposed on the uppermost sacrificial layer 110G2 of the sacrificial layer 110, and the uppermost sacrificial layer 110G2 will be formed in subsequent processes as shown in the image. Figure 16 The upper gate electrode 132b of the second gate electrode 132 shown corresponds to that of the upper gate electrode 132 shown. The second uppermost sacrificial layer 110G1 may be the same as that formed in subsequent processes. Figure 16 The second gate electrode 132 shown corresponds to the sacrificial layer of the lower gate electrode 132a. In some example embodiments, the level La of the upper surface 181T of the buried insulating pattern 181 can be appropriately adjusted to form a channel region for generating the transistor GIDL.

[0090] Reference Figure 12B A portion of the first channel structure 151 can be removed, such that the top end 151T of the first channel structure 151 can be recessed lower than the upper surface 181T of the buried insulating pattern 181.

[0091] The channel region of the transistor used to generate GIDL can be determined. The horizontal La of the upper surface 181T of the buried insulating pattern 181 can be adjusted first, and then the top end 151T of the first channel structure 151 can be recessed so that the channel region of the transistor used to generate GIDL can be precisely defined.

[0092] Reference Figure 12C A second channel structure 152 can be formed on the inner wall of each channel hole CH in the channel hole CH to connect to the first channel structure 151.

[0093] A second channel structure 152 may be formed in the region from which the first channel structure 151 has been removed. The second channel structure 152 may be formed on the upper surface 181T of the buried insulating pattern 181. The second channel structure 152 may include a channel layer 152a serving as a channel region for a transistor and an intermediate horizontal layer 152b disposed on the upper surface 181T of the buried insulating pattern 181. The channel layer 152a of the second channel structure 152 may include an extension 152R formed in a region Rp recessed lower than the horizontal La of the upper surface 181T of the buried insulating pattern 181, and may be connected to the top end 151T of the first channel structure 151 via the extension 152R.

[0094] The second channel structure 152 may include a doped semiconductor material (e.g., doped polysilicon) and / or a semiconductor material having a smaller bandgap than the material of the first channel structure 151 (e.g., silicon-germanium (SiGe) and / or germanium (Ge)). The second channel structure 152 may be formed by depositing the doped semiconductor material or by depositing the semiconductor material and then doping the semiconductor material to a desired doping concentration.

[0095] Reference Figure 12D A buried conductive pattern 192 may be formed in each of the channel holes CH having the second channel structure 152, and at least the sidewalls of the buried conductive pattern 192 may be surrounded (covered) by the second channel structure 152.

[0096] A buried conductive pattern 192 can be formed within the space defined by the second channel structure 152. For example, the buried conductive pattern 192 can be formed on the sidewall of the second channel structure 152. An additional doping process can be performed on the buried conductive pattern 192 so that the buried conductive pattern 192 can be configured as a pad region. An additional buried insulating pattern 182 can be formed prior to forming the buried conductive pattern 192. For example, as... Figure 4 As shown, an additional buried insulating pattern (second buried insulating pattern) 182 can be formed in the lower part of the space defined by the second channel structure 152, and then a buried conductive pattern 192 can be formed on the additional buried insulating pattern 182 to achieve a double-pad region. It is understood that... Figure 12D The sectional view is Figure 13 An enlarged view of part "B" shown in the image.

[0097] Reference Figure 14 A planarization process can be performed to expose the upper surface of the top insulating layer 120. A first opening OP1 can be formed to pass through the sacrificial layer 110 and the insulating layer 120.

[0098] A planarization process can remove a portion of the second channel structure 152 on the uppermost insulating layer 120 and a portion of the buried conductive pattern 192 on the uppermost insulating layer 120. The planarization process can be performed using an etch-back process or a chemical mechanical polishing process. The vertical insulating element 160, the first channel structure 151, the second channel structure 152, and the buried insulating pattern 181 can form a vertical structure VS. A protective insulating layer 145 can be formed after the planarization process. The protective insulating layer 145 can protect the uppermost insulating layer 120, the buried conductive pattern 192, and the second channel structure 152 in subsequent etching processes. The first opening OP1 can be formed by using a photolithography process to form a mask layer and using the mask layer as an etching mask to anisotropically etch the sacrificial layer 110 and the insulating layer 120. The first opening OP1 can be a trench extending in the vertical direction (in the third direction Z). The first opening OP1 can expose a portion of the substrate 101.

[0099] Reference Figure 15 The sacrificial layer 110 exposed by the first opening OP1 can be removed by an etching process to form multiple lateral openings LP.

[0100] Multiple lateral openings LP can be defined between insulating layers 120 by removing the sacrificial layer 110.

[0101] Reference Figure 16 A horizontal insulating element 170, a first gate electrode 131, and a second gate electrode 132 can be formed in multiple lateral openings LP.

[0102] The horizontal insulator 170 can contact the vertical insulator 160 exposed in the horizontal opening LP.

[0103] The material of the horizontal insulating member 170 and the first gate electrode 131 and the second gate electrode 132 formed in the first opening OP1 can be removed to form the second opening OP2. As a result, a stacked structure SS including the insulating layer 120 and the first gate electrode 131 and the second gate electrode 132 can be formed separately through the second opening OP2. The second gate electrode 132 may include a lower gate electrode 132a and an upper gate electrode 132b above the lower gate electrode 132a.

[0104] Reference Figure 17 A common source region 105 can be formed by implanting a dopant into the substrate 101 exposed by the second opening OP2. Electrode separation patterns 107 can be formed on the common source region 105 and at each of the opposing sidewalls of the stacked structure SS. A spacer insulating layer 184 can be formed prior to forming the electrode separation patterns 107.

[0105] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made to the inventive concept without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A three-dimensional semiconductor device comprising: a substrate; a plurality of first gate electrodes sequentially stacked on the substrate, the plurality of first gate electrodes including gate electrodes constituting string selection transistors and gate electrodes constituting memory cell transistors; a second gate electrode on the plurality of first gate electrodes, the second gate electrode being a gate electrode constituting a gate-drain leakage transistor; a first channel structure extending through a portion of the second gate electrode and the plurality of first gate electrodes; a buried insulating pattern on sidewalls of the first channel structure, the buried insulating pattern having an upper surface at a level higher than a top end of the first channel structure; a second channel structure extending through a remaining portion of the second gate electrode, the second channel structure connected to the first channel structure; and a buried conductive pattern on sidewalls of the second channel structure, wherein the second gate electrode includes a plurality of second gate electrodes, and wherein the top end of the first channel structure is at a level higher than a lower surface of a lowermost second gate electrode of the plurality of second gate electrodes and lower than an upper surface of an uppermost second gate electrode of the plurality of second gate electrodes. the first channel structure includes an undoped semiconductor material, and 2. The three-dimensional semiconductor device according to claim 1, wherein the second channel structure includes a doped semiconductor material. the second channel structure includes a semiconductor material having a smaller band gap than a material of the first channel structure.

3. The three-dimensional semiconductor device according to claim 1, wherein the buried conductive pattern includes a doped semiconductor material.

4. The three-dimensional semiconductor device according to claim 1, wherein the second channel structure includes an intermediate level layer on the upper surface of the buried insulating pattern.

5. The three-dimensional semiconductor device of claim 1, wherein, 6. The three-dimensional semiconductor device of claim 5, further comprising an additional buried insulating pattern between the intermediate level layer and the buried conductive pattern, the buried conductive pattern includes a doped semiconductor material. wherein the upper surface of the buried insulating pattern is at a level that is the same as or higher than an upper surface of the second gate electrode.

7. The three-dimensional semiconductor device according to claim 1, wherein the first channel structure extends through some of the plurality of second gate electrodes adjacent to an uppermost first gate electrode of the plurality of first gate electrodes, and the second channel structure extends through a remaining portion of the plurality of second gate electrodes.

8. The three-dimensional semiconductor device according to claim 1, wherein, the upper surface of the buried insulating pattern is at a level lower than an upper surface of an uppermost second gate electrode of the plurality of second gate electrodes.

9. The three-dimensional semiconductor device according to claim 1, wherein, 10. A three-dimensional semiconductor device comprising: a substrate; a plurality of first gate electrodes sequentially stacked on the substrate; a second gate electrode including a lower gate electrode and an upper gate electrode sequentially stacked on the plurality of first gate electrodes; a first channel structure extending through a portion of the lower gate electrode and the plurality of first gate electrodes; a buried insulating pattern on sidewalls of the first channel structure, the buried insulating pattern having an upper surface at a level higher than a top end of the first channel structure; a second channel structure extending through a remaining portion of the second gate electrode, the second channel structure connected to the first channel structure; and a buried conductive pattern on sidewalls of the second channel structure, wherein the second gate electrode includes a plurality of second gate electrodes, and wherein the top end of the first channel structure is at a level higher than a lower surface of a lowermost second gate electrode of the plurality of second gate electrodes and lower than an upper surface of an uppermost second gate electrode of the plurality of second gate electrodes. a buried conductive pattern on a sidewall of the second channel structure, the buried conductive pattern being separated from the buried insulating pattern.

11. The three-dimensional semiconductor device of claim 10, wherein, the top end of the first channel structure is located at a level higher than a lower surface of the lower gate electrode and lower than an upper surface of the upper gate electrode.

12. The three-dimensional semiconductor device of claim 11, wherein, the top end of the first channel structure is located at a level higher than an upper surface of the lower gate electrode and lower than a lower surface of the upper gate electrode.

13. The three-dimensional semiconductor device of claim 12, wherein, the upper surface of the buried insulating pattern is located at a level overlapping with the upper gate electrode in a horizontal direction parallel to an upper surface of the substrate.

14. The three-dimensional semiconductor device of claim 10, wherein the upper surface of the buried insulating pattern is located at a level lower than a lower surface of the upper gate electrode and higher than an upper surface of the lower gate electrode, and the top end of the first channel structure is located at a level lower than the upper surface of the lower gate electrode.

15. The three-dimensional semiconductor device of claim 10, wherein the upper surface of the buried insulating pattern is located at a level the same as or higher than an upper surface of the upper gate electrode, and the top end of the first channel structure is located at a level lower than the upper surface of the upper gate electrode.

16. The three-dimensional semiconductor device of claim 10, wherein the first channel structure includes undoped polysilicon, and the second channel structure includes silicon germanium, germanium, or doped polysilicon.

17. The three-dimensional semiconductor device of claim 10, wherein, The thickness of the second trench structure is in the range of 30 to 100 .

18. A three-dimensional semiconductor device, the three-dimensional semiconductor device comprising: a substrate; a stack structure including a plurality of first gate electrodes stacked on the substrate, at least one second gate electrode on the plurality of first gate electrodes, and a channel hole passing through the plurality of first gate electrodes and the at least one second gate electrode; a first channel structure on an inner sidewall of the channel hole, the first channel structure overlapping with a first portion of the at least one second gate electrode and the plurality of first gate electrodes in a horizontal direction parallel to an upper surface of the substrate; a first buried insulating pattern in the channel hole and on a sidewall of the first channel structure, the first buried insulating pattern having an upper surface at a level higher than a top end of the first channel structure; a second channel structure on the inner sidewall of the channel hole and on the top end of the first channel structure, the second channel structure including a channel layer overlapping with a second portion of the at least one second gate electrode in the horizontal direction and an intermediate horizontal layer on the upper surface of the first buried insulating pattern; a second buried insulating pattern in the channel hole and on the intermediate horizontal layer of the second channel structure and a sidewall of the channel layer of the second channel structure; and a buried conductive pattern in the channel hole and on the sidewall of the second buried insulating pattern and the channel layer of the second channel structure. ​

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