Display device

Abstract

A display device according to an example embodiment of the present inventive concept includes a first pixel circuit portion including at least one transistor, a second pixel circuit portion including at least one transistor, a first pixel electrode electrically connected to the first pixel circuit portion, a second pixel electrode electrically connected to the second pixel circuit portion, a first data line electrically connected to the first pixel circuit portion, and a second data line electrically connected to the second pixel circuit portion, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel electrode overlaps the first data line and the second data line in a plan view.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0065232, filed on June 3, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device. Background Technology

[0003] Display devices are devices used to display images, and light-emitting diode (LED) displays have recently attracted attention as self-emitting display devices.

[0004] Unlike liquid crystal displays (LCDs), light-emitting diode (LED) displays have a self-emission characteristic that eliminates the need for a separate light source, allowing them to be manufactured thinner and lighter. Furthermore, LED displays offer high-quality characteristics such as low power consumption, high brightness, and fast response times.

[0005] Generally, a light-emitting diode (LED) display comprises multiple pixels, each pixel including multiple transistors and a light-emitting element. Each of the multiple transistors is connected to a corresponding signal line and can transmit drive current to the corresponding light-emitting element. The transistors may include active patterns comprising channel regions and conductive regions.

[0006] The light-emitting element may include an anode and a cathode, with the anode connected to a transistor in the pixel to receive drive current.

[0007] The information disclosed in this background section is only intended to enhance the understanding of the background of the inventive concept, and therefore may contain information that does not constitute prior art known to a person skilled in the art in this country. Summary of the Invention

[0008] This disclosure improves display quality by reducing the capacitance of parasitic capacitors between the pixel electrodes of multiple pixels in a display device and the data lines, or by reducing deviations.

[0009] A display device according to an exemplary embodiment of the present invention includes: a first pixel circuit section including at least one transistor comprising a first transistor; a second pixel circuit section including at least one transistor comprising a second transistor; a first pixel electrode electrically connected to the first pixel circuit section; a second pixel electrode electrically connected to the second pixel circuit section; a first data line electrically connected to the first pixel circuit section; and a second data line electrically connected to the second pixel circuit section, wherein the first data line and the second data line are arranged adjacent to each other along a first direction, and the second pixel circuit section is superimposed on the first data line and the second data line in a plan view.

[0010] The first pixel circuit section and the second pixel circuit section can be arranged along a second direction perpendicular to the first direction.

[0011] The first pixel electrode and the second pixel electrode can be arranged along the first direction.

[0012] The first pixel electrode and the second pixel electrode can be arranged along the second direction.

[0013] The second pixel electrode may be superimposed on at least a portion of the first data line and the second data line, and the first pixel electrode may not be superimposed on the first data line and the second data line.

[0014] It may also include a first capacitor electrode in a first pixel circuit section and a second capacitor electrode in a second pixel circuit section disposed in the same conductive layer as the first data line and the second data line. The first pixel electrode may be electrically connected to the first transistor via the first capacitor electrode, and the second pixel electrode may be electrically connected to the second transistor via the second capacitor electrode. The first data line and the second data line may be disposed on the same side of the first capacitor electrode and the second capacitor electrode.

[0015] It may also include: a third pixel circuit section including at least one transistor; and a third pixel electrode electrically connected to the third pixel circuit section, wherein in a plan view, the third pixel circuit section is arranged along a second direction with the first pixel circuit section and the second pixel circuit section, and the third pixel electrode is arranged along a first direction with the first pixel electrode and the second pixel electrode.

[0016] The second pixel electrode may be superimposed on at least a portion of the first data line and the second data line, and has the smallest area among the first pixel electrode, the second pixel electrode and the third pixel electrode.

[0017] The second pixel electrode can be the blue pixel electrode.

[0018] The second pixel electrode can have the largest area among the first pixel electrode, the second pixel electrode, and the third pixel electrode.

[0019] The second pixel electrode can be the red pixel electrode.

[0020] The second pixel electrode can be stacked with the first data line, the second data line, and the third data line.

[0021] A display device according to an exemplary embodiment of the present invention includes: a first pixel circuit portion including a first transistor; a second pixel circuit portion including a second transistor; a first data line electrically connected to the first pixel circuit portion; a second data line electrically connected to the second pixel circuit portion; a first pixel electrode electrically connected to the first pixel circuit portion; a second pixel electrode electrically connected to the second pixel circuit portion; an emission layer disposed on the first pixel electrode and the second pixel electrode; and a common electrode disposed on the emission layer, wherein, in a plan view, the first pixel circuit portion and the second pixel circuit portion are arranged along a first direction, and the first pixel electrode and the second pixel electrode are arranged along the first direction, the first data line and the second data line are arranged adjacent to each other along a second direction different from the first direction, and the first pixel electrode and the second pixel electrode are respectively superimposed on at least one of the first data line and the second data line in the plan view.

[0022] The area of ​​the first pixel electrode can be different from the area of ​​the second pixel electrode.

[0023] It may also include a first capacitor electrode in a first pixel circuit section and a second capacitor electrode in a second pixel circuit section disposed in the same conductive layer as the first data line and the second data line. The first pixel electrode may be electrically connected to the first transistor via the first capacitor electrode, and the second pixel electrode may be electrically connected to the second transistor via the second capacitor electrode.

[0024] It may also include a first gate electrode contained in a first transistor and a second gate electrode contained in a second transistor. The first gate electrode may form a first capacitor together with a first capacitor electrode, and the second gate electrode may form a second capacitor together with a second capacitor electrode. The first capacitor and the second capacitor may be arranged along a first direction, and in a plan view, the first data line and the second data line may be located on the same side of the first capacitor and the second capacitor.

[0025] It may also include: a third pixel circuit section including a third transistor; and a third pixel electrode electrically connected to the third pixel circuit section, wherein the third pixel circuit section may be arranged along a first direction with the first pixel circuit section and the second pixel circuit section, the third pixel electrode may be arranged along the first direction with the first pixel electrode and the second pixel electrode, and the third pixel electrode may be superimposed on at least one of the first data line and the second data line.

[0026] A display device according to an exemplary embodiment of the present invention includes: a plurality of pixel circuit sections arranged along a first direction; a plurality of data lines arranged along a second direction different from the first direction and adjacent to each other; a plurality of pixel electrodes electrically connected to the plurality of pixel circuit sections respectively; an emission layer disposed on the plurality of pixel electrodes; and a common electrode disposed on the emission layer, wherein the plurality of data lines are disposed on one side of the plurality of pixel circuit sections, and at least one of the plurality of pixel electrodes is superimposed on at least one of the plurality of data lines in a plan view.

[0027] Multiple pixel electrodes can be arranged along the second direction, and at least one pixel electrode is superimposed on multiple data lines in the planar view.

[0028] At least one pixel electrode can be completely superimposed on multiple data lines in a planar diagram.

[0029] According to exemplary embodiments of the present disclosure, the capacitance of parasitic capacitors between pixel electrodes and data lines of a plurality of pixels in a display device can be reduced or the deviation can be reduced, thereby improving display quality. Attached Figure Description

[0030] Figure 1 This is a circuit diagram of a pixel of a display device according to an exemplary embodiment of the present invention.

[0031] Figure 2 This is a planar layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.

[0032] Figure 3 This is a plan view of the pixel electrode layer and multiple data lines of a display device according to an exemplary embodiment of the present invention.

[0033] Figure 4 It is intercepted along line IVa-IVb. Figure 2 The cross-sectional view of the display device shown.

[0034] Figure 5 This is a planar layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.

[0035] Figure 6 This is a plan view of the pixel electrode layer and multiple data lines of a display device according to an exemplary embodiment of the present invention.

[0036] Figure 7 This is a planar layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.

[0037] Figure 8This is a plan view of the pixel electrode layer and multiple data lines of a display device according to an exemplary embodiment of the present invention.

[0038] Figure 9 This is a planar layout diagram of the pixel electrode layer and multiple data lines of a display device according to an exemplary embodiment of the present invention, and

[0039] Figure 10 This is a cross-sectional view of a display device according to an exemplary embodiment of the present invention. Detailed Implementation

[0040] In the following detailed description, only certain exemplary embodiments of the inventive concept have been shown and described by way of illustration only. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the inventive concept.

[0041] In order to clearly describe the inventive concept, parts or elements not related to the description herein have been omitted. Throughout the specification, the same or similar constituent elements are indicated by the same reference numerals.

[0042] Furthermore, for better understanding and ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are arbitrarily illustrated, but the inventive concept is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0043] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on said other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in the specification, the terms "on" or "above" specify a location on or below the target portion and do not necessarily refer to a location positioned on the upper side of the target portion based on the direction of gravity.

[0044] Furthermore, unless explicitly stated otherwise, the word “including” and its variations shall be understood to mean that the stated element is included but not excluded any other element.

[0045] Throughout this specification and claims, a plan view refers to a view of a surface parallel to two intersecting directions (e.g., directions DR1 and DR2), and a sectional view refers to a view of a surface cut in a direction perpendicular to the surfaces parallel to directions DR1 and DR2 (e.g., direction DR3). Furthermore, unless otherwise stated, stacking two constituent elements means stacking two constituent elements in direction DR3 (e.g., a direction perpendicular to the upper surface of the substrate).

[0046] First, refer to Figure 1 The structure of a display device according to an exemplary embodiment of the present invention is described.

[0047] Figure 1 This is a circuit diagram of a pixel PX of a display device according to an exemplary embodiment of the present invention.

[0048] A display device according to an exemplary embodiment of the present invention includes a plurality of pixels PX, and each of the plurality of pixels PX may include a pixel circuit and at least one light-emitting diode (LED) as a light-emitting element connected to the pixel circuit. The pixel circuit includes a plurality of transistors T1, T2, and T3 and a capacitor Cst. In this exemplary embodiment, a pixel PX includes one light-emitting diode (LED) ED.

[0049] The plurality of transistors T1, T2, and T3 include a first transistor T1, a second transistor T2, and a third transistor T3. The source electrode and the drain electrode are electrodes disposed on the corresponding sides of the channel of each transistor T1, T2, and T3, and the terms are interchangeable.

[0050] The gate electrode G1 of the first transistor T1 is connected to one terminal of the capacitor Cst, the source electrode S1 of the first transistor T1 is connected to the drive voltage line for transmitting the drive voltage ELVDD, and the drain electrode D1 of the first transistor T1 is connected to the anode of the light-emitting diode (LED) ED and the other terminal of the capacitor Cst. The first transistor T1 receives the data voltage DAT in response to the switching operation of the second transistor T2, and can supply drive current to the light-emitting diode (LED) ED according to the voltage stored in the capacitor Cst.

[0051] The gate electrode G2 of the second transistor T2 is connected to the first scan line that transmits the first scan signal SC. The source electrode S2 of the second transistor T2 is connected to a data line that can transmit the data voltage DAT or the reference voltage. The drain electrode D2 of the second transistor T2 is connected to one terminal of the capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 can be turned on in response to the first scan signal SC to transmit the reference voltage or the data voltage DAT to the gate electrode G1 of the first transistor T1 and one terminal of the capacitor Cst.

[0052] The gate electrode G3 of the third transistor T3 is connected to the second scan line that transmits the second scan signal SS. The source electrode S3 of the third transistor T3 is connected to the other terminal of the capacitor Cst, the drain electrode D1 of the first transistor T1, and the anode of the light-emitting diode (LED) ED. The drain electrode D3 of the third transistor T3 is connected to the initialization voltage line that transmits the initialization voltage INIT. The third transistor T3 turns on in response to the second scan signal SS to transmit the initialization voltage INIT to the other terminal of the capacitor Cst and the anode of the light-emitting diode (LED) ED, thereby initializing the voltage at the anode of the light-emitting diode (LED) ED.

[0053] One terminal of capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other terminal is connected to the source electrode S3 of the third transistor T3 and the anode of the light-emitting diode (LED) ED. The cathode of the LED ED is connected to the common voltage line that transmits the common voltage ELVSS.

[0054] A light-emitting diode (LED) can emit light with a brightness determined by the drive current generated by a first transistor T1.

[0055] describe Figure 1 The circuit shown is an example of operation, specifically an example of operation during one frame. In this example, transistors T1, T2, and T3 are N-channel transistors, but the types of transistors T1, T2, and T3 are not limited to this.

[0056] At the start of a frame, during the initialization period, a high-level second scan signal SS and a high-level first scan signal SC are supplied, and the second transistor T2 and the third transistor T3 are turned on. A reference voltage from the data line is supplied via the turned-on second transistor T2 to the gate electrode G1 of the first transistor T1 and one terminal of the capacitor Cst, while the initialization voltage INIT is supplied via the turned-on third transistor T3 to the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode (LED) ED. Therefore, during the initialization period, the drain electrode D1 of the first transistor T1 and the anode of the LED ED are initialized using the initialization voltage INIT. During the initialization period, the capacitor Cst stores the voltage difference between the reference voltage and the initialization voltage INIT.

[0057] Then, during the sensing period, the second scan signal SS drops to a low level to turn off the third transistor T3, while the first scan signal SC remains high to keep the second transistor T2 on. The gate electrode G1 of the first transistor T1 and one terminal of the capacitor Cst maintain a reference voltage via the on-state second transistor T2, while the drain electrode D1 of the first transistor T1 and the anode of the light-emitting diode (LED) ED are disconnected from the initialization voltage INIT via the off-state third transistor T3. Therefore, the first transistor T1 is on, and current flows from the source electrode S1 to the drain electrode D1 until the voltage at the drain electrode D1 becomes the "reference voltage - Vth", where Vth represents the threshold voltage of the first transistor T1. During the sensing period, the voltage difference between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is stored in the capacitor Cst, completing the sensing of the threshold voltage (Vth) of the first transistor T1. Because a compensation data signal is supplied to the gate electrode G1 of the first transistor T1, characteristic deviations of the first transistor T1, which may vary between pixels, can be externally compensated.

[0058] Next, during the data input period, a high-level first scan signal SC is supplied to the second transistor T2 to turn it on, and a low-level second scan signal SS is supplied to the third transistor T3 to turn it off. The data voltage DAT from the data line is supplied via the turned-on second transistor T2 to one terminal of capacitor Cst and the gate electrode G1 of the first transistor T1. During the data input period, because the first transistor T1 is in the off state, the anode of the light-emitting diode (LED) ED and the drain electrode D1 of the first transistor T1 can be maintained substantially at the same potential as during the sensing period.

[0059] Next, during the light-emitting period, the first transistor T1, which is turned on by the data voltage DAT transmitted to the gate electrode G1, generates a drive current according to the data voltage DAT, and the light-emitting diode (LED) ED emits light according to the drive current.

[0060] Reference Figures 2 to 4 as well as Figure 1 The detailed structure of a display device according to an exemplary embodiment of the present invention is described.

[0061] Figure 2 This is a planar layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention. Figure 3 This is a plan view of the pixel electrode layer and multiple data lines of a display device according to an exemplary embodiment of the present invention. Figure 4 It is intercepted along line IVa-IVb. Figure 2 The cross-sectional view of the display device shown.

[0062] Here, each of the multiple pixel circuit sections PX1, PX2 and PX3 can be a portion or region in which multiple transistors T1, T2, T3 and capacitor Cst are formed in the constituent elements included in the aforementioned pixel PX.

[0063] The display device according to an exemplary embodiment may include a substrate 110. The substrate 110 may include an insulating material such as glass or plastic, and may be flexible.

[0064] A first conductive layer, including a lower pattern 111 and a lateral common voltage line 170a, can be disposed on the substrate 110. Each lower pattern 111 can be disposed at each pixel circuit portion PX1, PX2, and PX3 to overlap with the pixel circuit portions PX1, PX2, and PX3. The lateral common voltage line 170a can extend substantially in the first direction DR1. The lower pattern 111 can include various conductive metals or semiconductor materials with conductive properties.

[0065] The buffer layer 120, which serves as an insulating layer, can be disposed on the first conductive layer.

[0066] An active layer comprising multiple active patterns 130a, 130b, and 130c may be disposed on the buffer layer 120. The active patterns 130a, 130b, and 130c disposed in each of the pixel circuit sections PX1, PX2, and PX3 may include channel regions 134a, 134b, and 134c for forming each channel of the multiple transistors T1, T2, and T3, and conductive regions connected to the channel regions 134a, 134b, and 134c. The conductive regions of each of the active patterns 130a, 130b, and 130c may include source regions 133a, 133b, and 133c and drain regions 135a, 135b, and 135c for each transistor T1, T2, and T3.

[0067] The multiple active patterns 130a, 130b, and 130c disposed in the pixel circuit sections PX1, PX2, and PX3 can be separated from each other, but the construction of the multiple active patterns 130a, 130b, and 130c is not limited thereto. For example, active patterns 130a and active patterns 130c can be connected to each other. Figure 2 An example is shown in which active pattern 130a and active pattern 130c are separated from each other.

[0068] The active layer may include semiconductor materials such as amorphous silicon, polycrystalline silicon, and oxide semiconductors.

[0069] The insulating pattern 144 of the first insulating layer can be disposed on the active layer. The insulating pattern 144 overlaps with the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c, and can be disposed above the channel regions 134a, 134b, and 134c. The insulating pattern 144 may not overlap substantially with the conductive regions of the active patterns 130a, 130b, and 130c.

[0070] The second conductive layer can be disposed on the insulating pattern 144.

[0071] The second conductive layer may include a first scan line 151 capable of transmitting the first scan signal SC, a second scan line 152 capable of transmitting the second scan signal SS, a driving gate electrode 155, a second gate electrode 154b, and a third gate electrode 154c. Gate electrodes G1, G2, and G3 in the circuit diagram above may correspond to the first gate electrode 154a, the second gate electrode 154b, and the third gate electrode 154c included in the driving gate electrode 155, respectively. The driving gate electrode 155 may be referred to as the first gate electrode.

[0072] The first scan line 151 and the second scan line 152 can extend in the first direction DR1, respectively. The first scan line 151 and the second scan line 152 can be disposed above and below a group of pixel circuit sections including pixel circuit sections PX1, PX2 and PX3.

[0073] Each driving gate electrode 155 can be positioned corresponding to each pixel circuit section PX1, PX2, and PX3. The driving gate electrode 155 disposed at each pixel circuit section PX1, PX2, and PX3 may include a first gate electrode 154a protruding above or below and a protrusion 155a protruding below or above. The first gate electrode 154a intersects with the active pattern 130a and overlaps with the channel region 134a of the active pattern 130a.

[0074] Multiple second gate electrodes 154b corresponding to multiple pixel circuit sections PX1, PX2, and PX3 can be connected to each other and formed as a whole extending in the second direction DR2 and connected to the first scan line 151. The second gate electrodes 154b intersect with the active pattern 130b of each pixel circuit section PX1, PX2, and PX3 and are superimposed with the channel region 134b of the active pattern 130b.

[0075] Multiple third gate electrodes 154c corresponding to multiple pixel circuit units PX1, PX2, and PX3 can be connected to each other and formed as a whole extending in the second direction DR2 and connected to the second scan line 152. The third gate electrodes 154c intersect with the active pattern 130c of each of the pixel circuit units PX1, PX2, and PX3, and are superimposed with the channel region 134c of the active pattern 130c.

[0076] The second conductive layer may also include a conductive pattern 150a superimposed on the common voltage line 170, which will be described later.

[0077] The second insulating layer 160 may be disposed above the second conductive layer. The buffer layer 120 and / or the second insulating layer 160 may include a plurality of contact holes 60, 61, 62, 63a, 63b, 64, 65, 66 and 68.

[0078] The third conductive layer may be disposed on the second insulating layer 160. The third conductive layer based on a group of multiple pixel circuit sections PX1, PX2 and PX3 may include multiple data lines 171a, 171b and 171c, a driving voltage line 172, a common voltage line 170, an initialization voltage line 173, a capacitor electrode 175 and multiple connecting members 178.

[0079] The common voltage line 170 can be electrically connected to the transverse common voltage line 170a through the contact hole 60 of the second insulating layer 160. The conductive pattern 150a of the second conductive layer can be electrically connected to the common voltage line 170 through the contact hole 60a of the second insulating layer 160 to provide an additional conductive path to reduce the resistance of the common voltage line 170. The conductive pattern 150a can be omitted.

[0080] The driving voltage line 172 is electrically connected to the source region 133a of the active pattern 130a through the contact hole 61 of the second insulating layer 160.

[0081] The initialization voltage line 173 is electrically connected to the drain region 135c of the active pattern 130c through the contact hole 63a of the second insulating layer 160.

[0082] Multiple data lines 171a, 171b, and 171c can be arranged on the first side of pixel circuit sections PX1, PX2, and PX3, and configured to be adjacent to each other in the first direction DR1. There may be no third conductive layer between the multiple data lines 171a, 171b, and 171c. Each data line 171a, 171b, and 171c is electrically connected to the source region 133b of the active pattern 130b through a contact hole 64 in the second insulating layer 160. Figure 2 and Figure 3 As shown, each data line 171a, 171b and 171c can be bent at least once.

[0083] Each pixel circuit section PX1, PX2, and PX3 may have an island-shaped capacitor electrode 175. The capacitor electrode 175 may be disposed in a planar view between the driving voltage line 172 and the data lines 171a, 171b, and 171c. The capacitor electrode 175 may be stacked with a corresponding driving gate electrode 155, and a second insulating layer 160 is disposed between the driving gate electrode 155 and the capacitor electrode 175 to form a capacitor Cst. The driving gate electrode 155 is the first capacitor electrode, and the capacitor electrode 175 is the second capacitor electrode.

[0084] The capacitor electrode 175 is electrically connected to the drain region 135a of the active pattern 130a through the contact hole 62 of the second insulating layer 160, and is electrically connected to the source region 133c of the active pattern 130c through the contact hole 63b of the second insulating layer 160. Furthermore, the capacitor electrode 175 is electrically connected to the lower pattern 111 through the contact hole 68 of the second insulating layer 160 and the buffer layer 120. For contact between the capacitor electrode 175 and the drain region 135a of the active pattern 130a, the drive gate electrode 155 may include an opening 55a overlapping the contact hole 62, such that the drive gate electrode 155 may have a shape surrounding the periphery of the contact hole 62, however, it is not limited thereto.

[0085] The connecting member 178 is electrically connected to the drain region 135b of the active pattern 130b through the contact hole 65 in each of the pixel circuit sections PX1, PX2 and PX3, and is electrically connected to the protrusion 155a of the drive gate electrode 155 through the contact hole 66. As a result, the drain region 135b of the active pattern 130b and the protrusion 155a of the drive gate electrode 155 can be electrically connected to each other.

[0086] In the plan view, data lines 171a, 171b, and 171c, drive voltage line 172, common voltage line 170, and initialization voltage line 173 can extend along the second direction DR2, thereby intersecting with the first scan line 151 and the second scan line 152. Multiple data lines 171a, 171b, and 171c, drive voltage line 172, and initialization voltage line 173 can be positioned between two adjacent common voltage lines 170.

[0087] Figure 2 The multiple pixel circuit units PX1, PX2, and PX3 shown are arranged adjacent to each other on the second direction DR2 and can be repeatedly arranged on the first direction DR1 and the second direction DR2. The common voltage line 170 can be respectively provided on the left and right sides of the multiple pixel circuit units PX1, PX2, and PX3, and the first scan line 151 and the second scan line 152 can be respectively provided on the upper and lower sides of the multiple pixel circuit units PX1, PX2, and PX3.

[0088] If a repeating group of multiple pixel circuit sections PX1, PX2, and PX3 includes three pixel circuit sections PX1, PX2, and PX3, then three data lines 171a, 171b, and 171c, one driving voltage line 172, and one initialization voltage line 173 can be set between two adjacent common voltage lines 170.

[0089] At least one of the first, second, and third conductive layers is made of at least one metal or an alloy thereof, such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), or tantalum (Ta). Each of the first, second, and third conductive layers may comprise a single layer or multiple layers. For example, the third conductive layer may have a multilayer structure comprising a lower layer containing titanium and an upper layer containing copper.

[0090] The first transistor T1 includes a channel region 134a, a source region 133a, a drain region 135a, and a first gate electrode 154a. The source region 133a of the first transistor T1 can be electrically connected to the drive voltage line 172 to receive the drive voltage.

[0091] The lower pattern 111 corresponding to the first transistor T1 is superimposed on the channel region 134a between the first transistor T1 and the substrate 110 to prevent external light from reaching the channel region 134a, thereby reducing leakage current and preventing the characteristics of the first transistor T1 from deteriorating. The lower pattern 111 is electrically connected to the drain region 135a of the first transistor T1 via the capacitor electrode 175.

[0092] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 in each of the pixel circuit sections PX1, PX2, and PX3 is electrically connected to data lines 171a, 171b, and 171c, respectively, to receive data voltage or a reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a via the drive gate electrode 155.

[0093] The third transistor T3 includes a channel region 134c, a source region 133c, a drain region 135c, and a third gate electrode 154c. The drain region 135c of the third transistor T3 can receive an initialization voltage from the initialization voltage line 173.

[0094] The third insulating layer 180 may be disposed on the third conductive layer. The third insulating layer 180 may have a plurality of contact holes 71a, 72a, 73a, 74a, 75a, 76a and 77a disposed on the third conductive layer.

[0095] A fourth conductive layer may be disposed on the third insulating layer 180. The fourth conductive layer may include a plurality of conductive patterns having a planar shape similar to the planar shape of the conductive patterns of the third conductive layer (such as data lines 171a, 171b and 171c, drive voltage line 172, common voltage line 170, initialization voltage line 173 and capacitor electrode 175 disposed in the third conductive layer below) and electrically connected to the conductive patterns of the corresponding third conductive layer.

[0096] For example, data lines 171a, 171b, and 171c can be connected to corresponding conductive patterns in the fourth conductive layer through contact holes 74a, 75a, and 76a, respectively; drive voltage line 172 can be connected to corresponding conductive pattern 183a in the fourth conductive layer through contact hole 71a; common voltage line 170 can be connected to corresponding conductive pattern in the fourth conductive layer through contact hole 72a; initialization voltage line 173 can be connected to corresponding conductive pattern in the fourth conductive layer through contact hole 73a; and capacitor electrode 175 can be connected to corresponding conductive pattern 183b in the fourth conductive layer through contact hole 77a.

[0097] The conductive pattern of the fourth conductive layer can reduce the resistance of data lines 171a, 171b and 171c, drive voltage line 172, common voltage line 170, initialization voltage line 173 and capacitor electrode 175 by forming additional conductive paths.

[0098] The fourth insulating layer 181 may be disposed on the fourth conductive layer. The fourth insulating layer 181 may include contact holes 80 disposed on the conductive pattern 183b connected to the capacitor electrode 175 and contact holes 81 disposed on the common voltage line 170.

[0099] A fifth conductive layer comprising multiple contact pads (contact members) 190a, 190b, 190c and 190d may be disposed on the fourth insulating layer 181.

[0100] Each of the contact pads 190a, 190b, and 190c can be disposed at each of the pixel circuit sections PX1, PX2, and PX3, and can contact and be electrically connected to the corresponding conductive pattern 183b through the contact hole 80. Therefore, each of the contact pads 190a, 190b, and 190c can be electrically connected to the capacitor electrode 175 electrically connected to the conductive pattern 183b, respectively.

[0101] Contact pad 190d can make contact with and be electrically connected to common voltage line 170 through contact hole 81.

[0102] Contact pads 190a, 190b, 190c, and 190d can improve the adhesion between the conductive pattern of the fourth conductive layer that is in contact with each other and another conductive layer, and prevent oxidation of the fourth conductive layer.

[0103] Specifically, when the fourth conductive layer contains copper, it can prevent the oxidation of copper. For this purpose, the fifth conductive layer can include a conductive material that can prevent corrosion of the fourth conductive layer; for example, if the fourth conductive layer contains copper, then the conductive material can prevent copper corrosion by covering the fourth conductive layer. For example, the fifth conductive layer can include a conductive material such as a metal oxide (such as ITO or IZO).

[0104] The fifth insulating layer 182 may be disposed on the fifth conductive layer. The fifth insulating layer 182 may include contact holes 83 disposed on each of the contact pads (contact members) 190a, 190b and 190c.

[0105] In plan and sectional views, the center of contact hole 83 may not be the same as the center of contact hole 80. Contact hole 83 and contact hole 80 may not overlap each other in plan views, or they may partially overlap.

[0106] Contact holes 83 and 80 can be stacked with corresponding contact pads (contact members) 190a, 190b and 190c for each pixel circuit part PX1, PX2 and PX3.

[0107] At least one of the buffer layer 120, the first insulating layer 144, the second insulating layer 160, the third insulating layer 180, the fourth insulating layer 181, and the fifth insulating layer 182 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x Inorganic insulating materials such as silicon oxynitride (SiON) and / or organic insulating materials. Specifically, the fifth insulating layer 182 may include inorganic insulating materials and / or organic insulating materials such as polyimide, acrylic polymers, siloxane polymers, etc., and may have a substantially flat upper surface.

[0108] A pixel electrode layer comprising multiple pixel electrodes 191a, 191b, and 191c, serving as the sixth conductive layer, can be disposed on the fifth insulating layer 182.

[0109] Reference Figure 2 and Figure 3In the planar view, multiple pixel circuit sections PX1, PX2, and PX3 (or the first transistors T1 of multiple pixel circuit sections PX1, PX2, and PX3) of a repeating group are arranged on the second direction DR2. Multiple pixel electrodes 191c, 191b, and 191a corresponding to pixel circuit sections PX1, PX2, and PX3 can be arranged adjacent to each other and substantially on the first direction DR1. However, the arrangement and structure of the pixel circuit sections PX1, PX2, and PX3 and the corresponding pixel electrodes 191c, 191b, and 191a are not limited to this. The planar dimensions and shapes of the pixel electrodes 191a, 191b, and 191c can differ from each other, but are not limited to this.

[0110] Multiple pixel electrodes 191a, 191b, and 191c are electrically connected to contact pads (contact members) 190c, 190b, and 190a, which are electrically connected to capacitor electrode 175, through contact holes 83 in the fifth insulating layer 182. Each pixel electrode 191a, 191b, and 191c is electrically connected to the drain region 135a of the first transistor T1 via contact pads 190c, 190b, and 190a, conductive pattern 183b, and capacitor electrode 175, thereby receiving voltage from the first transistor T1.

[0111] For example, pixel electrode 191a can be connected to the first transistor T1 of pixel circuit section PX3, pixel electrode 191b can be connected to the first transistor T1 of pixel circuit section PX2, and pixel electrode 191c can be connected to the first transistor T1 of pixel circuit section PX1.

[0112] In a planar diagram, a portion of the plurality of pixel electrodes 191a, 191b, and 191c may be superimposed on at least a portion of the plurality of adjacent data lines 171a, 171b, and 171c. For example, as Figures 2 to 4 As shown, one of the plurality of pixel electrodes 191a, 191b, and 191c may be superimposed on at least a portion of the plurality of adjacent data lines 171a, 171b, and 171c. Specifically, Figures 2 to 4 The exemplary embodiment shown illustrates an example in which only one of the plurality of pixel electrodes 191a, 191b and 191c overlaps with at least a portion of the plurality of data lines 171a, 171b and 171c that are adjacent to each other, and the remaining pixel electrodes 191a and 191b do not overlap with the plurality of data lines 171a, 171b and 171c.

[0113] In detail, such as Figure 3As shown, pixel electrode 191c overlaps with the entire width of the first direction DR1 of one of the multiple adjacent data lines 171a, 171b, and 171c, and may overlap or not overlap with a portion of the width of the first direction DR1 of each of the remaining data lines 171a and 171c. According to another exemplary embodiment, pixel electrode 191c may overlap with the entire width of the first direction DR1 of each of two of the multiple adjacent data lines 171a, 171b, and 171c, and may overlap or not overlap with a portion of the width of the first direction DR1 of the remaining data lines. According to another exemplary embodiment, pixel electrode 191c may overlap with the entire width of the first direction DR1 of the multiple adjacent data lines 171a, 171b, and 171c. According to another exemplary embodiment, pixel electrode 191c overlaps with a portion of the width of the first direction DR1 of each of two of the adjacent data lines 171a, 171b, and 171c, and may not overlap with the remaining data lines.

[0114] The pixel electrode 191c, which is superimposed on at least a portion of the multiple data lines 171a, 171b and 171c, can have the smallest planar area among the multiple pixel electrodes 191a, 191b and 191c.

[0115] The pixel electrode layer may include a semi-transmissive conductive material or a reflective conductive material.

[0116] The sixth insulating layer 350 may be disposed on the fifth insulating layer 182. The sixth insulating layer 350 has openings 355a, 355b and 355c respectively disposed on the pixel electrodes 191a, 191b and 191c.

[0117] The sixth insulating layer 350 may include organic insulating materials such as polyacrylic resins, polyimide resins, etc.

[0118] An emissive layer 370 may be disposed on the sixth insulating layer 350 and the pixel electrode layer. The emissive layer 370 may include portions disposed within openings 355a, 355b, and 355c of the sixth insulating layer 350. The emissive layer 370 may include an organic or inorganic emissive material. As shown, the emissive layer 370 may include a portion disposed above the sixth insulating layer 350. In an exemplary embodiment, at least a portion of the sixth insulating layer 350 may not be covered by the emissive layer 370.

[0119] The sixth insulating layer 350 and the emission layer 370 may include contact holes 82 disposed on the contact pad (contact member) 190d.

[0120] A common electrode 270 is disposed on the emitter layer 370. The common electrode 270 can be continuously formed on multiple pixel circuit sections PX1, PX2, and PX3. The common electrode 270 can be electrically connected to the common voltage line 170 through the contact hole 82 via the contact pad 190d, thereby receiving the common voltage.

[0121] The common electrode 270 may include a conductive transparent material.

[0122] Each of pixel electrodes 191a, 191b, and 191c, together with the emitter layer 370 and the common electrode 270, forms a light-emitting diode (ED). One of the pixel electrodes 191a, 191b, and 191c and the common electrode 270 serves as the cathode, and the other as the anode. In the previous example, pixel electrodes 191a, 191b, and 191c were anodes.

[0123] In the plan view, the areas with openings 355a, 355b and 355c of the sixth insulating layer 350 can define the light-emitting area of ​​each pixel.

[0124] Reference Figure 2 and Figure 3 The multiple openings 355a, 355b and 355c corresponding to the multiple pixel electrodes 191a, 191b and 191c respectively connected to a group of multiple pixel circuit sections PX1, PX2 and PX3 can be arranged adjacent to each other in the first direction DR1.

[0125] According to an exemplary embodiment, in a planar view, among the plurality of pixel electrodes 191a, 191b, and 191c, pixel electrode 191a has the largest area, and pixel electrode 191c has the smallest area. Therefore, in a planar view, among the plurality of openings 355a, 355b, and 355c, the opening 355a provided on pixel electrode 191a has the largest area, and the opening 355c provided on pixel electrode 191c has the smallest area. In this case, the light-emitting area corresponding to pixel electrode 191a can be red, the light-emitting area corresponding to pixel electrode 191b can be green, and the light-emitting area corresponding to pixel electrode 191c can be blue.

[0126] Since the lower pattern 111 is electrically connected to the pixel electrodes 191a, 191b, and 191c via the capacitor electrode 175 and is also superimposed on the channel region 134a of the first transistor T1, the current variation in the saturation region of the voltage-current characteristic of the first transistor T1 is reduced, thus widening the region where the first transistor T1 has a constant output. Therefore, even with changes in the source-drain voltage Vds of the first transistor T1, the output current of the first transistor T1 remains constant, thereby improving the output saturation characteristics. Consequently, the brightness deviation between pixels caused by the deviation in the output current of the first transistor T1 is reduced, thereby improving image quality.

[0127] In accordance with exemplary embodiments of the present invention, such as Figure 2 and Figure 3 As shown, multiple pixel electrodes 191c, 191b, and 191a corresponding to a group of pixel circuit sections PX1, PX2, and PX3 arranged on the second direction DR2, and multiple openings 355c, 355b, and 355a (i.e., multiple light-emitting diodes (LEDs)) corresponding to the multiple pixel electrodes 191c, 191b, and 191a can be arranged along the first direction DR1. Therefore, even in high-resolution display devices, the efficiency of pixel arrangement (referred to as layout) can be increased.

[0128] Because the display device has a high resolution, the area of ​​pixel electrodes 191a, 191b, and 191c is reduced. Therefore, the capacitance of the storage capacitor is reduced. This reduction in capacitance may cause fluctuations in the voltage of pixel electrodes 191a, 191b, and 191c, potentially leading to deviations in the drive current of the light-emitting diode (LED). Specifically, similar to this exemplary embodiment, when only a portion of the plurality of pixel electrodes 191a, 191b, and 191c is superimposed on the plurality of data lines 171a, 171b, and 171c, the voltage of the pixel electrodes superimposed on the data lines 171a, 171b, and 171c is more likely to fluctuate due to parasitic capacitances formed between the data lines 171a, 171b, and 171c and the pixel electrodes 191a, 191b, and 191c, and crosstalk caused by these parasitic capacitances.

[0129] However, according to this exemplary embodiment, since the pixel electrode 191c, which has the smallest area among the plurality of pixel electrodes 191a, 191b, and 191c, is superimposed on the data lines 171a, 171b, and 171c, the parasitic capacitance and crosstalk with the data lines 171a, 171b, and 171c can be minimized. When the light-emitting area corresponding to the pixel electrode 191c is blue, since the blue pixel has the lowest visibility, the parasitic capacitance between the pixel electrode 191c and the data lines 171a, 171b, and 171c, as well as the resulting crosstalk, can be minimized, thereby reducing display malfunctions.

[0130] In this exemplary embodiment, the data line 171b having the largest overlap area with the pixel electrode 191c can provide data voltage to the pixel circuit section PX2 connected to the pixel electrode 191c, but the data line having the largest overlap area with the pixel electrode is not limited to this.

[0131] Next, refer to Figure 5 and Figure 6 The accompanying drawings illustrate a display device according to an exemplary embodiment of the present invention. Note the differences from the previous exemplary embodiments, and the same reference numerals are used for corresponding constituent elements.

[0132] Figure 5 This is a planar layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention. Figure 6 This is a plan view of the pixel electrode layer and multiple data lines of a display device according to an exemplary embodiment of the present invention.

[0133] Reference Figure 5 and Figure 6 Except for the arrangement of pixel electrodes 191a, 191b, and 191c and the arrangement of openings 355a, 355b, and 355c, the display device according to this exemplary embodiment is largely the same as the exemplary embodiment described above. Specifically, pixel electrode 191c (blue pixel electrode) may be disposed to the left of pixel electrode 191b (green pixel electrode), and pixel electrode 191a (red pixel electrode) may be disposed to the right of pixel electrode 191b.

[0134] This exemplary embodiment is an example in which only one pixel electrode 191a (red pixel electrode) of a plurality of pixel electrodes 191a, 191b, and 191c is superimposed on at least a portion of a plurality of adjacent data lines 171a, 171b, and 171c. In detail, as... Figure 5 and Figure 6 As shown, only one of the multiple pixel electrodes 191a, 191b and 191c, pixel electrode 191a, can be superimposed on the entire width of the multiple data lines 171a, 171b and 171c adjacent to each other along the first direction DR1, while the remaining pixel electrodes 191b and 191c can be not superimposed on the multiple data lines 171a, 171b and 171c.

[0135] According to another exemplary embodiment, pixel electrode 191a may be stacked with at least a portion of a plurality of adjacent data lines 171a, 171b and 171c. Pixel electrode 191a may be stacked with at least a portion of the width of the plurality of adjacent data lines 171a, 171b and 171c along the first direction DR1.

[0136] The pixel electrode 191a, which is superimposed on at least a portion of the multiple data lines 171a, 171b and 171c, can have the largest area among the multiple pixel electrodes 191a, 191b and 191c in a planar view.

[0137] According to this exemplary embodiment, since the pixel electrode 191a with the largest area among the plurality of pixel electrodes 191a, 191b, and 191c is stacked with the data lines 171a, 171b, and 171c, the effects caused by parasitic capacitors and the crosstalk generated with the data lines 171a, 171b, and 171c can be minimized. That is, for the pixel electrode 191a with the largest area among the plurality of pixel electrodes 191a, 191b, and 191c, since the capacitance of the storage capacitor that can maintain the voltage between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is relatively large, the voltage fluctuations caused by the parasitic capacitors between the pixel electrode 191a and the data lines 171a, 171b, and 171c can be relatively small.

[0138] Next, refer to Figure 7 and Figure 8 The accompanying drawings describe a display device according to an exemplary embodiment of the concept of the present invention.

[0139] Figure 7 This is a planar layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention. Figure 8 This is a plan view of the pixel electrode layer and multiple data lines of a display device according to an exemplary embodiment of the present invention.

[0140] Reference Figure 7 and Figure 8 Except for the arrangement of pixel electrodes 191a, 191b, and 191c and the arrangement of openings 355a, 355b, and 355c, the display device according to this exemplary embodiment is largely the same as that described in the exemplary embodiment above. Specifically, the plurality of pixel electrodes 191a, 191b, and 191c may be arranged along the second direction DR2, and the plurality of openings 355a, 355b, and 355c may be arranged along the second direction DR2.

[0141] Pixel electrode 191a can be connected to the first transistor T1 of pixel circuit section PX1, pixel electrode 191b can be connected to the first transistor T1 of pixel circuit section PX2, and pixel electrode 191c can be connected to the first transistor T1 of pixel circuit section PX3, but the connection is not limited to these. That is, the arrangement order of multiple pixel electrodes 191a, 191b, and 191c can be changed.

[0142] According to this exemplary embodiment, all of a plurality of pixel electrodes 191a, 191b, and 191c in a set can be superimposed on at least a portion of a plurality of data lines 171a, 171b, and 171c. Specifically, as Figure 7 and Figure 8 As shown, all of the plurality of pixel electrodes 191a, 191b, and 191c can be superimposed on the entire width of the plurality of adjacent data lines 171a, 171b, and 171c along the first direction DR1. The superimposed width of the data lines 171a, 171b, and 171c along the first direction DR1 with the plurality of pixel electrodes 191a, 191b, and 191c can be substantially the same.

[0143] According to this exemplary embodiment, since the plurality of pixel electrodes 191a, 191b, and 191c are stacked equally with the data lines 171a, 171b, and 171c, all of the plurality of pixel electrodes 191a, 191b, and 191c can form parasitic capacitors with the data lines 171a, 171b, and 171c. The plurality of pixel electrodes 191a, 191b, and 191c can be simultaneously affected by the parasitic capacitors. Therefore, the deviation in image quality between the light-emitting areas of the plurality of pixels can be reduced. In other words, the deviation of the parasitic capacitors and the crosstalk between the plurality of pixel electrodes 191a, 191b, and 191c and the data lines 171a, 171b, and 171c can be minimized, thereby improving display quality.

[0144] Next, refer to Figure 9 The accompanying drawings describe a display device according to an exemplary embodiment of the concept of the present invention.

[0145] Figure 9 This is a plan view of the pixel electrode layer and multiple data lines of a display device according to an exemplary embodiment of the present invention.

[0146] Reference Figure 9 The display device according to this exemplary embodiment is largely the same as the exemplary embodiment described above, but the arrangement of the pixel electrodes 191a, 191b, and 191c, and the arrangement of the openings 355a, 355b, and 355c, may differ. Specifically, two of the plurality of pixel electrodes 191a, 191b, and 191c are arranged along the second direction DR2, and the other pixel electrode 191b is arranged along the first direction DR1 on one side of the two pixel electrodes 191a and 191c. The openings 355a and 355c corresponding to the two pixel electrodes 191a and 191c are arranged along the second direction DR2, and the opening 355b corresponding to one pixel electrode 191b is arranged along the first direction DR1 on one side of the two openings 355a and 355c.

[0147] The construction of the pixel circuit that electrically connects each of pixel electrodes 191a, 191b, and 191c is similar to... Figure 7 The exemplary embodiments shown are the same, and therefore the same explanations and figures are omitted. For example, pixel electrode 191c is connected to the first transistor T1 of the pixel circuit section PX1, pixel electrode 191a is connected to the first transistor T1 of the pixel circuit section PX2, and pixel electrode 191b is connected to the first transistor T1 of the pixel circuit section PX3, but the connection relationship is not limited to this.

[0148] According to this exemplary embodiment, two pixel electrodes 191a and 191c of a group of multiple pixel electrodes 191a, 191b, and 191c may be superimposed on at least a portion of multiple data lines 171a, 171b, and 171c, while the remaining pixel electrode 191b may not be superimposed on the data lines 171a, 171b, and 171c. The light-emitting area corresponding to pixel electrode 191a may be red, the light-emitting area corresponding to pixel electrode 191b may be green, and the light-emitting area corresponding to pixel electrode 191c may be blue.

[0149] Optionally, Figure 9 The left and right positions of the two pixel electrodes 191a and 191c and one pixel electrode 191b shown can be changed. In this case, pixel electrode 191b of a group of multiple pixel electrodes 191a, 191b and 191c can be superimposed on at least a portion of multiple data lines 171a, 171b and 171c, while pixel electrodes 191a and 191c can be excluded from being superimposed on data lines 171a, 171b and 171c.

[0150] Next, refer to Figure 10 The accompanying drawings illustrate examples of cross-sectional structures of display devices according to exemplary embodiments of the present invention.

[0151] Figure 10 Cross-sectional structures of the multiple pixel circuit sections PX1, PX2, and PX3 as described above are shown, with details omitted for brevity. Figure 4 The cross-sectional structure shown is the same as the description of the same element.

[0152] A barrier layer 112 containing insulating material may be disposed on a substrate 110, and a first conductive layer containing a lower pattern 111 may be disposed on the barrier layer 112.

[0153] The buffer layer 120 can be disposed on the first conductive layer, and the active layer 130 can be disposed on the buffer layer 120.

[0154] The first insulating layer 121 may be disposed on the active layer 130. The first insulating layer 121 may be the same layer as the insulating pattern 144 described above; however, unlike the insulating pattern 144, the first insulating layer 121 may be formed over the entire area of ​​the substrate 110. Multiple contact holes may be formed in the first insulating layer 121. That is, unlike the insulating pattern 144, the first insulating layer 121 may also be disposed on the buffer layer 120. Optionally, the first insulating layer 121 may have the same structure as the insulating pattern 144.

[0155] The second conductive layer, including the gate electrode 154, can be disposed on the first insulating layer 121, and the second insulating layer 160 can be disposed on the second conductive layer.

[0156] The third conductive layer, including the capacitor electrode 175, can be disposed on the second insulating layer 160, and the third insulating layer 180 can be disposed on the third conductive layer.

[0157] A pixel electrode layer, including multiple pixel electrodes 191, can be disposed on the third insulating layer 180. The pixel electrodes 191 can be electrically connected to the capacitor electrode 175 through the contact holes 89 of the third insulating layer 180.

[0158] The sixth insulating layer 350 may be disposed on the third insulating layer 180. The emitting layer 370 and the common electrode 270 may be sequentially disposed on the pixel electrode layer and the sixth insulating layer 350. The emitting layer 370 may include a light-emitting material that emits light of the first color, which may be blue light.

[0159] An encapsulation layer 380, comprising multiple insulating layers 381, 382, ​​and 383, may be disposed on the common electrode 270. Insulating layers 381 and 383 may comprise inorganic insulating materials, and insulating layer 382 disposed between insulating layers 381 and 383 may comprise organic insulating materials.

[0160] A filler layer 390 containing filler may be disposed on the encapsulation layer 380. A cover layer 400 including insulating material, multiple color conversion layers 430a and 430b, and a transmissive layer 430c may be disposed on the filler layer 390.

[0161] The transmissive layer 430c can transmit incident light. Specifically, the transmissive layer 430c can transmit light of a first color, such as blue light. The transmissive layer 430c may include a polymer material that transmits the first color light. The region where the transmissive layer 430c is disposed may correspond to the blue light emitting region. The transmissive layer 430c allows the incident first color light to pass through as is without changing the color of the light. The transmissive layer 430c may not include semiconductor nanocrystals that alter the wavelength of the incident light.

[0162] Color conversion layers 430a and 430b may include semiconductor nanocrystals that are different from each other. For example, first-color light incident on color conversion layer 430a can be converted into second-color light by semiconductor nanocrystals included in color conversion layer 430a. First-color light incident on color conversion layer 430b can be converted into third-color light by semiconductor nanocrystals included in color conversion layer 430b.

[0163] Semiconductor nanocrystals may include at least one of phosphors and quantum dot materials that convert incident first color light into second or third color light.

[0164] The nucleus of a quantum dot can be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0165] Group II-VI compounds can be selected from the group consisting of binary, ternary, and quaternary compounds. Binary compounds are selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof. Ternary compounds are selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, ... The groups consisting of CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof, and the quaternary compounds selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof, are quaternary compounds selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, HgZnSTe and mixtures thereof.

[0166] III-V group compounds can be selected from the group consisting of binary, ternary and quaternary compounds. Binary compounds are selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof. Ternary compounds are selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InNP, InNAs, InNSb, InPAs, InPSb and mixtures thereof. Quaternary compounds are selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0167] Group IV-VI compounds can be selected from the group consisting of binary, ternary, and quaternary compounds. Binary compounds are selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof. Ternary compounds are selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof. Quaternary compounds are selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements can be selected from the group consisting of Si, Ge, and mixtures thereof. Group IV compounds can be binary compounds selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0168] In this context, binary, ternary, or quaternary compounds can exist in the particles at a uniform concentration, or they can exist in the same particle divided into states with locally different concentration distributions. Furthermore, the color conversion medium layer can have a core / shell structure with one quantum dot surrounding another. The interface between the core and shell can have a concentration gradient, such that the concentration of elements present in the shell gradually decreases towards its center.

[0169] In some exemplary embodiments, quantum dots may have a core-shell structure comprising a core containing the aforementioned nanocrystals and a shell surrounding the core. The shell of the quantum dot serves as a protective layer to prevent chemical denaturation of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be monolayer or multilayer. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center. Examples of shells for quantum dots include metal or nonmetal oxides, semiconductor compounds, or combinations thereof.

[0170] For example, the metal or non-metal oxide can be a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4 and NiO, or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4 and CoMn2O4, but the inventive concept is not limited thereto.

[0171] Furthermore, the semiconductor compound may be CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, or AlSb, however, the present invention is not limited thereto.

[0172] Quantum dots can have a full width at half maximum (FWHM) of about 45 nm or less in their emission wavelength spectrum, preferably about 40 nm or less, and more preferably about 30 nm or less, within which color purity or color reproducibility can be improved. Furthermore, since light emitted by quantum dots is emitted in all directions, the viewing angle can be improved.

[0173] Furthermore, the form of quantum dots is the commonly used form in the field and is not particularly limited, but more specifically, forms such as spherical, pyramidal, multi-armed or cubic nanoparticles, nanotubes, nanowires, nanofibers and nanosheet particles can be used.

[0174] Quantum dots can adjust the color of emitted light according to particle size, so quantum dots can have a variety of emitting colors such as blue, red and green.

[0175] An insulating layer 440 may be disposed on multiple color conversion layers 430a and 430b and a transmissive layer 430c. Multiple color filters 450a, 450b and 450c and a light-blocking member 460 may be disposed on the insulating layer 440.

[0176] Color filter 450a can display the second color light, color filter 450b can display the third color light, and color filter 450c can display the first color light.

[0177] The light-blocking component 460 can be disposed between adjacent color filters 450a, 450b and 450c.

[0178] The substrate 210 can be disposed on a plurality of color filters 450a, 450b and 450c and a light blocking member 460. That is, a plurality of color conversion layers 430a and 430b and a plurality of color filters 450a, 450b and 450c can be disposed between the substrate 110 and the substrate 210.

[0179] According to another exemplary embodiment of the present invention, when the emitting layer 370 includes quantum dots, the plurality of color conversion layers 430a and 430b and the transmission layer 430c may be omitted.

[0180] In this specification, constituent elements disposed in the same conductive layer may include the same material as each other, and constituent elements disposed in the same insulating layer may include the same material as each other.

[0181] While the inventive concept has been described in conjunction with embodiments now considered to be practical exemplary embodiments, it will be understood that the inventive concept is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, the display device comprising: The first pixel circuit section includes at least one transistor containing a first transistor; The second pixel circuit section includes at least one transistor containing a second transistor; The first pixel electrode is electrically connected to the first pixel circuit section; The second pixel electrode is electrically connected to the second pixel circuit section; The first data line is electrically connected to the first pixel circuit section; as well as The second data line is electrically connected to the second pixel circuit section. The first data line and the second data line are arranged adjacent to each other along a first direction. The second pixel circuit section is superimposed on the first data line and the second data line in the plan view. The first pixel circuit section and the second pixel circuit section are arranged along a second direction perpendicular to the first direction, and The second pixel electrode is superimposed on at least a portion of the first data line and the second data line, and the first pixel electrode is not superimposed on the first data line and the second data line.

2. The display device according to claim 1, wherein, The first pixel electrode and the second pixel electrode are arranged along the first direction.

3. The display device according to claim 1, wherein, The first pixel electrode and the second pixel electrode are arranged along the second direction.

4. The display device according to claim 1, further comprising: The first capacitor electrode in the first pixel circuit section and the second capacitor electrode in the second pixel circuit section are disposed in the same conductive layer as the first data line and the second data line. The first pixel electrode is electrically connected to the first transistor via the first capacitor electrode. The second pixel electrode is electrically connected to the second transistor via the second capacitor electrode, and The first data line and the second data line are located on the same side of the first capacitor electrode and the second capacitor electrode.

5. The display device according to claim 1, further comprising: The third pixel circuit section includes at least one transistor; The third pixel electrode is electrically connected to the third pixel circuit section; The third data line is electrically connected to the third pixel circuit section. In the plan view, the third pixel circuit section is arranged along the second direction with the first pixel circuit section and the second pixel circuit section, and the third pixel electrode is arranged along the first pixel electrode and the second pixel electrode along the first direction.

6. The display device according to claim 5, wherein, The second pixel electrode is superimposed on at least a portion of the first data line and the second data line, and has the smallest area among the first pixel electrode, the second pixel electrode and the third pixel electrode.

7. The display device according to claim 6, wherein, The second pixel electrode is the blue pixel electrode.

8. The display device according to claim 5, wherein, The second pixel electrode has the largest area among the first pixel electrode, the second pixel electrode, and the third pixel electrode.

9. The display device according to claim 8, wherein, The second pixel electrode is the red pixel electrode.

10. The display device according to claim 8, wherein, The second pixel electrode is stacked with the first data line, the second data line and the third data line.

11. A display device, the display device comprising: The first pixel circuit section includes a first capacitor electrode and a first transistor containing a first gate electrode; The second pixel circuit section includes a second capacitor electrode and a second transistor containing a second gate electrode; The first data line is electrically connected to the first pixel circuit section; The second data line is electrically connected to the second pixel circuit section; The first pixel electrode is electrically connected to the first pixel circuit section; The second pixel electrode is electrically connected to the second pixel circuit section; An emission layer is disposed on the first pixel electrode and the second pixel electrode; as well as A common electrode is disposed on the emitter layer. In the plan view, the first pixel circuit section and the second pixel circuit section are arranged along a first direction, and the first pixel electrode and the second pixel electrode are also arranged along the first direction. The first data line and the second data line are arranged adjacent to each other along a second direction different from the first direction. The first pixel electrode and the second pixel electrode are respectively superimposed on at least one of the first data line and the second data line in the planar view. The first capacitor electrode and the second capacitor electrode are disposed in the same conductive layer as the first data line and the second data line. The first pixel electrode is electrically connected to the first transistor via the first capacitor electrode, and the second pixel electrode is electrically connected to the second transistor via the second capacitor electrode. The first gate electrode and the first capacitor electrode together form a first capacitor, and the second gate electrode and the second capacitor electrode together form a second capacitor. The first capacitor and the second capacitor are arranged along the first direction, and in the plan view, the first data line and the second data line are arranged on the same side of the first capacitor and the second capacitor.

12. The display device according to claim 11, wherein, The area of ​​the first pixel electrode is different from the area of ​​the second pixel electrode.

13. The display device according to claim 11, further comprising: The third pixel circuit section includes a third transistor; as well as The third pixel electrode is electrically connected to the third pixel circuit section. The third pixel circuit section is arranged along the first pixel circuit section and the second pixel circuit section along the first direction. The third pixel electrode is arranged along the first pixel electrode and the second pixel electrode along the first direction, and The third pixel electrode is superimposed on at least one of the first data line and the second data line.

14. A display device, the display device comprising: Multiple pixel circuit sections are arranged along a first direction; Multiple data lines are arranged along a second direction different from the first direction and are adjacent to each other; Multiple pixel electrodes are electrically connected to the multiple pixel circuit sections, respectively; An emission layer is disposed on the plurality of pixel electrodes; as well as A common electrode is disposed on the emitter layer. The multiple data lines are located on one side of the multiple pixel circuit sections. At least one of the plurality of pixel electrodes is superimposed on the plurality of data lines in the planar view, and At least one of the plurality of pixel electrodes is not superimposed on the plurality of data lines in the planar view.

15. The display device according to claim 14, wherein, The plurality of pixel electrodes are arranged along the second direction.

16. The display device according to claim 15, wherein, The at least one pixel electrode is completely superimposed on the plurality of data lines in the planar view.

17. The display device according to claim 16, wherein, The at least one pixel electrode is superimposed on the plurality of data lines along the entire width of the first direction in the planar view.

18. The display device according to claim 14, wherein, The first direction is perpendicular to the second direction.

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