Memory cell and vertically extending memory cell string array

Abstract

The present application relates to a memory cell and an array of vertically extending memory cell strings. The memory cell includes a channel material, an insulating charge channel material, a programmable material, a control gate, and a charge blocking material between the programmable material and the control gate. The charge blocking material includes a non-ferroelectric insulator material and a ferroelectric insulator material including hafnium, zirconium, and oxygen. Other embodiments are disclosed.

Description

[0001] Related patent data

[0002] This patent is derived from a continuation-in-part application of U.S. patent application serial number 15 / 890,530, filed on February 7, 2018, with the inventors named Haitao Liu, Kamal M. Karda and Albert Fayrushin and entitled "Programmable Charge Storage Transistor, An Array Of Elevationally Extending Strings Of Memory Cells, And A Method Of Forming An Array Of Elevationally Extending Strings Of Memory Cells", and the application claims priority to U.S. Provisional Patent Application No. 62 / 610,846 filed on December 27, 2017, the contents of which are hereby incorporated by reference into this article. Technical Field

[0003] Embodiments disclosed herein relate to memory cells, and to arrays of vertically extending memory cell strings. Background Art

[0004] Memory is a type of integrated circuit and is used in computer systems to store data. Memory can be manufactured in one or more arrays of individual memory cells. Memory cells can be written or read using digit lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines can conductively interconnect memory cells along the columns of the array, and access lines can conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0005] Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is conventionally designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, the memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered to be "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0006] Field effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductor channel region between them. A conductive gate is adjacent to the channel region and separated therefrom by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region, as part of the gate construction between the gate insulator and the conductive gate.

[0007] Flash memory is a type of memory and has many uses in modern computers and devices. For example, a modern personal computer may have a BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives instead of conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices for enhanced features.

[0008] NAND may be the basic architecture for integrated flash memory. A NAND cell unit includes at least one selection device coupled in series to a series combination of memory cells (the series combination is often referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement that includes vertically stacked memory cells that individually include reversibly programmable vertical transistors. Control circuits or other circuits may be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors. Summary of the invention

[0009] In one aspect, the present application relates to a memory cell comprising: a channel material; an insulating charge path material; a programmable material; a control gate; and a charge blocking material between the programmable material and the control gate, the charge blocking material comprising: a non-ferroelectric insulator material; and a ferroelectric insulator material comprising hafnium, zirconium and oxygen.

[0010] On the other hand, the present application relates to a memory cell, which includes: a channel material; an insulating charge channel material; a programmable material; a control gate; and a charge blocking material between the programmable material and the control gate, the charge blocking material including: a non-ferroelectric insulator material; a ferroelectric insulator material; and a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material.

[0011] On the other hand, the present application relates to a memory cell comprising: a channel material extending vertically or within 10° of vertical; an insulating charge passage material; a programmable material; a control gate; and a charge blocking material between the programmable material and the control gate, the charge blocking material comprising: a non-ferroelectric insulator material; a ferroelectric insulator material; a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material; and the ferroelectric insulator material is thinner than the non-ferroelectric insulator material.

[0012] On the other hand, the present application relates to a vertically extending array of memory cell strings, comprising: a stack comprising vertically alternating insulating layers and conductive layers, the conductive layers comprising control gate material, the control gate material having terminals corresponding to control gate regions of individual memory cells, programmable material of the individual memory cells extending vertically along individual ones of the control gate regions; charge blocking material of the individual memory cells extending vertically along the individual control gate regions between the programmable material and the individual control gate regions, the charge blocking material comprising: a non-ferroelectric insulator material; and a ferroelectric insulator material comprising hafnium, zirconium and oxygen; transistor channel material of the individual memory cells extending vertically along the programmable material; and an insulating charge path material extending vertically along the programmable material between the transistor channel material and the programmable material.

[0013] On the other hand, the present application relates to a vertically extending array of memory cell strings, comprising: a stack comprising vertically alternating insulating layers and conductive layers, the conductive layers comprising control gate material, the control gate material having terminals corresponding to control gate regions of individual memory cells, programmable material of the individual memory cells extending vertically along individual ones of the control gate regions; charge blocking material of the individual memory cells extending vertically along the individual control gate regions between the programmable material and the individual control gate regions, the charge blocking material comprising: a non-ferroelectric insulator material; a ferroelectric insulator material; and a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material; a transistor channel material of the individual memory cells extending vertically along the programmable material; and an insulating charge channel material extending vertically along the programmable material between the transistor channel material and the programmable material. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0015] Figure 2 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0016] Figure 3 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0017] Figure 4 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0018] Figure 5 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0019] Figure 6 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0020] Figure 7 is a schematic cross-sectional view of a portion of a vertically extending memory cell string array according to an embodiment of the present invention.

[0021] Figure 8 is along Figure 7 A view taken along line 8-8 in FIG.

[0022] Fig. 9 is a schematic cross-sectional view of a portion of a vertically extending memory cell string array according to an embodiment of the present invention.

[0023] Fig.10is a schematic cross-sectional view of a portion of a vertically extending memory cell string array according to an embodiment of the present invention.

[0024] Fig.11 is a schematic cross-sectional view of a portion of a vertically extending memory cell string array according to an embodiment of the present invention.

[0025] Fig.12 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0026] Fig.13 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0027] Fig.14 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention.

[0028] Fig.15 is a schematic cross-sectional view of a portion of a vertically extending memory cell string array according to an embodiment of the present invention.

[0029] Fig.16 is along Fig.15 A view taken along line 16-16 in FIG.

[0030] Fig.17 is a schematic cross-sectional view of a memory cell according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] Embodiments of the present invention encompass memory cells and arrays of vertically extending memory cell strings. Figure 1 , which includes a substrate or substrate segment 100 having a base substrate 104 within and upon which a memory cell 102 is shown. The base substrate 104 may include a semiconductor substrate. In this document, the term "semiconductor substrate" or "semiconducting substrate" is defined to mean any construction including semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials thereon) and a layer of semiconducting material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above. By way of example, the base substrate 104 may be a portion of a larger substrate, such as a semiconductor wafer.

[0032] Transistor 102 includes an example gate structure 101, an example channel material 42, and example source / drain regions 103 and 105. Regions 103 and 105 and material 42 may include semiconductor materials (e.g., silicon) having suitable conductivity types and conductivity-modifying impurity concentrations therein to enable current to flow along an example linear direction 31 of current flow in channel material 42 based on selected operation of transistor gate structure 101. As an example, source / drain regions 103, 105 may be appropriately conductively doped with one type of conductivity-increasing dopant and channel material 42 may be doped to a lower concentration with impurities of another conductivity type. Additional regions (not shown) such as LDD and / or halo regions may be included.

[0033] The transistor gate structure 101 includes an insulating charge channel material 40 (e.g., a bandgap engineered structure having a nitrogen-containing material, such as silicon nitride sandwiched between two insulating oxides (e.g., silicon dioxide)), a programmable material 34 (e.g., a charge storage material, such as a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.), a control gate 28 (e.g., including a conductive control gate material 22, such as an elemental metal, a metallic material, and a conductive doped semiconductor material, including mixtures thereof), and a charge blocking material 32 between the programmable material 34 and the control gate 28. The charge blocking material 32 includes a non-ferroelectric insulator material 17 and a ferroelectric insulator material 15. In one embodiment and as shown, the ferroelectric insulator material 15 and the non-ferroelectric insulator material 17 are directly against each other, and in one embodiment, the ferroelectric insulator material 15 is thinner than the non-ferroelectric insulator material 17. In any case, an example thickness of the ferroelectric insulator material 15 is 10 to 100 angstroms, and ideally 20 to 50 angstroms. An example thickness of each of materials 40, 34, 17, and 22 is 30 to 250 angstroms. Example non-ferroelectric insulator materials are silicon dioxide and / or silicon nitride (e.g., silicon nitride sandwiched between two layers of silicon dioxide). Example ferroelectric insulators include materials including metal oxides including one or more of transition metal oxides, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconate titanate, tantalum oxide, strontium oxide, strontium titanium oxide, titanium oxide, and barium strontium titanate, and which may have dopants therein including one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, lutetium, dysprosium, gadolinium, praseodymium, chromium, niobium, tantalum, hafnium, zirconium, vanadium manganese, cobalt, nickel, carbon, and any other rare earth element. One specific example is a hafnium and zirconium-based oxide with a suitable dopant therein. Other examples include hafnium and silicon based oxides with suitable dopants therein; yttrium and zirconium based oxides with suitable dopants therein; and hafnium, silicon, and zirconium based oxides.

[0034] In one embodiment, the ferroelectric insulator material 15 includes hafnium, zirconium, and oxygen. In one such embodiment, the ferroelectric insulator material includes Hf xZr 1-x O 2 , or consisting essentially of Hf x Zr 1-x O 2 In one embodiment, the ferroelectric insulator material 15 comprises, consists of, or consists essentially of Hf x Zr y Q z O 2 Composition, of which:

[0035] x, y and z are greater than 0;

[0036] x+y+z is not greater than 1.0;

[0037] y is greater than 0.7 or less than 0.3; and

[0038] Q is the material whose presence makes a ferroelectric insulator material a ferroelectric.

[0039] By way of example, Q may be any of the elemental dopants mentioned in the previous paragraph. In one embodiment, y is greater than 0.7. In one embodiment, y is less than 0.3. In one embodiment, x+y+z is from 0.5 to 1.0, and in one such embodiment is 1.0.

[0040] In one embodiment, non-ferroelectric insulator material 17 is closer to programmable material 34 then ferroelectric insulator material 15, in one embodiment ferroelectric insulator material 15 is directly against control gate 28, and in one embodiment non-ferroelectric insulator material 17 is directly against programmable material 34. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0041] Figure 2 An alternative example memory cell 102a of substrate 100a is shown, which includes a gate construction 101a with a charge blocking material 32a. The same numbers from the embodiments described above are used where appropriate, with some construction differences being indicated by the suffix "a". In construction 101a, and in one embodiment, the ferroelectric insulator material 15 is closer to the programmable material 34 than the non-ferroelectric insulator material 17, in one embodiment, the non-ferroelectric insulator material 17 is directly against the control gate 28, and in one embodiment, the ferroelectric insulator material 15 is directly against the programmable material 34. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0042] Figure 3An alternative example memory cell 102b of a substrate 100b is shown, which includes a gate structure 101b with a charge blocking material 32b. The same numbers from the embodiments described above are used in appropriate places, with some structural differences being represented by suffixes "b" or different numbers. The ferroelectric insulator material 15 in the charge blocking material 32b is sandwiched between two regions 37, 39 of the non-ferroelectric insulator material 17 along a direction parallel to the linear direction 31 of the current flow in the channel material 42. The example thickness of each of the regions 37, 39 and the material 15 is 10 to 100 angstroms. In one embodiment and as shown, the ferroelectric insulator material 15 is directly against the non-ferroelectric insulator material 17 of each of the two regions 37, 39. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0043] Figure 4 An alternative example memory cell 102c of substrate 100c is shown, which includes a gate structure 101c with a charge blocking material 32c. The same numbers from the embodiments described above are used where appropriate, with some structural differences being represented by the suffix "c". The non-ferroelectric insulator material 17 of the charge blocking material 32c is sandwiched between two regions 37, 39 of the ferroelectric insulator material 15 along a direction parallel to the linear direction 31 of the current flow in the channel material 42. In one embodiment and as shown, the non-ferroelectric insulator material 17 directly abuts against the ferroelectric insulator material 15 in each of the two regions 37, 39. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0044] Figures 1 to 4 An example embodiment is shown in which the ferroelectric insulator material 15 is continuous between the edges 33, 35 of the control gate 28, parallel to the linear direction 31 of current flow in the channel material 42. Alternatively, this ferroelectric insulator material may be discontinuous between the edges. This example embodiment is Figure 5 102d is shown with respect to a memory cell 102d of a substrate 100d, the substrate 100d including a gate structure 101d having a charge blocking material 32d. The same numbers from the embodiments described above are used where appropriate, with some structural differences being represented by the suffix "d". The charge blocking material 32d is shown as a ferroelectric insulator material 15 being discontinuous between the edges 33, 35 of the control gate 28, parallel to the linear direction 31 of the current flow in the channel material 42. Only two example spacing sections of the ferroelectric insulator material segments 15 are shown, although more may be formed and various positionings may be performed. In one embodiment and as shown, the non-ferroelectric insulator material 17 is laterally located between the discontinuous sections of the ferroelectric insulator material 15. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0045] Figures 1 to 5 An example is shown where the transistors 102 / 102a / 102b / 102c / 102d are horizontal or within 10° of horizontal. Alternatively, the memory cells may be fabricated to extend vertically or not. Figure 6 An example memory cell 102e of substrate 100e is shown extending vertically, with the particular depicted embodiment transistor 102e being vertical or within 10° of vertical. Like numerals from the embodiments described above are used where appropriate, with some construction differences indicated by the suffix "e" or different numerals. Figure 6 The channel material 42e in the example embodiment of is shown as being sandwiched between an insulating charge path material 40e and a backing dielectric material 50 (e.g., silicon dioxide and / or silicon nitride). The source / drain regions are not Figure 6 As specifically shown in the foregoing, such as may occur with respect to a vertically extending string of memory cells, where source / drain regions are disposed at the top and bottom of a stack of such memory cells, such as will be described below. Dielectric material 27 (e.g., silicon dioxide and / or silicon nitride) is above and below gate structure 101e. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0046] Embodiments of the present invention include a vertically extending array of memory cell strings, such as Figure 7 and 8 Like numerals from the above described embodiments are used where appropriate, with some construction differences indicated by a suffix "f" or different numerals. Figure 7 and 8 A construction 10 is shown which may include any one or more of a conductive / conductor / conductive, a semiconductive / semiconductor / semiconductive, or an insulating / insulator / insulating (i.e., electrically herein) material. Various materials have been formed vertically on a base substrate 104. The materials may be Figure 7 and 8 11. For example, other partially or fully fabricated components of the integrated circuit may be disposed somewhere above, around, or within the base substrate 11. Control circuits and / or other peripheral circuits for operating components within the array of components (e.g., memory cells) may also be fabricated, and may or may not be completely or partially within the array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently, in series, or otherwise relative to each other. In this document, a "sub-array" may also be considered an array.

[0047] The construction 10 includes an array 12 of vertically extending strings 44 of memory cells 30. Only a single string 44 is shown, although hundreds, thousands, tens of thousands, etc. of such strings would be possible in the array 12. The approximate locations of the memory cells 30 are in FIG. Figure 7 In brackets and in Figure 8 1 and 2. The memory cells 30 are shown in dashed lines in the example depicted, where the memory cells 30 are substantially annular or ring-shaped in the depicted example. The array 12 includes a vertical stack 16 of alternating insulating layers 19 and conductive layers 20. The example layer 19 includes an insulating material 24, such as silicon dioxide. The example layer 20 includes a conductive control gate material 22 having a terminal 26 corresponding to a control gate region 28 of an individual memory cell 30. The control gate region 28 may be an individual control gate line 29 ( Figure 8 Only one is shown and indicated by a number in the figure, which interconnects a plurality of memory cells of a plurality of memory cell strings within an individual conductive layer 20 in the row direction. The dielectric material 23 ( Figure 8 ; For example, silicon dioxide and / or silicon nitride) is laterally located between the control gate lines 29. The array 12 is Figure 7 1 and 2. The memory cell 30 is shown as having seven vertical alternating layers 19, 20, but fewer or possibly more (e.g., tens, hundreds, etc.) may be formed. Thus, more layers 19 and 20 may be above and / or below the depicted layers. The layers 19 and 20 may have any suitable vertical thickness, and may have the same or different vertical thicknesses relative to each other. As an example, the layers 19 and 20 may have respective thicknesses of about 10 nanometers (nm) to 300 nm. The channel openings 13 extend through the alternating layers 19, 20, with only one channel opening 13 shown with respect to a single vertically extending string 44 of the memory cell 30.

[0048] The programmable material 34f of the individual memory cell 30 extends vertically along the individual control gate region 28. The charge blocking material 32f (i.e., the charge block) extends vertically along the individual control gate region 28 between the programmable material 34f and the individual control gate region 28. The charge blocking material 32f includes the non-ferroelectric insulator material 17 and the ferroelectric insulator material 15. The transistor channel material 42f of the individual memory cell 30 extends vertically along the programmable material 34f. The insulating charge channel material 40f extends vertically along the programmable material 34f between the transistor channel material 42f and the programmable material 34f. The example memory cell string 44 is shown as including a radially central solid dielectric material 50 (e.g., silicon nitride, spin-on dielectric, and / or silicon dioxide). Alternatively, and by way of example only, the radially central portion of the memory cell string 44 may include void space (not shown) and / or no solid material (not shown).

[0049] The charge block may have the following functions in a memory cell: in a programming mode, the charge block may prevent charge carriers from passing out of a programmable material (e.g., a floating gate material, a charge trapping material, etc.) toward a control gate, and in an erase mode, the charge block may prevent charge carriers from flowing from the control gate into the programmable material. Thus, the charge block may be used to block charge migration between a control gate region and a programmable material of an individual memory cell.

[0050] Alternative existing or yet to be developed configurations may be used. For example, multiple memory cells may be formed around a single string in individual conductive layers 20, such as by Figure 8 The depicted control gate line 29 bifurcates longitudinally down its middle (not shown) creating two memory cells (not shown) which could be individually controlled if such bifurcated control gate lines were individually controllable.

[0051] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0052] Figure 7 and 8 An example embodiment is shown in which the ferroelectric insulator material 15 and the non-ferroelectric insulator material 17 are each located directly above and directly below the programmable material 34f in the individual memory cells 30, and in which the non-ferroelectric insulator material 17 is directly against the top 41 and bottom 43 of the programmable material 34f in the individual memory cells 30. Fig. 9 An alternative embodiment example vertically extending string 44 of memory cells 30 is shown in FIG. Like numerals from the above described embodiments are used where appropriate, with some construction differences indicated by the suffix "g". Fig. 9 Also shown are embodiments in which each of the ferroelectric insulator material 15 and the non-ferroelectric insulator material 17 is directly above and directly below the programmable material 34f in individual memory cells 30, but in which the ferroelectric insulator material 15 is directly against the top 41 and bottom 43 of the programmable material. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0053] Fig.10 An alternative example vertically extending string 44h is shown with respect to the memory cell 30 of configuration 10h. The same numerals from the embodiments described above are used where appropriate, with some of the configuration differences being indicated by the suffix "h". The ferroelectric insulator material 15 is neither directly above nor directly below the programmable material 34h in the individual memory cells 30. In addition, Fig.10An embodiment is shown in which the non-ferroelectric insulator material 17 is neither directly above nor directly below the programmable material 34g in individual memory cells 30. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0054] refer to Fig.11 , another alternative embodiment is shown with respect to construction 10j, a string 44j of memory cells 30 extending vertically. The same numerals from the embodiments described above are used where appropriate, with some construction differences indicated by the suffix "j". The ferroelectric insulator material 15 of the programmable material 34f is directly above and directly below the control gate material 22 in the individual memory cells 30, and in one embodiment directly against the top 47 and bottom 49 of the control gate material 22 in the individual memory cells 30. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0055] As shown, the transistor channel material extends vertically continuously along multiple insulating and conductive layers ( Figures 7 to 11 In one embodiment, the programmable material extends vertically along multiple insulating layers and conductive layers ( Fig.10 and 11 In another embodiment, the programmable material extends vertically along only individual ones of the conductive layers and does not extend vertically along the insulating layers. Figures 7 to 9 ).

[0056] Fig.12 Another alternative embodiment memory cell 102f is shown including a substrate 100f having a gate structure 101f with a charge blocking material 32f. The same numbers from the embodiments described above are used where appropriate, with some construction differences being indicated by the suffix "f" or by different numbers. In construction 101f, the metal material 55 is between the non-ferroelectric insulator material 17 and the ferroelectric insulator material 15. An example thickness of the metal material 55 does not exceed 3 nanometers, and more preferably is from 1 nanometer to 2 nanometers. The metal material 55 can effectively increase the degree / amount of ferroelectricity of the ferroelectric insulator material 15. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used. For example, and by way of example only, Fig.13 , 14 15 / 16 show corresponding alternative embodiment memory cells 102g, 102h and 102k of substrates 100g, 100h and 100k, respectively, which include gate structures 101g, 101h and 101k having charge blocking materials 32g, 32h and 32k, respectively. The same numerals from the embodiments described above are used where appropriate, with some construction differences indicated by the suffixes "g", "h" or "k", respectively. Fig.13 , 14and 15 / 16 correspond to Figure 5 , 6 and 7 / 8, and have metal materials 55g, 55h and 55k, respectively. In addition, any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0057] Fig.17 Another alternative embodiment memory cell 102m of a substrate 100m including a gate structure 101m with a charge blocking material 32m is shown. The same numbers from the embodiments described above are used in appropriate places, with some structural differences being represented by the suffix "m" or by different numbers. In the structure 101m, the ferroelectric insulator material includes ferroelectric insulator materials 15 and 18 of first and second different compositions, and non-ferroelectric insulator material 17m, respectively. In one embodiment, the ferroelectric insulator materials of the first and second different compositions are directly against each other. In one embodiment, the ferroelectric insulator materials of the first and second different compositions each include hafnium, zirconium and oxygen (for example, but with at least one different molar concentration with respect to hafnium, zirconium and oxygen). In another embodiment, one of the ferroelectric insulator materials of the first and second different compositions does not include a combination of hafnium and zirconium. The ferroelectric insulator materials 15 and 18 may have the same thickness or different thicknesses relative to each other, and may be in different positions relative to each other. In addition, any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0058] Ferroelectric insulator materials used as disclosed herein can exhibit negative capacitance, whereby transistors can exhibit the advantageous property of low effective oxide thickness, which can result in faster programming and erasing.

[0059] The above processing or construction may be considered to be relative to a single stack or single platform of such components or an array of components therein formed on or as part of an underlying base substrate (although a single stack / platform may have multiple layers). Control circuits and / or other peripheral circuits for operating or accessing such components in the array may also be formed anywhere as part of the completed construction, and in some embodiments, may be below the array (e.g., CMOS below the array). In any case, one or more additional such stacks / platforms may be provided or manufactured above and / or below the stacks / platforms shown in the drawings or described above. In addition, the arrays of components may be the same or different in different stacks / platforms relative to each other. Intermediate structures (e.g., additional circuits and / or dielectric layers) may be provided between directly vertically adjacent stacks / platforms. In addition, different stacks / platforms may be electrically coupled relative to each other. Multiple stacks / platforms may be manufactured individually and sequentially (e.g., one above another), or two or more stacks / platforms may be manufactured substantially simultaneously.

[0060] The assemblies and structures discussed above can be used in integrated circuits and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0061] In this document, unless otherwise specified, "vertical", "higher", "upper", "lower", "top", "at the top of...", "bottom", "above", "below", "under", "below", "up", and "down" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees), and may be relative to the direction in which the substrate is handled during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "completely horizontal" is a direction along the surface of the main substrate (i.e., not forming an angle with the main substrate surface), and may be relative to the direction in which the substrate is handled during manufacturing. In addition, "vertical" and "horizontal" as used herein are generally vertical directions relative to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction that is inclined at least 45° from a precise horizontal direction. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending" and the like with respect to a field effect transistor are references to the orientation of the channel length of the transistor along which current flows in operation between source / drain regions. For bipolar junction transistors, "vertically extending", "extending vertically", "extending horizontally", and horizontally extending and the like are reference to the orientation of the base length along which current flows in operation between the emitter and the collector. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or extends within 10° of vertical.

[0062] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components relative to one another. Furthermore, the use of "above" without being preceded by "directly" merely requires that some portion of the stated region / material / component that is above another is vertically outward of the other (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, the use of "under" and "below" without being preceded by "directly" merely requires that some portion of the stated region / material / component that is below / below another is vertically inward of the other (i.e., regardless of whether there is any lateral overlap of the two stated regions / materials / components).

[0063] Any of the materials, regions, and structures described herein may be homogeneous or non-homogeneous, and may be continuous or discontinuous, whether or not overlying any material. Where one or more example compositions are provided for any material, the material may include, consist essentially of, or consist of the one or more compositions. Furthermore, unless otherwise noted, each material may be formed using any suitable present or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0064] In addition, "thickness" itself (without a directional adjective in front) is defined as the average straight-line distance through a given material or region perpendicular to the nearest surface of an adjacent material or the nearest surface of an adjacent region with a different composition. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If it is a variable thickness, then the thickness refers to the average thickness, unless otherwise specified, and since the thickness is variable, this material or region will have some minimum thickness and some maximum thickness. As used herein, "different composition" only requires that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as when the materials or regions are not homogeneous. If the two stated materials or regions do not directly abut against each other, then in the case where such materials or regions are not homogeneous, "different composition" only requires that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when the stated materials, regions or structures are in at least some physical touch contact relative to each other, the material, region or structure "directly abuts" another. In contrast, the terms "on," "above," "adjacent," "along," and "against" without the word "directly" in front of them encompass "directly against" as well as configurations in which the stated materials, regions, or structures result in no intervening materials, regions, or structures being in physical touching contact with each other.

[0065] As used herein, if the regions-material-components are "electrically coupled" relative to each other in normal operation, then current can flow continuously from one to the other, and in the event of sufficient generation of subatomic positive and / or negative charges, primarily through the movement of subatomic positive and / or negative charges. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when the region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0066] The composition of any of the conductive / conductor / conductive materials herein may be a metallic material and / or a conductively doped semiconductive / semiconductive / semiconductive material. "Metallic material" is an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0067] As used herein, "selectivity" with respect to etching, etched, removing, removing, depositing, forming, and / or forming, is the act of doing so at a rate of at least 2:1 by volume on one stated material relative to another stated material. Additionally, selective deposition, selective growth, or selective formation refers to depositing, growing, or forming one material relative to another stated material at a rate of at least 2:1 by volume for at least the first 75 angstroms of deposition, growth, or formation.

[0068] Unless stated otherwise, the use of "or" herein includes either and both of the two.

[0069] in conclusion

[0070] In some embodiments, a memory cell includes a channel material, an insulating charge path material, a programmable material, a control gate, and a charge blocking material between the programmable material and the control gate. The charge blocking material includes a non-ferroelectric insulator material and a ferroelectric insulator material including hafnium, zirconium, and oxygen.

[0071] In some embodiments, a memory cell includes a channel material, an insulating charge channel material, a programmable material, a control gate, and a charge blocking material between the programmable material and the control gate. The charge blocking material includes a non-ferroelectric insulator material, a ferroelectric insulator material, and a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material.

[0072] In some embodiments, a memory cell includes a channel material extending vertically or within 10° of vertical, an insulating charge channel material, a programmable material, a control gate, and a charge blocking material between the programmable material and the control gate. The charge blocking material includes a non-ferroelectric insulator material and a ferroelectric insulator material including hafnium, zirconium, and oxygen. The ferroelectric insulator material and the non-ferroelectric are directly against each other. The ferroelectric insulator material is thinner than the non-ferroelectric insulator material.

[0073] In some embodiments, a memory cell includes a channel material extending vertically or within 10° of vertical, an insulating charge channel material, a programmable material, a control gate, and a charge blocking material between the programmable material and the control gate. The charge blocking material includes a non-ferroelectric insulator material, a ferroelectric insulator material, and a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material. The ferroelectric insulator material is thinner than the non-ferroelectric insulator material.

[0074] In some embodiments, a vertically extending array of memory cell strings comprises: a stack comprising vertically alternating insulating layers and conductive layers. The conductive layers comprise control gate material having terminals corresponding to control gate regions of individual memory cells. The programmable material of the individual memory cells extends vertically along individual ones of the control gate regions. The charge blocking material of the individual memory cells extends vertically along the individual control gate regions between the programmable material and the individual control gate regions. The charge blocking material comprises a non-ferroelectric insulator material and a ferroelectric insulator material comprising hafnium, zirconium and oxygen. The transistor channel material of the individual memory cells extends vertically along the programmable material, and the insulating charge channel material extends vertically along the programmable material between the transistor channel material and the programmable material.

[0075] In some embodiments, a vertically extending array of memory cell strings includes: a stack including vertically alternating insulating layers and conductive layers. The conductive layer includes a control gate material having a terminal corresponding to a control gate region of an individual memory cell. The programmable material of the individual memory cell extends vertically along an individual of the control gate regions. The charge blocking material of the individual memory cell extends vertically along the individual control gate region between the programmable material and the individual control gate region. The charge blocking material includes a non-ferroelectric insulator material, a ferroelectric insulator material, and a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material. The transistor channel material of the individual memory cell extends vertically along the programmable material. An insulating charge channel material extends vertically along the programmable material between the transistor channel material and the programmable material.

[0076] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. It should be understood, however, that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims should be given the full scope as literally stated and appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A memory cell, comprising: Channel material; Insulating charge path materials; Programmable materials; Control grid; and a charge blocking material between the programmable material and the control gate, the charge blocking material comprising: Non-ferroelectric insulator materials; A ferroelectric insulator material comprising hafnium, zirconium and oxygen; and A metal material is between the non-ferroelectric insulator material and the ferroelectric insulator material so that the non-ferroelectric insulator material and the ferroelectric insulator material do not contact each other.

2. The memory cell of claim 1 , wherein the ferroelectric insulator material comprises Hf x Zr 1-x O2, wherein x is from 0.3 to 0.

7.

3. The memory cell of claim 1 , wherein the ferroelectric insulator material consists of or consists essentially of Hf x Zr 1- x O2, where x is 0.3 to 0.

7.

4. The memory cell of claim 1 , wherein the ferroelectric insulator material comprises Hf x Zr y Q z O2, where: x, y and z are greater than 0; x+y+z is not greater than 1.0; y is greater than 0.7 or less than 0.3; and Q is the material whose presence makes the ferroelectric insulator material a ferroelectric. The memory cell of claim 4 , wherein y is greater than 0.

7. The memory cell of claim 4 , wherein y is less than 0.

3.

7. The memory cell of claim 4, wherein x+y+z is from 0.5 to 1.

0.

8. The memory cell of claim 4, wherein x+y+z is 1.

0.

9. The memory cell of claim 1 wherein the ferroelectric insulator material consists of or consists essentially of Hf x Zr y Q z O2 composition, of which: x, y and z are greater than 0; x+y+z is not greater than 1.0; y is greater than 0.7 or less than 0.3; and Q is the material whose presence makes the ferroelectric insulator material a ferroelectric.

10. The memory cell of claim 1 wherein the ferroelectric insulator material comprises first and second ferroelectric insulator materials of different compositions.

11. The memory cell of claim 10 wherein the first and second ferroelectric insulator materials of different composition are directly against each other.

12. The memory cell of claim 10 wherein the first and second different composition ferroelectric insulator materials each comprise hafnium, zirconium, and oxygen.

13. The memory cell of claim 10 wherein one of the first and second different composition ferroelectric insulator materials does not include a combination of hafnium and zirconium.

14. The memory cell of claim 1 wherein the ferroelectric insulator material is thinner than the non-ferroelectric insulator material.

15. The memory cell of claim 1 wherein the ferroelectric insulator material is continuous between edges of the control gate, parallel to a linear direction of current flow in the channel material.

16. The memory cell of claim 1 wherein the ferroelectric insulator material is discontinuous between edges of the control gate, parallel to a linear direction of current flow in the channel material.

17. The memory cell of claim 1 wherein the ferroelectric insulator material is closer to the programmable material than the non-ferroelectric insulator material.

18. The memory cell of claim 1 wherein the non-ferroelectric insulator material is closer to the programmable material than the ferroelectric insulator material.

19. The memory cell of claim 1 wherein the ferroelectric insulator material is directly against the control gate.

20. The memory cell of claim 1 wherein the non-ferroelectric insulator material is directly against the control gate.

21. The memory cell of claim 1 wherein the ferroelectric insulator material is directly against the programmable material.

22. The memory cell of claim 1 wherein the non-ferroelectric insulator material is directly against the programmable material.

23. The memory cell of claim 1 wherein the ferroelectric insulator material is sandwiched between two regions of the non-ferroelectric insulator material along a direction parallel to a linear direction of current flow in the channel material.

24. The memory cell of claim 1 wherein the non-ferroelectric insulator material is sandwiched between two regions of the ferroelectric insulator material along a direction parallel to a linear direction of current flow in the channel material.

25. The memory cell of claim 1 extending vertically.

26. The memory cell of claim 25 which is vertical or within 10° of vertical.

27. The memory cell of claim 1 which is horizontal or within 10° of horizontal.

28. A memory cell comprising: Channel material; Insulating charge path materials; Programmable materials; Control grid; and a charge blocking material between the programmable material and the control gate, the charge blocking material comprising: Non-ferroelectric insulator materials; Ferroelectric insulator materials; and A metal material is between the non-ferroelectric insulator material and the ferroelectric insulator material so that the non-ferroelectric insulator material and the ferroelectric insulator material do not contact each other.

29. The memory cell of claim 28 wherein the ferroelectric insulator material comprises first and second ferroelectric insulator materials of different composition directly against each other.

30. A memory cell comprising: Channel material extending vertically or within 10° of vertical; Insulating charge path materials; Programmable materials; Control grid; and a charge blocking material between the programmable material and the control gate, the charge blocking material comprising: Non-ferroelectric insulator materials; A ferroelectric insulator material comprising hafnium, zirconium and oxygen; and a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material so that the non-ferroelectric insulator material and the ferroelectric insulator material do not contact each other, and The ferroelectric insulator material is thinner than the non-ferroelectric insulator material.

31. A memory cell comprising: Channel material extending vertically or within 10° of vertical; Insulating charge path materials; Programmable materials; Control grid; and a charge blocking material between the programmable material and the control gate, the charge blocking material comprising: Non-ferroelectric insulator materials; Ferroelectric insulator materials; a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material so that the non-ferroelectric insulator material and the ferroelectric insulator material do not contact each other; and The ferroelectric insulator material is thinner than the non-ferroelectric insulator material.

32. A vertically extending memory cell string array, comprising: a stack comprising vertically alternating insulating layers and conductive layers, the conductive layers comprising control gate material having terminals corresponding to control gate regions of individual memory cells, programmable material of the individual memory cells extending vertically along individual ones of the control gate regions; The charge blocking material of the individual memory cells extends vertically along the individual control gate regions between the programmable material and the individual control gate regions, the charge blocking material comprising: Non-ferroelectric insulator materials; A ferroelectric insulator material comprising hafnium, zirconium and oxygen; and a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material so that the non-ferroelectric insulator material and the ferroelectric insulator material do not contact each other, transistor channel material of the individual memory cells extending vertically along the programmable material; and An insulating charge path material extends vertically along the programmable material between the transistor channel material and the programmable material.

33. The array of claim 32 wherein in the individual memory cells the ferroelectric insulator material is directly above and directly below the programmable material.

34. The array of claim 33 wherein in the individual memory cells the ferroelectric insulator material is directly against top and bottom of the programmable material.

35. The array of claim 32 wherein in the individual memory cells the ferroelectric insulator material is neither directly above nor directly below the programmable material.

36. The array of claim 32 wherein in the individual memory cells the non-ferroelectric insulator material is directly above and directly below the programmable material.

37. The array of claim 36 wherein in the individual memory cells the non-ferroelectric insulator material is directly against the top and bottom of the programmable material.

38. The array of claim 32 wherein in the individual memory cells the non-ferroelectric insulator material is neither directly above nor directly below the programmable material.

39. The array of claim 32 wherein in the individual memory cells the ferroelectric insulator material is directly above and directly below the control gate material.

40. The array of claim 39 wherein in the individual memory cells the ferroelectric insulator material is directly against the top and bottom of the control gate material.

41. The array of claim 32, wherein the transistor channel material extends vertically continuously along a plurality of the insulating layer and the conductive layer, and the programmable material extends vertically along a plurality of the insulating layer and the conductive layer.

42. The array of claim 32, wherein the transistor channel material extends vertically continuously along multiple of the insulating layers and the conductive layers, the programmable material extends vertically along only individual ones of the conductive layers and does not extend vertically along the insulating layer extensions.

43. A vertically extending memory cell string array, comprising: a stack comprising vertically alternating insulating layers and conductive layers, the conductive layers comprising control gate material having terminals corresponding to control gate regions of individual memory cells, programmable material of the individual memory cells extending vertically along individual ones of the control gate regions; The charge blocking material of the individual memory cells extends vertically along the individual control gate regions between the programmable material and the individual control gate regions, the charge blocking material comprising: Non-ferroelectric insulator materials; Ferroelectric insulator materials; and a metal material between the non-ferroelectric insulator material and the ferroelectric insulator material so that the non-ferroelectric insulator material and the ferroelectric insulator material do not contact each other; transistor channel material of the individual memory cells extending vertically along the programmable material; and An insulating charge path material extends vertically along the programmable material between the transistor channel material and the programmable material.

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