Apparatus for improving the effective performance of a power supply and related methods

Abstract

Apparatuses and related methods for improving the effective performance of a power supply are disclosed. One apparatus includes a power management circuit to receive an input voltage and generate a first output voltage and provide it to an energy storage device. The power management circuit also generates a second output voltage and provides it to a load. The first output voltage is greater than the input voltage, and the second output voltage is less than the first output voltage. The apparatus also includes a monitoring circuit to monitor the first output voltage and provide a signal to the load to indicate when the load can perform an operation.

Description

Technical Field

[0001] This disclosure generally relates to devices with improved energy use performance, and more specifically, to devices and related methods for improving the effective performance of batteries. Background Technology

[0002] With the increasing prevalence of wireless technologies such as Wi-Fi, Bluetooth, and mobile or wireless Internet of Things (IoT) devices, more and more devices or systems are incorporating radio frequency (RF) circuitry, such as receivers and / or transmitters. To reduce cost, size, and bill of materials, and to improve the reliability of such devices or systems, various circuits or functions have been integrated into integrated circuits (ICs). For example, ICs typically include receiver and / or transmitter circuitry.

[0003] The increasing number of circuit elements, devices, subsystems, etc., also leads to a corresponding increase in the power consumed by products that include such components. In some applications, such as battery-powered mobile or portable products, a limited amount of power or energy is available. More specifically, a typical battery has a relatively limited capacity, meaning it can provide a limited amount of energy for a given period of time.

[0004] The descriptions and any one or more corresponding figures in this section are included as background information material. The material in this section should not be construed as an admission that such material constitutes prior art to this patent application. Summary of the Invention

[0005] According to exemplary embodiments, various devices and related methods are considered. According to one exemplary embodiment, a device includes a power management circuit for receiving an input voltage and generating a first output voltage and providing it to an energy storage device. The power management circuit also generates a second output voltage and provides it to a load. The first output voltage is greater than the input voltage, and the second output voltage is less than the first output voltage. The device also includes a monitoring circuit for monitoring the first output voltage and providing a signal to the load to indicate when the load can perform operations.

[0006] According to another exemplary embodiment, a device includes a power management circuit that receives an input voltage and boosts the input voltage to generate a storage voltage and supplies it to a capacitor. The power management circuit also converts the storage voltage into a supply voltage supplied to a transmit (TX) circuit system. The storage voltage is greater than the input voltage. Furthermore, the supply voltage is less than the storage voltage. The device further includes a monitoring circuit for monitoring the storage voltage and providing a signal to the TX circuit system to indicate when the TX circuit system can perform a transmit operation.

[0007] According to another exemplary embodiment, a method of providing power to a load includes: receiving an input voltage and generating a first output voltage; and providing the first output voltage to an energy storage device. The method further includes generating a second output voltage based on the first output voltage, and providing the second output voltage to the load. The method also includes monitoring the first output voltage and providing a signal to the load to indicate when the load can perform operations. Attached Figure Description

[0008] The accompanying drawings are merely illustrative of exemplary embodiments and should therefore not be construed as limiting the scope of this application or the claimed subject matter. Those skilled in the art will understand that the disclosed concepts make them applicable to other equivalent embodiments. In the drawings, the same reference numerals used in more than one drawing denote the same, similar, or equivalent functions, components, or blocks.

[0009] Figure 1 The typical circuit layout and related waveforms are shown.

[0010] Figure 2 The diagram illustrates a circuit arrangement for providing power to a load according to an exemplary embodiment.

[0011] Figure 3 The waveforms are shown in relation to the circuit arrangement according to an exemplary embodiment.

[0012] Figure 4 Additional waveforms are shown in relation to the circuit arrangement according to an exemplary embodiment.

[0013] Figure 5 The diagram illustrates a circuit arrangement for providing power to a load according to an exemplary embodiment.

[0014] Figure 6 The waveforms are shown in relation to the circuit arrangement according to an exemplary embodiment.

[0015] Figure 7 The diagram illustrates a circuit arrangement for providing power to a load according to an exemplary embodiment.

[0016] Figure 8 A circuit arrangement for providing power to a load is shown according to another exemplary embodiment.

[0017] Figure 9 A circuit arrangement for providing power to a load is shown according to another exemplary embodiment.

[0018] Figure 10 A circuit arrangement for providing power to a load is shown according to another exemplary embodiment.

[0019] Figure 11 A circuit arrangement for a monitoring circuit according to an exemplary embodiment is shown.

[0020] Figure 12 A circuit arrangement for a power management circuit is shown according to an exemplary embodiment.

[0021] Figure 13 A system for radio communication is shown according to an exemplary embodiment.

[0022] Figure 14 The diagram illustrates a circuit arrangement for an IC (including a transmitting circuit system) according to an exemplary embodiment.

[0023] Figure 15 The diagram illustrates a circuit arrangement for an IC (including both transmitting and receiving circuit systems) according to an exemplary embodiment. Detailed Implementation

[0024] The disclosed concepts generally relate to devices with improved energy efficiency. More specifically, this disclosure relates to devices such as ICs, subsystems, or systems for improving the effective performance of batteries in electronic devices and apparatuses, as well as related methods.

[0025] For example, some embodiments allow small batteries (which typically provide relatively small currents (e.g., less than 10 mA in some IoT applications)) to operate in applications that consume relatively large currents (e.g., up to 100 mA or even higher in the example given above for a relatively short duration). Furthermore, some embodiments allow batteries (whose performance (e.g., lifespan, capacity, etc.) is impaired in cold weather) to extend battery life or increase effective capacity.

[0026] In some applications, loads such as microcontroller units (MCUs) draw periodic bursts of current (or relatively large amounts of current) from a battery. For example, a battery may supply power to an MCU that includes a wireless device such as a transmitter. When a wireless device transmits a signal, it typically draws a relatively large amount of current from the battery relatively quickly (e.g., in bursts) to perform its operations, such as supplying power to a power amplifier.

[0027] In this scenario, the battery is typically designed to be sized based on cost, size, and similar factors, and may not be able to directly supply the current that the wireless device draws for normal operation. In conventional approaches, attempting to draw current from the battery can cause the MCU and / or the wireless device to malfunction.

[0028] Figure 1The standard circuit layout and related waveforms are shown. Battery 10 supplies voltage Vmcu to wireless MCU 15. Wireless MCU 15 transmits RF signals via antenna 20. The Vmcu waveform labeled 25 shows the drop 30 of Vmcu voltage when wireless MCU 15 transmits RF signals (as indicated by the “transmission active” waveform 35).

[0029] Attempting to draw too much current from battery 10 can cause the MCU voltage level Vmcu to drop to a level where the wireless MCU 15 stops working or ceases to operate as intended or designed. More specifically, by drawing a current greater than that that battery 10 can provide or sustain during transmit operations, Vmcu drops below the specified minimum operating voltage of the wireless MCU 15 (labeled the "MCU operating limit"). Drawing too much current from the battery can also shorten battery life, meaning that the battery provides less total energy than expected or specified over its entire lifespan.

[0030] Figure 2 This diagram illustrates a circuit arrangement for supplying power to a load using an energy storage capacitor, or typically a capacitor 56 (which holds a storage voltage Vstore (i.e., the voltage across the energy storage device, such as capacitor 56)). To improve the effective performance of the battery, a power management system is used to store energy in capacitor 56 (or other storage elements, components, or devices) for use when required by the transmitting circuit system (labeled "TX") 59 (or TX circuit system 59). TX circuit system 59 may include various circuit systems such as MCU circuit systems, RF circuit systems, other loads or circuits (whether transmitting or other types of circuitry), etc.

[0031] The circuit layout uses a power management circuit 53 to provide power to the transmitting circuit system 59. The power management circuit system 53 can provide a relatively large voltage (greater than the battery voltage Vbatt) across the capacitor 56, labeled Vstore. The voltage across the capacitor 56 is equal to the energy stored, and the stored energy can be used when the TX circuit system 59 draws more current than the battery 10 can provide, such as during transmission.

[0032] Figure 3 Showing with Figure 2 The waveforms are related to the circuit layout. During transmission, the level of Vstore 62 decreases, but the voltage Vtx 65 (the voltage across the TX circuit system 59) remains stable (or relatively or almost stable, as is the case in the actual physical implementation), due to the fact that Vstore is higher than Vbatt and Vtx, and due to the operation of the power management circuit 53 (which supplies energy to the capacitor 56).

[0033] like Figure 3 As shown, the circuit provides a voltage Vtx 65 that is higher than the minimum operating limit voltage 68 during the active period of the transmission active voltage 35. Therefore, the energy from the storage capacitor 56 is providing most of the power to the TX circuit system 59, and the battery 10 is primarily used to recharge the storage capacitor 56 between transmissions (i.e., when the TX circuit system 59 is not transmitting). Furthermore, since the recovery rate of Vstore 62 can be made relatively or considerably slow by the power management circuit 53, which is equivalent to drawing a relatively small current from the battery 10, the risk of damaging the battery 10 or shortening its lifespan is reduced.

[0034] In some cases, the TX circuit system 59 can perform a relatively large number of operations in a relatively short amount of time, such as sending RF signals. Figure 4 This situation is illustrated. More specifically, the transmission activity voltage 35 represents the transmission of a single message, which causes a corresponding drop in the Vstore voltage 62. The voltage difference between the Vstore voltage 62 and the minimum operating limit 68 represents the energy reserve stored in the capacitor 56, which can decrease during the activity of the TX circuit system 59. By appropriately designing the capacitance of the capacitor 56 and the nominal value of the Vstore voltage 62 compared to the minimum operating limit, the system has sufficient reserve energy to maintain the Vtx voltage 65 at a relatively constant value during a single TX operation. In other words, even when transmitting a single message, the Vtx voltage 65 remains above the minimum operating limit voltage 68.

[0035] In contrast, when multiple messages are sent (see transmit activity voltage 35), the energy stored in capacitor 56 can be fully depleted to cause Vstore voltage 62 to drop. As a result, power management circuitry system 53 has no energy reserve for capacitor 56 to draw upon to supplement the current from battery 10. Consequently, Vtx voltage 65 drops below the operating limit voltage 68. TX circuitry system 59 ceases normal operation or operates as expected or desired.

[0036] According to one aspect of this disclosure, a handshake mechanism is used to avoid the above situation. Figure 5 The diagram illustrates a circuit arrangement for supplying power to a load, according to an exemplary embodiment, using a handshake mechanism.

[0037] More specifically, the circuit arrangement includes monitoring circuitry 71. Monitoring circuitry 71 monitors the level of energy stored in capacitor 56 (or other energy storage device or component or circuitry used in various embodiments). Typically, depending on the type of storage device used, monitoring circuitry 71 determines the level of stored energy.

[0038] In the case of a capacitor, the level of stored energy depends on the capacitance of capacitor 56 and the voltage across it. Therefore, by using the capacitance of capacitor 56 (which is known a priori), monitoring circuit 71 derives the amount or level of energy stored in capacitor 56 and uses this amount to provide a signal to TX circuit system 59. When capacitor 56 is used as an energy storage device, monitoring circuit 71 can simply be configured as a voltage comparator, which compares the voltage across capacitor 56 with the minimum value of Vstore voltage 62 that allows for correct transmission operation (labeled "Vstore Min for transmission").

[0039] exist Figure 5 In the illustrated embodiment, the signal is labeled "OK-to-transmit" (OKTT). The OKTT signal is provided to the TX circuitry 59. Unless the OKTT signal indicates that the storage device (e.g., capacitor 56) has sufficient stored energy to sustain the transmission operation, the TX circuitry 59 does not participate in the transmission operation. Figure 6 The waveform corresponding to this scheme is shown.

[0040] When the Vstore voltage 62 is above the "Vstore Min." level for transmission, the OKTT signal 77 has a logic high value (the monitoring circuit 71 asserts the OKTT signal 77), which indicates to the TX circuit system 59 that it can perform a transmission operation. When a transmission operation is performed, the level of the Vstore voltage 62 decreases and eventually falls below the "Vstore Min." level for transmission.

[0041] At this point, the monitoring circuit 71 cancels the assertion on the OKTT signal 77, which will prevent the TX circuit system from performing further transmission operations. Figure 6 As shown, in the case of multiple messages (multiple send operations), the cancellation assertion of the OKTT signal 77 causes a delay in the send operation. In other words, the TX circuit system delays the send operation until the monitoring circuit 71 asserts the OKTT signal 77 again.

[0042] This approach can be used in communication systems that employ coexistence signaling. Coexistence signaling (also known as packet traffic arbitration or PTA signaling) is used in certain communication standards (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.15.2 standard). As understood by those skilled in the art, PTA or coexistence signaling is used to prevent two ICs or transmitters from transmitting simultaneously.

[0043] PTA or coexistence signaling can be applied to Figure 5 The circuit layout in the middle. Figure 7 The circuit arrangement obtained according to an exemplary embodiment is shown. More specifically, Figure 7The OKTT signal in the TX circuitry drives the "authorization" input of the TX circuitry 59. The authorization input is used by the TX circuitry 59 as part of a PTA or coexistence signaling scheme. In response to the assertion OKTT signal (assertion authorization signal), the TX circuitry 59 begins transmission operation, and vice versa.

[0044] Using the OKTT signal as a grant signal in PTA or coexistence signaling applications allows the utilization of well-defined transmit-hold mechanisms used in communication system standards. An example of such a standard is the IEEE 802.15.4 standard. Another example is a standard for managing Bluetooth applications.

[0045] Figure 5 and Figure 7 The scheme described above uses a one-way handshake (monitoring circuit 71 provides an OKTT signal (authorization signal) to the TX circuit system 59). In some embodiments, a two-way handshake scheme is used. Figure 7 The circuit arrangement according to the exemplary embodiment is described.

[0046] More specifically, similar to the embodiments described above, Figure 8 The embodiments in the example use the OKTT signal as an authorization signal as part of the PTA or coexistence signaling arrangement. Additionally, Figure 8 The embodiments in the example use a request (REQ) signal as part of a PTA or coexistence signaling arrangement.

[0047] By using the REQ signal, the TX circuit system 59 can signal the monitoring circuit 71 to prepare for or attempt to begin a transmission operation. The monitoring circuit 71 signals the TX circuit system 59 to begin a transmission operation via the OKTT (authorization) signal. In this way, a two-way handshake is established between the monitoring circuit 71 and the TX circuit system 59.

[0048] In some embodiments, the REQ signal can be used to reduce the power consumption of the monitoring circuit 71. More specifically, when the TX circuit system 59 does not assert the REQ signal, the monitoring circuit 71 or a portion thereof is de-energized (or turned off or placed in a low-power state (compared to the powered-on or normal operating state)).

[0049] In order to sense changes in the REQ signal, a portion of the monitoring circuit 71 remains powered even if the assertion of the REQ signal is canceled. Other parts of the monitoring circuit 71 can be powered off to save energy.

[0050] In contrast, when the REQ signal is asserted—that is, when the TX circuitry 59 indicates that it is attempting to perform a transmit operation—the monitoring circuitry 71 transitions from a power-off state to a normal operating state, in which it can respond to the assertion of the REQ signal as described above. In this way, the overall power consumption in this type of embodiment can be reduced.

[0051] As those skilled in the art will understand, power deactivation of the circuitry in monitoring circuitry 71 can be achieved in a variety of ways. For example, one or more bias signals in or used by monitoring circuitry 71 may be disabled or modified. As another example, power to a portion of monitoring circuitry 71 may be cut off (e.g., by controlling power supply using a transistor). As those skilled in the art will understand, other possibilities exist and are contemplated.

[0052] In the various embodiments described above, the monitoring circuit 71 is shown as a separate circuit system from the power management circuit 53 and the TX circuit system 59. However, other variations are possible and are considered. Figure 9 and 10 An example according to an exemplary embodiment is shown.

[0053] refer to Figure 9 In this embodiment, the circuitry in monitoring circuit 71 is combined with or included in the circuitry of power management circuit 53. The circuitry corresponding to monitoring circuit 71 (in this example, included in power management circuit 53) performs the above-described functionality in other ways.

[0054] refer to Figure 10 In this embodiment, the circuitry in monitoring circuit 71 is merged with or included in the circuitry of TX circuitry 59. The circuitry corresponding to monitoring circuit 71 (in this example, included in TX circuitry 59) performs the above-described functionality in other ways.

[0055] In various embodiments, as those skilled in the art will understand, the circuit system corresponding to the monitoring circuit 71 can be implemented in a variety of ways. For example, Figure 11 The monitoring circuit 71 according to the exemplary embodiment is described.

[0056] More specifically, in this embodiment, the monitoring circuit 71 includes a comparator 85 and a power control circuit 87. The comparator 85 compares the Vstore voltage with a reference voltage (Vref). Based on the relative values ​​of the Vstore and Vref voltages, the comparator 85 generates an OKTT signal (authorization signal) as its output voltage.

[0057] Therefore, if the Vstore voltage is higher than the threshold (Vref), there is sufficient energy in the energy storage device (e.g., capacitor 56 (not shown)) for transmission operation. Comparator 85 asserts the OKTT signal to indicate this condition. Conversely, if the Vstore voltage is lower than the threshold (Vref), there is insufficient energy in the energy storage device for transmission operation. In this case, comparator 85 cancels the assertion of the OKTT signal.

[0058] The power control circuit 87 provides power to the comparator 85. More specifically, the power control circuit 87 provides a supply voltage Vcomp to the comparator 85. The power control circuit 87 changes the value of the Vcomp voltage according to the state of the REQ signal.

[0059] More specifically, if the REQ signal is canceled from assertion (i.e., no transmit operation is sought), the power control circuit 87 reduces the Vcomp voltage (e.g., to ground potential). As a result, as described above, the circuitry in comparator 85 is de-energized to conserve energy.

[0060] In contrast, if the REQ signal is asserted (i.e., a transmit operation is sought), the power control circuit 87 increases the Vcomp voltage (e.g., to the appropriate supply voltage for comparator 85). As a result, the circuitry in comparator 85 is powered and performs the comparison operation described above.

[0061] It should be noted that Figure 11 The illustrated embodiment corresponds to controlling the power supply to comparator 85 by controlling the supply voltage of comparator 85. However, as mentioned above, there are other possibilities to reduce the power consumption of monitoring circuit 71, for example, by modifying one or more bias signals used by monitoring circuit 71. In this case, it is not as... Figure 11 The power control circuit 87 modifies one or more bias signals used by the comparator 85 by controlling the supply voltage of the comparator 85.

[0062] Figure 12 The diagram illustrates a circuit arrangement for a power management circuit 53 according to an exemplary embodiment. In this embodiment, the power management circuit 53 uses a step-up power converter 92 to generate a Vstore voltage, using a voltage Vbatt as the input voltage. Additionally, the power management circuit 53 uses a step-down power converter 94 to generate a Vtx voltage, using a voltage Vstore as the input voltage. A controller 90 controls the operation of the power management circuit 53, including the operation of the step-up converter 92 and the step-down converter 94.

[0063] More specifically, battery 10 (not shown) provides voltage Vbatt to boost converter 92. As those skilled in the art will understand, boost converter 92 uses inductor Lboost to perform the voltage increment operation. Therefore, boost converter 92 increments voltage Vbatt to output voltage Vstore.

[0064] As described above, voltage Vstore is supplied to the energy storage device. In the exemplary embodiment shown, the energy storage device constitutes capacitor 56. As described above, voltage Vstore is greater than voltage Vbatt.

[0065] The voltage Vstore is used as the input voltage of the buck converter 94. As those skilled in the art will understand, the buck converter 94 uses an inductor Lbuck to perform a voltage shaving operation. Therefore, the buck converter 94 reduces the voltage Vstore to the output voltage Vtx. As mentioned above, the voltage Vstore is greater than the voltage Vtx.

[0066] A voltage Vstore is also provided to the controller 90. As those skilled in the art will understand, the controller 90 uses the voltage Vstore to generate a set of control signals 96 and provides them to the boost converter 92. As those skilled in the art will understand, this set of control signals 96 is used to control various operations of the boost converter 92, such as turning a power switch (not shown) on and off, disabling or enabling the boost converter 92, etc.

[0067] Similarly, as those skilled in the art will understand, controller 90 uses voltages Vstore and Vtx to generate a set of control signals 98 and provides them to buck converter 94. As those skilled in the art will understand, this set of control signals 98 is used to control various operations of buck converter 94, such as turning a power switch (not shown) on and off, disabling or enabling buck converter 94, etc.

[0068] It should be noted that Figure 12 The circuit arrangement illustrated is merely an example. As will be understood by those skilled in the art, other ways of implementing the power management circuit 53 are possible and considered. Furthermore, other types of converters (e.g., buck-boost converters) may be used as needed and as will be understood by those skilled in the art. As will be understood by those skilled in the art, the choice of converter type and topology depends on factors such as design specifications, performance specifications, cost, IC or device area, available technologies such as semiconductor manufacturing technology, target market, target end user, etc.

[0069] Furthermore, although this disclosure uses transmitting circuit system 59 to illustrate various concepts, other circuit systems may be used in various embodiments, as will be understood by those skilled in the art. As will be understood by those skilled in the art, circuit 59 may typically constitute a load that draws periodic current or burst current during its operation.

[0070] The circuit systems according to various embodiments can be used as needed for various circuits, systems, subsystems, ICs, etc., such as communication setups, systems, subsystems, networks, etc. Figure 13 A system 500 for radio communication is illustrated according to an exemplary embodiment. The TX circuit system 59 in system 500 may use or be based on a circuit system according to various embodiments (as described above). Therefore, as described above, the TX circuit system 59 may include an energy storage device to provide power to the transmitting circuit system.

[0071] refer to Figure 13 System 500 includes a TX circuit system 59A coupled to antenna 20A. TX circuit system 59A transmits RF signals via antenna 20A. The RF signals can be received by receiver 510. Alternatively, transceiver 520A and / or transceiver 520B can receive the transmitted RF signals (via receiver 510).

[0072] In addition to their receiving capabilities, transceivers 520A and 520B can also transmit RF signals using the TX circuitry 59. The transmitted RF signals can be received by receiver 510 either in a separate receiver or via a receiver circuitry system other than the transmitting transceiver.

[0073] Other systems or subsystems with different configurations and / or capabilities are also considered. For example, in some exemplary embodiments, two or more transceivers (e.g., transceiver 520A and transceiver 520B) may form a network, such as an ad-hoc network. As another example, in some exemplary embodiments, transceiver 520A and transceiver 520B may form part of a network, for example, incorporating TX circuit system 59A.

[0074] The circuit systems according to the various embodiments described above can be used in a variety of circuits, blocks, subsystems, and / or systems. For example, in some embodiments, such circuit systems can be integrated into an IC, such as an MCU IC. Figure 14 A block diagram of IC 550 according to an exemplary embodiment is shown. Figure 15 A block diagram of IC 550 is shown, which (in addition to TX circuitry 59) also includes receiver 510 (as part of transceiver 520).

[0075] The circuit layout includes an IC 550 that constitutes or includes an MCU. The IC 550 includes multiple blocks (e.g., one or more processors 565, data converters 605, I / O circuitry systems 585, etc.) that communicate with each other via links 560. In an exemplary embodiment, the links 560 may constitute a coupling mechanism for transmitting information such as data, commands, status information, etc., such as a bus, a set of conductors, or semiconductor elements (e.g., traces, devices, etc.).

[0076] IC 550 may include links 560 coupled to one or more processors 565, clock circuitry 575, and power management circuitry or power management unit (PMU) 580. In some embodiments, the one or more processors 565 may include circuitry or blocks for providing information processing (or data processing or computation) functions, such as a central processing unit (CPU), an arithmetic logic unit (ALU), etc. In some embodiments, additionally or alternatively, the one or more processors 565 may include one or more DSPs. The DSP may provide various signal processing functions as needed, such as arithmetic functions, filtering, delay blocks, etc.

[0077] Clock circuitry system 575 can generate one or more clock signals that facilitate or control the timing of operation of one or more blocks in IC 550. Clock circuitry system 575 can also control the timing of operation using link 560 as needed. In some embodiments, clock circuitry system 575 can provide one or more clock signals to other blocks in IC 550 via link 560.

[0078] In some embodiments, for a portion of the circuit or all components of the circuit, such as one or more blocks in IC 550, PMU 580 may reduce the clock speed of the device (e.g., IC 550), turn off the clock, reduce power, turn off the power supply, disable (or power off or place in a lower power consumption or sleep or inactive or idle state), enable (or power on or place in a higher power consumption or normal or active state), or any combination of the foregoing. Furthermore, in response to a transition from an inactive state to an active state (including, but not limited to, when one or more processors 565 transition from a low power or idle or sleep state to a normal operating state), PMU 580 may turn on the clock, increase the clock rate, turn on the power supply, increase power, or any combination of the foregoing.

[0079] The PMU 580 may further include a controller 90 (not shown) and a power management circuit 53 (not shown). Thus, as described above, the PMU 580, together with the energy storage device (not shown), provides power to the TX circuit system 59.

[0080] Link 560 can be coupled to one or more circuits 600 via serial interface 595. Through serial interface 595, one or more circuits or blocks coupled to link 560 can communicate with circuit 600. Circuit 600 can use one or more serial protocols such as SMBUS, I... 2 Communication is achieved through C, SPI, etc.

[0081] Link 560 can be coupled to one or more peripheral devices 590 via I / O circuit system 585. Through I / O circuit system 585, one or more peripheral devices 590 can be coupled to link 560 and thus can communicate with one or more blocks (e.g., one or more processors 565, memory circuit 625, etc.) coupled to link 560.

[0082] In an exemplary embodiment, peripheral device 590 may include various circuit systems, blocks, etc. Examples include I / O devices (keyboard, keyboard, speaker, display device, storage device, timer, sensor, etc.). It should be noted that in some embodiments, some peripheral devices 590 may be external to IC 550. Examples include keyboard, speaker, etc.

[0083] In some embodiments, the I / O circuitry system 585 can be bypassed relative to some peripheral devices. In such embodiments, some peripheral devices 590 can be coupled to and communicate with the link 560 without using the I / O circuitry system 585. In some embodiments, as described above, such peripheral devices can be external to the IC 550.

[0084] Link 560 can be coupled to analog circuit system 620 via one or more data converters 605. The one or more data converters 605 may include one or more ADCs 605A and / or one or more DACs 605B.

[0085] One or more ADCs 605A receive one or more analog signals from analog circuitry 620 and convert them into digital format. The ADCs 605A then transmit these digital signals to one or more blocks coupled to link 560. In contrast, one or more DACs 605B receive one or more digital signals from one or more blocks coupled to link 560 and convert them into analog format. The DACs 605B then transmit these digital signals to analog circuitry 620.

[0086] Analog circuit system 620 may include a variety of circuit systems that provide and / or receive analog signals. Examples include sensors, transducers, etc., as will be understood by those skilled in the art. In some embodiments, analog circuit system 620 may communicate with circuit systems external to IC 550 as needed to form more complex systems, subsystems, control blocks or systems, feedback systems, and information processing blocks.

[0087] Control circuitry system 570 is coupled to link 560. Therefore, control circuitry system 570 can communicate with and / or control the operation of each block coupled to link 560 by providing control information or signals. In some embodiments, control circuitry system 570 also receives status information or signals from each block coupled to link 560. Additionally, in some embodiments, control circuitry system 570 facilitates (or controls or monitors) communication or cooperation between the blocks coupled to link 560.

[0088] In some embodiments, control circuitry 570 may initiate or respond to a reset operation or signal. As those skilled in the art will understand, this reset operation may cause a reset of one or more blocks coupled to link 560, one or more blocks of IC 550, etc. For example, control circuitry 570 may reset PMU 580 and circuitry such as TX circuitry 59 to an initial or known state.

[0089] In an exemplary embodiment, the control circuit system 570 may include various types of circuit systems and blocks of circuit systems. In some embodiments, the control circuit system 570 may include a logic circuit system, a finite state machine (FSM), or other circuit systems to perform operations as described above.

[0090] Communication circuitry 640 is coupled to link 560 and also to external circuitry or blocks (not shown) of IC 550. Through communication circuitry 640, various blocks coupled to link 560 (or IC 550 in general) can communicate with external circuitry or blocks (not shown) via one or more communication protocols. Examples of communication include USB, Ethernet, etc. In exemplary embodiments, as will be understood by those skilled in the art, other communication protocols may be used depending on factors such as the design or performance specifications of a given application.

[0091] As noted, memory circuitry 625 is coupled to link 560. Therefore, memory circuitry 625 can communicate with one or more blocks coupled to link 560, such as one or more processors 565, control circuitry 570, I / O circuitry 585, etc.

[0092] As will be understood by those skilled in the art, memory circuitry 625 provides storage for various information or data (such as operands, flags, data, instructions, etc.) in IC 550. Depending on the requirements, memory circuitry 625 can support various protocols, such as Double Data Rate (DDR), DDR2, DDR3, DDR4, etc.

[0093] In some embodiments, memory read and / or write operations performed by memory circuitry 625 involve the use of one or more blocks in IC 550, such as one or more processors 565. Direct memory access (DMA) arrangements (not shown) allow for improved memory operation performance in certain situations. More specifically, DMA (not shown) provides a mechanism for performing memory read and write operations directly between the source or destination of data and memory circuitry 625 without going through blocks (such as one or more processors 565).

[0094] Memory circuitry 625 may include various memory circuits or blocks. In the illustrated embodiment, memory circuitry 625 includes non-volatile (NV) memory 635. Alternatively, memory circuitry 625 may include volatile memory (not shown), such as random access memory (RAM). NV memory 635 may be used to store information relating to the performance, control, or configuration of one or more blocks in IC 550. For example, NV memory 635 may store configuration information relating to PMU 580, TX circuitry system 59, etc.

[0095] The various circuits and blocks described above and used in the exemplary embodiments can be implemented in various ways and using various circuit elements or blocks. For example, the TX circuit system 59, power management circuit 53, monitoring circuit 71, comparator 85, power control circuit 87, controller 90, boost converter 92, and buck converter 94, or portions thereof, can be implemented using a digital circuit system. As needed and as will be understood by those skilled in the art, the digital circuit system may include circuit elements or blocks such as gates, digital multiplexers (MUX), latches, flip-flops, registers, finite state machines (FSMs), processors, programmable logic (e.g., field-programmable gate arrays (FPGAs)) or other types of programmable logic), arithmetic logic units (ALUs), standard units, custom units, custom analog units, etc. Additionally, as needed, it may include analog circuit systems or mixed-signal circuit systems, or both, such as power converters, discrete devices (transistors, capacitors, resistors, inductors, diodes, etc.). As required and as understood by those skilled in the art, analog circuit systems may include bias circuits, decoupling circuits, coupling circuits, power supply circuits, current mirrors, current and / or voltage sources, filters, amplifiers, converters, signal processing circuits (e.g., multipliers), detectors, transducers, discrete components (transistors, diodes, resistors, capacitors, inductors), analog MUXs, etc. As required and as understood by those skilled in the art, in addition to the analog and digital circuit systems described above, mixed-signal circuit systems may also include analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc. As will be understood by those skilled in the art, the selection of a circuit system for a given implementation depends on a variety of factors. These factors include design specifications, performance specifications, cost, IC or device area, available technologies (such as semiconductor manufacturing technology), target market, target end user, etc.

[0096] Referring to the accompanying drawings, those skilled in the art will notice that the various blocks shown primarily depict conceptual functions and signal flows. Actual circuit implementations may or may not include individually identifiable hardware for each functional block, and may or may not use the specific circuitry shown. For example, the functions of various blocks may be combined into a single circuit block as needed. Furthermore, the functions of individual blocks among several circuit blocks may be implemented as needed. The choice of circuit implementation depends on various factors, such as the specific design and performance specifications for a given implementation. Other modifications and alternative embodiments besides those in this disclosure will be apparent to those skilled in the art. Therefore, this disclosure teaches those skilled in the art how to implement the disclosed concepts according to exemplary embodiments and is to be interpreted as exemplary only. As will be understood by those skilled in the art, the drawings may be drawn to scale or not, where applicable.

[0097] The specific forms and embodiments shown and described constitute exemplary embodiments only. Various changes can be made to the shape, size, and arrangement of the components by those skilled in the art without departing from the scope of this disclosure. For example, those skilled in the art can substitute equivalent elements for the illustrated and described elements. Furthermore, those skilled in the art can use certain features of the disclosed concepts independently of the use of other features without departing from the scope of this disclosure.

Claims

1. An apparatus comprising: A power management circuit is configured to receive an input voltage and generate a first output voltage and supply it to an energy storage device, the power management circuit is further configured to generate a second output voltage and supply it to a load, wherein the first output voltage is greater than the input voltage, and wherein the second output voltage is less than the first output voltage; and A monitoring circuit is used to monitor the first output voltage and provide a signal to the load to indicate when the load is able to perform an operation, wherein the monitoring circuit provides the signal to the TX circuit system to indicate when the TX circuit system is able to perform a transmission operation.

2. The device according to claim 1, wherein, The energy storage device includes a capacitor.

3. The device according to claim 2, wherein, The monitoring circuit includes a comparator to compare the first output voltage with a reference voltage.

4. The device according to claim 1, wherein, The load includes the transmitting circuit system, i.e., the TX circuit system.

5. The device according to claim 1, wherein, When the TX circuit system attempts to perform a transmission operation, the TX circuit system sends an assertion request signal, i.e., a REQ signal, to the monitoring circuit.

6. The device according to claim 5, wherein, The monitoring circuit is powered off until the REQ signal is asserted.

7. The device according to claim 1, wherein, The power management circuit includes a boost converter to convert the input voltage into the first output voltage, and wherein the power management circuit further includes a buck converter to convert the first output voltage into the second output voltage.

8. The device according to claim 1, further comprising: A battery for providing the input voltage, wherein the monitoring circuit provides the signal to the load to prevent the first output voltage from dropping below a level that would prevent the operation from being performed.

9. An apparatus comprising: A power management circuit is used to receive an input voltage and boost the input voltage to generate a storage voltage and supply it to a capacitor. The power management circuit is also used to convert the storage voltage into a supply voltage supplied to the transmitting circuit system, i.e., the TX circuit system, wherein the storage voltage is greater than the input voltage and wherein the supply voltage is less than the storage voltage. and A monitoring circuit is used to monitor the stored voltage and provide a signal to the TX circuit system to indicate when the TX circuit system is able to perform a transmission operation.

10. The device according to claim 9, wherein, The signals provided to the TX circuit system include a ready-to-transmit signal.

11. The device according to claim 10, wherein, The TX circuit system uses the ready transmit signal as the authorization signal.

12. The device according to claim 11, wherein, The TX circuit system provides a request signal, i.e., a REQ signal, to the monitoring circuit to request the execution of a transmission operation.

13. The device according to claim 9, wherein, The input voltage is provided by the battery, and the signal provided to the TX circuit system is used to prevent the stored voltage from dropping below the minimum operating limit of the TX circuit system.

14. A method for providing power to a load, the method comprising: It receives the input voltage and generates the first output voltage; The first output voltage is supplied to the energy storage device; A second output voltage is generated based on the first output voltage; The second output voltage is supplied to the load; Monitor the first output voltage and provide a signal to the load to indicate when the load is able to perform an operation.

15. The method according to claim 14, wherein, The energy storage device includes a capacitor.

16. The method of claim 14, wherein, The load includes a transmitting circuit system, i.e., a TX circuit system, and wherein the signal provided to the TX circuit system indicates when the TX circuit system is capable of performing a transmitting operation.

17. The method of claim 16, further comprising an assertion request signal, i.e., a REQ signal, when the TX circuitry attempts to perform a transmission operation.

18. The method according to claim 14, wherein, Receiving the input voltage includes receiving the battery voltage.

19. The method according to claim 15, wherein, The signal is provided to the load to prevent the first output voltage from dropping below a level that would prevent the operation from being performed.

Images