Semiconductor device and method of manufacturing semiconductor device

Abstract

Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a substrate having a substrate top side, a substrate lateral side, and a substrate bottom side; an electronic device on the substrate top side; and an encapsulant on the substrate top side contacting a lateral surface of the electronic device. The substrate includes a conductive structure and a dielectric structure, the dielectric structure including a protrusion in contact with the encapsulant. The conductive structure includes a lead, the lead including a lead flank, the lead flank including a cavity and a conductive coating on a surface of the lead in the cavity. The conductive structure includes a pad exposed at the substrate top side, the pad embedded in the dielectric structure and adjacent to the protrusion to electrically couple with the electronic device via a first internal interconnect. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] This disclosure relates generally to electronic devices, and more specifically to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] Existing semiconductor devices and methods for forming semiconductor devices are inadequate, for example, resulting in excessively high costs, reduced reliability, relatively low performance, or excessively large device sizes. By comparing conventional and traditional methods with this disclosure and referring to the accompanying drawings, those skilled in the art will understand the further limitations and disadvantages of conventional and traditional methods. Summary of the Invention

[0003] This disclosure provides a semiconductor device comprising: a substrate having a top side, a lateral side, and a bottom side; an electronic device on the top side of the substrate; and a sealant on the top side of the substrate and contacting the lateral surface of the electronic device; wherein the substrate includes a conductive structure and a dielectric structure, the dielectric structure including protrusions in contact with the sealant; wherein the conductive structure includes leads, the leads including lead wings, the lead wings including cavities and a conductive coating on the surface of the lead wings in the cavities; and wherein the conductive structure includes pads exposed at the top side of the substrate, the pads being embedded in the dielectric structure and adjacent to the protrusions for electrical coupling to the electronic device via a first internal interconnect. In the semiconductor device, the conductive structure includes a paddle pad; and a second internal interconnect extends from the bottom side of the electronic device and is coupled to the paddle pad. In the semiconductor device, the dielectric structure includes a dielectric layer extending from the bottom side of the substrate to the top side of the substrate. In the semiconductor device, the cavities of the lead wings are pit-shaped. In the semiconductor device, the substrate includes: a first inner side of the substrate perpendicular to its lateral side; and a second inner side of the substrate perpendicular to its bottom side; the first inner side of the substrate includes a first inner surface of the dielectric structure and a first coating surface of the conductive coating; the second inner side of the substrate includes a second inner surface of the dielectric structure and a second coating surface of the conductive coating; and the first inner side of the substrate is perpendicular to the second inner side of the substrate. In the semiconductor device, the protrusion defines the lateral surface of the pad and extends into the sealant. In the semiconductor device, the lead wing is electrically coupled to a circuit pattern of an external device via solder filling the cavity, the lead wing covering most of the height of the lead and being visible by visual inspection. In the semiconductor device, the dielectric structure includes a first molding material layer; and the sealant includes a second molding material layer in contact with the first material layer. In the semiconductor device, the cavity includes: a first lead surface of the lead; a second lead surface of the lead perpendicular to the first lead surface; a first side pillar surface of the dielectric structure perpendicular to the first lead surface and the second lead surface; and a second side pillar surface of the dielectric structure perpendicular to the first lead surface and the second lead surface, and spanning the cavity opposite to the first side pillar surface.

[0004] This disclosure provides a method for manufacturing a semiconductor device, comprising: forming a conductive layer on a carrier; forming pads and leads on a top surface of the conductive layer; forming a dielectric structure on the top surface of the conductive layer, wherein the dielectric structure covers the pads and leads; thinning the dielectric structure until the leads are exposed; etching the leads such that the surface of the leads is recessed relative to the surface of the dielectric structure; forming a cavity in the leads adjacent to the dielectric structure; forming an electroplated layer on the leads, including on the surface of the leads in the cavity, to form wettable winglets corresponding to the electroplated leads in the cavity; and removing the carrier and etching the conductive layer such that protrusions of the dielectric structure protrude beyond the bottom surface of the pads. The method further comprises: placing an electronic device on the bottom surface of the conductive layer to electrically couple the electronic device to a paddle pad or the pads; and forming a sealant on the electronic device, wherein the sealant contacts a lateral surface of the electronic device, and the protrusions of the dielectric structure extend into a film compound. In the method, forming the pads includes performing patterned electroplating on the conductive layer. The method further includes forming a paddle-shaped pad on the top surface of the conductive layer; wherein forming the leads includes performing electroplating on the conductive layer. In the method, thinning the dielectric structure includes polishing the dielectric structure. In the method, forming the pads and leads includes forming lead bases for the pads and leads on the conductive layer; and electroplating the lead bodies onto the lead bases.

[0005] This disclosure provides a method for manufacturing a semiconductor device, comprising: forming a dielectric structure in a conductive structure, wherein the dielectric structure includes protrusions and the conductive structure includes pads defined by the protrusions; forming cavities in leads adjacent to the dielectric structure; and forming an electroplating layer on the conductive structure to cover the leads, including covering the surfaces of the leads in the cavities, wherein the electroplated cavities form wettable winglets. The method further comprises: attaching an electronic device to the conductive structure, wherein the electronic device is electrically coupled to the pads via internal interconnects; and forming a film compound to cover the electronic device, wherein the film compound contacts side surfaces of the electronic device, and wherein the protrusions of the dielectric structure extend into the film compound. In the method, forming the cavity includes forming a first cavity surface perpendicular to a second cavity surface. In the method, forming the cavity includes forming a cavity surface with a pit shape. In the method, the protrusions above the top surface of the pads; and the bottom portion of the internal interconnects is defined by the protrusions. Attached Figure Description

[0006] Figure 1A A cross-sectional view of an example semiconductor device is shown. Figure 1B A bottom view of an example semiconductor device is shown, and Figure 1C It shows Figure 1B A magnified view of area 1C.

[0007] Figures 2A to 2L A cross-sectional view of an example method for manufacturing a semiconductor device is shown.

[0008] Figure 3 A partial enlarged view of an example of a wettable wing of a semiconductor device is shown.

[0009] Figure 4 A partial enlarged view of an example of a wettable wing of a semiconductor device is shown.

[0010] Figure 5 A cross-sectional view is shown of an instance state in which a semiconductor device can be soldered to an external device.

[0011] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are not limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0012] The accompanying drawings illustrate a general construction method, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring this disclosure. Furthermore, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different drawings denote the same elements.

[0013] The term "or" refers to any one or more items added to a list via "or". For example, "x or y" refers to any element in the set of three elements {(x), (y), (x,y)}. As another example, "x, y or z" refers to any element in the set of seven elements {(x), (y), (z), (x,y), (x,z), (y,z), (x,y,z)}.

[0014] The terms “comprises / comprising” and “includes / including” are “open-ended” terms and specify the presence of the stated feature, but do not exclude the presence or addition of one or more other features.

[0015] The terms “first,” “second,” etc., can be used to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, a first element discussed herein can be referred to as a second element.

[0016] Unless otherwise stated, the term "coupled" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A can be coupled to element B, then element A can be in direct contact with element B or indirectly connected to element B through an intermediate element C. Similarly, the terms "above" or "on" can be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. Geometric descriptive terms, such as coplanar, planar, perpendicular, horizontal, etc., not only cover such precise terms but also broad approximations of such terms, for example, within manufacturing tolerances. Detailed Implementation

[0017] A semiconductor device includes: a substrate having a top side, a lateral side, and a bottom side; an electronic device on the top side; and a sealant on the top side contacting the lateral surface of the electronic device. The substrate includes a conductive structure and a dielectric structure, the dielectric structure including protrusions in contact with the sealant. The conductive structure includes leads, the leads including lead wings, the lead wings including cavities, and a conductive coating on the surfaces of the lead wings within the cavities. The conductive structure includes pads exposed at the top side of the substrate, the pads being embedded in the dielectric structure and adjacent to the protrusions for electrical coupling to the electronic device via a first internal interconnect.

[0018] A method of manufacturing a semiconductor device includes: forming a conductive layer on a carrier; forming pads and leads on a top surface of the conductive layer; forming a dielectric structure on the top surface of the conductive layer, wherein the dielectric structure covers the pads and leads; thinning the dielectric structure until the leads are exposed; etching the leads such that the surface of the leads is recessed relative to the surface of the dielectric structure; forming a cavity in the leads adjacent to the dielectric structure; forming an electroplated layer on the leads (including on the surface of the cavity) to form wettable winglets corresponding to the electroplated cavity; and removing the carrier and etching the conductive layer such that protrusions of the dielectric structure protrude beyond the bottom surface of the pads.

[0019] A method of manufacturing a semiconductor device includes: providing a dielectric structure in a conductive structure, wherein the dielectric structure includes protrusions and the conductive structure includes pads defined by the protrusions; forming a cavity in a lead adjacent to the dielectric structure; and providing an electroplated layer on the conductive structure to cover the lead (including a surface covering the cavity), wherein the electroplated cavity forms wettable winglets.

[0020] Other examples are included in this disclosure. Such examples can be found in the accompanying drawings, claims, or description of this disclosure.

[0021] Figure 1A A cross-sectional view of the example semiconductor device 100 is shown. Figure 1B A bottom view of the example semiconductor device 100 is shown, and Figure 1C It shows Figure 1B A magnified view of area 1C. Figures 1A to 1C In the illustrated example, semiconductor device 100 may include a substrate 110, an electronic device 130 mounted on the substrate 110, and a sealant (or film compound) 140 covering the substrate 110 and the electronic device 130. In some examples, the substrate 110 may be referred to as a pre-molded substrate and may include a substrate top side 110X, a substrate lateral side 110Y, and a substrate bottom side 110Z. In some examples, the electronic device 130 may be on the substrate top side 110X, and the sealant 140 may be on the substrate top side 110X and contact the lateral surface of the electronic device 130. The substrate 110 may include a conductive structure 116 and a dielectric structure 127, the dielectric structure 127 mechanically (i.e., non-electrically) connecting different elements of the conductive structure 116. In some examples, the dielectric structure 127 may include a protrusion in a protrusion 128 that contacts the sealant 140.

[0022] In some instances, the conductive structure 116 may include a paddle 111 or a die pad. Furthermore, the conductive structure 116 may include pads 117 and leads 118. The paddle 111 may be exposed at the top side 110X of the substrate and embedded in the dielectric structure 127. The conductive structure 116 may include pads 117 exposed at the top side 110X of the substrate adjacent to the protrusion 128. Pads 117 may be electrically coupled to the electronic device 130 via internal interconnects 132. The paddle 111 may include: a planar surface 112; a planar surface 113 opposite to surface 112, mechanically connected to the sealant 140 and electrically connected to the electronic device 130; and a surface 114 mechanically connected to the dielectric structure 127 and connecting surface 112 to surface 113. Furthermore, the paddle 111 may further include an external conductive coating or layer 115 formed on surface 112. The outer coating 115 may include or be referred to as a wettable coating or electroplating layer, and may allow the paddle pad 111 to be wettable via, for example, solder material, for electrical connection to an external device.

[0023] The paddle pad 111 may be made of, but is not limited to, copper, copper / iron alloy, stainless steel, or copper / stainless steel / copper-clad metal. For example, the coating 115 may be made of, but is not limited to, gold, silver, nickel, palladium, tin, or an alloy.

[0024] In some instances, the conductive structure 116 may include or be referred to as a lead, pad, trace, wiring pattern, circuit pattern, or path. The conductive structure 116 may be arranged around the paddle pad 111. In some instances, the planar shape of the paddle pad 111 may be rectangular, and the conductive structure 116 may be arranged in four directions. The conductive structure 116 may include a relatively thin pad 117 and a lead 118 electrically connected to the pad 117, and may be relatively thick compared to the pad 117. In some instances, the pad 117 may be a segment of a trace coupled to an interconnect (such as internal interconnect 131). In some instances, the pad 117 may have a width similar to the width of an adjacent portion of the trace, but other instances exist where the pad 117 may be wider than such an adjacent portion of the trace.

[0025] The pad 117 can be electrically connected to the electronic device 130, and the lead 118 can be electrically connected to an external device via solder or the like. The pad 117 can be generally positioned on the dielectric structure 127 and mechanically connected to the dielectric structure 127 and the sealant 140. The lead 118 can also be mechanically connected to the dielectric structure 127 and the sealant 140.

[0026] In some instances, the conductive structure 116 may include a lead 118, which includes a lead wing (or wettable wing) 122. In some instances, the lead wing 122 may be referred to as a wettable wing, a detectable connector, or a solderable lead end. The lead wing 122 may include: a cavity 123 having a predetermined depth; and an external conductive coating or layer 126 comprising one or more conductive layers formed on the cavity 123. In some instances, the lead wing 122 may be a conductive coating 126 on the surface of the lead wing 122 within the cavity 123. Such an external conductive coating 126 may comprise or be referred to as a wettable coating or electroplated layer, or may be similar to or formed during the same process as external coating 115. In some instances, a cavity 123 may be provided in the lead 118 adjacent to the dielectric structure 127, and a wettable coating or electroplating layer may be provided on the conductive structure 127 to cover the lead 118, including covering the surface of the lead 118 in the cavity 123, wherein the plated lead 118 in the cavity forms a wettable wing.

[0027] In some instances, lead 118 may include a surface 119 facing the bottom of semiconductor device 100, a surface 120 opposite to surface 119 and connected to sealant 140, and surfaces 121 and 121A connecting surfaces 119 and 120 to each other. Here, surface 121A may be mechanically connected to dielectric structure 127, and surface 121 may be exposed to the outside of dielectric structure 127.

[0028] A cavity 123 may be formed between surfaces 119 and 121 of the lead 118. In some embodiments, a coating 126 may also be formed along the contour of the cavity 123 between surfaces 119 and 121 of the lead 118, thereby further defining the cavity 123. In some embodiments, the cavity 123 may include a lead surface 124 connected to surface 121 and parallel to surface 120, and a lead surface 125 connected to the lead surface 124 and surface 119 and parallel to surface 121 or surface 121A. Here, the lead surface 124 and the lead surface 125 may be perpendicular to each other. However, because in some embodiments the lead surface 124 and the lead surface 125 may actually be etched or formed by etching, the lead surface 124 and the lead surface 125 may be curved and may be connected to each other in a curved manner due to the characteristics of such processing.

[0029] Additionally, coating 126 can be formed on surface 119 of lead 118 and on lead surfaces 124 and 125 of cavity 123. Furthermore, coating 126 can be formed to conform to the contour of surface 119 of lead 118 and to the contours of lead surfaces 124 and 125 of cavity 123. In some embodiments, lead flanks 122 may have portions conforming to the surface contours of cavity 123 formed in lead 118. Here, lead surfaces 124 and 125 can be defined as components of lead 118.

[0030] Typically, the surface 121 of the lead 118 may be exposed to the outside via the outer surface of the dielectric structure 127, the outer surface of the sealant 140, or the outer surface of the coating 126. In some instances, the surface 121 of the lead 118 may be coplanar with the outer surface of the dielectric structure 127, the outer surface of the sealant 140, or the outer surface of the coating 126, wherein this feature may be the result of sawing or cutting operations during the manufacturing process.

[0031] The bottom surfaces of the coating 115 formed on the paddle pad 111, the dielectric structure 127, or the coating 126 formed on the surface 119 of the lead 118 can be coplanar with each other. However, because the coating 126 can be formed to have a shape that conforms to the surface profile of the cavity 123 (i.e., the lead surface 124 and the lead surface 125), the coating 126 can have a recessed shape consistent with the cavity 123.

[0032] Additionally, in some instances, the conductive structure 116 may be made of, but is not limited to, copper, copper / iron alloy, stainless steel, or copper / stainless steel / copper-clad metal. For example, the coating 126 may also be made of, but is not limited to, gold, silver, nickel, palladium, tin, or an alloy.

[0033] In some instances, the dielectric structure 127 may be referred to as a pre-molded part. The dielectric structure 127 may be interposed between the paddle pad 111, the pad 117, and the lead 118, thereby forming the substrate 110 into a structure including the dielectric structure 127 and the conductive structure 116. In some instances, the dielectric structure 127 may be used to mechanically (e.g., non-electrically grounded) connect the paddle pad 111 to the pad 117 and the lead 118. Furthermore, the dielectric structure 127 may be mechanically connected to the sealant 140, to a coating 115 connected to the paddle pad 111, or to a coating 126 also connected to the lead 118. In some instances, the dielectric structure 127 may further include a protrusion 128 that protrudes upwards around the pad 117 of the conductive structure 116 to a predetermined height and then couples to the sealant 140.

[0034] In some instances, the protrusion 128 of the dielectric structure 127 may be shaped to project upwards to a predetermined height, while generally defining or surrounding one or more lateral sides of the pad 117. In some instances, the protrusion 128 may guide or constrain the internal interconnect structure 131 such that it can be precisely aligned with the pad 117 and temporarily positioned before the internal interconnect structure 131 is permanently fixed to the pad 117. Furthermore, the protrusion 128 of the dielectric structure 127 may be coupled to the sealant 140, thereby tightly coupling the substrate 110 and the sealant 140. In some instances, the dielectric structure 127 includes the protrusion 128, and the conductive structure 116 includes the pad 117 defined by the protrusion 128.

[0035] In some instances, the dielectric structure 127 may include, but is not limited to, molding materials such as thermally curable epoxy molding compounds and epoxy molding resins. In some instances, the dielectric structure 127 may consist of only a single layer of molding material. In some instances, the dielectric structure 127 may include, but is not limited to, inorganic fillers (e.g., silica), epoxy resin, curing agents, flame retardants, curing accelerators, and release agents.

[0036] Electronic device 130 may be mounted on substrate 110. In some instances, electronic device 130 may be electrically connected to paddle pad 111, electrically connected to pad 117, or electrically connected to lead 118 of conductive structure 116. In some instances, electronic device 130 may be electrically connected to pad 117 of conductive structure 116. Examples of electronic device 130 may include, but are not limited to, logic dies, microcontrollers, memory, digital signal processors, network processors, power management units, audio processors, radio frequency (RF) circuits, wireless baseband chip-on-chip processors, application-specific integrated circuits, passive devices, or equivalents. In some instances, electronic device 130 may include semiconductor dies or semiconductor packages.

[0037] Additionally, the electronic device 130 can be electrically connected to the paddle pads 111 or pads 117 of the conductive structure 116 via an internal interconnect structure 131. For example, the internal interconnect structure 131 may include, but is not limited to, various types of materials for electrically bonding the electronic device 130 to the substrate 110, such as microbumps, metal pillars, solder bumps, solder balls, or equivalents. As an example, the internal interconnect structure 131 may include copper pillars with solder bumps or solder caps 132 that will be reflowed to or thermally pressed onto the substrate 110 and then bonded. In some instances, the internal interconnect structure 131 may have a pitch of about 20 to 50 μm or about 90 to 100 μm, but is not limited to these. Examples may also exist where the internal interconnect structure 131 can be a wire bond between the top surface of the electronic device 130 and the pads 117.

[0038] Although not illustrated, a non-conductive paste or capillary underfill may be further inserted between the substrate 110 and the electronic device 130. In some embodiments, the non-conductive paste or capillary underfill can mechanically connect the substrate 110 and the electronic device 130 to each other and can surround the internal interconnect structure 131. Therefore, due to the difference in the coefficients of thermal expansion between the substrate 110 and the electronic device 130, the non-conductive paste or capillary underfill can prevent the substrate 110 and the electronic device 130 from being peeled off.

[0039] In some instances, sealant 140 may be referred to as a post-molding component. Sealant 140 may cover substrate 110 and electronic device 130, thereby protecting electronic device 130 from external environmental influences. Examples of sealant 140 may include, but are not limited to, molding materials, such as thermosetting epoxy film compounds, epoxy molding resins, etc. In some instances, sealant 140 may consist of only a single layer of molding material. In some instances, sealant 140 may include, but is not limited to, inorganic fillers (e.g., silica), epoxy resin, curing agents, flame retardants, curing accelerators, release agents, etc. If the size of the inorganic filler is smaller than the gap between substrate 110 and electronic device 130, sealant 140 can be inserted into the gap between substrate 110 and electronic device 130, thereby directly surrounding the internal interconnect structure 131. Although Figure 1A The sealant 140 shown completely surrounds the electronic device 130, but the top surface of the electronic device 130 may be exposed or protrude to the outside through the top surface of the sealant 140. Additionally, as described above, the outer surfaces of the sealant 140, the conductive structure 116 or lead 118, the coating 126, and the dielectric structure 127 may all be coplanar. The dielectric structure 127 and the sealant 140 in the substrate 110 may be formed using the same or different materials.

[0040] In one example, dielectric structure 127 may have a smaller or much smaller elastic modulus than sealant 140. In some examples, dielectric structure 127 may have a larger or much larger elastic modulus than sealant 140. Therefore, dielectric structure 127 can mitigate or prevent breakage due to external mechanical shock or pressure, but its external shape can be altered to ultimately prevent breakage of dielectric structure 127 during the fabrication of semiconductor device 100. Damage to substrate 110 can be prevented when semiconductor device 100 is exposed to various environments while undergoing various processing operations.

[0041] Substrate 110, electronic device 130, and sealant 140 can be referred to as a semiconductor package, and can provide protection for electronic device 130 against external components or environmental exposure. Additionally, the semiconductor package can provide electrical coupling to external electrical components (not shown) via paddle pads 111 or leads 118. Figures 1A to 1C As shown, the semiconductor device 100 of this disclosure may include lead wing (or wettable wing) 122, which includes a cavity 123 formed in the lead 118 of the conductive structure 116.

[0042] In some embodiments, the cavity 123 of the lead wing 122 may include or be defined by the side pillar surface 129 of the dielectric structure 127, while engaging with the vertical lead surfaces 124 and 125 of the lead 118, or with the vertical coating surfaces 126A and 126B of the coating 126. The side pillar surface 129 of the dielectric structure 127 may be formed on opposite sides of the lead wing 122, while protruding at opposite sides of the lead surfaces 124 and 125 of the lead 118 to define the cavity 123. In some embodiments, the lead surface 124 or lead surface 125 of the lead 118 may be perpendicular to the side pillar surface 129 of the dielectric structure 127. The first surface 129 may be perpendicular to the lead surfaces 124 and 125, or perpendicular to the coating surfaces 126A and 126B. The second side post surface 129 may be perpendicular to the lead surface 124 and lead surface 125, or perpendicular to the coating surface 126A and coating surface 126B, and may be opposite to the first side post surface 129 passing through the cavity 123.

[0043] In some instances, the location or shape of the solder attached to the lead flank 122 during soldering can be defined by the side post surface 129 of the dielectric structure 127. For example, the side post surface 129 can restrict solder flow to adjacent lead flanks 122, thereby preventing short circuits between adjacent leads 118. As described above, the electrical connection area between the lead 118 and the solder can be increased or strengthened by forming lead flanks or wettable flanks 122 of the lead 118, thereby increasing secondary board-level reliability and facilitating bond visual inspection testing.

[0044] Figures 2A to 2L A cross-sectional view of an example method for manufacturing a semiconductor device is shown. Figure 2A An example operation of forming a conductive layer on a carrier is shown. For example... Figure 2A As shown, in the formation of the conductive layer on the carrier, a conductive layer 402 of predetermined thickness can be formed on a planar carrier 401 by sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma vapor deposition, electroless plating, or electroplating. In some examples, the conductive layer 402 may comprise one or more layers, such as a seed layer. Examples exist where the conductive layer 402 may comprise a metal foil or sheet attached to the carrier 401. In some examples, the conductive layer 402 may be, but is not limited to, titanium, tungsten, titanium / tungsten, copper, copper / iron alloy, or stainless steel. Examples of carrier 401 may be made of, but are not limited to, any suitable material, such as a silicon wafer, low-grade silicon wafer, glass, ceramic, or metal. The thickness of carrier 401 can range from about 500 μm to about 1500 μm, and the width of carrier 401 can range from about 100 mm to 500 mm. In some examples, the conductive layer 402 can be in the range of 500 Å to 3000 Å.

[0045] Figure 2B An example operation for forming pads is shown. For example... Figure 2B As shown, pads 117 having a predetermined thickness, length, width, and shape can be formed on the conductive layer 402, for example, on the top surface of the conductive layer 402. Here, paddle pad base region 111A and lead base region 118A can be formed on the conductive layer 402 and on the pads 117. Furthermore, the pads 117 and pad base region 118A can be electrically connected to each other. In some embodiments, the pads 117, lead base region 118A, or paddle pad base region 111A can be electroplated on the conductive layer 402 or etched into the conductive layer 402.

[0046] In some instances, the formation of pad 117 can be performed by performing process operations including but not limited to: coating a photoresist onto the conductive layer 402, exposing the resulting structure with a mask placed on the photoresist, removing unwanted photoresist by development, plating pad 117 onto the conductive layer 402, or removing residual photoresist around pad 117. In some instances, forming pad 117 may involve pattern plating on the conductive layer 402. The thickness of the paddle pad base region 111A, lead base region 118A, or pad 117 can range from about 1 μm to about 100 μm.

[0047] As Figure 2B The operation shown in the figure results in the formation of pad 117 and a base for paddle pad 111 and lead 118. In this way, pad 117 of conductive structure 116 can be completed.

[0048] Figure 2C An example operation of the portion forming the conductive structure 116 is shown. For example... Figure 2C As shown, further processing can be performed on the aforementioned base structure to complete the paddle pad 111 and lead 118. As an example, a photoresist mask can be applied over the pad 117, followed by electroplating the lead body 118B or paddle pad body 111B over the corresponding paddle pad base 111A or lead base 118A to the desired thickness. The paddle pad 111 and lead 118 can be relatively thicker than the pad 117. The thickness range of the paddle pad 111 and lead 118 can be from about 10 μm to about 1000 μm. In some instances, the paddle pad 111 and lead 118 can be formed by electroplating, pillar plating, or etching.

[0049] Figure 2D An example operation of pre-molded is shown. For example... Figure 2D As shown, in pre-molding, dielectric structure 127 can be formed on paddle pads 111, pads 117, and leads 118. For example, dielectric structure 127 can be formed using, but not limited to, epoxy film compounds or epoxy molding resins. In dielectric structure 127, epoxy film compounds or epoxy molding resins fill the gaps between multiple protruding pads 117, thereby naturally forming protrusions 128 between the pads 117. For example, dielectric structure 127 can be formed by, but not limited to, general distribution molding, compression molding, transfer molding, etc. The thickness of dielectric structure 127 can range from about 10 μm to about 1000 μm. In some examples, dielectric structure 127 can be formed on the top surface of conductive layer 402, wherein dielectric structure 127 covers pads 117 and leads 118.

[0050] Figure 2E An example operation of thinning pre-molding is shown. For example... Figure 2E As shown, dielectric structure 127 can be thinned until paddle pad 111 and lead 118 are exposed. Therefore, the resulting surfaces of paddle pad 111, lead 118, or dielectric structure 127 can become coplanar. In some instances, the above thinning process can be achieved by polishing.

[0051] Figure 2F An example of etching operation is shown. For example... Figure 2F As shown, the paddle pad 111 and a portion corresponding to the lead 118 can be etched such that the surfaces of the paddle pad 111 and the lead 118 can be recessed relative to the surface of the dielectric structure 127. In some instances, the etching operation may include a deep etching process. The etching depth of the paddle pad 111 and the portion corresponding to the lead 118 can range from approximately 1 μm to approximately 10 μm.

[0052] Alternatively, the cavity 123 may be formed on a portion of the lead 118. In some instances, the cavity 123 may be formed by mechanical grinding using a diamond blade, by laser ablation, or by etching. The cavity depth corresponding to the portion of the cavity 123 may range from about 10 μm to about 100 μm. In some instances, the cavity 123 may be formed in the lead 118 adjacent to the dielectric structure 127.

[0053] Figure 2G An example operation for forming an external conductive layer is shown. For example... Figure 2G As shown, coatings 115 and 126 of predetermined thickness can be formed on the respective surfaces of the paddle pad 111 and on the leads 118 forming on the surface including the cavity 123. Here, the surfaces of coatings 115 and 126 can be coplanar with the surface of the dielectric structure 127. Because the coating 126 of the cavity 123 can be formed conformally along the surface profile of the cavity 123, it can have a recessed shape defined by the cavity 123. In some embodiments, coatings 115 and 126 can protrude beyond the surface of the dielectric structure 127. In some embodiments, coatings 115 and 126 can be formed on the leads 118 (including on the surface of the leads 118 in the cavity 123) to form a shape corresponding to the electroplated leads 118 in the cavity, as follows: Figure 4 The wettable wing 422 is shown.

[0054] In some instances, coatings 115 and 126 can be formed by, but not limited to, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma vapor deposition, electroless plating, or electroplating. Alternatively, coatings 115 and 126 can be formed using the same process, or different processes can be combined to form a multilayer. For example, coatings 115 and 126 can be made of, but not limited to, gold, silver, nickel, palladium, tin, or alloys. The thickness of coatings 115 and 126 can range from about 1 μm to about 10 μm.

[0055] Figure 2H An example operation for removing the carrier is shown. For example... Figure 2H As shown, the carrier 401 can be removed from the conductive layer 402. In some instances, the carrier 401 can be removed by, but not limited to, etching, grinding, or physical stripping. Paddle pads 111 and pads 117 of different thicknesses and leads 118 can be formed on the conductive layer 402, and the bottom surface of the conductive layer 402 can remain planar when the carrier 401 is removed.

[0056] Figure 2I An example operation of soft etching is shown. For example... Figure 2I As shown, by removing the carrier 401, the conductive layer 402 is exposed downwards, and the bottom surfaces of the paddle pad 111, the pad 117, and the lead 118 can be etched (soft-etched) so that the bottom surfaces of the paddle pad 111, the pad 117, and the lead 118 can become slightly recessed relative to the bottom surface of the dielectric structure 127.

[0057] Therefore, a protrusion 128 can be formed on the dielectric structure 127 surrounding the pad 117, such that the protrusion 128 of the dielectric structure 127 protrudes beyond the bottom surface of the pad 117. In some embodiments, the protrusion 128 protrudes simultaneously around the opposing surfaces of the pad 117. The thickness of the protrusion 128 can range from about 1 μm to about 10 μm.

[0058] As a result of soft etching, substrate 110 can be completed. In some instances, such as Figure 2I As shown, the substrate 110 can be flipped to complete a substrate 110 including a conductive structure 116. The conductive structure 116 has pads 117 and leads 118 arranged around a paddle pad 111, and has a dielectric structure 127 connecting the components of the conductive structure 116 to each other. The conductive structure 116 may include pads 117 electrically connected to an electronic device 130 and leads 118 electrically connected to an external device 150, such as... Figure 5 As shown. Pads 117 and leads 118 can be connected to each other via traces or path portions of conductive structure 116.

[0059] In some instances, lead 118 may include cavity 123, and coating 126 may be formed along the surface of lead 118 and its cavity 123. In this way, lead flank 122, including cavity 123 and coating 126, can be defined. Coating 115 is also formed on the surface of paddle pad 111.

[0060] Figure 2J Example operation of attaching an electronic device (such as a semiconductor die) is shown. Figure 2J As shown, electronic device 130 can be electrically connected to paddle pads 111 and pads 117 of substrate 110 via internal interconnect structure 131. In some instances, electronic device 130 can be electrically connected to paddle pads 111 and pads 117 in substrate 110 via, but not limited to, thermal compression or mass reflow. Examples may also exist where the internal interconnect structure 131 can be a wire bond between the top surface of electronic device 130 and pads 117. The thickness of electronic device 130 can range from about 50 μm to about 1000 μm.

[0061] Prior to attaching the electronic device 130 (such as a semiconductor die), a non-conductive paste may optionally be inserted between the paddle pad 111 of the electronic device 130 and the substrate 110. Alternatively, after attaching the electronic device 130, a capillary bottom filler may optionally be injected into the gap between the paddle pad 111 of the electronic device 130 and the substrate 110.

[0062] Figure 2K Example operations of encapsulation or post-molding are shown. For example... Figure 2K As shown, substrate 110 and electronic device 130 attached to substrate 110 can be surrounded by sealant 140. For example, sealant 140 can be formed using, but is not limited to, epoxy film compounds or epoxy molding resins. In some instances, sealant 140 can be formed by, but is not limited to, general-purpose dispensing molding, compression molding, transfer molding, etc. As a result of post-molding, sealant 140 can be non-electrically connected to paddle pads 111, pads 117 and leads 118 in conductive structure 116, and dielectric structure 127 of substrate 110, while surrounding electronic device 130 and internal interconnect structure 131. The thickness of sealant 140 can range from about 50 μm to about 1000 μm.

[0063] Figure 2L Example operations for cutting are shown. For example... Figure 2LAs shown, the substrate 110 and sealant 140 can be cut using, for example, a sawing tool to provide a single semiconductor device 100. In some instances, to improve productivity, the semiconductor device 100 can be manufactured in a strip or matrix type and cut into individual semiconductor devices 100 as discrete semiconductor devices. Here, the area corresponding to the cavity 123 having the coating 126 can be sawed, and a conductive layer with wettable lead flanks 122 can be formed along the edge of the semiconductor device 100.

[0064] As a result of the cutting, the lateral surface of the substrate 110 and the outer surface of the sealant 140 may be coplanar. In some instances, the lateral surfaces of the leads 118, the dielectric structure 127, or the lead flanks 122 (the lateral surface of the coating 126) in the substrate 110 may be coplanar.

[0065] As described above, in the semiconductor device and method of manufacturing the semiconductor device of this disclosure, wettable winglets (detectable connectors or solderable lead ends) may be further formed on the lead 118, thereby increasing the solder joint area of ​​the lead 118. In some instances, in the semiconductor device and method of manufacturing the semiconductor device of this disclosure, secondary board-level reliability may be increased, and visual testing of the solder joint area may be facilitated by further forming wettable winglets.

[0066] Furthermore, in the semiconductor device and its manufacturing method disclosed herein, a conductive layer can be formed on a carrier and a conductive structure, and the conductive structure (pads and pads (land)) and dielectric structure can be formed on the conductive layer. A pre-molded substrate can be fabricated by forming wettable winglets including cavities and electroplated layers on the conductive structure, thereby easily manufacturing the wettable winglets without the need for busbars.

[0067] Figure 3 A partially enlarged view of an example of a wettable wing of a semiconductor device 300 is shown. The semiconductor device 300 includes a substrate 310, similar to substrate 110, having a substrate lateral side 310Y and a substrate bottom side 310Z. Substrate 310 also includes a substrate inner side 310A perpendicular to the substrate lateral side 310Y and a substrate inner side 310B perpendicular to the substrate bottom side 310Z. Substrate inner side 310A includes an inner surface 329A of dielectric structure 327 and a coating surface 126A of coating 126. Substrate inner side 310B includes an inner surface 329B of dielectric structure 327 and a coating surface 126B of coating 126. Substrate inner side 310A may be perpendicular to substrate inner side 310B. Figure 3As shown, lead flanks (or wettable flanks) 322 having cavities 123 formed in the lead 118 (i.e., between lead surfaces 124 and 125 shown in FIG. 1) can be coplanar with the inner surfaces 329A and 329B of the dielectric structure 327. The dielectric structure 327 can otherwise resemble the dielectric structure 127 previously described. In some instances, the inner surface 329A, which can be substantially perpendicular to the outer lateral surface of the dielectric structure 327, can be substantially coplanar with the lead surface 124 (FIG. 1) of the lead 118 or with the coating surface 126A of the coating 126 formed on the lead 118. In the same or other instances, the inner surface 329B, which can be substantially perpendicular to the outer bottom surface of the dielectric structure 327, can be substantially coplanar with the lead surface 125 (FIG. 1) of the lead 118 or with the coating surface 126B of the coating 126 formed on the lead 118. In some instances, the inner surfaces 329A and 329B of the dielectric structure 327 may be approximately perpendicular to each other.

[0068] Figure 4 A partial enlarged view of an example of a wettable wing of a semiconductor device 400 is shown. Figure 4 As shown, in the semiconductor device 400 of this disclosure, the lead wing (or wettable wing) 422 formed on the lead 118 can be similar to the lead wing 122 (FIG. 1), but includes a dimple. Specifically, the lead wing 422 includes a cavity 423, which can be similar to the cavity 123 (FIG. 1), but instead has a dimple shape by, for example, etching defining the dimple in the lead 118, and is otherwise similar to the above description. Figure 2F-2G The cavity 123 described herein. The lead wing 422 containing the cavity 423 can be similar to the coating 126 (Figure 1, Figure 2G The electroplated layer 426 covers the lead 118. In some instances, the electroplated layer 246 may be formed on the lead 118 (including on the surface of the lead 118 in the cavity) to form a wettable wing 422 corresponding to the electroplated lead 118 in the cavity.

[0069] Figure 5 A cross-sectional view is shown of an instance state in which a semiconductor device can be mounted to an external device. (See example...) Figure 5 As illustrated in the diagram, semiconductor device 100 can be mounted on circuit patterns 151 and 152 of external device 150 using, for example, solder 153 and solder 154. In some instances, in semiconductor device 100, solder 153 and solder 154 can be used to electrically connect the paddle pad 111 of substrate 110 and leads 118 or lead wings 122 to circuit patterns 151 and 152 of external device 150, respectively.

[0070] Here, a cavity 123 and a coating 126 can be further formed on the lead 118 to increase the solder joint area between the lead 118 and the solder 154, thereby improving the secondary board-level reliability of the semiconductor device 100. Furthermore, because of the increased joint height or volume provided by the cavity 123, the solder joint can be well observed even from the outside of the semiconductor device 100, allowing for more accurate and rapid device-based visual testing.

[0071] This disclosure includes references to certain examples; however, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the disclosed examples, but rather to include all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device comprising: A substrate having a top side, a lateral side, and a bottom side; Electronic device, which is located on the top side of the substrate; as well as A sealant, which is on the top side of the substrate and contacts the lateral surface of the electronic device; The substrate includes a conductive structure and a dielectric structure, the dielectric structure including protrusions that contact the sealant; The conductive structure includes a lead on a lateral side of the conductive structure, the lead including a lead wing, the lead including a cavity in the lead wing and a conductive coating on the surface of the lead wing in the cavity; and The conductive structure includes pads exposed at the top side of the substrate, the pads being embedded in the dielectric structure and adjacent to the protrusions for electrical coupling to the electronic device via a first internal interconnect. The conductive structure includes a paddle pad and a second internal interconnect extends from the bottom side of the electronic device and is coupled to the paddle pad, wherein the pad is between the paddle pad and the lead; The protrusion is located between the first internal interconnect and the second internal interconnect; and The dielectric structure includes a body and the protrusion extends from the body, and the conductive structure covers a first lateral side of the body and a second lateral side of the body opposite to the first lateral side.

2. The semiconductor device of claim 1, wherein the dielectric structure comprises a dielectric layer extending from the bottom side of the substrate to the top side of the substrate.

3. The semiconductor device of claim 1, wherein the cavity of the lead side wing is pit-shaped.

4. The semiconductor device according to claim 1, wherein: The substrate comprises: The first inner side of the substrate perpendicular to the lateral side of the substrate; and The second inner side of the substrate is perpendicular to the bottom side of the substrate; The first inner side of the substrate includes the first inner surface of the dielectric structure and the first coating surface of the conductive coating; The second inner side of the substrate includes the second inner surface of the dielectric structure and the second coating surface of the conductive coating; and The first inner side of the substrate is perpendicular to the second inner side of the substrate.

5. The semiconductor device of claim 1, wherein the protrusion defines the lateral surface of the pad and extends into the sealant.

6. The semiconductor device of claim 1, wherein the lead wing is electrically coupled to a circuit pattern of an external device via solder filling the cavity, the lead wing covering a large portion of the height of the lead and being visible by visual inspection.

7. The semiconductor device according to claim 1, wherein: The dielectric structure includes a first molding material layer; and The sealant comprises a second molding material layer that contacts the first molding material layer.

8. The semiconductor device of claim 1, wherein the cavity comprises: The first lead surface of the lead wire; The second lead surface of the lead is perpendicular to the first lead surface; The first side pillar surface of the dielectric structure is perpendicular to the first lead surface and the second lead surface; and The second side pillar surface of the dielectric structure is perpendicular to the first lead surface and the second lead surface, and spans the cavity opposite to the first side pillar surface.

9. A method for manufacturing a semiconductor device, comprising: A conductive layer is formed on the carrier; A pad is formed on the top surface of the conductive layer; A paddle pad and a lead are formed on the top surface of the conductive layer, wherein the thickness of the lead is greater than the thickness of the pad; A dielectric structure is formed on the top surface of the conductive layer, wherein the dielectric structure covers the pads and the leads; Thin the dielectric structure until the leads are exposed; The lead is etched such that the surface of the lead is recessed relative to the surface of the dielectric structure; A cavity is formed in the lead adjacent to the dielectric structure; An electroplating layer is formed on the lead to provide an electroplated lead, including forming on the surface of the lead in the cavity to form wettable wing corresponding to the electroplated lead in the cavity; Remove the carrier and etch the first side of the conductive layer opposite to the top surface side, such that the protrusion of the dielectric structure protrudes beyond the first surface of the pad; The electronic device is placed on the first surface of the pad and on the paddle pad; The electronic device is coupled to the pad via a first internal interconnect and to the paddle pad via a second internal interconnect; The bottommost surface of the lead is recessed from the bottom side of the dielectric structure, and the bottommost surface of the electroplated layer is coplanar with the bottom side of the dielectric structure; The protrusion is located between the first internal interconnect and the second internal interconnect; and The dielectric structure includes a body and the protrusion extends from the body, the paddle pad covers a first lateral side of the body and the lead covers a second lateral side of the body opposite to the first lateral side; The lead is located on the lateral side of the conductive layer; and the pad is located between the paddle pad and the lead.

10. The method of claim 9, further comprising: A sealant is formed on the electronic device, wherein the sealant contacts the lateral surface of the electronic device, and the protrusion of the dielectric structure extends into the sealant.

11. The method of claim 9, wherein the aforementioned formation of the pads comprises performing pattern plating on the conductive layer.

12. The method according to claim 9, The aforementioned formation of the leads involves electroplating performed on the conductive layer.

13. The method of claim 9, wherein thinning the dielectric structure comprises grinding the dielectric structure.

14. The method of claim 9, wherein forming the pads and the leads comprises: The pads and lead bases of the leads are formed on the conductive layer; and The lead body is electroplated onto the lead base.

15. A method of manufacturing a semiconductor device, comprising: A conductive structure is provided, which includes a first side and a second side opposite to the first side; Pads and leads are provided on the first side of the conductive structure; A dielectric structure is provided on the first side of the conductive structure and above the pad, wherein the dielectric structure includes a protrusion adjacent to the pad, wherein the protrusion is between the pad and the lead. A cavity is provided in the lead adjacent to the dielectric structure, wherein the cavity is located on the lateral side of the lead; Electroplating is performed on the conductive structure to cover the leads, including covering the surface of the leads in the cavity to provide the electroplated cavity, wherein the electroplated cavity forms wettable winglets; and An electronic device is attached to a second side of the conductive structure, wherein the electronic device is electrically coupled to the pads via a first internal interconnect. The bottommost surface of the lead is in a first plane, and the outer surface of the dielectric structure is in a second plane, the second plane being lower than the first plane, and the bottommost surface of the electroplating is coplanar with the outer surface of the dielectric structure; The conductive structure includes a paddle pad, and a second internal interconnect extends from the bottom side of the electronic device and is coupled to the paddle pad; The protrusion is located between the first internal interconnect and the second internal interconnect; The dielectric structure includes a body and the protrusion extends from the body, and the conductive structure covers a first lateral side of the body and a second lateral side of the body opposite to the first lateral side; The lead is located on the lateral side of the conductive structure; and The pad is located between the paddle pad and the lead.

16. The method of claim 15, further comprising: A film compound is formed to cover the electronic device, wherein the film compound contacts the side surface of the electronic device, and wherein the protrusion of the dielectric structure extends into the film compound.

17. The method of claim 15, wherein the cavity provided above comprises a first cavity surface formed perpendicular to the second cavity surface.

18. The method of claim 15, wherein the cavity provided above comprises a cavity surface forming a pit shape.

19. The method of claim 15, wherein: The protrusion extends above the top surface of the pad; and The bottom portion of the first internal interconnect is defined by the protrusion.

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