Memory array, integrated assembly, method of forming bit line, and method of forming integrated assembly

Abstract

The present application relates to a memory array, an integrated assembly, a method for forming a bit line, and a method for forming an integrated assembly. Some embodiments include an integrated assembly having bit lines spaced apart from each other by an intermediate gap. An insulating support is above the bit line. A conductive plate is supported by the insulating support and is close to the bit line to drain excess charge from the bit line. Some embodiments include a method for forming an integrated assembly. A stack is formed to have an insulating material above the bit line material. The stack is patterned into a track extending along a first direction. The track includes patterned bit line material as a bit line and includes patterned insulating material as an insulating support above the bit line. The tracks are spaced apart from each other by a gap along a second direction orthogonal to the first direction. A sacrificial material is formed in the gap. A conductive plate is formed above the insulating support and the sacrificial material. The sacrificial material is removed from under the conductive plate to reform the gap.

Description

Technical Field

[0001] An integrated assembly including a space between bit lines and including a conductive plate operably proximate to the bit lines and a method of forming the integrated assembly are provided. Background Art

[0002] Memory is used in modern computing architectures to store data. One type of memory is dynamic random access memory (DRAM). Compared to alternative types of memory, DRAM can provide advantages in terms of simplicity, low cost, and high speed.

[0003] DRAMs may utilize memory cells that each have one capacitor combined with one transistor (so-called 1T-1C memory cells), wherein the capacitor is coupled to the source / drain region of the transistor. DRAM cells may be utilized in DRAM arrays having hundreds, thousands, millions, etc. of memory cells. The transistors of the memory array have gates coupled to word lines. The memory cells of the memory array are addressed using a combination of bit lines (i.e., digit lines, sense lines) and word lines.

[0004] A problem that may be encountered with conventional DRAM arrays is parasitic capacitance between adjacent bit lines. As bit lines are packed more tightly in association with increased levels of integration, parasitic capacitance becomes increasingly problematic. It is desirable to develop arrangements that avoid parasitic capacitance between adjacent bit lines, and to develop methods of manufacturing such arrangements. Summary of the invention

[0005] Some embodiments of the present disclosure provide a memory array, the memory array comprising: bit lines, the bit lines being spaced apart from each other by intermediate gaps; word lines, the word lines being vertically offset from the bit lines and crossing the bit lines; and memory cells, the memory cells being close to the intersection of the word lines and the bit lines; each of the memory cells being uniquely addressed by a combination of the word lines and the bit lines; and the side periphery of each of the memory cells being matched at 4F 2 within the area.

[0006] Some embodiments of the present disclosure provide an integrated assembly comprising: bit lines, which are separated from each other by intermediate gaps; insulating supports, which are above the bit lines; and a conductive plate, which is supported by the insulating supports and is close to the bit lines to discharge excess charge from the bit lines.

[0007] Some embodiments of the present disclosure provide an integrated assembly, the integrated assembly comprising a row of vertically extending semiconductor pillars; each of the semiconductor pillars comprises a transistor channel region, the transistor channel region is vertically disposed between a first source / drain region and a second source / drain region; a word line, the word line extends along the row of vertically extending semiconductor pillars and is adjacent to the transistor channel region of the semiconductor pillars; the word line has a first side surface and an opposite second side surface; the semiconductor pillars are subdivided into a first group along the first side surface and a second group along the second side surface; the semiconductor pillars of the first group are connected along the row and the semiconductor pillars of the second group are connected along the first side surface. alternating; a gate dielectric material, the gate dielectric material being between the first side surface and the transistor channel region of the semiconductor pillars of the first group, and between the second side surface and the transistor channel region of the semiconductor pillars of the second group; a conductive shielding material, the conductive shielding material being between the semiconductor pillars of the first group, and between the semiconductor pillars of the second group; a bit line, the bit line is coupled to the first source / drain region, the bit lines are separated from each other by gaps and are operably close to a conductive plate, the conductive plate is configured to discharge excess charge from the bit line; and a storage element, the storage element is coupled to the second source / drain region.

[0008] Some embodiments of the present disclosure provide a method for forming a bit line, the method comprising: forming a bit line material above an underlying structure; patterning the bit line material into a bit line; the bit line extending along a first direction; the bit lines being spaced apart from each other by gaps along a second direction orthogonal to the first direction; forming a capping material above the gap; forming a word line vertically offset from the bit line and crossing the bit line; and forming a memory cell near a position where the word line crosses the bit line; each of the memory cells is uniquely addressed by a combination of a word line and a bit line; and the side periphery of each of the memory cells is matched at 4F 2 within the area.

[0009] Some embodiments of the present disclosure provide a method for forming an integrated assembly, the method comprising: forming a stack including an insulating material above a bit line material; patterning the stack into a track extending along a first direction; the track including patterned bit line material as a bit line and including patterned insulating material as an insulating support above the bit line; the tracks are separated from each other by intermediate gaps along a second direction orthogonal to the first direction; forming a sacrificial material within the intermediate gaps; forming a conductive plate above the insulating support and extending across the sacrificial material; and removing the sacrificial material from under the conductive plate to reform the gap. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and 1B are a diagrammatic top view and a diagrammatic cross-sectional side view, respectively, of an example assembly at example processing stages of an example method for fabricating a bit line. Figure 1B The view along Figure 1A Line BB.

[0011] Figure 2A and 2B They are Figure 1A and 1B The example assembly is in Figure 1A and 1B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Figure 2B The view along Figure 2A Line BB.

[0012] Figure 3A and 3B They are Figure 1A and 1B The example assembly is in Figure 2A and 2B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Figure 3B The view along Figure 3A Line BB.

[0013] Figure 4A and 4B They are Figure 1A and 1B The example assembly is in Figure 3A and 3B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Figure 4B The view along Figure 4A Line BB.

[0014] Figure 5A and 5B They are Figure 1A and 1B The example assembly is in Figure 4A and 4B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Figure 5B The view along Figure 5A Line BB.

[0015] Fig. 6A and 6B They are Figure 1A and 1B The example assembly is in Figure 5A and 5BA diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Figure 6B The view along Fig. 6A Line BB.

[0016] Fig. 7A and 7B are diagrammatic cross-sectional top and side views, respectively, of an example assembly at example processing stages of an example method for fabricating an example array of memory cells. Fig. 7A The view along Figure 7B The line AA, and Figure 7B The view along Fig. 7A Line BB.

[0017] Fig. 8A and 8B They are Fig. 7A and 7B The example assembly is in Fig. 7A and 7B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig. 8A The view along Figure 8B The line AA, and Figure 8B The view along Fig. 8A Line BB.

[0018] Fig.9A and 9B They are Fig. 7A and 7B The example assembly is in Fig. 8A and 8B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.9A The view along Fig. 9B The line AA, and Fig. 9B The view along Fig.9A Line BB.

[0019] Fig. 10A and 10B They are Fig. 7A and 7B The example assembly is in Fig.9A and 9B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig. 10A The view along Fig. 10B The line AA, and Fig. 10B The view along Fig. 10A Line BB.

[0020] Fig.11A and 11B They are Fig. 7A and 7B The example assembly is in Fig.9A and 9B The example processing phase after the example processing phase and in Fig. 10A and 10B Schematic cross-sectional top view and schematic cross-sectional side view of alternative example processing stages of an example processing stage. Fig.11A The view along Fig. 11B The line AA, and Fig. 11B The view along Fig.11A Line BB.

[0021] Fig. 12A and 12B They are Fig. 7A and 7B The example assembly is in Fig. 10A and 10B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig. 12A The view along Fig. 12B The line AA, and Fig. 12B The view along Fig. 12A Line BB.

[0022] Fig.13A and 13B They are Fig. 7A and 7B The area of ​​the example assembly is Fig. 12A and 12B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Fig. 13B The view along Fig.13A Line CC.

[0023] Fig.14A and 14B are diagrammatic cross-sectional top and side views, respectively, of an example assembly at example processing stages of an example method for fabricating an example array of memory cells. Fig.14A The view along Fig. 14B The line AA, and Fig. 14B The view along Fig.14A Line BB.

[0024] Fig.15A and 15B They are Fig.14A and 14B The example assembly is in Fig.14A and 14B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.15A The view along Fig. 15BThe line AA, and Fig. 15B The view along Fig.15A Line BB.

[0025] Fig.16A and 16B They are Fig.14A and 14B The example assembly is in Fig.15A and 15B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.16A The view along Fig. 16B The line AA, and Fig. 16B The view along Fig.16A Line BB.

[0026] Fig.17A and 17B They are Fig.14A and 14B The example assembly is in Fig.16A and 16B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.17A The view along Fig. 17B The line AA, and Fig. 17B The view along Fig.17A Line BB.

[0027] Fig.18A and 18B They are Fig.14A and 14B The example assembly is in Fig.17A and 17B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.18A The view along Fig.18B The line AA, and Fig.18B The view along Fig.18A Line BB.

[0028] Fig.19A and 19B They are Fig.14A and 14B The example assembly is in Fig.18A and 18B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.19A The view along Fig.19B The line AA, and Fig.19B The view along Fig.19A Line BB.

[0029] Fig. 20A and20B They are Fig.14A and 14B The area of ​​the example assembly is Fig.19A and 19B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Fig. 20B The view along Fig. 20A Line CC.

[0030] Fig.21A and 21B are diagrammatic cross-sectional top and side views, respectively, of an example assembly at example processing stages of an example method for fabricating an example array of memory cells. Fig.21A The view along Fig. 21B The line AA, and Fig. 21B The view along Fig.21A Line BB.

[0031] Fig.22A and 22B They are Fig.21A and 21B The example assembly is in Fig.21A and 21B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.22A The view along Fig. 22B The line AA, and Fig. 22B The view along Fig.22A Line BB.

[0032] Fig.23A and 23B They are Fig.21A and 21B The example assembly is in Fig.22A and 22B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.23A The view along Fig. 23B The line AA, and Fig. 23B The view along Fig.23A Line BB.

[0033] Fig.24A and 24B They are Fig.21A and 21B The area of ​​the example assembly is Fig.23A and 23B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Fig. 24B The view along Fig.24A Line CC.

[0034] Fig.25A and 25B They are Fig.21A and 21B The example assembly is in Fig.24A and 24B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.25A The view along Fig.25B The line AA, and Fig.25B The view along Fig.25A Line BB.

[0035] Fig.26A and 26B They are Fig.21A and 21B The example assembly is in Fig.25A and 25B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.26A The view along Fig.26B The line AA, and Fig.26B The view along Fig.26A Line BB.

[0036] Fig.27A and 27B They are Fig.21A and 21B The example assembly is in Fig.26A and 26B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.27A The view along Fig.27B The line AA, and Fig.27B The view along Fig.27A Line BB.

[0037] Fig.28A and 28B are diagrammatic cross-sectional top and side views, respectively, of an example assembly at example processing stages of an example method for fabricating an example array of memory cells. Fig.28A The view along Fig.28B The line AA, and Fig.28B The view along Fig.28A Line BB.

[0038] Fig.29A and 29B They are Fig.28A and 28B The example assembly is in Fig.28A and 28B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.29A The view along Fig.29B The line AA, and Fig.29B The view along Fig.29A Line BB.

[0039] Fig. 30A and 30B They are Fig.28A and 28B The area of ​​the example assembly is Fig.29A and 29B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Fig. 30B The view along Fig. 30A Line CC.

[0040] Fig.31A and 31B They are Fig.28A and 28B The example assembly is in Fig. 30A and 30B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.31A The view along Fig.31B The line AA, and Fig.31B The view along Fig.31A Line BB.

[0041] Fig.32A and 32B They are Fig.28A and 28B The example assembly is in Fig.31A and 31B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.32A The view along Fig.32B The line AA, and Fig.32B The view along Fig.32A Line BB.

[0042] Fig.33A and 33B They are Fig.28A and 28B The example assembly is in Fig.32A and 32B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.33A The view along Fig.33B The line AA, and Fig.33B The view along Fig.33A Line BB.

[0043] Fig.34A and 34Bare diagrammatic cross-sectional top and side views, respectively, of an example assembly at example processing stages of an example method for fabricating an example array of memory cells. Fig.34A The view along Fig.34B The line AA, and Fig.34B The view along Fig.34A Line BB.

[0044] Fig.35A and 35B They are Fig.34A and 34B The example assembly is in Fig.34A and 34B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.35A The view along Fig.35B The line AA, and Fig.35B The view along Fig.35A Line BB.

[0045] Fig.36A and 36B They are Fig.34A and 34B The area of ​​the example assembly is Fig.35A and 35B A diagrammatic top view and a diagrammatic cross-sectional side view of example processing stages after example processing stages of . Fig.36B The view along Fig.36A Line CC.

[0046] Fig.37A and 37B They are Fig.34A and 34B The example assembly is in Fig.36A and 36B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.37A The view along Fig.37B The line AA, and Fig.37B The view along Fig.37A Line BB.

[0047] Fig.38A and 38B They are Fig.34A and 34B The example assembly is in Fig.37A and 37B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.38A The view along Fig.38B The line AA, and Fig.38B The view along Fig.38ALine BB.

[0048] Fig.39A and 39B They are Fig.34A and 34B The example assembly is in Fig.38A and 38B A diagrammatic cross-sectional top view and a diagrammatic cross-sectional side view of an example processing stage after an example processing stage. Fig.39A The view along Fig.39B The line AA, and Fig.39B The view along Fig.39A Line BB.

[0049] Fig.40 is a diagrammatic representation of a region of an example memory array.

[0050] Fig.41 is a diagrammatic cross-sectional side view of a region of an example assembly including stacked layers. DETAILED DESCRIPTION

[0051] Some embodiments include memory structures having gaps between adjacent bit lines. In some embodiments, a conductive plate may be above the bit lines. The conductive plate may be operably close to the bit lines so that excess charge on the bit lines can drain to the plate rather than causing problematic parasitic capacitance. Some embodiments include methods of forming an integrated assembly. Example embodiments are described with reference to FIGS. 1-41.

[0052] Reference Figure 1A and 1B , the construction 10 includes a support structure 300 and a series of conductive interconnects 302 extending upward from the support structure. The conductive interconnects may include semiconductor material 14 and may correspond to source / drain regions 20.

[0053] Semiconductor material 14 may include any suitable composition or compositions; and in some embodiments may include, consist essentially of, or consist of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material including elements selected from Groups III and V of the periodic table (wherein Groups III and V are old nomenclatures, now referring to Groups 13 and 15). In some embodiments, semiconductor material 14 may include, consist essentially of, or consist of single crystal silicon.

[0054] The source / drain regions 20 may correspond to doped regions of the semiconductor material 14. Such doped regions may include any suitable dopant at any suitable concentration. In some embodiments, the doped regions may include at least about 1×10 20 Atom / cm3 n-type dopant provided at a concentration of at least about 1×10 20 Atom / cm 3 The concentration of p-type dopant is provided.

[0055] Regions 302 are separated from one another by insulating material 304. Insulating material 304 may include any suitable composition or compositions; and in some embodiments, may include, consist essentially of, or consist of silicon dioxide.

[0056] The bit line material 18 is above the semiconductor material 14 and the insulating material 304. The bit line material 18 may include any suitable one or more conductive compositions; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), one or more metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some example embodiments, the bit line material 18 may include one or more of tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, etc.

[0057] Overlying conductive material 18 is insulating material 308. Insulating material 308 may include any suitable composition or compositions; and in some embodiments, may include, consist essentially of, or consist of silicon nitride.

[0058] Materials 18 and 308 may be considered to comprise stack 310 .

[0059] Provides information about Figure 1A and 1B The x, y, and z axis system is provided to help the reader understand the relationship between the structures shown in the accompanying drawings.

[0060] Reference Figure 2A and 2B , the stack 310 is patterned into tracks 312. The tracks extend along a first direction along the illustrated y-axis, which may ultimately correspond to a column direction of the memory array.

[0061] The patterned bit line material 18 within the track 312 becomes the bit line 32 , and the patterned insulating material 308 becomes the insulating support 314 over the bit line.

[0062] Track 312 may be patterned by any suitable process. In some embodiments, the track may be patterned using a lithographically patterned mask material (e.g., a photolithographically patterned photoresist). A lithographic (e.g., photolithography) process will have a minimum feature size "F" associated with it. Track 312 may have a width corresponding to the minimum feature size of the lithographic process. Alternatively, using additional processing, the track may be formed to a size that is less than the minimum feature size of the lithographic process; such as, for example, by pitch multiplication. Example pitch multiplication processes are described, for example, in U.S. Patents Nos. 8,389,383 and 8,852,851 and U.S. Patent Publication No. 2014 / 0091434. A goal of integrated circuit manufacturing may be to form components of reduced size to achieve increased levels of integration. The size of a component may be expressed in terms of the minimum feature size F of the lithographic process utilized during the manufacture of the component. Some of the embodiments described herein include fitting within a region defined as 4F. 2 memory cells within the region.

[0063] The rails 312 are spaced apart from each other along the second direction (x-axis direction) by the middle region 316. A gap (also referred to as a middle gap) 318 is located within the middle region 316. In some embodiments, Figure 2A and 2B The void 318 at the processing stage in FIG. 304 may be referred to as a gap. Material 304 is along the bottom of the gap, and materials 14, 32, and 308 are along the sidewalls of the gap.

[0064] Reference Figure 3A and 3B , forming a sacrificial material 320 within the void 318. The sacrificial material 320 may include any suitable one or more compositions; and in some embodiments, the sacrificial material may include an organic polymer, silicon dioxide, etc. The sacrificial material 320 is shown in a stippled manner to help the reader identify such sacrificial material.

[0065] In the illustrated embodiment, sacrificial material 320 comprises a first insulating material (e.g., silicon dioxide) and is separated from materials 14, 18, 304, and 308 by an insulating liner 322 of a second insulating material 324. Second insulating material 324 may comprise any suitable composition or compositions; and in some embodiments, the insulating material may comprise, consist essentially of, or consist of silicon nitride.

[0066] In some embodiments, insulating material 324 can be considered to line the sidewalls of gap 318 and define void 326 within the lined gap. Sacrificial material 320 can be considered to be formed within void 326.

[0067] In the illustrated embodiment, voids 326 and gaps 318 are configured as trenches extending along a first direction along the y-axis.

[0068] The sacrificial material 320 may be formed by any suitable process. If the sacrificial material comprises silicon oxide (eg, silicon dioxide), the sacrificial material may be formed using a spin-on process; and may be formed, for example, as spin-on glass.

[0069] Reference Figure 4A and 4B , forming a capping material 330 over the gap 326. The capping material may include any suitable one or more compositions. In some embodiments, the capping material 330 is a conductive material and is patterned into a conductive plate 332. Such a conductive plate is supported by an insulating support 314. The conductive plate 332 may include a metal nitride; and may, for example, include, consist essentially of, or consist of titanium nitride.

[0070] A window 334 is formed to extend through the plate 332. The window 334 exposes an area of ​​the sacrificial material 320 within the trench (void) 326.

[0071] Reference Figure 5A and 5B , removing sacrificial material 320 to reform void 326. Such removal may be accomplished by flowing an etchant through window 334 to dig out sacrificial material from beneath plate 332.

[0072] Reference Fig. 6A and 6B , insulating material 336 is formed over plate 332. Insulating material 336 may include any suitable composition or compositions; and in some embodiments, the insulating material may include, consist essentially of, or consist of silicon dioxide. It may be considered that insulating material 336 is configured to extend across conductive plate 332 and across window 334 ( Figure 5A ) extending insulating extension portion 338.

[0073] Figure 6B The bit lines 32 are separated from each other by an intermediate region 316 including a void 326. The void can be used as a low-k dielectric region; wherein the term "low-k" means that the dielectric constant is less than the dielectric constant of silicon dioxide. The low-k dielectric region can reduce parasitic coupling between adjacent bit lines.

[0074] The void may have a width along the illustrated x-axis (i.e., along Figure 6BThe bit line 326 may have any suitable width along the x-axis (cross-section). In the illustrated embodiment, the bit line has a first width W1 along the x-axis, and the void 326 has a second width W2 along the x-axis. The second width W2 may be at least as large as the first width W1. In some example embodiments, the second width W2 may be at least about twice the first width W1.

[0075] The gap 326 has a Figure 6B The periphery of the cross section of . The periphery has a bottom region 327 and has a sidewall region 329. Regions 327 and 329 are defined by silicon nitride 324. In other embodiments, Figure 6B The silicon nitride 324 may not be present during the processing stage, and Figure 6B The remaining gaps in the processing stage may include Figure 2B The entire gap 318.

[0076] Figure 6B The conductive plate 332 is spaced a distance D from the bit line 32, and the distance D corresponds to the thickness of the insulating support material 308. In some embodiments, the distance D can be tailored to enable the conductive plate 332 to drain excess charge from the underlying bit line 32 and thereby reduce parasitic capacitance between adjacent bit lines. The distance D can be in any suitable range; and in some embodiments, the distance D can be in a range of about 5 nanometers (nm) to about 50 nm.

[0077] Conductive plate 332 may be electrically coupled to reference source 340 to better enable the plate to drain excess charge from the underlying bit lines. The reference source may have any suitable voltage, and in some embodiments may be at ground voltage (ie, conductive plate 332 may be electrically grounded).

[0078] exist Figure 6B In the illustrated embodiment, the void 326 extends to a bottom surface 331 of the conductive plate 332 .

[0079] It can be considered Fig. 6A and 6B The structure 10 includes a configuration suitable for reducing parasitic capacitance between adjacent bit lines. Such a configuration can be utilized in a DRAM array. An example DRAM array and an example method of forming a DRAM array are described with reference to FIGS. 7-40.

[0080] A first example method of forming a first example DRAM array is described with reference to FIGS. 7-13.

[0081] Reference Fig. 7A and 7B, construction 10a includes islands 80 of semiconductor material 14 extending upward from a block 82 of semiconductor material. These islands are capped with protective material 104. Protective material 104 may include any suitable composition or compositions; and in some embodiments, the insulating material may include, consist essentially of, or consist of silicon nitride.

[0082] Reference Fig. 8A and 8B , the areas between the islands 80 are lined with insulating material 40, shielding material 42 is then deposited and recessed, and further insulating material 40 is then provided over the shielding material.

[0083] Insulating material 40 may include any suitable composition or compositions; and in some embodiments, may include, consist essentially of, or consist of silicon dioxide.

[0084] Conductive shield material 42 may include any suitable one or more compositions; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), one or more metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive shield material 42 may include, consist essentially of, or consist of conductively doped semiconductor materials (e.g., conductively doped polysilicon). The conductively doped semiconductor materials may be doped to any suitable concentration, and in some embodiments may be doped to at least about 1×10 20 Atom / cm 3 In other words, in some example embodiments, the shielding material 42 may include a polycrystalline semiconductor material (eg, polysilicon) that is heavily doped with one or more impurities (eg, one or more of phosphorus, arsenic, boron, etc.).

[0085] In some embodiments, both semiconductor material 14 and shielding material 42 may include, consist essentially of, or consist of silicon; wherein the silicon of semiconductor material 14 is single crystalline and the silicon of shielding material 42 is polycrystalline (referred to as multicrystalline silicon in some applications).

[0086] Reference Fig.9A and 9B , remove the protective material 104 ( Fig. 8A and 8B), and then forming doped regions 22 along upper portions of islands 80. In the illustrated embodiment, doped regions 22 are formed after removing protective material 104. In other embodiments, semiconductor material 14 may be blanket doped before patterning the material into islands 80, and thus may be formed in a manner similar to that of the embodiment of FIG. Fig.9A and 9B Doped regions 22 are formed at an earlier processing stage than the processing stage of FIG. Doped regions 22 correspond to source / drain regions.

[0087] Capacitor 62 is formed to be coupled (electrically connected) to source / drain region 22. The capacitors shown are container-type capacitors; and each capacitor includes a container-shaped electrode 106, a dielectric material 108 within the container-shaped electrode, and another electrode 110 above the dielectric material 108 and within the container-shaped electrode. Electrodes 106 and 110 may include any suitable composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), one or more metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). Dielectric material 108 may include any suitable composition or compositions; and in some embodiments may include one or more of silicon dioxide, silicon nitride, and silicon oxynitride. Although capacitors are specifically shown, it should be understood that structure 62 may generally refer to any suitable memory element; including, for example, resistive memory, phase change memory, etc.

[0088] An insulating material 112 is disposed over and between capacitors 62. Insulating material 112 may include any suitable composition or compositions; and in some embodiments may include one or both of silicon dioxide and silicon nitride.

[0089] It may be considered that semiconductor material 14 , shielding material 42 , insulating material 40 , capacitor 62 , and insulating material 112 may together form a subassembly 114 .

[0090] Reference Fig. 10A and 10B , subassembly 114 is bonded to handle structure 94 via bonding region 96, and then inverted. Handle structure 94 may include any suitable configuration, and in some embodiments may correspond to a semiconductor wafer (e.g., a single crystal silicon wafer) or other suitable semiconductor substrate. For purposes of interpreting this disclosure, the term "semiconductor substrate" means any construction including semiconductor material, including but not limited to bulk semiconductor material, such as semiconductor wafers (alone or in an assembly including other materials) and layers of semiconductor material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrates described above.

[0091] The bonding of the subassembly 114 to the handle structure 94 can be accomplished using any suitable process; including, for example, techniques in which two silicon dioxide surfaces are placed relative to each other and subjected to appropriate treatment to induce covalent bonding between the surfaces and thereby form a composite structure. Thus, the bonding region 96 can include silicon dioxide. The treatment for inducing covalent bonding can be a thermal treatment. Such thermal treatment can utilize temperatures in excess of 800° C. Alternatively, one or both of the silicon dioxide surfaces can be subjected to a plasma treatment prior to the thermal treatment, and the temperature of the thermal treatment can then be reduced to a range of about 150° C. to about 200° C. The bonding of silicon dioxide surfaces to each other can be referred to as “hybrid bonding” (or “smart peeling”); example hybrid bonding procedures are described in U.S. Patents Nos. 9,666,573 and 10,103,053, both of which are assigned to Micron Technology, Inc., and both list Mitsunari Sukekawa as an inventor.

[0092] Block 82 of semiconductor material 14 is removed by suitable processing (e.g., CMP) Fig. 9B ), which exposes a region 98 of semiconductor material 14 (in some embodiments, region 98 may be considered to correspond to Fig. 9B The source / drain region 20 is formed along the region 98 and, in some embodiments, may be formed by implanting appropriate dopants into the region 98.

[0093] The groove 116 is formed to extend to the island 80 ( Fig. 9B ) and patterning pillars 48 from the islands. The trenches 116 extend along a first direction along the x-axis.

[0094] The trench 116 is lined with gate dielectric material 52, and then wordline material 54 is formed within such lined trenches and patterned into wordlines 58. Subsequently, further insulating material is formed over the wordlines. In the embodiment shown, the further insulating material has the same composition as material 52.

[0095] The conductive shielding material 42 is patterned into a shielding plate 43 .

[0096] Fig. 10A and 10B The embodiment of FIG. 1 shows trench 116 etched deep enough to reach doped region 22. In alternative embodiments, trench 116 may be etched shallower and a doped extension may be formed extending from the bottom of the trench to doped region 22. For example, Fig.11A and 11B Shows Fig. 10A and 10B1 and 12 are alternative embodiments, and show a doped extension 118 formed to extend from the bottom of trench 116 to doped region 22. Doped extension 118 may have the same conductivity type as region 22 and may be heavily doped with a suitable dopant. Alternatively, extension 118 may be less doped than region 22 and may correspond, for example, to a lightly doped diffusion region.

[0097] Reference Fig. 12A and 12B , showing that in Fig. 10A and 10B The bit line 32 is formed above the subassembly 114 and is coupled to the source / drain region 20. The bit line includes the above reference Figure 1A and 1B The bit line material 18 is described.

[0098] The conductive shield plate 43 is coupled (i.e., electrically connected) to a reference source (i.e., a reference voltage node, a reference structure, a reference terminal, etc.) 70. The reference source is configured to provide a desired voltage to the shield plate 43. This voltage may be any suitable voltage, and in some embodiments may be a ground voltage (i.e., the shield plate 43 may be electrically grounded).

[0099] Shielding material 42 may include any suitable composition and, in some embodiments, may be doped in a manner similar to source / drain regions 20 and 22. In some embodiments, doped regions 20 and 22 may be considered to include a first semiconductor material (i.e., material 14), and conductive shielding material 42 may be considered to include a second semiconductor material. If shielding material 42 includes conductively doped silicon, the shielding material may be doped to the same conductivity type as doped regions 20 and 22, or may be doped to the opposite conductivity type as doped regions 20 and 22 (p-type and n-type being understood as opposite conductivity types).

[0100] Fig. 12A and 12B The configuration of can be considered to correspond to an assembly including a memory array 60. The memory array includes bit lines 32 extending along a second direction along the y-axis (i.e., extending along columns 68 of the memory array 60), and includes word lines 58 extending along a first direction along the x-axis (i.e., extending along rows 66 of the memory array). The word lines 58 are vertically offset from the bit lines 32 and cross the bit lines (specifically, relative to the bit lines). Fig. 12B configuration crosses below the bit lines).

[0101] The pillars 48 are arranged in rows 66 and columns 68 of the memory array 60. The pillars 48 along a given column 68 are pillars coupled to a common bit line 32. The pillars 48 along a given row 66 are pillars coupled to a common word line. The word lines 58 are labeled 58a, 58b, and 58c so that the word lines can be distinguished from each other. The rows 66 are labeled 66a, 66b, and 66c so that the rows can be distinguished from each other; wherein row 66a includes pillars 48 associated with word line 58a, row 66b includes pillars 48 associated with word line 58b, and row 66c includes pillars associated with word line 58c. Individual pillars 48 are identified relative to a specific one of the rows 66a, 66b, and 66c associated with the pillar. The pillars associated with row 66a are labeled 166a, the pillars associated with row 66b are labeled 166b, and the pillars associated with row 66c are labeled 166c. It is noteworthy that each row includes a first series (i.e., a first group) of columns on one side of the word line and a second series (i.e., a second group) of columns on the opposite side of the word line. For example, one of the columns 166a is marked as 166a-1 to show that it is part of the first series on one side of the word line 58a, and the other columns of the column 166a are marked as 166a-2 to show that it is part of the second series on the opposite side of the word line 58a. The columns of the first group alternate with the columns of the second group along the row 66a. Similarly, the column 166b includes a first group 166b-1 and a second group 166b-2, and the column 166c includes a first group 166c-1 and a second group 166c-2 (not shown).

[0102] The opposite side edge of word line 58 Fig. 12A and 12B The cross-sectional view of the word line is labeled as sides 55 and 57. Sides 55 and 57 of the word line may be referred to as a first side surface and a second side surface of the word line.

[0103] Each semiconductor pillar in the semiconductor pillars 48 includes a channel region (i.e., a transistor channel region) 25 vertically disposed between the first source / drain region 20 and the second source / drain region 22. The channel region can be considered to be within the body region 24 of the transistor 132, wherein such body region extends between the first source / drain region and the second source / drain region. The word line 58 is adjacent to the channel region and is separated from the channel region by an intermediate insulating region including a gate dielectric material 52. The gate dielectric material is between the first side surface 55 and the channel region of the semiconductor pillars 48 of the first group (e.g., the pillar 166a-1 along the word line 58a), and the gate dielectric material is between the second side surface 57 and the semiconductor pillars 48 of the second group (e.g., the pillars marked as 166a-2 along the word line 58a). The conductive shielding material 42 is between the semiconductor pillars of the first group and the second group.

[0104] exist Fig. 12BIn the embodiment of FIG. 5 , the conductive shield material 42 does not extend below the word line 58 , but instead the shield plate 43 is configured as a vertical pillar.

[0105] Fig. 12B The embodiment of FIG. 5 shows a gate dielectric material 52 that spaces shielding material 42 from a second side 57 of word line 58 a and spaces channel region 25 from a first side 55 of word line 58 a. In other embodiments, the insulating material that spaces shielding material from one side of the word line can be different from the insulating material that spaces transistor channel material from the other side of the word line.

[0106] Fig. 12B The cross section of can be considered as a cross section along the column direction (i.e., along the y-axis direction). This cross section passes through a series of first semiconductor pillars (specifically, pillars identified as 166a-1, 166b-1, and 166c-1), and through a series of conductive plates 43 of shielding material 42. The word lines (58a, 58b, and 58c) along the cross section have first side surfaces 55 along channel regions 25 of the semiconductor pillars (i.e., along transistor channel regions including active regions within the semiconductor pillars) and are separated from such channel regions by gate dielectric material 52; and the word lines have second side surfaces 57 along conductive plates 43 and are separated from the conductive plates by gate dielectric material 52. The shielding plates 43 shown are pillars extending vertically along the cross section, wherein the area of ​​the shielding material does not extend below the word lines 58a-c.

[0107] It can be considered Fig. 12A and 12B The configuration includes a memory cell 130 that includes a capacitor 62 and a transistor 132. Such memory cells may have a maximum dimension along the x and y axes of 2F (where F is the maximum dimension of the memory cell 130). Figure 2A and 2B The minimum feature size discussed), and therefore the side periphery of the memory cell can fit within 4F 2 This is in the area Fig. 12A The diagram is shown in FIG. 4 , where the size is 2F×2F (i.e., the area 4F 2 ) box contains the entire side periphery of the memory unit 130.

[0108] In some embodiments, Fig. 12B The structure below the source / drain region 20 may correspond to Figure 1A and 1B Structure 300. Fig.13A and 13B It shows that it can be Fig. 12A and 12Band specifically, after processing of the type described with reference to FIGS. 1-6 , the configuration is used to form gaps 326 between adjacent bit lines 32 and to form conductive plates 332 above the bit lines. Plates 332 may be electrically grounded to the same Fig. 12B The shielding wires of the same reference structure 70 (or different reference structures). Fig. 12B Understandably, Fig. 13B Region 304 may include dielectric material 52 and portions of word line 58 .

[0109] 7-13, shielding plate 43 is completely electrically isolated from body region 24 of semiconductor pillar 48. In other embodiments, shielding plate may be electrically connected (electrically coupled) to body region 24. Examples of such other embodiments are described with reference to FIGS. 14-20.

[0110] Reference Fig.14A and 14B , construction 10b includes islands 80 of semiconductor material 14 extending upwardly from a block 82 of semiconductor material. These islands are capped with protective material 104. Fig.14A and 14B The construction can be compared with the above reference Fig. 7A and 7B The construction described is the same.

[0111] Reference Fig.15A and 15B , the areas between the islands 80 are lined with insulating material 40, shielding material 42 is then deposited and recessed, and further insulating material 40 is then provided over the shielding material. Fig.15A and 15B Configuration and Fig. 8A and Figure 8B The configuration of is different in that shielding material 42 penetrates through a bottom region of insulating material 40 such that a section along an outer boundary of the shielding material directly contacts semiconductor material 14 at interface region 120 .

[0112] Reference Fig.16A and 16B , perform similar operations as in the reference above Fig.9A and 9B Processing is described to form doped regions 22 and capacitor 62 of subassembly 114 .

[0113] Reference Fig.17A and 17B , perform similar operations as in the reference above Fig. 10A and 10B The process is described to key the subassembly 114 to the handle structure 94 and invert the subassembly.

[0114] Block 82 of semiconductor material 14 is removed by suitable processing (e.g., CMP) Fig. 16B ), which exposes region 98 of semiconductor material 14 (in some embodiments, region 98 can be considered to correspond to the bottom region of island 80). After removing block 82, an interface region 120 remains where conductive shielding material 42 is in contact with semiconductor material 14.

[0115] Reference Fig.18A and 18B , source / drain regions 20 are formed along an upper portion of the semiconductor material 14 . Fig.18A and 18B The source / drain regions 20 can be formed by referring to the above Fig. 10A and 10B The process described is similar to the process formation.

[0116] The trench 116 is formed to extend along the first direction of the x-axis. The trench 116 patterns the pillar 48 from the semiconductor material 14. The trench 116 can be formed by Fig. 10A and 10B The process described is similar to the process formation.

[0117] The trench 116 is lined with gate dielectric material 52, and then wordline material 54 is formed within such lined trenches and patterned into wordlines 58. Subsequently, additional insulating material is formed over the wordlines. In the embodiment shown, the additional insulating material has the same composition as material 52 (in other embodiments, the additional insulating material may have a different composition).

[0118] Conductive shielding material 42 is patterned into shielding plates 43. The shielding plates 43 are shown as gusseted plates with the bottom portion extending below the word lines 58.

[0119] Fig.18A and 18B The embodiment of FIG. 1 shows a trench 116 formed so as to be shallow enough to provide a doped extension 118 (having the same properties as described above with reference to FIG. 1 ) between the bottom of the trench and the source / drain region 22. Fig.11A and 11B In other embodiments, trench 116 may be etched deep enough that doped extension 118 may be omitted.

[0120] Reference Fig.19A and 19B , a bit line 32 is formed above the subassembly 114 and is coupled to the source / drain region 20 .

[0121] Conductive shield plate 43 is electrically coupled to reference structure 70 .

[0122] Fig.19A and 19B The construction of can be considered to correspond to an assembly including a memory array 60. The memory array includes bit lines 32 extending in a second direction along the y-axis (i.e., extending along columns 68 of the memory array 60), and includes word lines 58 extending in a first direction along the x-axis (i.e., extending along rows 66 of the memory array). Pillars 48 are arranged in rows 66 and columns 68 of the memory array 60. Pillars 48 along a given column 68 are pillars coupled to a common bit line 32. Pillars 48 along a given row 66 are pillars coupled to a common word line. Word lines 58 are labeled 58a, 58b, and 58c so that these word lines can be distinguished from each other. Rows 66 are labeled 66a, 66b, and 66c so that these rows can be distinguished from each other; wherein row 66a includes pillars 48 associated with word line 58a, row 66b includes pillars 48 associated with word line 58b, and row 66c includes pillars associated with word line 58c. Individual columns 48 are identified relative to a specific one of the rows 66a, 66b, and 66c associated with the column. The column associated with row 66a is labeled 166a, the column associated with row 66b is labeled 166b, and the column associated with row 66c is labeled 166c. It is noteworthy that each row includes a first series (i.e., a first group) of columns on one side of the word line and a second series (i.e., a second group) of columns on the opposite side of the word line. For example, one of the columns 166a is labeled 166a-1 to show that it is part of the first series on one side of the word line 58a, and the other columns of the column 166a are labeled 166a-2 to show that it is part of the second series on the opposite side of the word line 58a. The columns of the first group alternate with the columns of the second group along the row 66a. Similarly, column 166b includes a first group 166b-1 and a second group 166b-2, and column 166c includes a first group 166c-1 and a second group 166c-2 (not shown).

[0123] The opposite side edge of word line 58 Fig.19A and 19B The cross-sectional view of FIG. 5 is identified as first and second sides (side surfaces) 55 and 57 .

[0124] Each of the semiconductor pillars 48 includes a channel region 25 vertically disposed between a first source / drain region 20 and a second source / drain region 22. A word line 58 is adjacent to this channel region and is spaced apart from the channel region by an intermediate insulating region including a gate dielectric material 52. The gate dielectric material is between the first side surface 55 and the channel region of the semiconductor pillars 48 of the first group (e.g., pillar 166a-1 along word line 58a), and the gate dielectric material is between the second side surface 57 and the semiconductor pillars 48 of the second group (e.g., pillars labeled 166a-2 along word line 58a). Conductive shielding material 42 is between the semiconductor pillars of the first group and the second group.

[0125] Fig.19B 4 and 5. The embodiment of FIG. 6 shows an interface region 120 that enables the shielding material 42 to directly contact the body region 24 of the access device (transistor) including the semiconductor pillar 48. In some embodiments, the shielding material 42 can include a suitable composition at a suitable reference voltage so that during operation of the access device associated with the memory array 60, the shielding material can mitigate floating body effects (i.e., charge accumulation) that may be associated with the body region 24. For example, in some embodiments, the shielding material can include a doped semiconductor material, wherein the doped semiconductor material has an opposite type of conductivity relative to the source / drain regions 20 and 22. For example, if the source / drain regions 20 and 22 are n-type, the shielding material can be p-type. The voltage source 70 can be configured to operate with the shielding plate 43 to mitigate floating body effects within the body region 24.

[0126] Fig.19B The cross section of can be considered as a cross section along the column direction (i.e., along the y-axis direction). This cross section passes through a series of first semiconductor pillars (specifically, pillars identified as 166a-1, 166b-1, and 166c-1), and through a series of conductive plates 43 of the shielding material 42. The word lines (58a, 58b, and 58c) along the cross section have a first side surface 55 along the channel regions 25 of the semiconductor pillars and are separated from these channel regions by the gate dielectric material 52; and the word lines have a second side surface 57 along the conductive plates 43 and are separated from the conductive plates by the gate dielectric material 52.

[0127] It can be considered Fig.19A and 19B The configuration includes a memory cell 130 that includes a capacitor 62 and a transistor 132. Such memory cells may have a maximum dimension along the x and y axes of 2F (where F is the minimum feature dimension), and thus the side periphery of the memory cell may fit within a 4F 2 within the area; Fig.19A , where the dimensions are 2F×2F (i.e., area 4F 2 ) box contains the entire side periphery of the memory unit 130.

[0128] In some embodiments, Fig.19B The structure below the source / drain region 20 may correspond to Figure 1A and 1B The structure of 300. Fig. 20A and 20B , which graphically shows that Fig.19A and 19Band specifically, after processing of the type described above with reference to FIGS. 1-6, the configuration is used to form gaps 326 between adjacent bit lines 32 and to form conductive plates 332 above the bit lines. Plate 332 may be electrically grounded to the Fig.19B The shielding wire (not shown) may be electrically coupled to the same reference structure 70, or may be electrically coupled to a different reference structure. Fig.19B Understandably, Fig. 20B Region 304 may include dielectric material 52 and portions of word line 58 .

[0129] The embodiment of Figures 7-20 shows that a capacitor is formed above a semiconductor substrate, the substrate is subsequently inverted and bonded to a handle, and then a bit line is formed. In an alternative process, a bit line can be formed above a semiconductor substrate, and then the substrate is inverted and the capacitor is formed. This alternative process is described with reference to Figures 21-33; wherein Figures 21-27 describe a process similar to the process of Figures 7-13 (i.e., a process without forming a body in contact with the shield plate), and Figures 28-33 describe a process similar to the process of Figures 14-20 (i.e., a process of forming a body in contact with the shield plate).

[0130] Reference Fig.21A and 21B , construction 10c includes islands 80 of semiconductor material 14 extending upwardly from a block 82 of semiconductor material. These islands are capped with protective material 104.

[0131] Reference Fig.22A and 22B , the areas between the islands 80 are lined with insulating material 40, shielding material 42 is then deposited and recessed, and further insulating material 40 is then provided over the shielding material.

[0132] Reference Fig.23A and 23B , remove the protective material 104 ( Fig.22A and 22B ), and a doped region 20 is formed at the top of the island 80 of semiconductor material. Then, a bit line 32 is formed over the doped region 20. Fig.23A A portion of doped region 20 is shown in the view of FIG. 1 to help the reader visualize the relationship of the bit line to region 20, but the portion is shown in a dashed (virtual) view to indicate that it is in the Fig.23A outside the plane of the cross section. Fig.23A and 23B The structure of the subassembly 114 is similar to the subassembly described above. The area below the bit line 32 can be considered to include the bottom area 300 ( Fig.23A and 23B Not marked in ), the underlying region is similar to Figure 1A and 1B area 300.

[0133] Reference Fig.24A and 24B 1-6, gaps 326 are formed between adjacent bit lines 32, and conductive plates 332 are formed over the bit lines. Plates 332 may be electrically grounded to reference structure 70 (or a different reference structure). Fig.24A and 24B The materials and structures become part of the subassembly 114.

[0134] Reference Fig.25A and 25B , the subassembly 114 is keyed to the handle structure 94 and is utilized similarly to the above reference Fig. 10A and 10B The hybrid bonding described is performed inverted. In the illustrated embodiment, insulating material 336 of extension 338 is bonded to structure 94 via bonding region 96.

[0135] Block 82 of semiconductor material 14 is removed by suitable processing (e.g., CMP) Fig. 23B ), which exposes a region 98 of semiconductor material 14 (in some embodiments, region 98 can be considered to correspond to the bottom region of island 80).

[0136] Reference Fig.26A and 26B , forming source / drain regions 22 along the upper portion of semiconductor material 14. Fig. 10A and 10B The source / drain regions 22 are formed by a process similar to that described.

[0137] The trench 116 is formed to extend along the first direction of the x-axis. The trench 116 patterns the semiconductor material 14 into the pillar 48. The trench 116 can be formed by Fig. 10A and 10B The process described is similar to the process formation.

[0138] The trench 116 is lined with gate dielectric material 52, and then wordline material 54 is formed within such lined trenches and patterned into wordlines 58. Subsequently, additional insulating material is formed over the wordlines. In the embodiment shown, the additional insulating material has the same composition as material 52 (in other embodiments, the additional insulating material may have another composition).

[0139] The conductive shielding material 42 is patterned into a shielding plate 43 .

[0140] exist Fig.26A and 26BIn the illustrated embodiment, the doped extension 118 is formed to extend from the bottom of the trench 116 to the doped region 20 .

[0141] Reference Fig.27A and 27B , capacitors 62 (shown as blocks) are electrically coupled to source / drain regions 22. Insulating material 102 is provided between capacitors 62. Shield plate 43 is electrically coupled to reference voltage 70.

[0142] Fig.27A and 27B The memory cell 130 of the embodiment may be configured to have a side periphery that is contained within the 4F 2 In the region, such as relative to Fig.33A shown.

[0143] The next embodiment is described with reference to Figures 28-33.

[0144] Reference Fig.28A and 28B , showing that it can be Fig.21A and 21B The construction of the processing stage after the processing stage 10d. Fig.28A and 28B Configuration and Fig.22A and Fig. 22B The configuration of is different in that shielding material 42 penetrates through a bottom region of insulating material 40 such that a section along an outer boundary of the shielding material directly contacts semiconductor material 14 at interface region 120 .

[0145] Reference Fig.29A and 29B , remove the protective material 104 ( Fig.28A and 28B ), and a doped region 20 is formed at the top of the island 80 of semiconductor material. Then, a bit line 32 is formed over the doped region 20. Fig.29A A portion of doped region 20 is shown in the view of FIG. 1 to help the reader visualize the relationship of the bit line to region 20, but the portion is shown in a dashed (virtual) view to indicate that it is in the Fig.29A outside the plane of the cross section. Fig.29A and 29B The structure of the subassembly 114 is similar to the subassembly described above. The area below the bit line 32 can be considered to include the bottom area 300 ( Fig.29A and 29B Not marked in ), the underlying region is similar to Figure 1A and 1B area 300.

[0146] Reference Fig. 30A and 30B1-6, gaps 326 are formed between adjacent bit lines 32, and conductive plates 332 are formed over the bit lines. Plates 332 may be electrically grounded to reference structure 70 (or another suitable structure). Fig. 30A and 30B The materials and structures become part of the subassembly 114.

[0147] Reference Fig.31A and 31B , the subassembly 114 is keyed to the handle structure 94 and is utilized similarly to the above reference Fig. 10A and 10B The described process is reversed.

[0148] Block 82 of semiconductor material 14 is removed by suitable processing (e.g., CMP) Fig.29B ).

[0149] Reference Fig.32A and 32B , source / drain regions 22 are formed along an upper portion of the semiconductor material 14 .

[0150] The trenches 116 are formed to extend along a first direction of the x-axis. The trenches 116 pattern the semiconductor material 14 into the pillars 48.

[0151] The trench 116 is lined with gate dielectric material 52, and then wordline material 54 is formed within such lined trenches and patterned into wordlines 58. Subsequently, additional insulating material is formed over the wordlines. In the embodiment shown, the additional insulating material has the same composition as material 52 (in other embodiments, the additional insulating material may have another composition).

[0152] The conductive shielding material 42 is patterned into a shielding plate 43 .

[0153] exist Fig.32A and 32B In the illustrated embodiment, the doped extension 118 is formed to extend from the bottom of the trench 116 to the doped region 20 .

[0154] Reference Fig.33A and 33B , capacitors 62 (shown as blocks) are electrically coupled to source / drain regions 22. Insulating material 102 is provided between capacitors 62. Shield plate 43 is electrically coupled to reference voltage 70.

[0155] Fig.33B The embodiment of FIG. 1 shows an interface region 120 that enables the shielding material 42 to be similar to the above referenced Fig.19B The described approach directly contacts the body region 24 of the access device (transistor).

[0156] Fig.33A and 33B The memory cell of the embodiment can be configured to have a side periphery that is contained within a 4F 2 In the region, such as relative to Fig.33A shown.

[0157] Another example embodiment for forming an example memory array is described with reference to Figures 34-39.

[0158] Reference Fig.34A and 34B , construction 10e includes islands 80 of semiconductor material 14 extending upwardly from a block 82 of semiconductor material. These islands have doped regions 20. Such regions 20 are Fig.34B In some embodiments, doped region 20 may be considered to correspond to a first source / drain region.

[0159] The insulating material 40 is formed to laterally surround the island and line the outer side surface 81 of the island. The insulating material 40 may be referred to as a first insulating material to distinguish it from other insulating materials formed in subsequent processing stages.

[0160] Conductive shielding material 42 is formed between the lined islands.

[0161] Reference Fig.35A and 35B , bit line 32 is formed above the island and is electrically coupled (i.e., electrically connected) to doped region 20. In some embodiments, the planarized surface may extend across doped region 20 and insulating material 40, and the bit line may be formed along the planarized surface. Bit line 32 includes bit line material 18 described above with reference to FIG. 1, and extends along the second direction of the y-axis.

[0162] exist Fig.35A The bit line 32 is shown in a dashed view to indicate the relative position of the bit line Fig.35A The cross section is out of plane.

[0163] In some embodiments, the insulating material 40, the semiconductor material 14, and the conductive shielding material 42 may be considered to form a structure 84 together, and the bit lines 32 may be considered to be formed to extend across the upper surface of this structure. It is worth noting that two bit lines extend across each of the islands, such as with respect to Fig.35A 84. The bit lines 32 may be considered to form a pattern across the structure 84. The bit lines 32 are separated by gaps 86. These gaps extend into the structure 84.

[0164] Reference Fig.36A and 36B, gaps 326 are formed between adjacent bit lines 32, and conductive plates 332 are formed over the bit lines using processes of the type described above with reference to FIGS. 1-6. Fig.36A and 36B The materials and structures become part of the subassembly 114.

[0165] Reference Fig.37A and 37B , the subassembly 114 is bonded to the handle structure 94 via the bonding area 96 and then inverted.

[0166] Block 82 of semiconductor material 14 is removed by suitable processing (e.g., CMP) Fig.35B ), which exposes the bottom region 98 of the island 80. The source / drain region 22 is formed along the exposed bottom region 98 of the island 80, and in some embodiments, can be formed by implanting appropriate dopants into the bottom region of the island.

[0167] Reference Fig.38A and 38B , forming an additional insulating material 40, and then forming a trench 100 to extend to the bottom of the island 80. The trench 100 subdivides the island into pillars 48. The trench 100 may be referred to as a second trench. The second trench 100 extends along the first direction of the x-axis.

[0168] The second trench is lined with a gate dielectric material 52, and then a word line material 54 is formed within the lined trench and patterned into a word line 58. Subsequently, an insulating material 56 is formed over the word line.

[0169] Reference Fig.39A and 39B , capacitor 62 (shown as a block) is electrically coupled to source / drain region 22. Insulating material 102 is provided between capacitor 62. To simplify the drawings, Fig.39A The cross-hatching of conductive material 56 is not shown.

[0170] The conductive shielding material is patterned into a shielding plate 43 , and the shielding plate is electrically coupled to the reference structure 70 .

[0171] Fig.39A and 39BThe construction 10e can be considered to correspond to an assembly including a memory array 60. The memory array 60 includes bit lines 32 extending in a second direction along the y-axis (i.e., extending along columns 68 of the memory array 60), and includes word lines 58 extending in a first direction along the x-axis (i.e., extending along rows 66 of the memory array). Pillars 48 are arranged in rows 66 and columns 68 of the memory array 60. Pillars 48 along a given column 68 are pillars coupled to a common bit line 32. Pillars 48 along a given row 66 are pillars coupled to a common word line. Word lines 58 are labeled 58a, 58b, and 58c so that these word lines can be distinguished from each other. Rows 66 are labeled 66a, 66b, and 66c so that these rows can be distinguished from each other; wherein row 66a includes pillars 48 associated with word line 58a, row 66b includes pillars 48 associated with word line 58b, and row 66c includes pillars associated with word line 58c. Individual columns 48 are identified relative to a specific one of the rows 66a, 66b, and 66c associated with the column. The column associated with row 66a is labeled 166a, the column associated with row 66b is labeled 166b, and the column associated with row 66c is labeled 166c. It is noteworthy that each row includes a first series (i.e., a first group) of columns on one side of the word line and a second series (i.e., a second group) of columns on the opposite side of the word line. For example, a pair of columns 166a is labeled 166a-1 to show that it is part of the first series on one side of the word line 58a, and another pair of columns 166a is labeled 166a-2 to show that it is part of the second series on the opposite side of the word line 58a. The columns of the first group alternate with the columns of the second group along the row 66a. Similarly, column 166b includes a first group 166b-1 and a second group 166b-2, and column 166c includes a first group 166c-1 and a second group 166c-2.

[0172] The opposite side edge of word line 58 Fig.39A and 39B The cross-sectional view of FIG. 5 is identified as first and second sides (side surfaces) 55 and 57 .

[0173] Each of the semiconductor pillars 48 includes a channel region 25 vertically disposed between a first source / drain region 20 and a second source / drain region 22. A word line 58 is adjacent to this channel region and is spaced apart from the channel region by an intermediate insulating region including a gate dielectric material 52. The gate dielectric material is between the first side surface 55 and the channel region of the semiconductor pillars 48 of the first group (e.g., pillars 166a-1 along word line 58a), and the gate dielectric material is between the second side surface 57 and the semiconductor pillars 48 of the second group (e.g., pillars 166a-2 along word line 58a). The conductive shielding material 42 is between the semiconductor pillars of the first group and the second group.

[0174] Fig.39B The cross section of can be considered as a cross section along the column direction (i.e., along the y-axis direction). This cross section passes through a series of first semiconductor pillars (specifically, pillars identified as 166a-1, 166b-1, and 166c-1), and through a series of conductive plates 43 of shielding material 42. The word lines (58a, 58b, and 58c) along the cross section have a first side surface 55 along the channel regions 25 of the semiconductor pillars and are separated from these channel regions by gate dielectric material 52; and the word lines have a second side surface 57 along the conductive plates 43 and are separated from the conductive plates by gate dielectric material 52. The shielding plates 43 shown are angled plates along the cross section, wherein the bottom area of ​​the angled plates partially extends across the bottom of the word lines 58a-c.

[0175] Fig.39A and 39B The memory array 60 includes a memory cell 130. In some embodiments, an individual memory cell may be configured to have a side periphery that is contained within a 4F 2 In the region, such as relative to Fig.39A shown.

[0176] The memory array 60 described herein may be a DRAM array and may include memory cells having a combination of one transistor and one capacitor (1T-1C memory cells). Fig.40 A portion of an example DRAM array 60 is schematically illustrated. Bit lines (digit lines) 32 are shown corresponding to bit lines BL1, BL2, BL3, and BL4; and word lines 58 are shown corresponding to word lines WL1, WL2, WL3, and WL4. Memory cells 130 extend across the array, wherein each of the memory cells includes a capacitor 62 and a transistor (access device) 132. The access device may include an active region within a pillar 48 as described with reference to various embodiments herein; wherein the active region includes the pair of source / drain regions 20 and 22 and a channel region 25 between the source / drain regions. Fig.40 Each memory cell 130 within the memory array 60 of the memory cell is uniquely addressed by a combination of one of the word lines and one of the bit lines. The memory array may contain any suitable number of memory cells; and in some embodiments, the memory array may include hundreds, millions, tens of millions, etc. of memory cells.

[0177] In some embodiments, any type of memory array 60 described herein may be within a memory hierarchy (ie, a memory stack) that is within a vertically stacked arrangement of the hierarchy (or stack). For example, Fig.41A portion of an integrated assembly 140 is shown, which includes a vertically stacked arrangement of layers (labeled as layers 1-4). The vertically stacked arrangement can be extended upward to include additional layers. Layers 1-4 can be considered as examples of levels stacked one on top of another. The levels can be in different semiconductor die, or at least two of the levels can be in the same semiconductor die.

[0178] The bottom tier (tier 1) may include control circuitry and / or sensing circuitry (e.g., may include word line drivers, sense amplifiers, etc.); and in some applications, may include CMOS circuitry (diagrammatically shown as CMOS circuitry 142). One or more of the upper tiers (tiers 2-4) may include memory arrays, such as, for example, any type of memory array 60 described herein. If multiple tiers include memory arrays, the memory arrays within each tier may be identical to one another (e.g., may all be DRAM arrays), or may be different relative to one another (e.g., some may be DRAM arrays while others are NAND arrays). Fig.41 The memory array 60 is diagrammatically indicated to be within a second tier (tier 2), and electrical connections 143 are shown between CMOS circuitry 142 of tier 1 and components of the memory array 60 of tier 2. In some embodiments, CMOS circuitry 142 may be electrically coupled to word lines and / or bit lines of memory 60; and may include, for example, word line drivers, sense amplifiers, etc.

[0179] The assemblies and structures discussed above may be used within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer multi-chip modules. The electronic system may be any of a variety of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0180] Unless otherwise stated, the various materials, substances, compositions, etc. described herein may be formed by any suitable method currently known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0181] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. In this disclosure, the terms are considered synonymous. The use of the term "dielectric" in some cases and the term "insulating" (or "electrically insulating") in other cases may be intended to provide language changes within the disclosure to simplify the premise basis within the subsequent claims, rather than to indicate any significant chemical or electrical differences.

[0182] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the claims that follow are directed to any structure having the described relationships between the various features, whether the structure is in a specific orientation of the drawings or rotated relative to such orientation.

[0183] Unless otherwise noted, the cross-sectional views illustrated in the drawings only show features within the plane of the cross-section and do not show material behind the plane of the cross-section to simplify the drawings.

[0184] When a structure is referred to above as being "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly over," and the like do not denote direct physical contact (unless expressly stated otherwise), but rather denote vertical alignment.

[0185] Structures (eg, layers, materials, etc.) may be referred to as "vertically extending" to indicate that the structures extend generally upward from an underlying base (eg, substrate). Vertically extending structures may or may not extend substantially orthogonally relative to an upper surface of a base.

[0186] Some embodiments include a memory device having a buried word line, a shielding plate, and an access device. The access device includes a first diffusion region and a second diffusion region and a channel region. The diffusion region and the channel region are arranged vertically so that the channel region is between the first diffusion region and the second diffusion region. The access device is adjacent to the word line and the shielding plate so that a portion of the word line is adjacent to a first side surface of the channel region, with an intervening portion of a first insulating material interposed therebetween, and a portion of the shielding plate is adjacent to a second side surface of the channel region, with an intervening portion of a second insulating material interposed therebetween.

[0187] Some embodiments include a memory array having bit lines spaced apart from each other by intervening gaps. Word lines are vertically offset from and intersect the bit lines. Memory cells are located near where the word lines intersect the bit lines. Each of the memory cells is uniquely addressed by a combination of word lines and bit lines. The side periphery of each of the memory cells fits within a 4F 2 within the area.

[0188] Some embodiments include an integrated assembly having bit lines spaced apart from each other by a gap in between, an insulating support over the bit lines, and a conductive plate supported by the insulating support and close to the bit lines to drain excess charge from the bit lines.

[0189] Some embodiments include an integrated assembly having a row of vertically extending semiconductor pillars. Each of the semiconductor pillars includes a transistor channel region disposed vertically between a first source / drain region and a second source / drain region. A word line extends along the row of vertically extending semiconductor pillars and is adjacent to the transistor channel region of the semiconductor pillars. The word line has a first side surface and an opposite second side surface. The semiconductor pillars are subdivided into a first group along the first side surface and a second group along the second side surface. The semiconductor pillars of the first group alternate with the semiconductor pillars of the second group along the row. A gate dielectric material is between the first side surface and the transistor channel region of the semiconductor pillars of the first group, and between the second side surface and the transistor channel region of the semiconductor pillars of the second group. A conductive shielding material is between the semiconductor pillars of the first group, and between the semiconductor pillars of the second group. A bit line is coupled to the first source / drain region. The bit lines are spaced apart from each other by gaps and are operably adjacent to a conductive plate configured to drain excess charge from the bit lines. A storage element is coupled to the second source / drain region.

[0190] Some embodiments include a method of forming a bit line. A bit line material is formed above an underlying structure. The bit line material is patterned into a bit line. The bit line extends along a first direction. The bit lines are spaced apart from each other by gaps along a second direction orthogonal to the first direction. A capping material is formed above the gap. A word line is formed to be vertically offset from the bit line and intersects the bit line. A memory cell is formed near the intersection of the word line and the bit line. Each of the memory cells is uniquely addressed by a combination of the word line and the bit line. The side periphery of each of the memory cells is matched at 4F 2 within the area.

[0191] Some embodiments include a method of forming an integrated assembly. A stack is formed to have an insulating material above a bit line material. The stack is patterned into a track extending along a first direction. The track includes the patterned bit line material as a bit line and includes the patterned insulating material as an insulating support above the bit line. The tracks are spaced apart from each other by an intermediate gap along a second direction orthogonal to the first direction. A sacrificial material is formed within the intermediate gap. A conductive plate is formed above the insulating support and the sacrificial material. The sacrificial material is removed from under the conductive plate to reform the gap.

[0192] As specified, the subject matter disclosed herein has been described in language more or less specific in terms of structural and methodological features. However, it will be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes example embodiments. The claims are therefore to be given full scope in their literal terms and appropriately interpreted under the doctrine of equivalents.

Claims

1. An integrated assembly comprising: a row of vertically extending semiconductor pillars; each of the semiconductor pillars comprising a transistor channel region, the transistor channel region being vertically disposed between a first source / drain region and a second source / drain region; a word line extending along the row of vertically extending semiconductor pillars and adjacent to the transistor channel regions of the semiconductor pillars; The word line has a first side surface and an opposite second side surface; the semiconductor pillars are subdivided into a first group along the first side surface and a second group along the second side surface; the semiconductor pillars of the first group are alternated with the semiconductor pillars of the second group along the row; a gate dielectric material between the first side surface and the transistor channel region of the first group of semiconductor pillars and between the second side surface and the transistor channel region of the second group of semiconductor pillars; a conductive shielding material between the semiconductor pillars of the first group and between the semiconductor pillars of the second group; a bit line coupled to the first source / drain region, the bit lines being spaced apart from each other by gaps and operably proximate to a conductive plate configured to drain excess charge from the bit line; as well as A storage element is coupled to the second source / drain region.

2. The integrated assembly of claim 1, wherein the conductive shielding material comprises a metal.

3. The integrated assembly of claim 1, wherein the conductive shielding material comprises a conductively doped semiconductor material.

4. The integrated assembly of claim 1, wherein the conductive shielding material comprises conductively doped silicon.

5. The integrated assembly of claim 1, wherein the conductive shielding material and the conductive plate are coupled to a reference source having a ground voltage.

6. The integrated assembly of claim 1, wherein the transistor channel region is within a body region of the semiconductor pillar, and wherein the conductive shielding material directly contacts the body region.

7. The integrated assembly of claim 1, wherein the word lines are vertically offset from and intersect the bit lines; and the integrated assembly further comprises: a memory cell, the memory cell being close to a location where the word line crosses the bit line; Each of the memory cells is uniquely addressed by a combination of a word line and a bit line; The side periphery of each memory cell in the memory cell is matched at 4F 2 within the area.

8. The integrated assembly of claim 7, wherein the bit line extends along a first direction and has a first width along a cross section orthogonal to the first direction; and wherein the gap has a second width along the cross section, the second width being at least as large as the first width.

9. The integrated assembly of claim 8, wherein the second width is greater than the first width.

10. The integrated assembly of claim 9, wherein the second width is at least twice the first width.

11. The integrated assembly of claim 1 wherein the void has a periphery along a cross-section; the periphery has a bottom region and a sidewall region; the bottom region and the sidewall region of the periphery of the void are defined by silicon nitride.

12. The integrated assembly of claim 1, further comprising: an insulating support, the insulating support being located above the bit line; as well as A conductive plate is supported by the insulating support.

13. The integrated assembly of claim 12, wherein the conductive plate is electrically coupled to a reference source.

14. The integrated assembly of claim 13, wherein the reference source has a ground voltage.

15. The integrated assembly of claim 12, wherein the void extends to a lower surface of the conductive plate.

16. The integrated assembly of claim 12, wherein the conductive plate comprises a metal nitride.

17. The integrated assembly of claim 12, wherein the conductive plate comprises titanium nitride.

18. The integrated assembly of claim 12, wherein the void has a periphery along a cross-section; the periphery has a bottom region and a sidewall region; the bottom region and the sidewall region of the periphery of the void are defined by silicon nitride.

19. The integrated assembly of claim 12, wherein the word lines are vertically offset from and intersect the bit lines; and the integrated assembly further comprises: a memory cell, the memory cell being close to a location where the word line crosses the bit line; Each of the memory cells is uniquely addressed by a combination of a word line and a bit line; The side periphery of each memory cell in the memory cell is matched at 4F 2 within the area.

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