Integrated circuit device and method of manufacturing the same

Abstract

The present disclosure provides an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes a capacitor structure, wherein the capacitor structure includes: a bottom electrode over a substrate; a support on sidewalls of the bottom electrode; a dielectric layer on the bottom electrode and the support; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode includes: a base electrode layer over the substrate and extending in a first direction perpendicular to a top surface of the substrate; and a conductive capping layer including niobium nitride between sidewalls of the base electrode layer and the dielectric layer and between a top surface of the base electrode layer and the dielectric layer.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit device and a method for manufacturing the integrated circuit device, and more specifically, to an integrated circuit device including a capacitor structure and a method for manufacturing the integrated circuit device. Background Technology

[0002] As integrated circuit devices shrink proportionally, the size of the capacitor structure in dynamic random access memory (DRAM) devices also decreases. With this reduction in capacitor structure size, methods have been proposed to form a capacitor dielectric layer in a crystalline phase with a high dielectric constant to increase the capacitance of the capacitor structure. However, since the aspect ratio of the bottom electrode has also increased with the decrease in capacitor structure size, voids or seams may form within the conductive layer during the formation of the bottom electrode. Such voids and seams can lead to a deterioration in the electrical performance of the DRAM device. Summary of the Invention

[0003] This disclosure provides an integrated circuit device including a capacitor structure comprising a capacitor dielectric layer having a relatively high dielectric constant, and even simultaneously including a bottom electrode without gaps or seams.

[0004] This disclosure also provides a method for manufacturing an integrated circuit device, which allows the formation of a bottom electrode without gaps or seams and allows the formation of a capacitor dielectric layer with a relatively high dielectric constant.

[0005] According to some aspects of the present invention, an integrated circuit device including a capacitor structure is provided, wherein the capacitor structure includes: a bottom electrode on a substrate; a support on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the support; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode includes: a substrate electrode layer extending on the substrate in a first direction perpendicular to the top surface of the substrate; and a conductive overlay layer including niobium nitride and located between the sidewall of the substrate electrode layer and the dielectric layer, and between the top surface of the substrate electrode layer and the dielectric layer.

[0006] According to some aspects of the present invention, an integrated circuit device including a capacitor structure is provided, wherein the capacitor structure includes: a bottom electrode on a substrate; a support on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the support; and a top electrode on the dielectric layer and covering the bottom electrode. The bottom electrode includes: a substrate electrode layer comprising niobium nitride and extending on the substrate in a first direction perpendicular to the top surface of the substrate; and a first seed layer surrounded by the support and in contact with at least a portion of the substrate electrode layer.

[0007] According to some aspects of the present invention, an integrated circuit device including a capacitor structure is provided, wherein the capacitor structure includes: a landing pad on a substrate; a bottom electrode on the landing pad; a support on a sidewall of the bottom electrode; a dielectric layer on the bottom electrode and the support; and a top electrode on the dielectric layer to cover the bottom electrode. The bottom electrode includes a base electrode layer comprising niobium nitride, extending on the substrate in a first direction perpendicular to the top surface of the substrate. The portion of the dielectric layer in contact with the base electrode layer comprises hafnium oxide having a tetragonal phase, and the bottom surface of the bottom electrode contacts the top surface of the landing pad.

[0008] According to some aspects of the present invention, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a landing pad on a substrate; forming a mold structure on the landing pad, the mold structure including an opening exposing a top surface of the landing pad; and forming a base electrode layer within the opening, the base electrode layer comprising niobium nitride, wherein the formation of the base electrode layer includes selectively depositing the base electrode layer on the top surface of the landing pad relative to the sidewalls of the mold structure. Attached Figure Description

[0009] Various aspects of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a layout diagram showing an integrated circuit device according to some embodiments;

[0011] Figure 2 It is along Figure 1 A cross-sectional view of line A1-A1';

[0012] Figure 3 yes Figure 2 A magnified view of region CX1;

[0013] Figure 4 This is a cross-sectional view showing an integrated circuit device according to some embodiments;

[0014] Figure 5 yes Figure 4 A magnified view of region CX2;

[0015] Figure 6 This is a cross-sectional view showing an integrated circuit device according to some embodiments;

[0016] Figure 7 yes Figure 6 A magnified view of region CX3;

[0017] Figure 8 This is a cross-sectional view showing an integrated circuit device according to some embodiments;

[0018] Figure 9 yes Figure 8 A magnified view of region CX4;

[0019] Figure 10 This is a cross-sectional view showing an integrated circuit device according to some embodiments;

[0020] Figure 11 yes Figure 10 A magnified view of the CX5 region;

[0021] Figures 12 to 19 This is a cross-sectional view illustrating the sequential process of a method for manufacturing an integrated circuit device according to some embodiments;

[0022] Figures 20 to 23 This is a cross-sectional view illustrating the sequential process of a method for manufacturing an integrated circuit device according to some embodiments;

[0023] Figures 24 to 26 This is a cross-sectional view illustrating the sequential process of a method for manufacturing an integrated circuit device according to some embodiments;

[0024] Figures 27 to 33 This is a cross-sectional view illustrating the sequential process of a method for manufacturing an integrated circuit device according to some embodiments; and

[0025] Figures 34 to 41 This is a cross-sectional view illustrating the sequential process of a method for manufacturing an integrated circuit device according to some embodiments. Detailed Implementation

[0026] In the following, some embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0027] Figure 1 This is a layout diagram showing an integrated circuit device 100 according to some embodiments. Figure 2 It is along Figure 1 The cross-sectional view taken by line A1-A1'. Figure 3 yes Figure 2 A magnified view of region CX1.

[0028] Reference Figures 1 to 3 The substrate 110 may include an active region AC defined by a device isolation film 112. In an example embodiment, the substrate 110 may include a semiconductor material such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In an example embodiment, the substrate 110 may include conductive regions, such as impurity-doped traps or impurity-doped structures.

[0029] The device isolation film 112 may have a shallow trench isolation (STI) structure. For example, the device isolation film 112 may include an insulating material filling the device isolation trenches 112T formed in the substrate 110. The insulating material may include fluoride silicate glass (FSG), undoped silicate glass (USG), borosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), or toron silazane (TOSZ), however, this disclosure is not limited thereto.

[0030] The active region AC can have a relatively long island shape with a short axis and a long axis. For example... Figure 1 As shown in the example, the long axis of the active region AC can be arranged in the D3 direction, parallel to the top surface of the substrate 110. In the example embodiment, the active region AC can be doped with P-type or N-type impurities.

[0031] The substrate 110 may further include a gate trench 120T extending in the X direction parallel to the top surface of the substrate 110. The gate trench 120T may intersect the active region AC and may have a certain depth from the top surface of the substrate 110. A portion of the gate trench 120T may extend into the device isolation film 112, and the portion of the gate trench 120T formed in the device isolation film 112 may have a bottom surface at a level lower than the level of the bottom surface of the portion of the gate trench 120T formed in the active region AC.

[0032] The first source / drain region 114A and the second source / drain region 114B can be respectively arranged in the upper part of the active region AC located on both sides of the gate trench 120T. The first source / drain region 114A and the second source / drain region 114B can be impurity regions doped with impurities, which have a different conductivity type than the impurities doped into the active region AC. The first source / drain region 114A and the second source / drain region 114B can be doped with N-type or P-type impurities.

[0033] A gate structure 120 may be formed in a gate trench 120T. The gate structure 120 may include a gate insulating layer 122, a gate electrode 124, and a gate capping layer 126, which may be formed sequentially on the inner wall of the gate trench 120T in the order described herein.

[0034] The gate insulating layer 122 can be formed to a certain thickness on the inner wall of the gate trench 120T. The gate insulating layer 122 may include at least one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxide nitride, oxide / nitride / oxide (ONO), and high-k dielectric materials having a dielectric constant higher than that of silicon oxide. For example, the gate insulating layer 122 may have a dielectric constant of about 10 to about 25. In some embodiments, the gate insulating layer 122 may include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), HfAlO3, tantalum oxide (Ta2O3), titanium dioxide (TiO2), or combinations thereof; however, this disclosure is not limited thereto.

[0035] Gate electrode 124 may be formed on gate insulating layer 122 to fill gate trench 120T to a certain height from the bottom of gate trench 120T. Gate electrode 124 may include a work function adjustment layer (not shown) on gate insulating layer 122 and a gap fill metal layer (not shown) disposed on work function adjustment layer to fill the bottom of gate trench 120T. For example, work function adjustment layer may include metal, metal nitride or metal carbide, such as titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), TiAlCN, TiSiCN, tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), TaAlCN, TaSiCN, etc., and gap fill metal layer may include at least one selected from the group consisting of tungsten (W), tungsten nitride (WN), TiN and TaN.

[0036] A gate capping layer 126 may be disposed on the gate electrode 124 to fill the remainder of the gate trench 120T. As an example, the gate capping layer 126 may include at least one selected from the group consisting of silicon oxide, silicon oxide nitride, and silicon nitride.

[0037] Bit line structure 130 may be formed on first source / drain region 114A to extend in a Y direction parallel to the top surface of substrate 110 and perpendicular to the X direction. Bit line structure 130 may include bit line contacts 132, bit lines 134, and bit line capping layer 136, which may be stacked sequentially on substrate 110 in the order stated herein. Bit line structure 130 may also include bit line spacers 138 that may contact the sidewalls of bit line contacts 132, bit lines 134, and bit line capping layer 136. As an example, bit line contacts 132 may include polysilicon, and bit lines 134 may include a metallic material. As an example, bit line capping layer 136 may include an insulating material such as silicon nitride or silicon oxide nitride. As an example, bit line spacers 138 may have a single-layer or multi-layer structure comprising an insulating material such as silicon oxide, silicon oxide nitride, or silicon nitride. In some embodiments, bit line spacers 138 may also include air spaces (not shown). Optionally, a bit line interlayer (not shown) may be disposed between bit line contact 132 and bit line 134. As an example, if a bit line interlayer is present, it may comprise a metal silicide such as tungsten silicide or a metal nitride such as tungsten nitride.

[0038] although Figure 2 An example is shown in which the bit line contact 132 has a bottom surface at a level equal to the top surface of the substrate 110. However, in some embodiments, a recess (not shown) may be formed in the substrate 110, extending from the top surface of the substrate 110 to a certain depth. The bit line contact 132 may extend into this recess such that the bottom surface of the bit line contact 132 may be at a level lower than the top surface of the substrate 110.

[0039] The first insulating layer 142 and the second insulating layer 144 may be arranged sequentially on the substrate 110 in the order stated herein. In some embodiments, the bit line structure 130 may be arranged on the first source / drain region 114A and may extend through the first insulating layer 142 and the second insulating layer 144.

[0040] Capacitor contact 150 may be disposed on the second source / drain region 114B. The outer sidewalls of capacitor contact 150 may be surrounded by a first insulating layer 142 and a second insulating layer 144. In some embodiments, capacitor contact 150 may include a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) stacked sequentially on substrate 110 in the order stated herein, and may include barrier layers (not shown) on the side and bottom surfaces of the upper contact pattern. In some embodiments, the lower contact pattern may include polysilicon, and the upper contact pattern may include a metallic material. The barrier layer may include a conductive metal nitride.

[0041] The third insulating layer 146 can be disposed on the second insulating layer 144, and the landing pad 152 can be arranged to pass through the third insulating layer 146 and connect to the capacitor contact 150. For example... Figure 2 As shown, the landing pad 152 may overlap perpendicularly with the capacitor contact 150 and may have a width larger than that of the capacitor contact 150. Thus, in some embodiments, the landing pad 152 may completely overlap with the capacitor contact 150. In some embodiments, the landing pad 152 may include at least one selected from the group consisting of metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and tungsten (W) and conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN). In some examples, the landing pad 152 may include titanium nitride (TiN).

[0042] An etch stop layer 162 may be formed on the landing pad 152 and the third insulating layer 146. The etch stop layer 162 may include an opening 162H that exposes the top surface of the landing pad 152.

[0043] The capacitor structure CS1 can be disposed on the etch stop layer 162. The capacitor structure CS1 may include: a bottom electrode 170 electrically connected to the capacitor contact 150 such that a landing pad 152 is therebetween; a dielectric layer 180 covering a portion of the sidewall and a portion of the top surface of the bottom electrode 170; and a top electrode 185 on the dielectric layer 180.

[0044] The bottom electrode 170 can be disposed on the landing pad 152, and the bottom of the bottom electrode 170 can be disposed in the opening 162H of the etch stop layer 162. The width of the bottom of the bottom electrode 170 can be smaller than the width of the landing pad 152, so that the entire bottom surface of the bottom electrode 170 can contact the landing pad 152.

[0045] For example, such as Figure 2 As shown, the bottom electrode 170 can have a columnar or pillar-shaped form extending in the vertical direction (Z direction). For example... Figure 1 As shown, although the bottom electrode 170 may have a circular horizontal cross-section, this disclosure is not limited thereto. In some embodiments, the horizontal cross-section of the bottom electrode 170 may have various polygonal and rounded polygonal shapes, such as ellipse, quadrilateral, rounded quadrilateral, rhombus, trapezoid, etc.

[0046] like Figure 1 As shown, the bottom electrode 170 and capacitor contact 150 can be repeatedly arranged in a first direction (X direction) and a second direction (Y direction). Furthermore, although not in... Figure 1As shown, however, the landing pads 152 can be arranged in a matrix to be separated from each other in the first direction (X direction) and the second direction (Y direction) while overlapping each other with the bottom electrode 170 respectively and perpendicularly.

[0047] In some implementations and with Figure 1 As shown, capacitor contacts 150 can be repeatedly arranged in a first direction (X direction) and a second direction (Y direction), and bottom electrodes 170 can be arranged in a hexagonal, such as honeycomb structure. In such an embodiment, landing pads 152 can overlap perpendicularly and completely with bottom electrodes 170 while also overlapping perpendicularly with a portion of capacitor contacts 150.

[0048] The bottom electrode 170 may include a substrate electrode layer 172. The substrate electrode layer 172 may include at least one material selected from the group consisting of metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and tungsten (W); conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN); and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), and strontium ruthenium oxide (SrRuO3). In some embodiments, the substrate electrode layer 172 may include niobium nitride.

[0049] In some embodiments, the substrate electrode layer 172 may not include voids or seams. In other words, the substrate electrode layer 172 may be free of voids or seams. In some embodiments, the presence of voids and seams in the substrate electrode layer 172 can be reduced. For example, the substrate electrode layer 172 can be referenced... Figure 16 The manufacturing process described is used to form it. For example, the base electrode layer 172 can be formed by filling the opening 210H of the mold structure 210 in a bottom-up filling manner using the top surface of the landing pad 152 as a seed layer. When the base electrode layer 172 is formed in a bottom-up filling manner, the base electrode layer 172 may not include voids or seams.

[0050] The first support 192 and the second support 194 can be arranged separately on the sidewall of the bottom electrode 170. In other words, the first support 192 and the second support 194 can be spaced apart from each other in the Z direction, such as... Figure 2 As shown. The bottom electrode 170 may include a first sidewall 172S1 and a second sidewall 172S2, the first sidewall 172S1 being surrounded by a first support 192 and a second support 194. For example, as Figure 3As shown, the first sidewall 172S1 of the bottom electrode 170 can contact the sidewall 192S of the first support 192. The first sidewall 172S1 and the second sidewall 172S2 can be coplanar and aligned with each other.

[0051] The first support 192 and the second support 194 are arranged between the first bottom electrode 170 and the adjacent second bottom electrode 170, and can be used to prevent the bottom electrode 170 from being removed during the process of removing the mold structure 210 (see...). Figure 17 The first support 192 and the second support 194 may be silicon nitride, silicon oxide nitride, silicon boron nitride (SiBN), or silicon carbon nitride (SiCN).

[0052] The second support 194 may have a top surface at the same level as the top surface of the bottom electrode 170, and the first support 192 may be arranged at a lower level than the second support 194 relative to the top surface of the substrate 110. Although Figure 2 A first support 192 and a second support 194 are shown formed on the sidewall of the bottom electrode 170, but the number of each of the first support 192 and the second support 194 can vary. For example, in some embodiments, a plurality of first supports 192 may be formed and arranged apart from each other in the vertical direction with substantially equal spacing.

[0053] A dielectric layer 180 may be disposed on the sidewalls and top surface of the bottom electrode 170. In some embodiments, the dielectric layer 180 may be disposed on the second sidewall 172S2 of the bottom electrode 170. The dielectric layer 180 may extend from the sidewalls of the bottom electrode 170 to the top and bottom surfaces of the first and second supports 192 and 194, and may also be disposed on the etch stop layer 162. The dielectric layer 180 may have approximately [missing information - likely a specific shape or dimension] in a direction perpendicular to the top surface of the bottom electrode 170. to approximately The thickness, however, is not limited thereto.

[0054] In some embodiments, the dielectric layer 180 may include at least one selected from the group consisting of zirconium oxide, hafnium oxide, titanium oxide, niobium oxide, tantalum oxide, yttrium oxide, strontium titanium oxide, barium strontium titanium oxide, scandium oxide, and lanthanide oxides. In some examples, the dielectric layer 180 may include hafnium oxide having a predominantly tetragonal crystal phase. In other examples, the dielectric layer 180 may have a stacked structure of a first dielectric layer and a second dielectric layer, and at least one of the first dielectric layer and the second dielectric layer may include hafnium oxide having a predominantly tetragonal crystal phase.

[0055] The top electrode 185 may be disposed on the dielectric layer 180 and may cover or substantially cover the bottom electrode 170. The top electrode 185 may include at least one selected from the group consisting of metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and tungsten (W), conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN), and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), and strontium ruthenium oxide (SrRuO3).

[0056] In some embodiments, the top electrode 185 may comprise a single material layer or a stacked structure comprising multiple material layers. In one example, the top electrode 185 may comprise a single layer of titanium nitride (TiN) or niobium nitride (NbN). In another example, the top electrode 185 may comprise a stacked structure comprising a first top electrode layer comprising titanium nitride (TiN) and a second top electrode layer comprising niobium nitride (NbN).

[0057] Optionally, an interface layer (not shown) may be further formed between the dielectric layer 180 and the top electrode 185. The interface layer may include at least one selected from the group consisting of metal oxides such as titanium oxide, tantalum oxide, niobium oxide, molybdenum oxide, and iridium oxide, and metal nitrides such as titanium nitride (TiON), tantalum nitride (TaON), niobium nitride (NbON), and molybdenum nitride (MoON).

[0058] In an example embodiment, the base electrode layer 172 may include niobium nitride, and the dielectric layer 180 in contact with the base electrode layer 172 may include hafnium oxide having a tetragonal crystal phase. For example, when the base electrode layer 172 comprising niobium nitride contacts the dielectric layer 180, the dielectric layer 180 may have a predominantly tetragonal crystal phase rather than a monoclinic crystal phase during the process of forming the dielectric layer 180. Alternatively, in a heat treatment process performed after the process of forming the dielectric layer 180, the dielectric layer 180 may crystallize to have a predominantly tetragonal crystal phase rather than a monoclinic crystal phase. In this case, the dielectric layer 180 may exhibit crystal peaks originating from hafnium oxide having a tetragonal crystal phase in X-ray diffraction analysis. Hafnium oxide having a tetragonal crystal phase may have a larger dielectric constant than hafnium oxide having a monoclinic crystal phase, and therefore the capacitor structure CS1 may have a relatively large capacitance.

[0059] Typically, as the aspect ratio of the bottom electrode 170 increases, voids or seams may form during the process of filling the opening 210H with a conductive layer to form the bottom electrode 170, and in this case, the electrical characteristics or reliability of the capacitor structure may deteriorate. However, according to at least the above-described exemplary embodiments, the opening 210H can be filled with a conductive layer using a bottom-up filling method using the landing pad 152 as a seed layer, and since the bottom-up filling method can prevent or reduce the formation of voids or seams within the bottom electrode 170, the capacitor structure CS1 can include a dielectric layer 180 for the capacitor having a relatively high dielectric constant, and simultaneously include a bottom electrode 170 without voids or seams or with a reduced number of voids and seams.

[0060] Figure 4 This is a cross-sectional view showing an integrated circuit device 100A according to some embodiments. Figure 5 yes Figure 4 A magnified view of region CX2. Figure 4 and Figure 5 In, with Figures 1 to 3 The same reference numerals denote the same parts.

[0061] Reference Figure 4 and Figure 5 The bottom electrode 170A may include a base electrode layer 172A and a conductive capping layer 174A.

[0062] The bottom of the base electrode layer 172A may be formed in the opening 162H of the etch stop layer 162, and the base electrode layer 172A may have a columnar or pillar-like shape extending in the vertical direction (Z direction). The base electrode layer 172A may include at least one selected from the group consisting of metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and tungsten (W), conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN), and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), and strontium ruthenium oxide (SrRuO3). In some embodiments, the base electrode layer 172A may include titanium nitride.

[0063] The conductive capping layer 174A can be disposed on the sidewalls and top surface of the substrate electrode layer 172A. The conductive capping layer 174A can be disposed between the substrate electrode layer 172A and the dielectric layer 180, so the substrate electrode layer 172A does not need to directly contact the dielectric layer 180.

[0064] In some embodiments, the conductive capping layer 174A may include at least one selected from the group consisting of metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and tungsten (W); conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN); and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), and strontium ruthenium oxide (SrRuO3). In some embodiments, the conductive capping layer 174A may include niobium nitride.

[0065] The substrate electrode layer 172A may include a first sidewall 172AS1 and a second sidewall 172AS2. The first sidewall 172AS1 of the substrate electrode layer 172A may be surrounded by a first support 192, and the second sidewall 172AS2 of the substrate electrode layer 172A may be surrounded by a conductive capping layer 174A. The first sidewall 172AS1 and the second sidewall 172AS2 may be coplanar and aligned with each other. The conductive capping layer 174A may have approximately [missing information - likely a specific shape or shape] in a direction perpendicular to the sidewalls of the substrate electrode layer 172A. to approximately The first thickness T11A is specified, however, this disclosure is not limited thereto. For example, the conductive capping layer 174A can be formed on the top surface of the substrate electrode layer 172A by a selective deposition method, thus the conductive capping layer 174A can be formed on the second sidewall 172AS2, except for the first sidewall 172AS1 surrounded by the first support 192 and the second support 194. Furthermore, the conductive capping layer 174A may not be formed on the etch stop layer 162 and on the top and bottom surfaces of the first support 192 and the second support 194.

[0066] In the example manufacturing process, according to the reference Figure 22According to the described manufacturing process, the conductive capping layer 174A can be formed on the sidewalls and top surface of the substrate electrode layer 172A (e.g., on the second sidewall 172AS2 and top surface of the substrate electrode layer 172A) by selective deposition. For example, the conductive capping layer 174A can be selectively formed on the surface of the substrate electrode layer 172A relative to the surface of the etch stop layer 162, the surface of the first support 192, and the surface of the second support 194. Therefore, the portion of the bottom electrode 170A that contacts the dielectric layer 180 can be the conductive capping layer 174A, and the dielectric layer 180 may not be in contact with the substrate electrode layer 172A. For example, since the dielectric layer 180 is arranged to contact the conductive capping layer 174A, the dielectric layer 180 can include hafnium oxide having a tetragonal phase. Hafnium oxide having a tetragonal phase can have a larger dielectric constant than hafnium oxide having a monoclinic phase, so the capacitor structure CS1A can have a relatively large capacitance.

[0067] Figure 6 This is a cross-sectional view showing an integrated circuit device 100B according to some embodiments. Figure 7 yes Figure 6 A magnified view of region CX3. Figure 6 and Figure 7 In, with Figures 1 to 5 The same reference numerals in the figures represent the same parts.

[0068] Reference Figure 6 and Figure 7 The bottom electrode 170B may include a base electrode layer 172B and a conductive capping layer 174B.

[0069] The base electrode layer 172B can be formed in the opening 162H of the etch stop layer 162. The conductive capping layer 174B can be disposed on the sidewalls and top surface of the base electrode layer 172B. The conductive capping layer 174B can be disposed between the base electrode layer 172B and the dielectric layer 180, so that the base electrode layer 172B does not directly contact the dielectric layer 180.

[0070] The first sidewall 172BS1 of the base electrode layer 172B may be surrounded by the first support 192, and the second sidewall 172BS2 of the base electrode layer 172B may be surrounded by the conductive capping layer 174B. The second sidewall 172BS2 may be recessed inward (in the direction toward the center of the base electrode layer 172B) relative to the first sidewall 172BS1. Furthermore, the second sidewall 172BS2 may be recessed inward relative to the sidewall 192S of the first support 192. The conductive capping layer 174B may have approximately [missing information] in a direction perpendicular to the sidewall of the base electrode layer 172B. to approximately The first thickness is T11B.

[0071] For example, when the dielectric layer 180 is arranged as a contact conductive capping layer 174B, the dielectric layer 180 may include hafnium oxide having a tetragonal crystal phase. For example, hafnium oxide having a tetragonal crystal phase may have a larger dielectric constant than hafnium oxide having a monoclinic crystal phase, so the capacitor structure CS1B may have a relatively large capacitance.

[0072] Figure 8 This is a cross-sectional view showing an integrated circuit device 100C according to some embodiments. Figure 9 yes Figure 8 A magnified view of region CX4. Figure 8 and Figure 9 In, with Figures 1 to 7 The same reference numerals in the figures represent the same parts.

[0073] Reference Figure 8 and Figure 9 The bottom electrode 170C may include a base electrode layer 172C, a first seed layer 176C1, and a second seed layer 176C2.

[0074] The base electrode layer 172C may have a columnar or pillar-shaped structure extending in the vertical direction (Z direction), and a first seed layer 176C1 may be disposed between the base electrode layer 172C and the landing pad 152. The first seed layer 176C1 may be formed on the inner wall of the opening 162H of the etch stop layer 162, and the top surface of the first seed layer 176C1 may contact the entire bottom surface of the base electrode layer 172C. A second seed layer 176C2 may be disposed between the first support 192 and the base electrode layer 172C, and between the second support 194 and the base electrode layer 172C.

[0075] The substrate electrode layer 172C may include at least one selected from the group consisting of metals such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), and tungsten (W), conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), and tungsten nitride (WN), and conductive metal oxides such as iridium oxide (IrO2), ruthenium oxide (RuO2), and strontium ruthenium oxide (SrRuO3). In some embodiments, the substrate electrode layer 172C may include niobium nitride. In some embodiments, each of the first seed layer 176C1 and the second seed layer 176C2 may include titanium nitride.

[0076] like Figure 9As shown, the substrate electrode layer 172C may include a first sidewall 172CS1 and a second sidewall 172CS2. The first sidewall 172CS1 may be surrounded by a second seed layer 176C2 and may not contact the sidewall 192S of the first support 192. The second sidewall 172CS2 of the substrate electrode layer 172C may contact the dielectric layer 180. In some embodiments, the first sidewall 172CS1 and the second sidewall 172CS2 may be coplanar and aligned with each other. In some embodiments, the second sidewall 172CS2 may be... Figure 9 The difference shown can be recessed inward relative to the first sidewall 172CS1 (in the direction toward the center of the base electrode layer 172C).

[0077] The second seed layer 176C2 can have approximately [a certain shape] in a direction perpendicular to the sidewall of the base electrode layer 172C. to approximately The second thickness T12C, but not limited to it.

[0078] In the example manufacturing process, the initial seed layer is 176CL (see...). Figure 27 An opening 210H can be formed in the mold structure 210, and then a base electrode layer 172C can be formed on the initial seed layer 176CL by a bottom-up filling method. Next, in the process of removing the mold structure 210, the sidewalls of the base electrode layer 172C can be exposed by removing the initial seed layer 176CL exposed by the first mold opening 212OP and the second mold opening 214OP. Then, a dielectric layer 180 can be formed on the sidewalls of the base electrode layer 172C. In these processes, the portions of the initial seed layer 176CL arranged between each of the first support 192 and the second support 194 and the base electrode layer 172C can be retained without removal.

[0079] According to some embodiments, the portion of the bottom electrode 170C surrounded by the first support 192 and the second support 194 may include a second seed layer 176C2, and the portion of the bottom electrode 170C surrounded by the dielectric layer 180 may correspond to the sidewalls and top surface of the base electrode layer 172C. Therefore, the dielectric layer 180 may include hafnium oxide having a tetragonal crystal phase. Hafnium oxide having a tetragonal crystal phase can have a larger dielectric constant than hafnium oxide having a monoclinic crystal phase, thus the capacitor structure CS1C can have a relatively large capacitance.

[0080] Furthermore, according to the example embodiment, the substrate electrode layer 172C can be formed in the opening 210H by a bottom-up filling method using an initial seed layer 176CL as a seed layer, and the bottom-up filling method can prevent or reduce the generation of voids or seams in the substrate electrode layer 172C.

[0081] Figure 10 This is a cross-sectional view showing an integrated circuit device 100D according to an example embodiment. Figure 11 yes Figure 10 A magnified view of region CX5. Figure 10 and Figure 11 In, with Figures 1 to 9 The same reference numerals in the figures represent the same parts.

[0082] Reference Figure 10 and Figure 11 The bottom electrode 170D may include a first base electrode layer 172D1, a second base electrode layer 172D2, a first seed layer 176D1, and a second seed layer 176D2.

[0083] The first base electrode layer 172D1 may have a cylindrical shape extending in the vertical direction (Z direction). The bottom of the first base electrode layer 172D1 may be disposed in the opening 162H of the etch stop layer 162, and the bottom surface of the first base electrode layer 172D1 may be disposed on the landing pad 152. The top surface of the first base electrode layer 172D1 may be at a level substantially equal to the level of the bottom surface of the first support 192.

[0084] The first seed layer 176D1 can be disposed on the first base electrode layer 172D1 and surrounded by the first support 192. The first seed layer 176D1 can cover the entire top surface of the first base electrode layer 172D1 and can have approximately [missing information] in a direction perpendicular to the top surface of the substrate 110. to approximately The first thickness is T12D.

[0085] The second base electrode layer 172D2 may have a columnar shape extending in the vertical direction (Z direction) on the first seed layer 176D1. The upper sidewall of the second base electrode layer 172D2 may be surrounded by the second seed layer 176D2. The first seed layer 176D1 may be disposed between the second base electrode layer 172D2 and the first support 192, and the second seed layer 176D2 may be disposed between the second base electrode layer 172D2 and the second support 194.

[0086] like Figure 11As shown, the second base electrode layer 172D2 may include a first sidewall 172DS1 and a second sidewall 172DS2, and the first base electrode layer 172D1 may include a third sidewall 172DS3. The first sidewall 172DS1 may be surrounded by a first seed layer 176D1 and may not contact the sidewall 192S of the first support 192. The second sidewall 172DS2 and the third sidewall 172DS3 may be surrounded by a dielectric layer 180 and may contact the dielectric layer 180. In some embodiments, the first sidewall 172DS1 and the second sidewall 172DS2 may be coplanar and aligned with each other. The third sidewall 172DS3 may be coplanar with the sidewall 192S of the first support 192. The first sidewall 172DS1 and the second sidewall 172DS2 may be recessed inward (in the direction toward the center of the second base electrode layer 172D2) relative to the third sidewall 172DS3. Furthermore, the first sidewall 172DS1 and the second sidewall 172DS2 may be recessed inward (in the direction toward the center of the second base electrode layer 172D2) relative to the sidewall 192S of the first support 192.

[0087] In some embodiments, each of the first base electrode layer 172D1 and the second base electrode layer 172D2 may include niobium nitride, and each of the first seed layer 176D1 and the second seed layer 176D2 may include titanium nitride. The portion of the bottom electrode 170D surrounded by the dielectric layer 180 may correspond to the sidewalls of the first base electrode layer 172D1 and the sidewalls and top surface of the second base electrode layer 172D2. Therefore, the dielectric layer 180 may include hafnium oxide having a tetragonal phase, and the capacitor structure CS1D may have a relatively large capacitance.

[0088] Furthermore, according to some embodiments, the first base electrode layer 172D1 and the second base electrode layer 172D2 can be achieved by using landing pad 152 and initial seed layer 176DL (see...). Figure 35 The seed crystal layers are formed in the opening 210H as a bottom-up filling method, and this bottom-up filling method can prevent or reduce the generation of voids or seams in the first base electrode layer 172D1 and the second base electrode layer 172D2.

[0089] Figures 12 to 19 This illustrates the manufacturing process according to some embodiments. Figures 1 to 3 A cross-sectional view of the sequential process of the method for the integrated circuit device 100 shown.

[0090] Reference Figure 12 Device isolation trenches 112T can be formed in the substrate 110, and device isolation films 112 can be formed in the device isolation trenches 112T. The active region AC can be defined in the substrate 110 by the device isolation films 112.

[0091] Next, a first mask (not shown) can be formed on the substrate 110, and gate trenches 120T can be formed in the substrate 110 by using the first mask as an etching mask. The gate trenches 120T can have a line shape that extends parallel to each other and intersects the active region AC.

[0092] Next, a gate insulating layer 122 can be formed on the inner wall of the gate trench 120T. A gate conductive layer (not shown) can be formed on the gate insulating layer 122 to fill the gate trench 120T, and then the upper part of the gate conductive layer is removed to a certain height by an etch-back process to form the gate electrode 124.

[0093] Next, an insulating material can be formed to fill the remaining portion of the gate trench 120T, and then the insulating material is planarized to expose the top surface of the substrate 110, thereby forming a gate capping layer 126 on the inner wall of the gate trench 120T. Next, the first mask can be removed.

[0094] Next, the first source / drain region 114A and the second source / drain region 114B can be formed by implanting impurity ions into the substrate 110 on both sides of the gate structure 120. Alternatively, after forming the device isolation film 112 and before forming the gate trench 120T and the gate structure 120, the first source / drain region 114A and the second source / drain region 114B can be formed in the upper part of the active region AC by implanting impurity ions into the substrate 110.

[0095] Reference Figure 13 A bit line structure 130 and a first insulating layer 142 and a second insulating layer 144 surrounding the bit line structure 130 can be formed on the substrate 110. For example, the first insulating layer 142 can be formed first, and an opening (not shown) can be formed in the first insulating layer 142 to expose the top surface of the first source / drain region 114A. A bit line contact 132 can be formed in the first insulating layer 142 to fill the opening in the first insulating layer 142.

[0096] Next, a conductive layer (not shown) and an insulating layer (not shown) can be sequentially formed on the first insulating layer 142 in the order stated herein, and a bit line capping layer 136 and a bit line 134 can be formed by patterning the insulating layer and the conductive layer. The bit line capping layer 136 and the bit line 134 can be formed in the Y direction parallel to the top surface of the substrate 110 (see [link to documentation]). Figure 1 Extending on. Next, bit line spacers 138 can be formed on the sidewalls of bit line contact 132, bit line 134, and bit line cover layer 136.

[0097] The second insulating layer 144 may be formed on the first insulating layer 142 to at least cover the sidewalls of the bit line structure 130.

[0098] Next, openings (not shown) can be formed in the first insulating layer 142 and the second insulating layer 144 to expose the top surface of the second source / drain region 114B, and capacitor contacts 150 can be formed in these openings in the first insulating layer 142 and the second insulating layer 144. In some embodiments, capacitor contacts 150 can be formed by sequentially forming a lower contact pattern (not shown), a metal silicide layer (not shown), a barrier layer (not shown), and an upper contact pattern (not shown) in these openings in the first insulating layer 142 and the second insulating layer 144 in the order stated herein.

[0099] Next, a third insulating layer 146 may be formed on the capacitor contact 150 and the second insulating layer 144. An opening (not shown) may be formed in the third insulating layer 146 to expose the top surface of the capacitor contact 150, and a landing pad 152 may be formed in the opening of the third insulating layer 146.

[0100] Reference Figure 14 An etch stop layer 162 and a mold structure 210 may be sequentially formed on the landing pad 152 and the third insulating layer 146 in the order stated herein. The mold structure 210 may include a first mold layer 212, a first support 192, a second mold layer 214, and a second support 194 sequentially formed on the etch stop layer 162 in the order stated herein. In some embodiments, multiple first mold layers 212 and multiple first supports 192 may be arranged alternately. In some embodiments, an etch stop layer (not shown) may be further formed between or on the second support 194 and the second mold layer 214.

[0101] In some embodiments, the first mold layer 212 and the etch stop layer 162 may each comprise a material that is etch-selective relative to each other. For example, when the first mold layer 212 comprises silicon oxide, the etch stop layer 162 may comprise silicon nitride, silicon oxide nitride, or silicon carbon nitride (SiCN). Furthermore, each of the first mold layer 212 and the second mold layer 214 may comprise a material that is etch-selective relative to each of the first support 192 and the second support 194, and vice versa. For example, when each of the first mold layer 212 and the second mold layer 214 comprises silicon oxide, each of the first support 192 and the second support 194 may comprise silicon nitride, silicon oxide nitride, silicon boron nitride (SiBN), or silicon carbon nitride (SiCN).

[0102] Reference Figure 15A mask layer (not shown) can be formed on the second support 194, and an opening 210H can be formed in the mold structure 210 using this mask layer. Here, the etch stop layer 162 can be partially removed, and an opening 162H can be formed in the etch stop layer 162 to communicate with the opening 210H. The top surface of the landing pad 152 can be exposed through the openings 210H and 162H.

[0103] Reference Figure 16 A base electrode layer 172 can be formed on the landing pad 152 and the mold structure 210 to fill the openings 162H and 210H.

[0104] For example, the process for forming the substrate electrode layer 172 may include chemical vapor deposition (CVD), metal-organic CVD (MOCVD), atomic layer deposition (ALD), or metal-organic ALD (MOALD).

[0105] For example, the process of forming the substrate electrode layer 172 may include an ALD process performed in a bottom-up fill manner using the exposed top surface of the landing pad 152 as a seed layer and niobium halide (such as niobium pentafluoride (NbF5) or niobium pentachloride (NbCl5)) as a precursor source. In other embodiments, the process of forming the substrate electrode layer 172 may include an ALD process performed in a bottom-up fill manner using the exposed top surface of the landing pad 152 as a seed layer and a metal-organic precursor including niobium as a precursor source. For example, the metal-organic precursor may include tris(diethylamino)(tert-butylimide)niobium (TBTDEN), (tert-butylimide)bis(dimethylamino)niobium (TBTDMN), (tert-butylimide)bis(ethylmethylamino)niobium (TBTEMN), or bis(cyclopentadienyl)niobium(IV) dichloride, however, this disclosure is not limited thereto.

[0106] In some embodiments, the process of depositing the substrate electrode layer 172 can be performed by repeatedly forming a material layer in cycles, and the material layer forming cycle can include supplying a first precursor source including niobium, removing excess of the first precursor source, supplying a second precursor source including nitrogen, and removing excess of the second precursor source.

[0107] In some embodiments, when niobium halide is used as the first precursor source, the material layer can be grown as a continuous layer on the surface of the landing pad 152, and the material layer can be grown as islands or dots on the first mold layer 212, the second mold layer 214, the first support 192, and the second support 194. Therefore, the formation rate of the material layer on the surface of the landing pad 152 exposed at the bottom of the opening 210H can be significantly higher than the formation rate of the material layer on the surfaces of the first mold layer 212, the second mold layer 214, the first support 192, and the second support 194 exposed at the sidewalls of the opening 210H, and the base electrode layer 172 can be formed from the bottom of the opening 210H at a relatively high rate in the vertical direction. Due to the selective deposition characteristics of the base electrode layer 172 at the bottom of the opening 210H, the base electrode layer 172 can fill the opening 210H in a bottom-up filling manner, thus preventing or reducing voids or seams within the base electrode layer 172, even if the aspect ratio of the opening 210H is high.

[0108] Reference Figure 17 The first mold opening 212OP and the second mold opening 214OP can be formed by removing the first mold layer 212 and the second mold layer 214, respectively. In the process of removing the first mold layer 212 and the second mold layer 214, the first support 192 and the second support 194 may not be removed, and the base electrode layer 172 may be connected to and supported by the first support 192 and the second support 194.

[0109] Reference Figure 18 The dielectric layer 180 can be conformally formed on the exposed surfaces of the substrate electrode layer 172, the first support 192, and the second support 194.

[0110] In an example embodiment, the dielectric layer 180 can be formed by CVD, MOCVD, ALD, MOALD, or similar processes. In an example embodiment, the dielectric layer 180 can be formed using hafnium oxide, and the portion of the dielectric layer 180 in contact with the substrate electrode layer 172 can primarily have a tetragonal crystal phase.

[0111] Reference Figure 19 A top electrode 185 can be formed on the dielectric layer 180.

[0112] Optionally, after forming the top electrode 185, an annealing process can be further performed.

[0113] According to the above method for manufacturing an integrated circuit device 100 according to some embodiments, due to the selective deposition characteristics of the substrate electrode layer 172 on the bottom of the opening 210H, the substrate electrode layer 172 can fill the opening 210H in a bottom-up filling manner, thereby preventing or reducing the generation of voids or seams in the substrate electrode layer 172, even if the aspect ratio of the opening 210H is high.

[0114] Figures 20 to 23 This illustrates the manufacturing process according to an example embodiment. Figure 4 and Figure 5 A cross-sectional view of the sequential process of the method for the integrated circuit device 100A shown.

[0115] First, it can be done by executing the reference. Figures 12 to 15 The process described is used to form a mold structure 210 including an opening 210H.

[0116] Reference Figure 20 An initial base electrode layer 172AL can be formed on the mold structure 210. In some examples, the initial base electrode layer 172AL can be formed using titanium nitride. The initial base electrode layer 172AL can be formed on the inner wall of the opening 210H and on the top surface of the mold structure 210.

[0117] Reference Figure 21 The initial substrate electrode layer 172AL can be removed (see...). Figure 20 The upper part of the second support 194 exposes the top surface of the second support 194, thereby forming the base electrode layer 172A.

[0118] Next, the first mold opening 212OP and the second mold opening 214OP can be formed by removing the first mold layer 212 and the second mold layer 214. In the process of removing the first mold layer 212 and the second mold layer 214, the first support 192 and the second support 194 may not be removed, and the base electrode layer 172A may be connected to and supported by the first support 192 and the second support 194.

[0119] Reference Figure 22 The conductive capping layer 174A can be formed on the exposed sidewalls and top surface of the substrate electrode layer 172A.

[0120] For example, the process of forming the conductive capping layer 174A may include an ALD process performed in a bottom-up filling manner by using the exposed surface of the substrate electrode layer 172A as a seed layer and using niobium halide (such as niobium pentafluoride (NbF5) or niobium pentachloride (NbCl5)) or a metal-organic precursor including niobium as a precursor source.

[0121] In some embodiments, when niobium halide is used as a precursor source, the conductive capping layer 174A can be grown as a continuous layer on the surface of the substrate electrode layer 172A, while the conductive capping layer 174A can be grown as islands or dots on the etch stop layer 162 and the first support 192 and the second support 194. Therefore, although the conductive capping layer 174A is formed on the sidewalls and top surface of the substrate electrode layer 172A with a first thickness T11A (see...), Figure 5 The conductive capping layer 174A may be formed almost not or minimally on the etch stop layer 162 and the first support 192 and the second support 194, or even if it is slightly formed, it may be removed in a cleaning process or a selective cleaning process.

[0122] Therefore, a conductive capping layer 174A can be selectively deposited on the substrate electrode layer 172A.

[0123] Reference Figure 23 The dielectric layer 180 can be formed on the exposed surfaces of the conductive capping layer 174A, the first support 192, and the second support 194, and the top electrode 185 can be formed to cover the dielectric layer 180. The dielectric layer 180 can be formed using hafnium oxide, and the portion of the dielectric layer 180 in contact with the conductive capping layer 174A can primarily have a tetragonal phase.

[0124] According to the above method for manufacturing integrated circuit device 100A according to some embodiments, conductive capping layer 174A can be formed on the exposed surface of substrate electrode layer 172A by selective deposition, and dielectric layer 180 can be formed on conductive capping layer 174A such that dielectric layer 180 has a tetragonal crystal phase with a relatively high dielectric constant.

[0125] Figures 24 to 26 This illustrates the manufacturing process according to some embodiments. Figure 6 and Figure 7 A cross-sectional view of the sequential process of the method for the integrated circuit device 100B shown.

[0126] First, by executing the reference Figure 20 The process described involves forming a substrate electrode layer 172B on the inner wall of the opening 210H of the mold structure 210.

[0127] Reference Figure 24 The first module layer 212 can be removed (see Figure 20 ) and second module layer 214 (see Figure 20 Furthermore, the first mold opening 212OP and the second mold opening 214OP can be formed in the space from which the first mold layer 212 and the second mold layer 214 are removed.

[0128] Next, the sidewalls of the substrate electrode layer 172B exposed by the first mold opening 212OP and the second mold opening 214OP can be further removed by a certain thickness. In some embodiments, the process of removing the sidewalls of the substrate electrode layer 172B can be performed in the same process as the process of removing the first mold layer 212 and the second mold layer 214, or it can be performed separately after the process of removing the first mold layer 212 and the second mold layer 214.

[0129] Reference Figure 25 A conductive capping layer 174B can be formed on the sidewalls and top surface of the substrate electrode layer 172B. The process for forming the conductive capping layer 174B can be similar to that already referenced. Figure 22 The process for forming the conductive capping layer 174A is described.

[0130] Reference Figure 26 The dielectric layer 180 can be formed on the conductive cover layer 174B, the first support 192 and the second support 194, and the top electrode 185 can be formed to cover the dielectric layer 180.

[0131] Figures 27 to 33 This illustrates the manufacturing process according to an example embodiment. Figure 8 and Figure 9 A cross-sectional view of the sequential process of the method for the integrated circuit device 100C shown.

[0132] Reference Figure 27 An initial seed layer 176CL can be formed on the inner wall of the opening 210H of the mold structure 210 and on the top surface of the mold structure 210. For example, the initial seed layer 176CL can be formed by CVD, MOCVD, ALD, MOALD, etc., using titanium nitride, tungsten, etc. to approximately The second thickness T12C (see Figure 9 ).

[0133] Reference Figure 28An initial substrate electrode layer 172CL can be formed on an initial seed layer 176CL to fill the internal space of the opening 210H. The process for forming the initial substrate electrode layer 172CL can include an ALD process performed in a bottom-up filling manner using the exposed top surface of the initial seed layer 176CL as a seed layer and niobium halide (such as niobium pentafluoride (NbF5) or niobium pentachloride (NbCl5)) as a precursor source. In other embodiments, the process for forming the initial substrate electrode layer 172CL can include an ALD process performed in a bottom-up filling manner using the exposed top surface of the initial seed layer 176CL as a seed layer and a metal-organic precursor including niobium as a precursor source. The process for forming the initial substrate electrode layer 172CL can be similar to that already referred to... Figure 16 The process for forming the substrate electrode layer 172 is described.

[0134] Due to the selective deposition characteristics of the initial base electrode layer 172CL on the bottom of the opening 210H, the initial base electrode layer 172CL can fill the opening 210H in a bottom-up filling manner, thus preventing or reducing the generation of voids or seams in the initial base electrode layer 172CL, even if the aspect ratio of the opening 210H is high.

[0135] Reference Figure 29 The upper portions of both the initial substrate electrode layer 172CL and the initial seed layer 176CL can be removed, exposing the top surface of the second support 194. Here, the substrate electrode layer 172C in one opening 210H can be separated from the substrate electrode layer 172C in the adjacent opening 210H.

[0136] Reference Figure 30 The first mold opening 212OP and the second mold opening 214OP can be formed by removing the first mold layer 212 and the second mold layer 214, respectively. In the process of removing the first mold layer 212 and the second mold layer 214, the first support 192 and the second support 194 can be left unremoved, and the sidewalls of the initial seed layer 176CL can be exposed through the first mold opening 212OP and the second mold opening 214OP.

[0137] Reference Figure 31 This can remove the portion of the initial seed layer 176CL exposed by the first mold opening 212OP and the second mold opening 214OP.

[0138] In some embodiments, the process of removing the exposed portion of the initial seed layer 176CL may include a wet etching process. After the process of removing the exposed portion of the initial seed layer 176CL, the sidewalls of the base electrode layer 172C may be exposed. In the process of removing the exposed portion of the initial seed layer 176CL, the portions of the initial seed layer 176CL disposed in the opening 162H of the etch stop layer 162 and between the bottom of the base electrode layer 172C and the landing pad 152 may not be removed. The portion of the initial seed layer 176CL thus retained may be referred to as the first seed layer 176C1. Furthermore, in the process of removing the exposed portion of the initial seed layer 176CL, the portions of the initial seed layer 176CL disposed between the sidewall of the base electrode layer 172C and the first support 192 and the portions of the initial seed layer 176CL disposed between the sidewall of the base electrode layer 172C and the second support 194 may not be removed. The portion of the initial seed layer 176CL retained between the sidewall of the substrate electrode layer 172C and the first support 192, and between the sidewall of the substrate electrode layer 172C and the second support 194, can be referred to as the second seed layer 176C2.

[0139] Reference Figure 32 The dielectric layer 180 can be formed on the substrate electrode layer 172C, the first support 192, and the second support 194. The dielectric layer 180 can be formed using hafnium oxide, and the portion of the dielectric layer 180 that contacts the top surface and sidewalls of the substrate electrode layer 172C can primarily have a tetragonal phase.

[0140] Reference Figure 33 A top electrode 185 can be formed on the dielectric layer 180.

[0141] Figures 34 to 41 This illustrates the manufacturing process according to some embodiments. Figure 10 and Figure 11 A cross-sectional view of the sequential process of the method for the integrated circuit device 100D shown.

[0142] Reference Figure 34 The first base electrode layer 172D1 can be formed on the landing pad 152 and the mold structure 210 to fill the lower part of the opening 210H and the opening 162H.

[0143] For example, the process of forming the first substrate electrode layer 172D1 may include an ALD process performed in a bottom-up fill manner using the exposed top surface of the landing pad 152 as a seed layer and niobium halide (such as niobium pentafluoride (NbF5) or niobium pentachloride (NbCl5)) as a precursor source. In other embodiments, the process of forming the first substrate electrode layer 172D1 may include an ALD process performed in a bottom-up fill manner using the exposed top surface of the landing pad 152 as a seed layer and a metal-organic precursor including niobium as a precursor source. The process of forming the first substrate electrode layer 172D1 may be similar to that already referred to Figure 16 The process for forming the substrate electrode layer 172 is described.

[0144] For example, the first base electrode layer 172D1 may have a top surface that is at the same level as the bottom surface of the first support 192. However, this disclosure is not limited thereto, and the top surface of the first base electrode layer 172D1 may be at a level higher or lower than the bottom surface of the first support 192.

[0145] Reference Figure 35 An initial seed layer 176DL can be formed on the top surface of the first substrate electrode layer 172D1, the top surface of the mold structure 210, and the sidewall of the opening 210H. The initial seed layer 176DL can be formed using titanium nitride, tungsten, or other materials via CVD, MOCVD, ALD, or MOALD processes. to approximately The second thickness T12D (see) Figure 11 ).

[0146] Reference Figure 36 An initial second base electrode layer 172DL can be formed on the initial seed layer 176DL to fill the remainder of the opening 210H. The process for forming the initial second base electrode layer 172DL can include an ALD process performed in a bottom-up filling manner using the exposed top surface of the initial seed layer 176DL as a seed layer. The process for forming the initial second base electrode layer 172DL can be similar to that already referenced... Figure 16 The process for forming the substrate electrode layer 172 is described.

[0147] Reference Figure 37 The upper part of the initial second base electrode layer 172DL and the upper part of the initial seed layer 176DL can be removed, so that the top surface of the second support 194 is exposed, thereby separating the second base electrode layer 172D2 in one opening 210H from the second base electrode layer 172D2 in the adjacent opening 210H.

[0148] Reference Figure 38The first mold opening 212OP and the second mold opening 214OP can be formed by removing the first mold layer 212 and the second mold layer 214. In the process of removing the first mold layer 212 and the second mold layer 214, the sidewalls of the first base electrode layer 172D1 and the sidewalls of the initial seed layer 176DL can be exposed through the first mold opening 212OP and the second mold opening 214OP.

[0149] Reference Figure 39 This can remove the portion of the initial seed layer 176DL exposed by the first mold opening 212OP and the second mold opening 214OP.

[0150] In some embodiments, the process of removing the exposed portion of the initial seed layer 176DL may include a wet etching process using an etchant that has etch selectivity relative to the initial seed layer 176DL. The sidewalls of the second base electrode layer 172D2 may be exposed due to the process of removing the exposed portion of the initial seed layer 176DL, and in this removal process, the sidewalls of the first base electrode layer 172D1 may be removed little or no.

[0151] In the process of removing the exposed portion of the initial seed layer 176DL, the portion of the initial seed layer 176DL disposed between the top surface of the first base electrode layer 172D1 and the bottom surface of the second base electrode layer 172D2 and surrounded by the first support 192 may not be removed. This retained portion of the initial seed layer 176DL may be referred to as the first seed layer 176D1. Furthermore, in the process of removing the exposed portion of the initial seed layer 176DL, the portion of the initial seed layer 176DL disposed between the sidewall of the second base electrode layer 172D2 and the second support 194 may not be removed; this retained portion of the initial seed layer 176DL may be referred to as the second seed layer 176D2.

[0152] Reference Figure 40 The dielectric layer 180 can be formed on the first base electrode layer 172D1, the second base electrode layer 172D2, the first support 192, and the second support 194. The dielectric layer 180 can be formed using hafnium oxide, and the portions of the dielectric layer 180 that contact the sidewalls of the first base electrode layer 172D1 and the top surface and sidewalls of the second base electrode layer 172D2 can primarily have a tetragonal phase.

[0153] Reference Figure 41 A top electrode 185 can be formed on the dielectric layer 180.

[0154] Some examples of embodiments of the inventive concept have been described herein with reference to the accompanying drawings. Although embodiments have been described using specific terminology, it should be understood that these terms are for illustrative purposes only and are not to be construed in any way as limiting this disclosure or the inventive concept disclosed herein. It will be understood that various modifications, alterations, variations, and equivalent embodiments can be made by those skilled in the art without departing from the scope of the inventive concept. Therefore, the scope of the inventive concept should be defined by the appended claims and their equivalents.

[0155] This application claims the benefit of Korean Patent Application No. 10-2019-0068805, filed on June 11, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device including a capacitor structure, wherein the capacitor structure comprises: Bottom electrode on the substrate; Support on the sidewall of the bottom electrode; Dielectric layer on the bottom electrode and the support; as well as The top electrode is on the dielectric layer and covers the bottom electrode, and The bottom electrode includes: A base electrode layer extends on the substrate in a first direction perpendicular to the top surface of the substrate; as well as A conductive capping layer comprising niobium nitride is located between the sidewalls of the substrate electrode layer and the dielectric layer, and between the top surface of the substrate electrode layer and the dielectric layer. The portion of the dielectric layer in contact with the conductive capping layer comprises hafnium oxide having a tetragonal crystal phase. The base electrode layer includes a first sidewall and a second sidewall, wherein the first sidewall is surrounded by the support, and wherein the second sidewall is surrounded by the conductive cover layer.

2. The integrated circuit device according to claim 1, wherein the substrate electrode layer comprises titanium nitride or tungsten.

3. The integrated circuit device according to claim 1, wherein the substrate electrode layer is isolated from the dielectric layer.

4. The integrated circuit device of claim 1, wherein the first sidewall and the second sidewall of the substrate electrode layer are coplanar.

5. The integrated circuit device of claim 1, wherein the second sidewall of the substrate electrode layer is recessed inward relative to the first sidewall of the substrate electrode layer.

6. An integrated circuit device including a capacitor structure, wherein the capacitor structure comprises: Bottom electrode on the substrate; Support on the sidewall of the bottom electrode; Dielectric layer on the bottom electrode and the support; as well as The top electrode is located on the dielectric layer and covers the bottom electrode. The bottom electrode includes: The substrate electrode layer comprises niobium nitride and extends in a first direction perpendicular to the top surface of the substrate; A first seed layer, surrounded by the support and in contact with at least a portion of the base electrode layer; and The second seed layer is located between the bottom surface of the base electrode layer and the substrate, and Each of the first seed layer and the second seed layer comprises titanium nitride or tungsten. The substrate electrode layer is formed in a bottom-up filling manner. The substrate electrode layer includes a first sidewall and a second sidewall, wherein the first sidewall of the substrate electrode layer is surrounded by the first seed crystal layer, and wherein the second sidewall of the substrate electrode layer is surrounded by the dielectric layer.

7. The integrated circuit device of claim 6, wherein the first sidewall and the second sidewall of the substrate electrode layer are coplanar.

8. The integrated circuit device of claim 6, wherein the substrate electrode layer is isolated from the support, and wherein the first seed layer is located between the first sidewall of the substrate electrode layer and the sidewall of the support.

9. The integrated circuit device of claim 6, wherein the portion of the dielectric layer in contact with the substrate electrode layer comprises hafnium oxide having a tetragonal crystal phase.

10. An integrated circuit device including a capacitor structure, wherein the capacitor structure comprises: Bottom electrode on the substrate; Support on the sidewall of the bottom electrode; Dielectric layer on the bottom electrode and the support; as well as The top electrode is located on the dielectric layer and covers the bottom electrode. The bottom electrode includes: The base electrode layer includes niobium nitride and extends in a first direction perpendicular to the top surface of the substrate. The base electrode layer includes a first base electrode layer and a second base electrode layer that is above the first base electrode layer and spaced apart from the first base electrode layer in the first direction. A first seed layer is located between the first base electrode layer and the second base electrode layer and is surrounded by the support; and The second seed layer is located on the sidewall of the second base electrode layer and is surrounded by the support. Each of the first seed layer and the second seed layer comprises titanium nitride or tungsten. The first base electrode layer and the second base electrode layer are formed in a bottom-up filling manner.

11. The integrated circuit device of claim 10, wherein the second substrate electrode layer includes a first sidewall and a second sidewall, wherein the first substrate electrode layer includes a third sidewall, wherein the first sidewall of the second substrate electrode layer is surrounded by the first seed layer, and wherein the second sidewall of the second substrate electrode layer and the third sidewall of the first substrate electrode layer are surrounded by the dielectric layer.

12. The integrated circuit device of claim 11, wherein the first sidewall and the second sidewall of the second base electrode layer are coplanar, and wherein the first sidewall of the second base electrode layer is recessed inward relative to the third sidewall of the first base electrode layer.

13. The integrated circuit device of claim 11, wherein the first base electrode layer and the second base electrode layer are isolated from the support, and wherein the first seed layer is located between the first sidewall of the second base electrode layer and the sidewall of the support.

14. The integrated circuit device of claim 11, wherein the third sidewall of the first substrate electrode layer is coplanar with the sidewall of the support.

15. The integrated circuit device of claim 10, wherein the portion of the dielectric layer in contact with the substrate electrode layer comprises hafnium oxide having a tetragonal crystal phase.

16. An integrated circuit device including a capacitor structure, wherein the capacitor structure comprises: Landing pads on the substrate; The bottom electrode includes a bottom surface that contacts the top surface of the landing pad; Support on the sidewall of the bottom electrode; Dielectric layer on the bottom electrode and the support; as well as A top electrode covering the bottom electrode on the dielectric layer. The bottom electrode includes: The substrate electrode layer comprises niobium nitride and extends in a first direction perpendicular to the top surface of the substrate; A first seed layer, surrounded by the support and in contact with at least a portion of the base electrode layer; and The second seed layer is located between the bottom surface of the base electrode layer and the substrate, and The portion of the dielectric layer in contact with the substrate electrode layer comprises hafnium oxide having a tetragonal crystal phase. The substrate electrode layer is formed in a bottom-up filling manner. The substrate electrode layer includes a first sidewall and a second sidewall, wherein the first sidewall of the substrate electrode layer is surrounded by the first seed crystal layer, and wherein the second sidewall of the substrate electrode layer is surrounded by the dielectric layer.

17. The integrated circuit device of claim 16, wherein the substrate electrode layer has no seams or gaps.

18. The integrated circuit device of claim 16, wherein the first sidewall and the second sidewall of the substrate electrode layer are coplanar.

19. A method for manufacturing an integrated circuit device, the method comprising: A landing pad is formed on the substrate; A mold structure is formed on the landing pad, the mold structure including an opening that exposes the top surface of the landing pad; as well as A base electrode layer is formed within the opening, the base electrode layer comprising niobium nitride. The formation of the substrate electrode layer includes selectively depositing the substrate electrode layer on the top surface of the landing pad relative to the sidewalls of the mold structure. The selective deposition of the substrate electrode layer includes: A first base electrode layer is formed to fill the lower part of the opening; A seed layer is formed on the top surface of the first base electrode layer and on the upper inner wall of the opening; and A second base electrode layer is formed on the seed crystal layer to fill the remainder of the opening.

20. The method of claim 19, wherein in the selective deposition of the substrate electrode layer, the growth rate of the material layer on the top surface of the landing pad is greater than the growth rate of the material layer on the sidewall of the mold structure exposed by the opening.

21. The method of claim 19, wherein selectively depositing the substrate electrode layer comprises: The top surface of the landing pad is used as a seed layer to selectively deposit the substrate electrode layer.

22. The method of claim 19, further comprising: Remove the module structure; as well as A dielectric layer is formed on the sidewall of the substrate electrode layer.

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