Memory device having a common source line including different material layers

Abstract

A memory device includes: a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate; a plurality of channel regions passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate; a source region arranged on the substrate and extending in a first direction and including impurities; and a common source line extending in a direction perpendicular to the upper surface of the substrate, connected to the source region, and including multiple layers containing different materials.

Description

[0001] This application is a divisional application of the Chinese patent application "Memory device with a common source line comprising different material layers" with an application date of March 28, 2017 and application number 201710195350.1.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 325,565, filed on April 21, 2016, and Korean Patent Application No. 10-2016-0064692, filed on May 26, 2016, which are hereby incorporated by reference in their entirety. Technical Field

[0004] The inventive concept relates generally to semiconductors, and more particularly to memory devices. Background Art

[0005] Electronic devices are becoming smaller and smaller, but they need to process a large amount of data. Therefore, the integration of semiconductor memory devices used in these electronic products should be increased. In order to provide semiconductor memory devices with increased integration, some memory devices with vertical transistor structures have been proposed to replace memory devices with planar transistor structures. Summary of the invention

[0006] Some embodiments of the present invention provide a memory device comprising: a gate structure comprising a plurality of gate electrode layers stacked on an upper surface of a substrate; a plurality of channel regions passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate; a source region arranged on the substrate extending in a first direction and comprising impurities; and a common source line extending in a direction perpendicular to the upper surface of the substrate, connected to the source region, and comprising a plurality of layers containing different materials.

[0007] Another embodiment of the present inventive concept provides a memory device, comprising: a substrate; a source region, arranged on the substrate to extend along a first direction and including n-type impurities; a plurality of channel regions, extending in a direction perpendicular to an upper surface of the substrate; a plurality of gate electrode layers, stacked on the upper surface of the substrate and arranged to be adjacent to at least a portion of the plurality of channel regions; and a common source line, arranged on the source region to extend along the first direction and including a first layer and a second layer, wherein the first layer includes polysilicon having a higher concentration of n-type impurities than the source region, and the second layer is arranged on an upper surface of the first layer and includes at least one of a metal, a metal silicide, and a metal compound.

[0008] Other embodiments of the present inventive concept provide a vertical memory device comprising: a source region on a substrate, the source region extending in a first direction and comprising impurities; and a common source line extending in a direction perpendicular to an upper surface of the substrate, connected to the source region, and comprising multiple layers comprising different materials. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a schematic block diagram of a memory device according to some embodiments of the inventive concept.

[0011] Figure 2 is a circuit diagram illustrating a memory cell array of a memory device according to some embodiments of the inventive concept.

[0012] Figure 3 is a plan view schematically illustrating a portion of a memory device according to some embodiments of the inventive concept.

[0013] Figure 4 It shows that according to Figure 3 A perspective view of a portion of a storage device of some embodiments is shown.

[0014] Figure 5 It shows that according to Figure 3 A cross-sectional view of a portion of a memory device of some embodiments is shown.

[0015] Figure 6 It shows Figure 5 An enlarged view of region A1 of the memory device is shown.

[0016] Figure 7 It shows Figure 5 An enlarged view of region A2 of the memory device is shown.

[0017] FIG. 8A to FIG. 8D is a perspective view illustrating a portion of a memory device according to some embodiments of the inventive concept.

[0018] Fig. 9 It shows that according to Fig. 8A A cross-sectional view of a portion of a memory device of some embodiments is shown.

[0019] Fig.10 It shows Fig. 9 An enlarged view of region B1 of the memory device is shown.

[0020] Fig.11is a perspective view illustrating a portion of a memory device according to some embodiments of the inventive concept.

[0021] Fig.12 It shows that according to Fig.11 A cross-sectional view of a portion of a memory device of some embodiments is shown.

[0022] Figures 13 to 36 It shows the manufacturing Figures 3 to 7 Schematic diagram of the process steps for the memory device described in FIG.

[0023] Figures 37 to 46 is a diagram showing the manufacture of Fig.10 2. A view of the process steps of the memory device shown in FIG.

[0024] Fig.47 is a block diagram illustrating an electronic device including a memory device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0025] Hereinafter, the concept of the present invention will be described by explaining exemplary embodiments of the present invention in detail with reference to the accompanying drawings. Like reference numerals in the drawings represent like elements, and thus their detailed description will be omitted for the sake of brevity.

[0026] First reference Figure 1 , a memory device 1 according to some embodiments of the inventive concept may include a memory cell array 2, a row decoder 3, and a core logic circuit 6. The core logic circuit 6 may include a read / write circuit 4 and a control circuit 5.

[0027] The memory cell array 2 may include a plurality of memory cells arranged in a plurality of rows and columns. The plurality of memory cells included in the memory cell array 2 may be connected to the row decoder 3 via word lines WL, common source lines CSL, string selection lines SSL, ground selection lines GSL, etc., and may be connected to the read / write circuit 4 via bit lines BL. In some example embodiments, a plurality of memory cells arranged in the same row may be connected to the same word line WL, and a plurality of memory cells arranged in the same column may be connected to the same bit line BL.

[0028] The plurality of memory cells included in the memory cell array 2 may be divided into a plurality of memory blocks. Each memory block may include a plurality of word lines WL, a plurality of string selection lines SSL, a plurality of ground selection lines GSL, a plurality of bit lines BL, and at least one common source line CSL.

[0029] The row decoder 3 may receive address information ADDR from an external source and decode the received address information ADDR to determine voltages provided to at least a portion of word lines WL, common source lines CSL, string selection lines SSL, and ground selection lines GSL connected to the memory cell array 2 .

[0030] The read / write circuit 4 can select at least a portion of the bit lines BL connected to the memory cell array 2 according to a command received from the control circuit 5. The read / write circuit 4 can read data stored in the memory cells connected to the selected portion of the bit lines BL, or can write data to the memory cells connected to the selected portion of the bit lines BL. The read / write circuit 4 may include circuits such as a page buffer circuit, an input / output buffer circuit, a data latch circuit, etc., in order to perform the above operations.

[0031] The control circuit 5 can control the operation of the row decoder 3 and the read / write circuit 4 in response to the control signal CTRL sent from the external source. When reading the data stored in the memory cell array 2, the control circuit 5 can control the operation of the row decoder 3 to provide a voltage for a read operation to the word line WL storing the data to be read. When the voltage for a read operation is provided to a specific word line WL, the control circuit 5 can control the read / write circuit 4 to read the data stored in the memory cell connected to the word line WL provided with the voltage for the read operation.

[0032] Meanwhile, when writing data to the memory cell array 2, the control circuit 5 may control the operation of the row decoder 3 to supply a voltage for a write operation to the word line WL to which the data is to be written. When the voltage for a write operation is supplied to a specific word line WL, the control circuit 5 may control the read / write circuit 4 to write data to a memory cell connected to the word line WL supplied with the voltage for a write operation.

[0033] Figure 2 is an equivalent circuit diagram illustrating a memory cell array of a memory device according to some example embodiments of the inventive concept. The memory device according to example embodiments of the inventive concept may be a vertical NAND flash memory device.

[0034] refer to Figure 2 , the memory cell array may include a plurality of memory cell strings S, each memory cell string S includes n memory cells MC1 to MCn connected in series with each other, and a ground selection transistor GST and a string selection transistor SST, the ground selection transistor GST and the string selection transistor SST are respectively connected to both ends of the memory cells MC1 to MCn connected in series. The n memory cells MC1 to MCn connected in series with each other may be respectively connected to n word lines WL1 to WLn, and the word lines WL1 to WLn are used to select at least a portion of the memory cells MC1 to MCn. At the same time, a dummy cell may be further provided between the ground selection transistor GST and the first memory cell MC1 and between the string selection transistor SST and the nth memory cell MCn.

[0035] The gate terminal of the ground selection transistor GST may be connected to the ground selection line GSL, and the source terminal of the ground selection transistor GST may be connected to the common source line CSL. At the same time, the gate terminal of the string selection transistor SST may be connected to the string selection line SSL, and the source terminal of the string selection transistor SST may be connected to the drain terminal of the memory cell MCn. Figure 2 In the embodiment, one ground selection transistor GST and one string selection transistor SST are connected to n memory cells MC1 to MCn connected in series with each other. However, without departing from the scope of the present invention, a plurality of ground selection transistors GST or a plurality of string selection transistors SST may be connected to n memory cells MC1 to MCn.

[0036] The drain terminal of the string selection transistor SST may be connected to a plurality of bit lines BL1 to BLm. When a signal is applied to the gate terminal of the string selection transistor SST via the string selection line SSL, the signal applied via the bit lines BL1 to BLm may be transmitted to the n memory cells MC1 to MCn connected in series with each other, so that a data read or data write operation may be performed. In addition, an erase operation may be performed by applying a predetermined erase voltage via a well region formed in the substrate, in which the data written in the n memory cells MC1 to MCn is removed.

[0037] Reference again Figure 2 , a memory device according to some example embodiments of the inventive concepts may include at least one dummy string DS. The dummy string DS may be a string including a dummy channel that is not connected to the bit lines BL1 to BLm.

[0038] Reference now Figure 3 , a plan view showing a portion of a memory device according to some embodiments of the inventive concept will be discussed. Figure 3 As shown, the memory device 100 according to some example embodiments of the inventive concept may include a plurality of channel regions CH, a plurality of dummy channel regions DCH, a common source line 150, and an isolation insulating layer 155. Figure 3 In the example embodiment shown in , a plurality of channel regions CH and a plurality of dummy channel regions DCH may be arranged on an XY plane to be isolated from each other. A plurality of gate electrode layers and a plurality of insulating layers may be alternately stacked along a z-axis direction to provide a gate structure, and a plurality of channel regions CH and a plurality of dummy channel regions DCH may extend along the z-axis direction through the gate structure.

[0039] The gate structure may be divided into a plurality of parts by side spacers 109 disposed on side surfaces of the common source line 150. The side spacers 109 may reduce or prevent the possibility of direct contact between the common source line 150 and the gate structure, and may include an insulating material such as silicon oxide.

[0040] In the memory device 100 according to the example embodiment of the inventive concept, the common source line 150 may include multiple layers formed of different materials. In some example embodiments, the common source line 150 may include a first layer 151 disposed at a lower portion along the z-axis direction and a second layer 152 disposed on the first layer 151. The first layer 151 and the second layer 152 may be formed of different materials. In addition, the first layer 151 and the second layer 152 may be formed of one of a metal, a metal silicide, a metal compound, and polysilicon doped with impurities.

[0041] In some example embodiments, the first layer 151 may be formed of polysilicon doped with n-type impurities. Typically, the common source line 150 is formed of a metal such as tungsten (W). However, according to example embodiments of the inventive concept, a portion of the common source line 150, i.e., the first layer 151, may be formed by depositing polysilicon doped with n-type impurities. Because the first layer 151 is formed of polysilicon, the gate structure may not melt or bend, and a peeling phenomenon occurring in the common source line 150 may be suppressed. Therefore, the reliability of the memory device 100 may be improved.

[0042] Polysilicon doped with n-type impurities may have a relatively high resistance compared to metals such as tungsten (W). In order to compensate for the resistance component present in polysilicon, the second layer 152 may be formed on the first layer 151. The second layer 152 may include Ti / TiN used as a barrier layer and a metal such as tungsten (W).

[0043] The second layer 152 may extend in the first direction (x-axis direction) like the first layer 151. In some example embodiments, the second layer 152 may extend longer in the first direction than the first layer 151. Since the second layer 152 is disposed on the first layer 151, the resistance component of the first layer 151 may be compensated. In order to increase the effect of compensating the resistance by forming the second layer 152, the second layer 152 may be formed to be longer than the first layer 151 in the first direction.

[0044] Figure 4 It shows that according to Figure 3 A perspective view of a portion of a memory device of an example embodiment is shown. Figure 4 As shown, a memory device 100 according to an example embodiment of the inventive concept may include a substrate 101, a substrate 102 disposed with an upper surface (at Figure 4The substrate 101 includes a plurality of channel regions CH and a dummy channel region DCH that are perpendicular to the xy plane in the illustrated example embodiment, and a plurality of gate electrode layers 131 to 138 (collectively referred to as 130) disposed adjacent to the channel regions CH on the substrate 101. The plurality of gate electrode layers 130 may be alternately stacked with a plurality of insulating layers 141 to 149 (collectively referred to as 140) to provide a gate structure, and at least a portion of the gate electrode layers 130 (e.g., the gate electrode layers 138) may be divided into several portions by an isolation insulating layer 155.

[0045] The plurality of channel regions CH and the dummy channel region DCH may be arranged along a direction perpendicular to the upper surface of the substrate 101 ( Figure 4 The drain region 113 may include a channel layer 110, a filling insulating layer 115 filling an inner space of the channel layer 110, and a drain region 113 disposed on the channel layer 110. In some example embodiments, the channel layer 110 may have a columnar shape such as a cylindrical shape or a prism shape without including the filling insulating layer 115. In addition, each channel region CH may have an inclined side surface depending on its aspect ratio, so that the width of the channel region CH may decrease toward the substrate 101.

[0046] The plurality of channel regions CH and the dummy channel regions DCH may be arranged to be isolated from each other on the XY plane. The number and arrangement of the plurality of channel regions CH and the dummy channel regions DCH may be changed differently according to example embodiments. For example, the plurality of channel regions CH and the dummy channel regions DCH may be arranged to form a zigzag pattern along at least one direction. Figure 4 In the illustrated example embodiment, the plurality of channel regions CH may be symmetrically arranged with respect to the isolation insulating layer 155 therebetween, and the plurality of dummy channel regions DCH may pass through the isolation insulating layer 155. However, it should be understood that the inventive concept is not limited thereto.

[0047] The channel layer 110 may be electrically connected to the substrate 101 via the underlying epitaxial layer 111. The channel layer 110 may include a semiconductor material such as polycrystalline silicon or single crystal silicon. The semiconductor material may be doped with n-type or p-type impurities, or may not be doped with impurities. The epitaxial layer 111 may be a layer grown by a selective epitaxial growth (SEG) process. The epitaxial layer 111 may be formed to be recessed into the substrate 101 to a predetermined depth, such as Figure 4 shown.

[0048] The plurality of dummy channel regions DCH may have a structure similar to that of the channel region CH. In other words, the plurality of dummy channel regions DCH may include a drain region 113, a channel layer 110, and a filling insulating layer 115, and may selectively include an epitaxial layer 111. However, unlike the channel region CH, the plurality of dummy channel regions DCH may be electrically isolated from the bit lines on the gate structure. Therefore, a write operation, etc., cannot be performed in the memory cells MC1 to MCn provided by the dummy channel region DCH.

[0049] The plurality of gate electrode layers 130 may be alternately stacked with the plurality of insulating layers 140 along the z-axis direction. Each of the plurality of gate electrode layers 130 may be adjacent to at least one channel layer 110 and may be used as a gate electrode of the ground selection transistor GST, the plurality of memory cells MC1 to MCn, and the string selection transistor SST. In some example embodiments, a gate electrode layer for a dummy device may also be disposed between the ground selection transistor GST and the first memory cell MC1 and between the string selection transistor SST and the nth memory cell MCn. At the same time, in Figure 4 In the illustrated example embodiment, the total number of memory cells MC1 to MCn is n, where n is a sum of 2 a A defined number (here, a is a natural number).

[0050] The plurality of gate electrode layers 130 may extend to form word lines WL1 to WLn. In some example embodiments, the plurality of gate electrode layers 130 may extend along a first direction ( Figure 4 The gate electrode layers 130 and the gate electrode layers 140 are connected to each other in the pad region.

[0051] The plurality of gate electrode layers 130 may be formed of a conductive material such as polysilicon or a metal silicide material, and the plurality of insulating layers 140 may be formed of an insulating material such as silicon oxide or silicon nitride. For example, the metal silicide material may be a silicide of a metal selected from Co, Ni, Hf, Pt, W, and Ti, or a combination thereof. In some example embodiments, the plurality of gate electrode layers 130 may include a metal such as tungsten (W). In addition, although not shown, the plurality of gate electrode layers 130 may further include a barrier layer for reducing diffusion, and the barrier layer may include at least one of tungsten nitride (WN), tantalum nitride (TaN), and titanium nitride (TiN).

[0052] The plurality of gate electrode layers 130 may provide memory cells MC1 to MCn, a ground selection transistor GST, and a string selection transistor SST together with the channel layer 110 and the gate insulating layer 160. The gate insulating layer 160 may include a tunneling layer 162, a charge storage layer 164, and a blocking layer 166 sequentially stacked between the channel layer 110 and the plurality of gate electrode layers 130. The structure of the gate insulating layer 160 is not limited to the above three layers.

[0053] The blocking layer 166 may include a high-k dielectric material. In these embodiments, the high-k dielectric material may refer to a dielectric material having a higher dielectric constant than silicon oxide. The tunneling layer 162 may allow charges to move to the charge storage layer 164 according to the FN tunneling mechanism. For example, the tunneling layer 162 may include silicon oxide. The charge storage layer 164 may be a charge trapping layer or a floating gate conductive layer. For example, the charge storage layer 164 may include a dielectric material, quantum dots, or nanocrystals. In these embodiments, the quantum dots or nanocrystals may be formed of microparticles of metal or semiconductor materials. This will be referred to later. Figure 7 The gate insulating layer 160 is described.

[0054] When a write operation is performed in the memory device 100, charges moving through the tunnel layer 162 may be trapped in the charge storage layer 164. The memory cells MC1 to MCn including the charge storage layer 164 having the charges trapped may have a threshold voltage different from that of the memory cells MC1 to MCn not having the charges trapped. During a read operation, the memory device 100 may detect whether charges are trapped based on the threshold voltage of each of the memory cells MC1 to MCn, and determine whether data is written.

[0055] A source region 103 may be formed in the substrate 101. The source region 103 may be formed by implanting n-type impurities into a portion of the substrate 101, and may be formed along a first direction ( Figure 4 A common source line 150 and a spacer 109 may be formed on the source region 103. The spacer 109 may be disposed on an outer surface of the common source line 150 and may divide the gate structure into a plurality of parts.

[0056] The common source line 150 may be connected to the source region 103 below the plurality of gate electrode layers 130, and may extend in the first direction like the source region 103. In addition, the common source line 150 may be formed perpendicular to the upper surface of the substrate 101. In an example embodiment of the inventive concept, the common source line 150 may include a first layer 151 and a second layer 152 formed of different materials.

[0057] In the memory device 100 according to the example embodiment of the inventive concept, the first layer 151 of the common source line 150 may be formed of polysilicon doped with n-type impurities. Since the first layer 151 disposed in the relatively lower portion of the common source line 150 is not formed of metal but of polysilicon, melting or warping of the gate structure that occurs when the common source line 150 is formed of only metal may be reduced, and the possibility of peeling of the common source line 150 may be reduced.

[0058] The common source line 150 may be formed by forming a spacer 109 and then sequentially depositing different materials between the spacer 109. The first layer 151 may be formed by depositing polysilicon including n-type impurities. Therefore, the concentration of the n-type impurities in the common source line 150 may be higher than that in the source region 103 formed by implanting the n-type impurities into a portion of the substrate 101.

[0059] The second layer 152 may be disposed on the upper surface of the first layer 151. The lower surface of the second layer 152 may be in direct contact with the upper surface of the first layer 151, and the second layer 152 may extend in the first direction like the first layer 151. In some example embodiments, the second layer 152 may extend longer than the first layer 151 in the first direction. Since the second layer 152 is disposed on the upper surface of the first layer 151, the influence of polysilicon having a higher resistance than metal may be compensated. The width (dimension in the y-axis direction) of the second layer 152 may be determined to be within a range that does not interfere with a stud connected to an adjacent channel region CH.

[0060] Figure 5 It shows that according to Figure 3 1 is a cross-sectional view of a portion of a memory device of an exemplary embodiment shown in FIG. Figure 5 and Figure 4 The memory device 100 is described together.

[0061] refer to Figure 5 , the memory device 100 according to example embodiments of the inventive concepts may include a cell region C and a peripheral circuit region P. The peripheral circuit region P is a region disposed around the cell region C, and a plurality of peripheral circuit devices 190 may be disposed therein.

[0062] The plurality of peripheral circuit devices 190 are circuit devices for transmitting signals required to write or erase data to or from the memory cells MC1 to MCn and to read the written data, and may include horizontal type transistors. Figure 5, the peripheral circuit device 190 may include an active region 191, a horizontal gate electrode 192, and a horizontal gate insulating layer 193. A horizontal spacer 194 may be disposed on a sidewall of the horizontal gate electrode 192, and the active region 191 may be formed adjacent to a device isolation layer 195. The horizontal gate electrode 192 and the active region 191 may be connected to at least one peripheral contact 175.

[0063] The peripheral contact 175 may pass through the interlayer insulating layer 170 and extend in a direction perpendicular to the upper surface of the substrate 101. The interlayer insulating layer 170 through which the peripheral contact 175 passes may be formed on the cell region C and the peripheral circuit region P. In addition, the interlayer insulating layer 170 may include an insulating material such as silicon oxide or silicon nitride. The peripheral contact 175 may be connected to a contact metal layer 183 on the interlayer insulating layer 170. The contact metal layer 183 may be connected to an interconnection line M0 formed in the upper insulating layers 171 and 172 via an interconnection contact C0.

[0064] The contact metal layer 183 may be disposed on the same level as the second layer 152 belonging to the common source line 150. In other words, the upper surface of the contact metal layer 183 may be coplanar with the upper surface of the second layer 152, and the contact metal layer 183 and the second layer 152 may have substantially the same thickness. This is because the contact metal layer 183 and the second layer 152 are formed in the same manufacturing process, and will be discussed further below.

[0065] As described above, the cell region C may include a plurality of channel regions CH, a plurality of gate electrode layers 130, a source region 103, a common source line 150 disposed on the source region 103, and an isolation insulating layer 155. The isolation insulating layer 155 may divide the gate electrode layer 138 serving as a gate electrode of the string selection transistor SST into a plurality of portions.

[0066] Each of the plurality of channel regions CH may include a channel layer 110, a filling insulating layer 115, an epitaxial layer 111, and a drain region 113, and the drain region 113 may be connected to at least one of the plurality of interconnection lines M0 via a nail column S. Each of the plurality of interconnection lines M0 formed in the cell region C may be electrically connected to a bit line disposed thereon. Each of the plurality of interconnection lines M0 may be connected to a different bit line. Meanwhile, unlike the plurality of channel regions CH, the plurality of dummy channel regions DCH may not be connected to the nail column S.

[0067] The interlayer insulating layer 170 may be disposed on the gate structure including the plurality of gate electrode layers 130 and the plurality of insulating layers 140. As described above, the interlayer insulating layer 170 may be disposed on the cell region C and the peripheral circuit region P. Upper insulating layers 171 and 172 may be disposed on the interlayer insulating layer 170. The upper insulating layers 171 and 172 may include a first upper insulating layer 171 and a second upper insulating layer 172. The thickness of the first upper insulating layer 171 may be substantially the same as the thickness of the contact metal layer 183 and the second layer 152 of the common source line 150. This may be a characteristic due to a manufacturing process.

[0068] Figure 6 It shows Figure 5 is an enlarged view of region A1 of the memory device shown in FIG. Figure 7 It shows Figure 5 First, refer to the enlarged view of the area A2 of the memory device shown in FIG. Figure 6 , Figure 5 The region A1 may include a first upper insulating layer 171 and a second upper insulating layer 172, an interlayer insulating layer 170, a spacer 109, and a common source line 150. The common source line 150 may include a first layer 151 and a second layer 152. The spacer 109 included in the common source line 150 may be disposed on an outer surface of the first layer 151 to reduce the possibility that the common source line 150 contacts the gate electrode layer 130. The first layer 151 may be formed of polysilicon doped with n-type impurities, and the concentration of the n-type impurities in the first layer 151 may be higher than the concentration of the n-type impurities in the source region 103.

[0069] Compared to a common source line formed only of metal, the common source line 150 according to the example embodiments of the inventive concept may have a relatively high resistance value. Therefore, according to the example embodiments of the inventive concept, the common source line 150 may include a second layer 152 formed of a material different from the first layer 151, so as to reduce the influence of the high resistance value of the common source line 150. The second layer 152 may be formed of a material having a higher conductivity than the first layer 151. The second layer 152 may extend in the first direction like the first layer 151, and may be longer than the first layer 151 in the first direction.

[0070] The second layer 152 of the common source line 150 may include a barrier layer 152a and a metal layer 152b. The barrier layer 152a may be formed of Ti, TiN, etc., and the metal layer 152b may be formed of tungsten (W). In some example embodiments, the second layer 152 may be formed by a damascene process.

[0071] Reference now Figure 7 , Figure 5The region A2 of the gate electrode layer 133 may include the gate electrode layer 133, the insulating layers 143 and 144, the gate insulating layer 160, and the filling insulating layer 115 and the channel layer 110 included in the channel region CH. The channel layer 110 may have a ring shape, and the filling insulating layer 115 may be disposed inside thereof. The gate insulating layer 160 may have a structure in which a tunneling layer 162, a charge storage layer 164, and a blocking layer 166 are sequentially stacked between the channel layer 110 and the gate electrode layer 133.

[0072] The relative thickness of each layer forming the gate insulating layer 160 is not limited to Figure 7 The thickness shown may be variously changed. In addition, the barrier layer 166 may have a shape surrounding the gate electrode layer 133, and the charge storage layer 164 and the tunneling layer 162 may be disposed on the outer peripheral surface of the channel layer 110. However, it should be understood that the embodiments of the inventive concept are not limited thereto.

[0073] The barrier layer 166 may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a high-k dielectric material. In these embodiments, the high-k dielectric material may be one of the following: aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 )、ZrO 2 ), zirconium oxide (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 ).exist Figure 7, the blocking layer 166 is shown as including a single layer, but may include a high-k dielectric layer and a low-k dielectric layer having different dielectric constants. In these embodiments, the low-k dielectric layer may be disposed in contact with the charge storage layer 164. The high-k dielectric layer may be formed of a material having a higher dielectric constant than the tunneling layer 162, and the low-k dielectric layer may be formed of a material having a lower dielectric constant than the high-k dielectric layer. Because the low-k dielectric layer is disposed on the side surface of the high-k dielectric layer, energy bands such as barrier height may be controlled, thereby improving the characteristics of the non-volatile memory device such as the erase characteristics.

[0074] The charge storage layer 164 may be a charge trapping layer or a floating gate conductive layer. When the charge storage layer 164 is a floating gate conductive layer, the charge storage layer 164 may be formed by depositing polysilicon using a low pressure chemical vapor deposition (LPCVD) method. When the charge storage layer 164 is a charge trapping layer, the charge storage layer 164 may include at least one of the following: silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), Hafnium Aluminum Oxide (HfAl x O y ), Hafnium Tantalum Oxide (HfTa x O y ), Hafnium Silicon Oxide (HfSi x O y ), aluminum nitride (Al x N y ) and aluminum gallium nitride (AlGa x N y ).

[0075] The tunneling layer 162 may include at least one of the following: silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), aluminum oxide (Al 2 O 3 ) and zirconium oxide (ZrO 2 ).

[0076] In the following, reference will be made to Figures 8A to 8D and Fig. 9A memory device 200 according to some example embodiments of the inventive concepts is described. Figures 8A to 8D is a perspective view illustrating a portion of a memory device according to an example embodiment of the inventive concept, and Fig. 9 It shows that according to Fig. 8A A cross-sectional view of a portion of a memory device of an example embodiment is shown.

[0077] refer to Fig. 8A and Fig. 9 , a memory device 200 according to an example embodiment of the inventive concept may include a substrate 201, a plurality of gate electrode layers 231 to 238 (collectively referred to as 230) and insulating layers 241 to 249 (collectively referred to as 240) alternately stacked on the substrate 201, and a plurality of channel regions CH and dummy channel regions DCH extending in a direction perpendicular to the substrate 201 through the plurality of gate electrode layers 230. Each of the plurality of channel regions CH may include a channel layer 210, a filling insulating layer 215, and a drain region 213. Unlike the memory device 100 described in the previous example embodiment, in Fig. 8A and Fig. 9 In the illustrated example embodiment, an epitaxial layer may not be formed in each channel region CH.

[0078] The gate insulating layer 260 may be disposed between the plurality of gate electrode layers 230 and the channel layer 210. The gate insulating layer 260 may include a tunneling layer 262, a charge storage layer 264, and a blocking layer 266 sequentially stacked between the channel layer 110 and the gate electrode layer 230. Fig. 8A and Fig. 9 In the illustrated example embodiment, the blocking layer 266 is illustrated as surrounding the gate electrode layer 230, and the charge storage layer 264 and the tunneling layer 262 are illustrated as surrounding the channel layer 210. However, it should be understood that embodiments of the inventive concept are not limited thereto.

[0079] The plurality of gate electrode layers 230 may be divided into a plurality of portions by a common source line 250 and a sidewall spacer 209 extending in a direction perpendicular to the substrate 201 (z-axis direction) and in a first direction (x-axis direction). The common source line 250 may include multiple layers 251, 252, and 253 formed of different materials. At least a portion of the multiple layers 251, 252, and 253 included in the common source line 250 may be formed of polysilicon including impurities of the same conductivity type as the source region 203. In some example embodiments, the first layer 251 of the common source line 250 and the source region 203 may include n-type impurities. In addition, the concentration of the n-type impurities in the first layer 251 may be higher than the concentration of the n-type impurities in the source region 203.

[0080] The height of the first layer 251 formed of polysilicon including n-type impurities along the z-axis direction may be smaller than the sidewall spacer 209 disposed on the side thereof. Fig. 8A and Fig. 9 , the second layer 252 and the third layer 253 may be disposed on the upper surface of the first layer 251, and the second layer 252 may be disposed between the spacers 209. The second layer 252 and the third layer 253 may be formed of a material different from that of the first layer 251, such as a metal or a metal silicide. The upper surface of the second layer 252 may be disposed on the same level as the upper surface of the interlayer insulating layer 270 and the upper surface of the spacer 209, and may be coplanar therewith.

[0081] The third layer 253 may be disposed on the second layer 252. The second layer 252 and the third layer 253 may extend in the first direction (x-axis direction) like the first layer 251. In some example embodiments, the second layer 252 and the third layer 253 may extend longer than the first layer 251 in the first direction. In addition, in some embodiments, the third layer 253 may extend longer than the second layer 252. Because the second layer 252 and the third layer 253 are formed longer than the first layer 251, a larger resistance component of the first layer 251 formed of polysilicon including n-type impurities may be compensated.

[0082] Each of the second layer 252 and the third layer 253 may include a multilayer formed of Ti, TiN, W, etc., and may be formed by a damascene process. A method of forming the second layer 252 and the third layer 253 will be further discussed herein.

[0083] refer to Fig. 9 , the memory device 200 may include a cell region C and a peripheral circuit region P. The cell region C may be a region where memory cells MC1 to MCn provided by a plurality of gate electrode layers 230, a gate insulating layer 260, a channel layer 210, etc. are disposed. Meanwhile, the peripheral circuit region P may be a region where a peripheral circuit device 290 configured to drive the memory device 200 is disposed. An interlayer insulating layer 270 formed on the cell region C and the peripheral circuit region P may be disposed on the peripheral circuit device 290 and the plurality of gate electrode layers 230.

[0084] The peripheral circuit device 290 may be connected to a peripheral contact 275 passing through the interlayer insulating layer 270, and the peripheral contact 275 may be connected to a contact metal layer 283. The contact metal layer 283 may be connected to an interconnection line M0 provided in the upper insulating layers 271 and 272 via an interconnection contact C0.

[0085] The contact metal layer 283 may have substantially the same thickness as the third layer 253 disposed on the second layer 252 of the common source line 250. Therefore, an upper surface of the contact metal layer 283 may be coplanar with an upper surface of the third layer 253. In addition, an upper surface of the first upper insulating layer 271 may be coplanar with an upper surface of the third layer 253. This is because the contact metal layer 283 and the third layer 253 are formed in the same process, and will be discussed further below.

[0086] Each of the plurality of channel regions CH may include a channel layer 210, a filling insulating layer 215, and a drain region 213, and the drain region 213 may be connected to at least one of the plurality of interconnection lines M0 via a nail column S. Each of the plurality of interconnection lines M0 formed in the cell region C may be electrically connected to a bit line formed thereon. Each of the plurality of interconnection lines M0 may be connected to a different bit line. Meanwhile, unlike the plurality of channel regions CH, the plurality of dummy channel regions DCH may not be connected to the nail column S.

[0087] refer to FIG. 8B to FIG. 8D , describes memory devices 200A, 200B, and 200C according to different example embodiments of the inventive concept. Figures 8B to 8D In the memory devices 200A, 200B, and 200C of the exemplary embodiment shown, the components related to the embodiment according to the present invention may be omitted for the sake of simplicity. Fig. 8A Description of similar or identical components in the memory device 200 of the illustrated example embodiment.

[0088] refer to Figure 8B , the memory device 200A may include a common source line including first to third layers 251A, 252A, and 253. At least one of the first to third layers 251A, 252A, and 253 may be formed of different materials. In some example embodiments, the first layer 251A may be formed of polysilicon doped with n-type impurities, and the second layer 252A and the third layer 253 may be formed of metal, metal silicide, or metal compound.

[0089] exist Figure 8B In the example embodiment shown, the second layer 252A may be Fig. 8A The second layer 252 in the illustrated example embodiment is thin, and may be thinner than the third layer 253. In other words, a lower surface of the second layer 252A may be disposed higher than an upper surface of the uppermost gate electrode layer 238 in the z-axis direction.

[0090] refer to Figure 8C , the common source line of the memory device 200B may include first to third layers 251B, 252B, and 253. Figure 8C In the example embodiment shown, the thickness of the second layer 252B may be greater than Fig. 8A and Figure 8B Thicknesses of the second layers 252 and 252A in the illustrated example embodiment. A lower surface of the second layer 252B may be disposed lower than a lower surface of the uppermost gate electrode layer 238 in the z-axis direction.

[0091] refer to Fig.8D , the common source line of the memory device 200C may include first to third layers 251C, 252C, and 253. Fig.8D In the example embodiment shown, the lower surface of the second layer 252C may be disposed in a middle region of the gate structure formed by the plurality of gate electrode layers 230 and the insulating layer 240. In other words, the second layer 252C may have a thickness greater than that of the gate electrode layer 230 and the insulating layer 240. FIG. 8A to FIG. 8C The second layer 252, 252A, 252B of the illustrated example embodiment has a large thickness. Therefore, the thickness of the first layer 251C formed of polysilicon including n-type impurities can be reduced, and the influence of the large resistance component of polysilicon can be effectively compensated.

[0092] Fig.10 It shows Fig. 9 FIG. 1 is an enlarged view of a region B1 of a memory device shown in FIG. Fig.10 As shown, Fig. 9 The region B1 may include a first upper insulating layer 271 and a second upper insulating layer 272, an interlayer insulating layer 270, a spacer 209, and first to third layers 251, 252, and 253 belonging to the common source line 250. The spacer 209 may be disposed on the outer side surfaces of the first layer 251 and the second layer 252 to reduce the possibility that the common source line 250 contacts the gate electrode layer 230. At least a portion of the first to third layers 251, 252, and 253 may be formed of polysilicon doped with n-type impurities, and the concentration of the n-type impurities in the polysilicon may be higher than the concentration of the n-type impurities in the source region 203.

[0093] Compared to a common source line formed of only metal, the common source line 250 according to the example embodiments of the inventive concept may have a relatively high resistance value. Therefore, according to the example embodiments of the inventive concept, the common source line 250 may include a second layer 252 and a third layer 253 including a metal on the first layer 251, so as to reduce the influence of the resistance of the polysilicon included in the first layer 251 of the common source line 250. Each of the second layer 252 and the third layer 253 may extend in the first direction like the first layer 251, and may be longer than the first layer 251 in the first direction.

[0094] Each of the second layer 252 and the third layer 253 may include multiple layers. In some example embodiments, the second layer 252 may include a barrier layer 252a and a metal layer 252b disposed on the barrier layer 252a. The third layer 253 may also include a barrier layer 253a and a metal layer 253b disposed on the barrier layer 253a. The barrier layers 252a and 253a may be formed of Ti / TiN, and the metal layers 252b and 253b may be formed of tungsten (W). The thickness of the second layer 252 and the third layer 253 may be variously changed.

[0095] Fig.11 A perspective view illustrating a portion of a memory device according to some example embodiments of the inventive concept, and Fig.12 It shows that according to Fig.11 FIG. 1 is a cross-sectional view of a portion of a memory device of an exemplary embodiment. Fig.11 and Fig.12 As shown, the memory device 300 according to some example embodiments of the inventive concept may have a cell-on-periphery (COP) structure in which the cell region C is disposed above the peripheral circuit region P. Meanwhile, in other embodiments of the inventive concept, the memory device 300 may be implemented to have a periphery-on-cell (POC) structure in which the peripheral circuit region P is disposed above the cell region C.

[0096] The memory device 300 may include a first substrate 301 and a second substrate 302. The first substrate 301 may be included in a cell region C, and the second substrate 302 may be included in a peripheral circuit region P. A plurality of peripheral circuit devices 390 and a second interlayer insulating layer 396 may be formed on the second substrate 302. The plurality of peripheral circuit devices 390 may include an active region 391, a horizontal gate electrode 392, a horizontal gate insulating layer 393, and a horizontal spacer 394. A device isolation layer 397 may be disposed between the plurality of peripheral circuit devices 390.

[0097] A plurality of peripheral circuit devices 390 may be connected to the peripheral interconnection line 395, and the peripheral interconnection line 395 may be embedded in the second interlayer insulating layer 396. The second interlayer insulating layer 396 may be formed of an insulating material such as silicon oxide or silicon nitride. The first substrate 301 may be disposed on the second interlayer insulating layer 396, and the first substrate 301 may have a different crystal structure from the second substrate 302.

[0098] The cell region C may include a plurality of gate electrode layers 331 to 338 (collectively referred to as 330) and insulating layers 341 to 349 (collectively referred to as 340) alternately stacked on the first substrate 301, and a plurality of channel regions CH and dummy channel regions DCH extending vertically to the upper surface of the first substrate 301. The structure of the plurality of channel regions CH may be similar to that of the memory device 100 according to the above-described example embodiments.

[0099] A source region 303 including n-type impurities may be formed on the first substrate 301, and a common source line 350 and a spacer 309 may be formed on the source region 303. The common source line 350 and the spacer 309 may extend along a first direction (x-axis direction), and the plurality of gate electrode layers 330 may be divided into a plurality of portions by the common source line 350 and the spacer 309.

[0100] The first layer 351 of the common source line 350 may be formed of polysilicon doped with n-type impurities instead of metal. In some example embodiments, the concentration of n-type impurities in the first layer 351 may be higher than the concentration of n-type impurities in the source region 303. In order to compensate for the disadvantage that the resistance value of polysilicon is higher than that of metal, the second layer 352 may be formed on the first layer 351. The second layer 352 may include metal and may extend in the first direction while being attached to the upper surface of the first layer 351. The second layer 352 may be longer than the first layer 351 in the first direction.

[0101] Figures 13 to 36 It shows the manufacturing Figures 3 to 7 First, refer to the process steps of the memory device shown in FIG. Fig.13 and 14 , Fig.14 is shown along Fig.13 1-1' line in FIG. 1. A cell region C and a peripheral circuit region P may be defined in the substrate 101, and a plurality of peripheral circuit devices 190 may be formed in the peripheral circuit region P. The peripheral circuit device 190 may include an active region 191 and a horizontal gate electrode 192, and a horizontal gate insulating layer 193 may be disposed between the horizontal gate electrode 192 and the substrate 101. A horizontal spacer 194 may be formed on a side surface of the horizontal gate electrode 192, and the active region 191 may be formed in a region outside the device isolation layer 195.

[0102] The substrate 101 may be a single crystal silicon substrate and may include at least one well region doped with first conductive type impurities. A plurality of peripheral circuit devices 190 may be formed on the well region, and the well region disposed below the cell region C may be a region doped with p-type impurities.

[0103] refer to Fig.15 and 16, a plurality of sacrificial layers 121 to 128 (collectively referred to as 120), a plurality of insulating layers 141 to 149 (collectively referred to as 140), and an interlayer insulating layer 170 may be formed on the substrate 101. The plurality of sacrificial layers 120 and the insulating layer 140 may be formed on the cell region C and the peripheral circuit region P, and then removed from the region outside the cell region C. The interlayer insulating layer 170 may be formed in the peripheral circuit region P and the cell region C, and the plurality of sacrificial layers 120 and the insulating layer 140 may be particularly formed in the cell region C.

[0104] The plurality of sacrificial layers 120 may include a material having a predetermined etching selectivity with respect to the plurality of insulating layers 140. In some example embodiments, when the plurality of insulating layers 140 are formed of silicon oxide, the plurality of sacrificial layers 120 may be formed of silicon nitride. Therefore, in a subsequent process, only the plurality of sacrificial layers 120 may be removed while the plurality of insulating layers 140 remain. In various example embodiments, the number and thickness of the plurality of sacrificial layers 120 and the insulating layers 140 may be variously changed. Fig.16 In the illustrated example embodiment, the plurality of sacrificial layers 120 and the insulating layer 140 may have substantially the same thickness. However, it should be understood that the inventive concept is not limited thereto. Portions of the sacrificial layer 120 or the insulating layer 140 may have different thicknesses.

[0105] The interlayer insulating layer 170 may include an insulating material such as silicon oxide, high density plasma (HDP) oxide, or tetraethoxysilane (TEOS) oxide. Depending on its manufacturing process, the interlayer insulating layer 170 may be formed in different process steps. In some example embodiments, the lower portion of the interlayer insulating layer 170 directly covering the plurality of peripheral circuit devices 190 may be formed of HDP oxide having excellent gap filling properties, while the upper portion of the interlayer insulating layer 170 may be formed of TEOS oxide having a high deposition rate.

[0106] refer to Fig.17 and 18 , an isolation insulating layer 155 may be formed on the upper surface of the interlayer insulating layer 170. Like the interlayer insulating layer 170 or the plurality of insulating layers 140, the isolation insulating layer 155 may include an insulating material such as silicon oxide. In some example embodiments, the isolation insulating layer 155 may include a material having a predetermined etching selectivity with respect to the plurality of sacrificial layers 120.

[0107] The isolation insulating layer 155 may divide at least one sacrificial layer (eg, the sacrificial layer 128) into a plurality of parts. The sacrificial layer 128 divided by the isolation insulating layer 155 may be a layer to be replaced by a gate electrode layer of the string selection transistor SST in a subsequent process.

[0108] Reference now Fig.19 and 20, a plurality of channel regions CH and a plurality of dummy channel regions DCH may be formed. The channel regions CH and the dummy channel regions DCH may pass through the plurality of sacrificial layers 120, the insulating layer 140, and the interlayer insulating layer 170. Fig.19 , the dummy channel region DCH may be formed to pass through the isolation insulating layer 155, and may be disposed in a region where the isolation insulating layer 155 is not formed. The number and position of the dummy channel region DCH and the channel region CH are not limited to Fig.19 and 20 The number and position shown in , and may be changed variously.

[0109] refer to Fig. 20 The channel region CH may include a channel layer 110 , a filling insulating layer 115 , a drain region 113 , and an epitaxial layer 111 , and the dummy channel region DCH may have a similar structure to the channel region. A tunneling layer 162 and a charge storage layer 164 may be disposed on an outer surface of the channel layer 110 .

[0110] In order to form the dummy channel region DCH and the channel region CH, a channel hole may first be formed through the interlayer insulating layer 170, the plurality of sacrificial layers 120, and the insulating layer 140. The channel hole may be recessed to a predetermined depth in the substrate 101. Thus, a portion of the substrate 101 may be exposed to the bottom of the channel hole. The portion of the substrate 101 exposed to the bottom of the channel hole may be used as a seed layer to form an epitaxial layer 111 in a selective epitaxial growth (SEG) process.

[0111] After forming the epitaxial layer 111, an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process may be used to form a charge storage layer 164 and a tunnel layer 162 in the channel hole, and a channel layer 110 may be formed inside the tunnel layer 162. The channel layer 110 may have a thickness of about 1 / 50 to 1 / 5 of the diameter of the channel hole. The channel layer 110 may be formed of polysilicon including a predetermined amount of impurities.

[0112] The channel layer 110 may have a ring shape with an inner side being empty, and a filling insulating layer 115 may be formed in the channel layer 110. Optionally, before forming the filling insulating layer 115, a hydrogen annealing process may be further performed, in which the structure including the channel layer 110 is heat-treated under a gas atmosphere including hydrogen and deuterium. In the hydrogen annealing process, a large number of crystal defects present in the channel layer 110 may be eliminated. The drain region 113 may be formed of a conductive material such as polysilicon on the channel layer 110.

[0113] refer to Fig.21 and 22, a word line cutout WC that divides the plurality of sacrificial layers 120 and the insulating layer 140 into a plurality of parts may be formed. The word line cutout WC may extend along the first direction (x-axis direction), and the substrate 101 may be partially exposed at the bottom of the word line cutout WC.

[0114] refer to Fig.23 and 24 , the plurality of sacrificial layers 120 may be replaced with a plurality of gate electrode layers 131 to 138 (collectively referred to as 130 ) through the word line cuts WC. The plurality of gate electrode layers 130 together with the plurality of insulating layers 140 may provide a gate structure.

[0115] In order to form a plurality of gate electrode layers 130, an etching process may be performed to selectively remove a plurality of sacrificial layers 120 through word line cuts WC. While removing the plurality of sacrificial layers 120, a plurality of insulating layers 140 may remain. Subsequently, a barrier layer 166 and a gate electrode layer 130 may be formed in the portion where the plurality of sacrificial layers 120 are removed. The barrier layer 166 may include a high-k dielectric material, and may include two or more layers. In these embodiments, the high-k dielectric material may refer to a dielectric material having a higher dielectric constant than silicon oxide.

[0116] The gate electrode layer 130 may include a metal, polysilicon, or a metal silicide material. For example, the metal silicide material may include a silicide of a metal selected from Co, Ni, Hf, Pt, W, Ti, or a combination thereof. When the gate electrode layer 130 is formed of a metal silicide material, the gate electrode layer 130 may be formed by filling a side opening with silicon, forming an additional metal layer, and performing a silicide process. Meanwhile, in some example embodiments, the gate electrode layer 130 may include a plurality of metal layers such as Ti, TiN, and W.

[0117] Reference now Fig.25 and 26 , a spacer 109 may be formed on the inner side surface of the word line cutout WC, and the source region 103 may be formed by implanting impurities into the substrate 101 exposed by the word line cutout WC. The spacer 109 may be formed by depositing an insulating material in the word line cutout WC and then removing the insulating material from the remaining portion other than the inner side surface of the word line cutout WC using an anisotropic etching process. The source region 103 may be formed by implanting impurities using an ion implantation process. In some example embodiments, the source region 103 may include n-type impurities.

[0118] refer to Figures 27 to 28, a first layer 151 of a common source line may be formed in the inner space of the spacer 109. The first layer 151 may extend in a direction perpendicular to the substrate 101 (z-axis direction) and in a first direction (x-axis direction) in which the word line cutout WC extends. The first layer 151 may include a conductive material and may directly contact the source region 103 to be connected thereto under the plurality of gate insulating layers 130.

[0119] According to example embodiments of the inventive concept, the first layer 151 may be formed of polysilicon including n-type impurities, and the impurity concentration of the first layer 151 may be greater than the impurity concentration of the source region 103. The first layer 151 may be formed by depositing polysilicon including n-type impurities in the space between the sidewall spacers 109 and performing a chemical mechanical polishing (CMP) process on the upper surface of the interlayer insulating layer 170.

[0120] Reference now Fig.29 and 30 , a peripheral contact portion 175 may be formed through the interlayer insulating layer 170, and then an upper insulating layer 171 may be formed on the interlayer insulating layer 170 and the first layer 151. Like the interlayer insulating layer 170 or the isolation insulating layer 155, the upper insulating layer 171 may include silicon oxide.

[0121] refer to Fig.31 and 32 , the cell opening region HC1 and the peripheral opening region HP1 may be formed by partially removing the upper insulating layer 171 on the first layer 151 and the peripheral contact portion 175. The upper surface of the first layer 151 may be partially exposed in the cell opening region HC1, and the upper surfaces of the peripheral contact portion 175 and the interlayer insulating layer 170 may be partially exposed in the peripheral opening region HP1. The cell opening region HC1 may extend in the first direction (x-axis direction) like the first layer 151, and may extend longer than the first layer 151 in the first direction.

[0122] refer to Fig.33 and 34 The upper metal layer 180 may be formed of a metal such as tungsten (W). In some example embodiments, the upper metal layer 180 may include a plurality of metal layers, specifically, Ti / TiN and W layers stacked in sequence. The Ti / TiN layer may be used as a barrier layer. Fig.35 and 36 , the contact metal layer 183 and the second layer 152 of the common source line 150 may be formed by performing a CMP process on the upper metal layer 180 .

[0123] As referenced above Figures 29 to 36As described above, the second layer 152 of the common source line 150 may be formed in a damascene process together with the contact metal layer 183. Therefore, the second layer 152 and the contact metal layer 183 may have substantially the same thickness, and the upper surface of the second layer 152 may be coplanar with the upper surface of the contact metal layer 183.

[0124] At the same time, reference Fig.35 , the second layer 152 may extend along the first direction (x-axis direction) on the upper surface of the first layer 151. In some example embodiments, the second layer 152 may extend longer than the first layer 151 along the first direction. Therefore, the resistance component caused by the first layer 151 formed of polysilicon doped with n-type impurities may be compensated to a certain extent by the second layer 152.

[0125] Figures 37 to 46 is a diagram showing the manufacture of Fig.10 2. A view of the process steps of the memory device shown in FIG. Fig.38 is along Fig.37 The cross section is obtained by taking the line II-II' in the reference Fig.37 and 38 , a cell region C and a peripheral circuit region P may be defined, and a plurality of gate electrode layers 231 to 238 (collectively referred to as 230), a plurality of channel regions CH and dummy channel regions DCH, a source region 203, and a first layer 251 of a common source line may be formed on a substrate 201 in the cell region C. A plurality of peripheral circuit devices 290 may be formed in the peripheral circuit region P disposed adjacent to the cell region C. The peripheral circuit device 290 may include an active region 291, a horizontal gate electrode 292, a horizontal gate insulating layer 293, and a horizontal spacer 294. A device isolation layer 295 may be disposed around the active region 291.

[0126] Each channel region CH may include a channel layer 210, a drain region 213 disposed on the channel layer 210, and a filling insulating layer 215 filling an inner space of the channel layer 210. A gate insulating layer 260 may be disposed between the plurality of gate electrode layers 230 and the channel layer 210. The gate insulating layer 260 may include a tunneling layer 262, a charge storage layer 264, and a blocking layer 266.

[0127] The first layer 251 of the common source line may be connected to the source region 203. The first layer 251 may include n-type impurities like the source region 203. In some example embodiments, the first layer 251 may be formed of polysilicon doped with n-type impurities. The concentration of the n-type impurities in the first layer 251 may be higher than the concentration of the n-type impurities in the source region 203.

[0128] refer to Fig.39 and 40, the opening area HE may be formed by removing at least a portion of the first layer 251, and the opening area HE may extend longer than the first layer 251 in the first direction. Fig.40 In the illustrated exemplary embodiment, the bottom surface of the opening region HE is disposed between the upper surface and the lower surface of the uppermost gate electrode layer 238. However, embodiments of the inventive concept are not limited thereto. In other words, the depth of the opening region HE may be varied, and the common source line 250 may be varied depending on the depth of the opening region HE, such as Figures 8B to 8D shown.

[0129] refer to Fig.41 and 42 , the second layer 252 may be formed in the opening region HE. The second layer 252 may be formed by depositing a metal on the inner surface of the opening region HE and the interlayer insulating layer 270, and performing a CMP process (removing the metal provided on the interlayer insulating layer 270). Therefore, the upper surface of the second layer 252 may be coplanar with the upper surface of the interlayer insulating layer 270.

[0130] The second layer 252 may include multiple layers. Fig.10 As shown, the second layer 252 may include a barrier layer 252a and a metal layer 252b formed on the barrier layer 252a. The barrier layer 252a may be formed of Ti / TiN, and the metal layer 252b may be formed of tungsten (W).

[0131] Reference now Fig.43 and 44 , an upper insulating layer 271 may be formed on the interlayer insulating layer 270 and the second layer 252. Similar to the interlayer insulating layer 270 and the isolation insulating layer 255, the upper insulating layer 271 may be formed of silicon oxide. After forming the upper insulating layer 271, a damascene process may be used to form the third layer 253, as shown in FIG. Figures 29 to 36 described.

[0132] refer to Fig.45 and 46 The third layer 253 may be formed together with the contact metal layer 283 disposed on the peripheral contact portion 275. The third layer 253 may be formed on the second layer 252 and may extend beyond the first layer 251 along the first direction (x-axis direction).

[0133] Similar to the second layer 252, the third layer 253 may include multiple layers. Fig.10 As shown, the third layer 253 may include a barrier layer 253 a formed of Ti / TiN or the like and a metal layer 253 b formed of tungsten (W) or the like.

[0134] In reference Figures 37 to 46In the process of manufacturing the memory device 200, both the second layer 252 and the third layer 253 may be formed according to the damascene process. Since the first layer 251 is formed of polysilicon doped with n-type impurities, and the second layer 252 and the third layer 253 are formed on the first layer 251, the high resistance component of the polysilicon of the first layer 251 may be compensated. In particular, by forming at least one of the second layer 252 and the third layer 253 to be longer than the first layer 251, the high resistance component of the polysilicon may be effectively compensated.

[0135] Fig.47 is a block diagram illustrating an electronic device including a memory device according to an example embodiment of the inventive concept. Fig.47 , a storage device 1000 according to some example embodiments of the inventive concept may include a controller 1010 communicating with a host HOST and memories 1020-1, 1020-2, and 1020-3 storing data. Each of the memories 1020-1, 1020-2, and 1020-3 may include the storage devices 100, 200, and 300 according to the above-described various example embodiments of the inventive concept.

[0136] The host HOST communicating with the controller 1010 may be various electronic devices such as a smart phone, a digital camera, a desktop PC, a laptop PC, or a media player on which the storage device 1000 is installed. The controller 1010 may receive a request for data reading or writing from the host HOST to generate a command CMD for writing data to the memories 1020-1, 1020-2, and 1020-3 or reading data from the memories 1020-1, 1020-2, and 1020-3.

[0137] like Fig.47 As shown, one or more memories 1020-1, 1020-2, and 1020-3 may be connected in parallel to the controller 1010 in the storage device 1000. By connecting multiple memories 1020-1, 1020-2, and 1020-3 in parallel to the controller 1010, a large-capacity storage device 1000, such as a solid state drive (SSD), may be implemented.

[0138] As described above, according to the exemplary embodiments of the inventive concept, the common source line may include multiple layers formed of different materials, and at least a portion of the multiple layers may be formed of a semiconductor material doped with impurities. Therefore, since the problem generated when the common source line is formed only of metal is solved, the reliability of the memory device can be improved.

[0139] While example embodiments have been shown and described above, it will be understood by those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A storage device, comprising: A cell region, comprising a first substrate, a plurality of gate electrode layers, a plurality of channel regions, a source region, a spacer and a common source line, wherein the plurality of channel regions extend in a direction perpendicular to an upper surface of the first substrate and pass through the plurality of gate electrode layers, the source region is formed in the first substrate and doped with n-type impurities, the spacer divides the plurality of gate electrode layers into a plurality of parts, and the common source line is connected to the source region and extends along the direction between the spacer; as well as A peripheral circuit area, comprising a second substrate and a plurality of peripheral circuit devices arranged on the second substrate; wherein the cell region and the peripheral circuit region are stacked in the direction; as well as The common source line comprises: a first layer arranged between the sidewall spacers on the source region; and a second layer comprising a barrier layer on the first layer between the sidewall spacers and a metal layer on the barrier layer. 2 . The memory device according to claim 1 , wherein the first layer comprises polysilicon doped with n-type impurities, and the barrier layer comprises at least one of a metal, a metal silicide, and a metal compound. 3 . The memory device of claim 2 , wherein in a first direction parallel to the upper surface of the first substrate, a length of the second layer is greater than a length of the first layer. 4 . The memory device according to claim 2 , wherein an impurity concentration of the first layer is greater than an impurity concentration of the source region. 5 . The memory device of claim 1 , wherein the common source line comprises a third layer disposed on the second layer, the third layer comprising at least one of a metal, a metal silicide, and a metal compound. The memory device according to claim 5 , wherein a thickness of the third layer is greater than a thickness of the second layer. 7 . The memory device of claim 5 , wherein in a first direction parallel to the upper surface of the first substrate, a length of the third layer is greater than a length of the first layer and a length of the second layer. 8 . The memory device according to claim 1 , wherein a thickness of the first layer is greater than a thickness of the second layer.

9. The memory device according to claim 1, further comprising: an interlayer insulating layer, arranged on the plurality of gate electrode layers; The upper surface of the second layer is coplanar with the upper surface of the interlayer insulating layer. 10 . The memory device according to claim 1 , wherein at least a portion of the barrier layer is disposed between one of the spacers and the metal layer in a direction parallel to the upper surface of the first substrate.

11. The memory device according to claim 1, further comprising: an isolation insulating layer, dividing the uppermost gate electrode layer among the plurality of gate electrode layers, Wherein, the bottom surface of the second layer is higher than the bottom surface of the isolation insulating layer.

12. A storage device comprising: a first substrate; a source region formed in the first substrate and doped with n-type impurities; A plurality of gate electrode layers, stacked on the first substrate; an isolation insulating layer, dividing the uppermost gate electrode layer among the plurality of gate electrode layers; a plurality of channel regions extending in a direction perpendicular to the upper surface of the first substrate and passing through the plurality of gate electrode layers; a common source line, contacting the source region, extending in a first direction parallel to the upper surface of the first substrate, and comprising a first layer and a second layer, the first layer comprising polysilicon doped with n-type impurities at a higher impurity concentration than the source region, the second layer comprising at least one of a metal, a metal silicide, and a metal compound and arranged on the first layer; as well as A plurality of peripheral circuit devices are on the second substrate; wherein the first substrate and the second substrate are divided in the direction, and A bottom surface of the second layer is higher than a bottom surface of the isolation insulating layer.

13. The memory device according to claim 12, further comprising: A plurality of dummy channel regions pass through the isolation insulating layer and extend along the direction.

14. The memory device according to claim 13, further comprising: a plurality of peripheral contacts connected to a plurality of peripheral circuit devices; as well as a contact metal layer disposed on at least one peripheral contact of the plurality of peripheral contacts, Wherein, an upper surface of the contact metal layer is coplanar with an upper surface of the second layer.

15. The memory device according to claim 14, wherein: The at least one peripheral contact among the plurality of peripheral contacts has a height greater than a height of the plurality of channel regions.

16. The memory device according to claim 12, further comprising: sidewall spacers are arranged on both sides of the common source line in a second direction parallel to the upper surface of the first substrate and intersecting the first direction, The second layer includes a barrier layer in contact with the sidewall spacer and the first layer and a metal layer in contact with the barrier layer.

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