Thin film devices

Abstract

A thin film device includes a polysilicon element and an oxide semiconductor element. The polysilicon element includes a first portion made of low-resistance polysilicon. The oxide semiconductor element includes a second portion made of low-resistance oxide semiconductor. The first portion and the second portion are arranged to overlap and connect with each other.

Description

Technical Field

[0001] The present disclosure relates to a thin film device. Background Art

[0002] In fact, a technology that combines a low-temperature polysilicon thin-film transistor (LTPS TFT) and an oxide semiconductor TFT into one pixel circuit is used. This technology is referred to as a hybrid TFT display (HTD) technology in this article. The HTD technology combines a low-temperature polysilicon TFT with high mobility and an oxide semiconductor TFT that generates a small leakage current into a pixel circuit to achieve higher display quality and lower power consumption.

[0003] For example, US 2015 / 0055051A and US 2018 / 0240855A disclose technologies in HTD technology. According to these patent documents, the technology connects the source / drain of the low-temperature polysilicon TFT with the source / drain of the oxide semiconductor TFT through one or more vias (one or more contact holes) and metal lines. Summary of the invention

[0004] As mentioned above, in order to obtain the contact between the source / drain of the low-temperature polysilicon TFT and the source / drain of the oxide semiconductor TFT through vias and metal wires, multiple vias are required in the pixel circuit. The vias require a large area and design margin between each via and other components. For this reason, increasing the number of vias will hinder the realization of higher resolution. The same applies to thin film devices, including polysilicon components and oxide semiconductor components that are different from display devices. Increasing the number of vias will hinder the reduction of circuit size.

[0005] One aspect of the present disclosure is a thin film device, comprising a polysilicon element and an oxide semiconductor element. The polysilicon element comprises a first portion made of low-resistance polysilicon. The oxide semiconductor element comprises a second portion made of low-resistance oxide semiconductor. The first portion and the second portion are arranged to overlap and connect with each other.

[0006] Another aspect of the present disclosure is a method for manufacturing a thin film device, comprising: forming a polysilicon film, which includes a third portion made of high-resistance polysilicon and a fourth portion made of low-resistance polysilicon; and forming an oxide semiconductor film, which includes a fifth portion made of a high-resistance oxide semiconductor and a sixth portion made of a low-resistance oxide semiconductor, wherein the low-resistance oxide semiconductor is configured to overlap and connect with the fourth portion.

[0007] An aspect of the present disclosure can reduce the size of a circuit including a polysilicon element and an oxide semiconductor element.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematically shows an example of the configuration of an OLED display device;

[0010] Figure 2A An example of the configuration of a pixel circuit is shown;

[0011] Figure 2B Another configuration example of a pixel circuit is shown;

[0012] Figure 2C Still another configuration example of a pixel circuit is shown;

[0013] Figure 3 shows the cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are in direct contact with each other;

[0014] Figure 4 Is manufacturing Figure 3 A flowchart of an example of a method of constructing an example is shown in;

[0015] Figure 5 is a schematic diagram showing an example of a process for achieving lower contact resistance;

[0016] Fig. 6A is a schematic diagram showing another example of a process for reducing contact resistance;

[0017] Figure 6B is a schematic diagram showing another example of a process for obtaining a lower contact resistance;

[0018] Figure 7 shows the cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are in direct contact with each other;

[0019] Figure 8 Is manufacturing Figure 7 A flowchart of an example of a method of constructing an example is shown in;

[0020] Fig. 9 The cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a metal film is shown;

[0021] Fig.10 Is manufacturing Fig. 9 A flowchart of an example of a method of constructing an example is shown in;

[0022] Fig.11AThe cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a through hole is shown;

[0023] Fig. 11B Other cross-sectional structures of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are connected to each other through a through hole are shown;

[0024] Fig. 12A Is manufacturing Fig.11A A flowchart of an example of a method of constructing an example is shown in;

[0025] Fig. 12B Is manufacturing Fig. 11B A flowchart of an example of a method of constructing an example is shown in;

[0026] Fig.13 The cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a through hole is shown;

[0027] Fig.14 Is manufacturing Fig.13 A flowchart of an example of a method of constructing an example is shown in;

[0028] Fig.15 The cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a through hole is shown;

[0029] Fig.16 Is manufacturing Fig.15 A flowchart of an example of a method of constructing an example is shown in;

[0030] Fig.17 The cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are connected to each other through a through hole and a laminate of a metal film is shown;

[0031] Fig.18 Is manufacturing Fig.17 A flowchart of an example of a method of constructing an example is shown in;

[0032] Fig.19 The cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a through hole is shown;

[0033] Fig. 20 Is manufacturing Fig.19 A flowchart of an example of a method of constructing an example is shown in;

[0034] Fig.21 The cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a through hole is shown;

[0035] Fig. 22 Is manufacturing Fig.21 A flowchart of an example of a method of constructing an example is shown in;

[0036] Fig.23 shows the cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are in direct contact with each other;

[0037] Fig.24 The cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a through hole is shown;

[0038] Fig.25 shows the cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are in direct contact with each other;

[0039] Fig.26 Is manufacturing Fig.25 A flowchart of an example of a method of constructing an example is shown in;

[0040] Fig. 27 shows the cross-sectional structure of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are in direct contact with each other; and

[0041] Fig.28 Is manufacturing Fig. 27 A flowchart of an example of a method of constructing an example is shown in FIG. DETAILED DESCRIPTION

[0042] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that these embodiments are merely examples for implementing the present disclosure and do not limit the technical scope of the present disclosure. Commonly used elements in the figures are represented by the same reference numerals, and some elements in the figures are enlarged in size or shape to clearly understand the description.

[0043] Overview

[0044] The following description uses an organic light emitting diode (OLED) display device as an example of a thin film device. The OLED display device in the present disclosure includes a low temperature polysilicon thin film transistor (LTPS TFT) and an oxide semiconductor TFT in a pixel circuit and / or a peripheral circuit, wherein the source / drain of the low temperature polysilicon TFT is physically connected to the source / drain of the oxide semiconductor TFT.

[0045] In particular, the low temperature polysilicon TFT has a source / drain made of polysilicon with reduced resistance (low resistance polysilicon), and the oxide semiconductor TFT has a source / drain made of an oxide semiconductor with reduced resistance (low resistance oxide semiconductor). The sheet resistance of a common low resistance source / drain is in the range of 10Ω to 100kΩ, for example, from tens of ohms to tens of thousands of ohms. The sheet resistance of a common channel (i.e., a high resistance channel) whose resistance is not reduced is generally in the range of 1MΩ to 10GΩ, for example, from several megaohms to several gigaohms.

[0046] When viewed from the layer structure direction, the source / drain of the low-temperature polysilicon TFT and the source / drain of the oxide semiconductor TFT overlap each other at least partially, and they are connected to each other directly or through a conductor. The conductor connecting the source / drain of the two TFTs can be a metal or a low-resistance semiconductor.

[0047] The structure in which the source / drain of the low-temperature polysilicon TFT is connected to the source / drain of the oxide semiconductor TFT through two vias (contact holes) and a metal film causes the circuit to have a larger area because of the two vias. In particular, the vias occupy a larger area between the vias and other components and require a design margin. Therefore, increasing the number of vias will hinder the realization of higher resolution. The structure disclosed in the present invention has a smaller number of vias for connecting the source / drain of the low-temperature polysilicon TFT and the oxide semiconductor TFT to achieve a smaller circuit area.

[0048] The aforementioned thin film devices include polysilicon components and oxide semiconductor components that are different from display devices. Increasing the number of vias will hinder the reduction of circuit size. Therefore, the connection between the above-mentioned low-temperature polysilicon TFT and the oxide semiconductor TFT can be used for the connection of other semiconductor components. One of the semiconductor components is a polysilicon component, which includes a conductive component (first part) made of low-resistance polysilicon, and the other is an oxide semiconductor component, which includes a conductive part (second part) made of low-resistance oxide semiconductor. The two conductive components are arranged to overlap and connect each other. The polysilicon component does not have to be made of low-temperature polysilicon.

[0049] Oxide semiconductors have low tolerance to hydrogen fluoride (HF). If HF treatment is applied to etch silicon oxide on the source / drain (contact region) surface of a low-temperature polysilicon TFT, the exposed oxide semiconductor will be etched together. This HF treatment can be eliminated by providing an oxide semiconductor film on the contact region of the source / drain of a low-temperature polysilicon TFT.

[0050] Example 1

[0051] Display device configuration

[0052] Figure 1The configuration example of an OLED display device 1 is schematically shown. The OLED display device 1 includes a thin film transistor (TFT) substrate 10 on which an OLED element is formed, an encapsulation substrate 20 for encapsulating the OLED element, and a bonding member (glass paste sealing layer) 30 for bonding the TFT substrate 10 to the encapsulation substrate 20. The space between the TFT substrate 10 and the encapsulation substrate 20 is filled with dry nitrogen and sealed with the bonding member 30. The encapsulation substrate 20 and the bonding member 30 constitute a structural encapsulation unit. The structural encapsulation unit may have a thin film encapsulation (TFE) structure.

[0053] A scan driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a multiplexer 36 are provided at the periphery of the cathode electrode region 14 outside the display region 25 of the TFT substrate 10. The driver IC 34 is connected to an external device via a flexible printed circuit (FPC) 35. The scan driver 31, the emission driver 32, and the protection circuit 33 are peripheral circuits built on the TFT substrate 10.

[0054] The scan driver 31 drives the scan lines on the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emission period of the pixels. The protection circuit 33 protects the elements from electrostatic discharge. The driver IC 34 may be mounted with, for example, an anisotropic conductive film (ACF).

[0055] The driver IC 34 supplies power and a timing signal (control signal) to the scan driver 31 and the emission driver 32 , and further supplies power and a data signal to the demodulator 36 .

[0056] The multiplexer 36 outputs the output of one pin of the driver IC 34 in series to d data lines (d is an integer greater than 1). The multiplexer 36 changes the output data line of the data signal from the driver IC 34 d times per scanning cycle to drive the data line of the output pin of the driver IC 34 d times.

[0057] Pixel circuit structure

[0058] A plurality of pixel circuits are formed on the TFT substrate 10 to control current supplied to anodes of sub-pixels (also simply referred to as pixels). Figure 2A An example of the configuration of a pixel circuit is shown. Each pixel circuit includes a driving transistor T1, a selecting transistor T2, an emitting transistor T3 and a storage capacitor C1. The pixel circuit controls light emission of the OLED element E1. The transistor is a TFT.

[0059] The selection transistor T2 is a switch for selecting a sub-pixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and its gate terminal is connected to the scanning line 16. The source terminal is connected to the data line 15. The drain terminal is connected to the gate terminal of the driving transistor T1.

[0060] The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is a p-channel low-temperature polysilicon TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the driving transistor T1 is connected to the power line (Vdd) 18. The drain terminal is connected to the source terminal of the emission transistor T3. The storage capacitor C1 is provided between the gate terminal and the source terminal of the driving transistor T1.

[0061] The emission transistor T3 is a switch for controlling the supply / stop of the driving current to the OLED element E1. The emission transistor T3 is an n-channel oxide semiconductor TFT, and its gate terminal is connected to the emission control line 17. The source terminal of the emission transistor T3 is connected to the drain terminal of the driving transistor T1. The drain terminal of the emission transistor T3 is connected to the OLED element E1.

[0062] Next, the operation of the pixel circuit is described. The scan driver 31 outputs a selection pulse to the scan line 16 to turn on the selection transistor T2. The data voltage supplied from the driver IC 34 is stored in the storage capacitor C1 via the data line 15. During the period of one frame, the storage capacitor C1 holds the stored voltage. The conductivity of the drive transistor T1 changes in an analog manner according to the stored voltage, so that the drive transistor T1 supplies a forward bias current corresponding to the light emission level to the OLED element E1.

[0063] The emission transistor T3 is located on the supply path of the drive current. The emission driver 32 outputs a control signal to the emission control line 17 to control the on / off of the emission transistor T3. When the emission transistor T3 is on, the drive current is supplied to the OLED element E1. When the emission transistor T3 is off, the supply is stopped. The light emission period (duty cycle) within a frame period can be controlled by controlling the on / off of the transistor T3.

[0064] Figure 2B Another configuration example of a pixel circuit is shown. Figure 2A The pixel circuit includes an emission transistor T3 in the pixel circuit, and a reset transistor T4. The reset transistor T4 is an n-channel oxide semiconductor TFT. The reset transistor T4 controls the electrical connection between the reference voltage supply line 11 and the anode of the OLED element E1. The control is performed according to a reset control signal supplied from the reset control line 19 to the gate of the reset transistor T4. The reset transistor T4 can be used for various purposes.

[0065] Figure 2C Another configuration example of a pixel circuit is shown. The pixel circuit includes n-channel transistors T1 to T7. The gate terminal of the selection transistor T2 is supplied with a Vscan2 signal. The storage capacitor C1 is supplied with a data voltage through the selection transistor T2. The gates of the transistors T4 and T6 are supplied with a Vscan1 signal. The transistors T4 and T6 supply Vref to the anode of the OLED element E1 to set a threshold voltage for the storage capacitor C1. The gates of the transistors T3 and T5 are supplied with Vem1 and Vem2 signals, respectively, to control the light emission of the OLED element E1.

[0066] The driving transistor T1 may be a low temperature polysilicon TFT and the transistor T6 may be an oxide semiconductor TFT. The other transistors may be a low temperature polysilicon TFT or an oxide semiconductor TFT. The source / drain of the driving transistor T1 is connected to the source / drain of the transistor T6. Figure 2A , 2B The circuit configurations in 2C are examples; the pixel circuit may have a different circuit configuration.

[0067] The above-mentioned pixel circuit includes a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other. The connection described in this specification realizes a smaller number of vias in the pixel circuit and contributes to higher resolution.

[0068] Connection between low-temperature polysilicon TFT and oxide semiconductor TFT

[0069] Hereinafter, a configuration example of interconnecting a low-temperature polysilicon TFT and an oxide semiconductor TFT is described. The oxide semiconductor in the example described below is assumed to be indium gallium zinc oxide (IGZO). The configuration described in this specification is applicable to elements made of other oxide semiconductors.

[0070] Figure 3 The cross-sectional structure of a low-temperature polysilicon TFT 510 and an oxide semiconductor TFT 560 whose sources / drains are in direct contact with each other is shown. The low-temperature polysilicon TFT 510 and the oxide semiconductor TFT 560 are constructed on a flexible or non-flexible insulating substrate 101 made of resin or glass.

[0071] The low temperature polysilicon TFT 510 includes a source and a drain 105 and 107, and a channel 103 sandwiched between the source / drain 105 and 107 in the in-plane direction. The source / drain 105 and 107 are made of low temperature polysilicon whose resistance is reduced by doping high concentration impurities. The channel 103 is made of low temperature polysilicon (high resistance low temperature polysilicon) whose resistance is not reduced.

[0072] The source / drain 105 and 107 and the channel 103 (semiconductor film) are included in the low temperature polysilicon layer. The low temperature polysilicon layer is directly formed on the insulating substrate 101. Figure 3 The source / drain electrodes 105 and 107 and the channel 103 in the example are in contact with the insulating substrate 101, but another insulating layer such as a silicon nitride layer may be provided therebetween.

[0073] The low-temperature polysilicon TFT 510 further includes a gate electrode 123 and a gate insulating film 115, which is inserted between the gate electrode 123 and the channel 103 in the stacking structure direction. The channel 103, the gate insulating film 115, and the gate electrode 123 are stacked in this order from the bottom (from the substrate side), and the gate insulating film 115 is in contact with the channel 103 and the gate electrode 123. The gate electrode 123 is made of metal and is included in the metal layer M1. The gate insulating film 115 in this example is made of silicon oxide and is included in the silicon oxide layer SiO_1. Although in Figure 3 The low-temperature polysilicon TFT 510 in the example has a top gate structure, but the low-temperature polysilicon TFT 510 may have a bottom gate structure.

[0074] The oxide semiconductor TFT 560 includes source and drain electrodes 111 and 113, and a channel 109 sandwiched between the source / drain electrodes 111 and 113 in the in-plane direction. The source / drain electrodes 111 and 113 are made of IGZO that reduces resistance. The channel 109 is made of IGZO that does not reduce resistance (high resistance IGZO).

[0075] The source / drain electrodes 111 and 113 and the channel 109 (semiconductor film) are included in the oxide semiconductor layer. The oxide semiconductor layer is formed directly on the insulating substrate 101. Figure 3 The source / drain electrodes 111 and 113 and the channel 109 in the example are in contact with the insulating substrate 101 , but another insulating layer such as a silicon nitride layer may be provided therebetween.

[0076] The oxide semiconductor TFT 560 also includes a gate 125 and a gate insulating film 117, which is inserted between the gate 125 and the channel 109 in the stacking structure direction. The channel 109, the gate insulating film 117 and the gate 125 are stacked in this order from the bottom (from the substrate side), and the gate insulating film 117 is in contact with the channel 109 and the gate 125. The gate 125 is made of metal and is included in the metal layer M2. The gate insulating film 117 in this example is made of silicon oxide and is included in the silicon oxide layer SiO_2. Although in Figure 3 The oxide semiconductor TFT 560 in the example has a top gate structure, but the oxide semiconductor TFT 560 may have a bottom gate structure.

[0077] The source / drain 105 of the low-temperature polysilicon TFT 510 and the source / drain 113 of the oxide semiconductor TFT 560 are connected at the junction 150. At the junction 150, a portion (first portion) of the source / drain 105 of the low-temperature polysilicon TFT 510 and a portion (second portion) of the source / drain 113 of the oxide semiconductor TFT 560 overlap each other. When viewed from the stacked structure direction, these portions are stacked and they are in direct contact with each other. Figure 3 In the example of FIG. 5 , one end of the source / drain 113 of the oxide semiconductor TFT 560 is located above one end of the source / drain 105 of the low-temperature polysilicon TFT 510 .

[0078] The interlayer insulating film 119 covers and contacts the source / drain 107, the gate 123, and portions of the source / drain 105 of the low-temperature polysilicon TFT 510 and the source / drain 113 of the oxide semiconductor TFT 560. The interlayer insulating film 119 in this example is made of silicon oxide and is included in the silicon oxide layer SiO_2.

[0079] The interlayer insulating film 121 covers and contacts portions of the source / drain 113, the gate 125, and the source / drain 111 of the oxide semiconductor TFT 560. The interlayer insulating film 121 in this example is made of silicon oxide and is included in the silicon oxide layer SiO_3. Figure 3 The interlayer insulating film 119 in the configuration example has a single-layer structure including a silicon oxide layer SiO_2, but the interlayer insulating film 119 may have a multilayer structure including a silicon oxide layer and a silicon nitride layer stacked in this order.

[0080] The electrode 129 is disposed above the interlayer insulating film 121 and is connected to the source / drain 107 of the low-temperature polysilicon TFT 510 through a via hole opened in the interlayer insulating films 119 and 121. The through hole inside the via hole interconnects the electrode 129 and the source / drain 107. The electrode 129 and the through hole are made of the same metal. The electrode 129 is made of metal and is included in the metal layer M3.

[0081] The electrode 127 is disposed above the interlayer insulating film 121 and is connected to the source / drain 111 of the oxide semiconductor TFT 560 through a via hole opened in the interlayer insulating film 121. The through hole inside the via hole interconnects the electrode 127 and the source / drain 111. The electrode 127 and the through hole are made of the same metal. The electrode 127 is made of metal and is included in the metal layer M3. The insulating layer may be made of a material other than silicon oxide (such as silicon nitride).

[0082] Manufacturing method

[0083] Describes a method of making Figure 3The method of TFT 510 and 560 is shown. Figure 4 1 is a flow chart of an example of a method for manufacturing these TFTs. The method forms a low-temperature polysilicon layer on an insulating substrate 101 (S101). In particular, the (low-temperature) polysilicon film can be formed by depositing amorphous silicon by CVD and crystallizing the amorphous silicon by excimer laser annealing. The polysilicon film is patterned into an island shape by photolithography.

[0084] Next, the method forms a silicon oxide layer SiO_1 by CVD (S102), further forms a metal layer M1 by sputtering, and patterns the metal layer M1 and the silicon oxide layer SiO_1 together by photolithography (S103). Next, the method uses the gate 123 (metal layer M1) as a mask, dopes the source / drain region of the polysilicon film with impurities, and activates the impurities. In addition, the method terminates dangling bonds by hydrogenation (S104).

[0085] Next, the method forms an IGZO layer by sputtering and patterns the IGZO layer by photolithography (S105). Next, the method forms a silicon oxide layer SiO_2 (S106). Next, the method forms a metal layer M2 by sputtering and patterns the metal layer M2 by photolithography (S107). The material for the gates 123 and 125 can be desirably selected from, for example, Mo, W, Nb, and Al. The gates 123 and 125 can have a single-layer structure or a multi-layer structure.

[0086] Next, the method patterns the silicon oxide layer SiO_2 by photolithography (S108). Next, the method uses the metal layer M2 (gate 125) as a mask to reduce the resistance of the source / drain region of the IGZO layer (S109). The resistance can be reduced by exposing the source / drain region of the IGZO layer to He plasma or injecting B, Ar or H ions. Next, the method forms a silicon oxide film SiO_3 (S110). Next, the method opens vias in the silicon oxide layers SiO_2 and SiO_3 by anisotropic etching (S111).

[0087] Next, the method forms a metal layer M3 by sputtering and patterns the metal layer M3 by photolithography (S112). The metal layer M3 includes electrodes 127 and 129, and also includes through holes (coating or filling the inner part of the via holes) for connecting the electrodes 127 and 129 to the source / drain 111 of the oxide semiconductor TFT and the source / drain 107 of the low-temperature polysilicon TFT, respectively.

[0088] The electrodes 127 and 129 may be formed by depositing and patterning a conductive (eg, Ti, Al, Ti) film. The electrodes 127 and 129 may have a single-layer structure or be made of a metal different from these metals.

[0089] exist Figure 3 In the configuration example in , the low resistance LTPS portion of the low temperature polysilicon TFT 510 and the low resistance IGZO portion of the oxide semiconductor TFT 560 are in direct contact with each other at the junction 150. An example of a process (manufacturing method) for obtaining lower contact resistance at their contact surfaces is described. Figure 5 is a schematic diagram showing an example of a process for achieving lower contact resistance.

[0090] After preparing the source / drain 105 by doping the low temperature polysilicon layer with impurities, the method forms an oxide semiconductor layer IGZO_1 (first oxide semiconductor film) by sputtering only argon (Ar) gas ( S301 ). The oxide semiconductor layer IGZO_1 covers the surface of the source / drain 105 .

[0091] Next, the method forms another oxide semiconductor layer IGZO_2 (second oxide semiconductor film) by sputtering argon (Ar) gas and oxygen (O2) gas, and patterns the oxide semiconductor layers IGZO_1 and IGZO_2 by photolithography (S302). Next, the method reduces the resistance of portions of the oxide semiconductor layers IGZO_1 and IGZO_2 with He plasma to prepare a source / drain 113 (S303). Portions of the source / drain 113 cover and contact portions of the source / drain 105 including one end thereof.

[0092] As described above, the oxide semiconductor layer IGZO_1 is formed without using oxygen, and therefore the contact surface between the low resistance LTPS portion and the low resistance IGZO portion is not oxidized when the oxide semiconductor layer is formed. As a result, a lower contact resistance is obtained at the contact surface between the low resistance LTPS portion and the low resistance IGZO portion.

[0093] FIG.6A is a schematic diagram showing another example of a process for obtaining lower contact resistance. After preparing the source / drain 105 by doping the low-temperature polysilicon layer with impurities, the method forms an IGZO layer by sputtering a gas of argon and oxygen, and patterns the IGZO layer by photolithography to prepare an IGZO film 303 (S311). A portion of the IGZO film 303 covers and contacts a portion of the source / drain 105 including one end thereof.

[0094] Next, the method implants ions (such as B, Ar or H ions) into the IGZO film 303 to reduce the resistance of the IGZO film 303 (S312). The ion implantation reduces the contact resistance at the contact surface between the low resistance LTPS portion and the low resistance IGZO portion. Since the ions are implanted into the low temperature polysilicon layer except the contact area, an element with less influence on the characteristics of other areas is selected.

[0095] Figure 6B is a schematic diagram showing another example of a process for obtaining a lower contact resistance. After preparing the source / drain 105 by doping the low temperature polysilicon layer with impurities, the method forms a metal film 311 by sputtering (S321). The metal film 311 may be a molybdenum or titanium film. When the metal film 311 is formed, an interface reaction generates a metal silicide film 313 at the contact surface between the low resistance LTPS and the metal film 311.

[0096] Next, the method removes the metal film 311 by wet etching (S322). After etching, the metal silicide film 313 remains on the surface of the low resistance LTPS. Next, the method forms an IGZO layer by sputtering a gas of argon and oxygen, and patterns the IGZO layer by photolithography to prepare an IGZO film 303 (S323). A portion of the IGZO film 303 covers and contacts a portion of the source / drain 105 including one end thereof. Next, the method reduces the resistance of the IGZO film 303 with He plasma (S324).

[0097] As described above, a metal silicide film is formed at the contact surface of the low resistance LTPS portion and the low resistance IGZO portion. The metal silicide film reduces the contact resistance at the contact surface of the low resistance LTPS portion and the low resistance IGZO portion. The metal silicide film may be a layer of a mixture of at least one of indium, gallium and zinc elements, a component element of the low resistance IGZO, silicon elements and metal elements. The metal element may be molybdenum or titanium.

[0098] Example 2

[0099] Another configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are in direct contact with each other is described. Figure 7 The cross-sectional structure of the low-temperature polysilicon TFT 512 and the oxide semiconductor TFT 562 whose source / drain electrodes are in direct contact with each other is shown. Figure 3 The difference is the configuration example shown in .

[0100] The source / drain 113 of the oxide semiconductor TFT 562 is in a layer above the interlayer insulating film 119. Figure 7 In the example of FIG. 5 , at the junction 150, a portion of the source / drain 113 covers and contacts a portion of the source / drain 105, and another portion of the source / drain 113 covers and contacts a portion of the interlayer insulating film 119. The gate insulating film 117 of the oxide semiconductor TFT 562 is included in the silicon oxide layer SiO_3. The interlayer insulating film 133 covers the low-temperature polysilicon TFT 512 and the oxide semiconductor TFT 562 is included in the silicon oxide layer SiO_4.

[0101] As mentioned above, Figure 7 The low-temperature polysilicon TFT 512 in the configuration example in FIG. 1 includes a gate electrode 123 which is disposed above the channel 103 with a gate insulating film 115 sandwiched therebetween, and the gate electrode 123 is covered with an interlayer insulating film 119. Part of the source / drain 113 of the oxide semiconductor TFT 562 is located above the interlayer insulating film 119.

[0102] Figure 8 Is manufacturing Figure 7 A flowchart of an example of a method of constructing an example is shown in FIG. Steps S121 to S124 are Figure 4 The method is the same as S101 to S104 in the flowchart of. After doping the low-temperature polysilicon layer with impurities, activating the impurities, and hydrogenating the low-temperature polysilicon layer (S124), the method forms a silicon oxide layer SiO_2 by CVD and patterns the silicon oxide layer SiO_2 by photolithography (S125). Next, the method forms an IGZO layer by sputtering and patterns the IGZO layer by photolithography (S126).

[0103] Next, the method forms a silicon oxide layer SiO_3 by CVD ( S127 ), further forms a metal layer M2 by sputtering, and patterns the metal layer M2 and the silicon oxide layer SiO_3 together by photolithography ( S128 ).

[0104] Next, the method uses the metal layer M2 (gate 125) as a mask to reduce the resistance of the source / drain region of the IGZO layer (S129). The resistance can be reduced by exposing the source / drain region of the IGZO layer to He plasma. The resistance can also be reduced by injecting B, Ar or H ions.

[0105] Next, the method forms a silicon oxide layer SiO_4 (S130). Next, the method opens a via hole by anisotropically etching the silicon oxide layers SiO_2 and SiO_4 (S131). Step S132 and Figure 4 The same as step S112 in the flowchart.

[0106] As described above, the method patterns the IGZO layer after forming the interlayer insulating film 119 covering part of the low-temperature polysilicon layer and the entire metal layer M1. When the IGZO layer is patterned, the low-temperature polysilicon layer is covered with the interlayer insulating film 119 or the IGZO layer. The low-temperature polysilicon layer and the metal layer M1 are not exposed to the etchant, so that the low-temperature polysilicon layer and the metal layer are not affected by the etchant.

[0107] Example 3

[0108] Configuration examples of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a metal film are described. Fig. 9 The cross-sectional structure of the low-temperature polysilicon TFT 514 and the oxide semiconductor TFT 564 whose source / drain are connected to each other through a metal film is shown. Figure 7 The difference is the configuration example shown in .

[0109] The junction 151 between the low temperature polysilicon TFT 514 and the oxide semiconductor TFT 564 includes a metal film 141. The metal film 141 is included in the metal layer M2. The metal film 141 may be made of the same material as the gates 123, 125 and the electrodes 127, 129 or have the same structure as them. The metal film 141 may be made of a different material than the gates 123, 125 and any of the electrodes 127, 129 or have a different structure as them. The gate 125 of the oxide semiconductor TFT 564 is included in the metal layer M3. The electrodes 127 and 129 are included in the metal layer M4.

[0110] When viewed from the stacked structure direction, the metal film 141 is provided between the source / drain 105 (part thereof) of the low temperature polysilicon TFT 514 and the source / drain 113 (part thereof) of the oxide semiconductor TFT 564, and is in contact with and interconnected with them. The junction 151 has a laminated structure including a film of low resistance LTPS, a metal, and low resistance IGZO. The metal film 141 ensures stable contact between the source / drain 105 and 113.

[0111] Fig.10 Is manufacturing Fig. 9 The flowchart of the example of the method of constructing the example is shown in FIG. Steps S141 to S144 are Figure 8 The steps S121 to S124 in the flowchart of FIG. 14 are the same. At step S145, the method forms a metal layer M2 by sputtering and patterns the metal layer M2 by photolithography. Through these processes, a metal film 141 is prepared.

[0112] Next, the method forms a silicon oxide layer SiO_2 by CVD and patterns the silicon oxide layer SiO_2 by photolithography (S146). Next, the method forms an IGZO layer by sputtering and patterns the IGZO layer by photolithography (S147).

[0113] Next, the method forms a silicon oxide layer SiO_3 by CVD ( S148 ), further forms a metal layer M3 by sputtering, and patterns the metal layer M3 and the silicon oxide layer SiO_3 together by photolithography ( S149 ).

[0114] Next, the method uses the metal layer M3 (gate 125) as a mask to reduce the resistance of the source / drain region of the IGZO layer (S150). The resistance can be reduced by exposing the source / drain region of the IGZO layer to He plasma. The resistance can also be reduced by injecting B, Ar or H ions. Next, the method forms a silicon oxide layer SiO_4 (S151). Next, the method opens a via by anisotropically etching the silicon oxide layers SiO_2 and SiO_4 (S152).

[0115] Next, the method forms a metal layer M4 by sputtering and patterns the metal layer M4 by photolithography (S153). For example, the metal layer M4 can be formed by depositing and patterning a conductive (e.g., Ti, Al, Ti) film. The metal layer M4 can have a single-layer structure or be made of a metal different from these metals. The metal layer M4 includes electrodes 127 and 129, and through holes (coating or filling the inner part of the vias) for connecting the electrodes 127 and 129 to the source / drain 111 of the oxide semiconductor TFT and the source / drain 107 of the low-temperature polysilicon TFT.

[0116] Example 4

[0117] Described is a construction example of a low-temperature polysilicon TFT and an oxide semiconductor TFT, whose source / drain are connected to each other through a through hole. The semiconductor film of one of the low-temperature polysilicon TFT and the oxide semiconductor TFT is arranged higher than the semiconductor film of the other TFT, and the parts overlapping each other when viewed from the stacked structure direction are connected by a through hole passing through the insulating film therebetween. The through hole is made of the semiconductor of the upper semiconductor film. Below, an example is described in which the oxide semiconductor film is arranged in the upper layer.

[0118] Fig.11A The cross-sectional structure of the low-temperature polysilicon TFT 516 and the oxide semiconductor TFT 566 whose source / drain are connected to each other through a through hole is shown. Figure 3 The difference between the construction examples shown in Figure 3 In the configuration example in , a low-temperature polysilicon layer and an IGZO layer (oxide semiconductor layer) are formed on the same insulating layer (insulating substrate 101). Fig.11A In the example shown in , these layers are formed on different insulating layers.

[0119] The junction 153 between the low-temperature polysilicon TFT 516 and the oxide semiconductor TFT 566 includes a through hole 142 that passes through the interlayer insulating film 119. The through hole 142 is made of low-resistance IGZO. The source / drain 111 and 113 and the channel 109 of the oxide semiconductor TFT 566 are formed on the interlayer insulating film 119. The source / drain 113 of the oxide semiconductor TFT 566 and the source / drain 105 of the low-temperature polysilicon TFT 516 are connected through the through hole 142.

[0120] When viewed from the stacked structure direction, the through hole 142 contacts and interconnects the source / drain 105 (part thereof) of the low-temperature polysilicon TFT 516 and the source / drain 113 (part thereof) of the oxide semiconductor TFT 566. When viewed from the stacked structure direction, a portion (first portion) of the source / drain 105 of the low-temperature polysilicon TFT 516, a portion (second portion) of the source / drain 113 of the oxide semiconductor TFT 566, and the through hole 142 overlap each other.

[0121] The gate insulating film 117 of the oxide semiconductor TFT 566 is included in the silicon oxide layer SiO_3. The interlayer insulating film 121 covering the oxide semiconductor TFT 566 and the silicon oxide layer SiO_2 covering the low-temperature polysilicon TFT 516 are included in the silicon oxide layer SiO_4.

[0122] Fig. 12A Is manufacturing Fig.11A A flowchart of an example of a method of constructing an example is shown in FIG. Steps S161 to S164 are Figure 4 The steps S101 to S104 in the flowchart of are the same. After step S164, the method forms a silicon oxide layer SiO_2 by CVD (S165). Next, the method opens a via hole for the joint 153 in the silicon oxide layer SiO_2 by anisotropic etching (S166).

[0123] Next, the method forms an IGZO layer by sputtering and patterns the IGZO layer by photolithography (S167). The IGZO layer includes an IGZO film of the oxide semiconductor TFT 566 and coats or fills the inner portion of the via hole of the joint 153. Next, the method forms a silicon oxide layer SiO_3 by CVD (S168), further forms a metal layer M2 by sputtering, and patterns the metal layer M2 and the silicon oxide layer SiO_3 together by photolithography (S169).

[0124] Next, the method uses the metal layer M2 (gate 125) as a mask to reduce the resistance of the source / drain region of the IGZO layer (S170). The resistance can be reduced by exposing the source / drain region of the IGZO layer to He plasma. The resistance can also be reduced by injecting B, Ar or H ions. In addition to the resistance of the source / drain 111 and 113, this process also reduces the resistance of the through hole 142.

[0125] Next, the method forms a silicon oxide layer SiO_4 by CVD (S171). Next, the method opens a via hole by anisotropically etching the silicon oxide layers SiO_2 and SiO_4 (S172).

[0126] Next, the method forms a metal layer M3 by sputtering and patterns the metal layer M3 by photolithography (S173). For example, the metal layer M3 can be formed by depositing and patterning a conductive (e.g., Ti, Al, Ti) film. The metal layer M3 can have a single-layer structure or be made of a metal different from these metals. The metal layer M3 includes electrodes 127 and 129, and through holes (coating or filling the inner part of the vias) for connecting the electrodes 127 and 129 to the source / drain 111 of the oxide semiconductor TFT and the source / drain 107 of the low-temperature polysilicon TFT.

[0127] Fig. 11B Other cross-sectional structures of low-temperature polysilicon TFTs and oxide semiconductor TFTs whose source / drain electrodes are connected to each other through through holes are shown. Fig.11A The difference between the construction examples shown in Fig. 11B In the configuration example in , the metal silicide films 341 and 342 are provided at the contact surfaces of the vias between the low resistance LTPS portion and the metal portion and between the low resistance LTPS portion and the low resistance IGZO portion.

[0128] The metal silicide film reduces the contact resistance at the contact surface of the low resistance LTPS part and the low resistance IGZO part. The metal silicide film can be a layer of a mixture of at least one of the component elements of the low resistance IGZO, indium, gallium and zinc, and silicon and metal elements. The metal element can be molybdenum or titanium.

[0129] Fig. 12B Is manufacturing Fig. 11B A flowchart of an example method of constructing an example is shown in FIG. Fig. 12AAfter the steps S161 to S166 that are substantially the same as those in the method, the method forms a metal layer by sputtering (S261). The metal film may be a molybdenum or titanium film. When the metal film is formed, an interface reaction generates a metal silicide film at the contact surface between the low resistance LTPS and the metal film in the via. The interface reaction may be accelerated by annealing the metal film at about 200° C. to 300° C. to enhance the formation of the metal silicide film.

[0130] Next, the method removes the metal film by wet etching (S262). After etching, the metal silicide film remains on the surface of the low resistance LTPS in the via hole. Next, the method performs Fig. 12A The steps after step S167 in the above are substantially the same steps. In addition to the annealing at about 200° C. to 300° C., the TFT substrate may also be subjected to a temperature history of about 200° C. to 300° C., for example, when a SiO film is formed thereon. The formation of metal silicide is enhanced at high temperatures.

[0131] By the above-mentioned manufacturing method, a metal silicide film is generated at the contact surface between the low resistance LTPS part and the low resistance IGZO part in the via hole. The metal silicide further reduces the contact resistance at the contact surface between the low resistance LTPS part and the low resistance IGZO part. The metal silicide film can be a layer of a mixture of at least one of the component elements of the low resistance IGZO, indium, gallium and zinc, and silicon and metal elements. The metal element can be molybdenum or titanium. This structure in which the metal silicide film is arranged at the contact surface between the low resistance LTPS part and the low resistance IGZO part is not only applicable to Fig. 11B The present invention is not limited to the configuration shown in the specification, but is applicable to all configurations described in this specification.

[0132] Still another configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are connected to each other through a through hole is described. Fig.13 The cross-sectional structure of the low-temperature polysilicon TFT 516 and the oxide semiconductor TFT 566 whose sources and drains are connected to each other through a through hole is shown.

[0133] In this configuration example, the interlayer insulating film has a multilayer structure. Fig.11A The difference of the configuration example shown in is that the interlayer insulating film is composed of a lower film 120 and an upper film 119 from the bottom (from the side closer to the insulating substrate 101). The lower film 120 is included in the silicon nitride layer SiN_1 and the upper film 119 is included in the silicon oxide layer SiO_2.

[0134] Fig.14 Is manufacturing Fig.13 A flowchart of an example method of constructing an example is shown in FIG. Fig. 12AThe difference of the flowchart is that step S175 of forming a silicon nitride layer SiN_1 is added before step S165 of forming a silicon oxide layer SiO_2. Through this process, the interlayer insulating film can have a laminated structure in which two layers of a silicon nitride layer SiN_1 and a silicon oxide layer SiO_2 are laminated in this order.

[0135] Still another configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are connected to each other through a through hole is described. Fig.15 The cross-sectional structure of the low-temperature polysilicon TFT 516 and the oxide semiconductor TFT 566 whose sources and drains are connected to each other through a through hole is shown.

[0136] In this configuration example, the interlayer insulating film has a multilayer structure. Fig.13 The difference of the configuration example shown in FIG. 5 is that the lower film 120 of the silicon nitride layer SiN_1 is patterned into a shape covering the gate electrode 123 of the low-temperature polysilicon TFT 516 .

[0137] Fig.16 Is manufacturing Fig.15 A flowchart of an example method of constructing an example is shown in FIG. Fig. 12A The difference from the flowchart is that step S177 of forming and patterning the silicon nitride layer SiN_1 is added before step S165 of forming the silicon oxide layer SiO_2. By this process, the interlayer insulating film can have a structure in which the lower film of the interlayer insulating film is patterned into a shape covering the gate 123 of the low-temperature polysilicon TFT 516.

[0138] Although not shown in the drawings, the interlayer insulating film may have a structure in which three layers of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are stacked in this order from the bottom (from the side closer to the insulating substrate 101) or two layers of a silicon oxide film and a silicon nitride film are stacked in this order.

[0139] In the aforementioned construction example, the low temperature polysilicon layer and the oxide semiconductor layer are formed on different insulating layers. The characteristics of the low temperature polysilicon TFT and the oxide semiconductor TFT can be controlled separately by controlling the thickness of these layers. In addition, the storage capacitor can be configured with a low resistance polysilicon film, a low resistance oxide semiconductor film and an insulating film therebetween.

[0140] Example 5

[0141] A configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are connected to each other through a laminated via and a metal film is described. Fig.17 The cross-sectional structure of the low-temperature polysilicon TFT 518 and the oxide semiconductor TFT 568 whose source / drain electrodes are connected to each other through a through hole and a lamination of a metal film is shown. Fig.11AThe difference is the configuration example shown in .

[0142] The junction 155 between the low temperature polysilicon TFT 518 and the oxide semiconductor TFT 568 includes a metal film 144. The metal film 144 is included in the metal layer M2. The metal film 144 may be made of the same material as the gates 123, 125 and the electrodes 127, 129 or have the same structure. The metal film 144 may be made of a different material than the gates 123, 125 and any of the electrodes 127, 129 or have a different structure. The gate 125 of the oxide semiconductor TFT 568 is included in the metal layer M3. The electrodes 127 and 129 are included in the metal layer M4.

[0143] When viewed from the stacked structure direction, the metal layer 144 is disposed between the source / drain 105 (part thereof) and the through hole 142 of the low temperature polysilicon TFT 518, and contacts and interconnects them. The junction 155 has a laminated structure including a film of low resistance LTPS, a metal, and low resistance IGZO. The metal film 144 ensures stable contact between the source / drain 105 and the through hole 142.

[0144] Fig.18 Is manufacturing Fig.17 A flowchart of an example of a method of constructing an example is shown in FIG. Steps S181 to S186 are Fig. 12A The steps S161 to S166 in the flowchart of are the same. After step S186, the method forms a metal layer M2 by sputtering and patterns the metal layer M2 by photolithography (S187). Through these processes, a metal film 144 is prepared in the via hole.

[0145] Next, the method forms an IGZO layer by sputtering and patterns the IGZO layer by photolithography (S188). The IGZO layer includes an IGZO film of the oxide semiconductor TFT 568 and coats or fills the inner portion of the via hole of the joint 155. Next, the method forms a silicon oxide layer SiO_3 by CVD (S189), further forms a metal layer M3 by sputtering, and patterns the metal layer M3 and the silicon oxide layer SiO_3 together by photolithography (S190).

[0146] Next, the method uses the metal layer M3 (gate 125) as a mask to reduce the resistance of the source / drain region of the IGZO layer (S191). The resistance can be reduced by exposing the source / drain region of the IGZO layer to He plasma. The resistance can also be reduced by injecting B, Ar or H ions. In addition to the resistance of the source / drain 111 and 113, this process also reduces the resistance of the through hole 142.

[0147] Next, the method forms a silicon oxide layer SiO_4 by CVD (S192). Next, the method opens a via hole by anisotropically etching the silicon oxide layers SiO_2 and SiO_4 (S193).

[0148] Next, the method forms a metal layer M4 by sputtering and patterns the metal layer M4 by photolithography (S194). For example, the metal layer M4 can be formed by depositing and patterning a conductive (e.g., Ti, Al, Ti) film. The metal layer M4 can have a single-layer structure or be made of a metal different from these metals. The metal layer M4 includes electrodes 127 and 129, and through holes (coating or filling the inner part of the vias) for connecting the electrodes 127 and 129 to the source / drain 111 of the oxide semiconductor TFT and the source / drain 107 of the low-temperature polysilicon TFT.

[0149] Example 6

[0150] The foregoing embodiments describe the construction of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain are connected to each other through a through hole. Compared to those constructions, a portion 352 of the low-resistance IGZO in the through hole is connected to the low-resistance LTPS, and a portion 351 of the low-resistance IGZO corresponding to the source / drain of the oxide semiconductor TFT can be formed as separate patterns respectively when they are no longer continuous with each other. The portions 351 and 352 of the low-resistance IGZO are interconnected through an electrode 353 of the metal layer M3.

[0151] Because the silicon nitride film includes enough hydrogen to neutralize the dangling bond defects in the polysilicon, ordinary low-temperature polysilicon TFTs use a silicon nitride film (formed by plasma CVD) as an interlayer insulating film. The silicon nitride film includes hydrogen at a concentration of 20 to 30% atomic; this hydrogen diffuses downward into the polysilicon and bonds to the dangling bonds to neutralize the defects.

[0152] At the same time, the hydrogen diffuses into the low-resistance IGZO in contact with the low-temperature polysilicon in the via. Fig.13 As shown in the figure, the low-resistance IGZO in contact with the low-resistance LTPS in the via is continuous with the low-resistance IGZO of the source / drain of the oxide semiconductor TFT, and the hydrogen diffused into the low-resistance IGZO in the via can diffuse into the low-resistance IGZO of the source / drain and further into the IGZO of the channel.

[0153] In this case, the resistance of the IGZO in the channel may be reduced to weaken the function of the TFT (the TFT may be turned off). Fig.19In the structure, part 352 of the low resistance IGZO connected to the low resistance LTPS in the via hole is separated from part 351 of the low resistance IGZO corresponding to the source / drain of the oxide semiconductor TFT; accordingly, hydrogen does not diffuse into the channel IGZO to achieve reliable TFT operation.

[0154] Fig. 20 Is manufacturing Fig.19 A flowchart of an example of a method of constructing an example is shown in FIG. Fig.14 The flowchart of FIG. 1 describes steps S161 to S166. After step S166, the method forms an IGZO film by photolithography and patterns the IGZO film (S265). In this process, the IGZO film connected to the LTPS in the via hole and the IGZO film as the source / drain of the oxide semiconductor TFT form separate patterns. Then, the method performs the same Fig.14 The same processing as steps S168 to S172 in the flowchart.

[0155] Next, the method forms a metal layer M3 by sputtering and patterns the metal layer M3 by photolithography (S266). For example, the metal layer M3 can be formed by depositing and patterning a conductive (e.g., Ti, Al, Ti) film. The metal layer M3 can have a single-layer structure or be made of a metal different from these metals. The electrode 353 of the metal layer M3 connects a portion 351 of the low-resistance IGZO corresponding to the source / drain of the oxide semiconductor TFT and a portion 352 of the low-resistance IGZO, which is connected to the low-resistance LTPS of the source / drain of the low-temperature polysilicon TFT in the via.

[0156] Example 7

[0157] Still another configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are connected to each other through a through hole is described. Fig.21 The cross-sectional structure of the low-temperature polysilicon TFT 520 and the oxide semiconductor TFT 570 whose source / drain are connected to each other through a through hole is shown. Fig.11A The difference is the configuration example shown in .

[0158] The oxide semiconductor TFT 570 has a bottom gate structure. The gate 126 is disposed above and in contact with the insulating film 118. The insulating film 118 is included in the silicon oxide layer SiO_1. The gate 126 is disposed on a layer lower than the channel 109 in such a manner that the gate 126 and the channel 109 overlap when viewed from the stacking direction. The gate insulating film 122 between the gate 126 and the channel 109 is included in the silicon oxide layer SiO_2 together with the interlayer insulating film 119.

[0159] The insulating film 134 is provided on a layer above the channel 109 so that the insulating film 134 and the channel 109 overlap when viewed in the stacking direction. Fig.21 In the example of FIG. 1 , the insulating film 134 covers and contacts the channel 109. In the process of reducing the resistance to prepare the source / drain 111 and 113, the insulating film 134 functions as a mask.

[0160] The gate electrode 123 of the low temperature polysilicon TFT 520 and the gate electrode 126 of the oxide semiconductor TFT 570 are both included in the metal layer M1. The electrodes 127 and 129 are included in the metal layer M2.

[0161] Fig. 22 Is manufacturing Fig.21 The flowchart of the example of the method of constructing the example is shown in FIG. Steps S201 and S202 are Fig.18 The steps S181 and S182 in the flowchart of are the same. After step S202, the method forms a metal layer M1 by sputtering, and patterns the metal layer M1 together with the silicon oxide layer SiO_1 by photolithography (S203). Through these processes, the gate 123 and the gate insulating film 115 of the low-temperature polysilicon TFT 520 and the gate 126 and the insulating film 118 of the oxide semiconductor TFT 570 are prepared.

[0162] Next, the method uses the gate 123 (metal layer M1) as a mask, dopes the source / drain region of the polysilicon film with impurities, and activates the impurities. In addition, the method terminates dangling bonds by hydrogenation (S204). Next, the method forms a silicon oxide layer SiO_2 (S205).

[0163] Next, the method opens a via hole for the junction 153 in the silicon oxide layer SiO_2 by anisotropic etching (S206). Next, the method forms an IGZO layer by sputtering and patterns the IGZO layer by photolithography (S207). The IGZO layer includes an IGZO film of the oxide semiconductor TFT 570 and coats or fills the inner portion of the via hole of the junction 153.

[0164] Next, the method forms a silicon oxide layer SiO_3 and patterns the silicon oxide layer SiO_3 by photolithography (S208). Through these treatments, an insulating film 134 is prepared on the oxide semiconductor film. Next, the method uses the insulating film 134 (silicon oxide layer SiO_3) as a mask to reduce the resistance of the source / drain region of the IGZO layer (S209). The resistance can be reduced by exposing the source / drain region of the IGZO layer to He plasma or injecting B, Ar or H ions. In addition to the resistance of the source / drain 111 and 113, the treatment also reduces the resistance of the through hole 142.

[0165] Next, the method forms a silicon oxide layer SiO_4 by CVD (S210). Next, the method opens via holes in the silicon oxide layers SiO_2 and SiO_4 by anisotropic etching (S211).

[0166] Next, the method forms a metal layer M2 by sputtering and patterns the metal layer M2 by photolithography (S212). For example, the metal layer M2 can be formed by depositing and patterning a conductive (e.g., Ti, Al, Ti) film. The metal layer M2 can have a single-layer structure or be made of a metal different from these metals. The metal layer M2 includes electrodes 127 and 129, and also includes through holes (coating or filling the inner part of the vias) for connecting the electrodes 127 and 129 to the source / drain 111 of the oxide semiconductor TFT and the source / drain 107 of the low-temperature polysilicon TFT.

[0167] Example 8

[0168] Still another configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are in direct contact with each other is described. Fig.23 The cross-sectional structure of the low-temperature polysilicon TFT 522 and the oxide semiconductor TFT 572 whose source / drain electrodes are in direct contact with each other is shown. Figure 3 The difference is the configuration example shown in .

[0169] Fig.23 The configuration example in includes a low-resistance IGZO film 114 between the source / drain 107 and the through hole 130 of the low-temperature polysilicon TFT 522. The low-resistance IGZO film 114 is on the same layer as the source / drain 111 and 113 of the oxide semiconductor TFT 572, and is formed together with them in the same process. When viewed from the stacked structure direction, the low-resistance IGZO film 114 is located between the source / drain 107 (part thereof) and the through hole 130 of the low-temperature polysilicon TFT 522, and is in contact with and interconnected with them. The through hole 130 is provided to connect the electrode 129 and the source / drain 107, and is continuous from the electrode 129.

[0170] In the case where the low-resistance IGZO film 114 is not provided, the manufacturing method may include a process of removing silicon oxide generated on the surface of the source / drain 107 of the low-temperature polysilicon TFT 522 by hydrofluoric acid (HF treatment) after opening via holes in the silicon oxide layers SiO_2 and SiO_3. In the HF treatment, the source / drain 111 of the oxide semiconductor TFT 572 is also exposed to hydrofluoric acid. Since the oxide semiconductor is not highly resistant to hydrofluoric acid, the source / drain 111 may be etched.

[0171] exist Fig.23The low-resistance IGZO film 114 in the configuration example in eliminates the necessity for HF treatment. Fig.23 The source / drain 107 of the low-temperature polysilicon TFT 522 in the construction example in is not exposed to the through hole and is covered with the low-resistance IGZO film 114. When the via hole is formed in the silicon oxide layers SiO_2 and SiO_3, the low-resistance IGZO film 114 is contacted by the etchant while the source / drain 107 is not contacted. Therefore, the HF treatment for removing the silicon oxide on the surface of the source / drain 107 can be eliminated.

[0172] Still another configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are connected to each other through a through hole is described. Fig.24 The cross-sectional structure of the low-temperature polysilicon TFT 524 and the oxide semiconductor TFT 574 whose source / drain are connected to each other through a through hole is shown. Fig.21 The difference is the configuration example shown in .

[0173] Fig.24 The configuration example in includes a low-resistance IGZO film 116 between the source / drain 107 of the low-temperature polysilicon TFT 524 and the through hole 130. The low-resistance IGZO film 116 is on the same layer as the source / drain 111 and 113 of the oxide semiconductor TFT 574, and is formed together with them in the same process. When viewed from the stacking direction, the low-resistance IGZO film 116 is located between the source / drain 107 (part thereof) of the low-temperature polysilicon TFT 524 and the through hole 130, and is in contact with and interconnected with them. The through hole 130 is provided to connect the electrode 129 and the source / drain 107, and is continuous from the electrode 129.

[0174] exist Fig.24 The low-resistance IGZO film 116 in the configuration example in Fig.23 The low-resistance IGZO film 114 shown in FIG. 1 eliminates the necessity of HF treatment for removing silicon oxide on the surface of the source / drain 107 .

[0175] Example 9

[0176] Another configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT is described, in which the source / drain electrodes are in direct contact with each other. Figure 7 The configuration example described below includes a silicon nitride film covering at least a portion of a polysilicon TFT and a silicon oxide film provided between the silicon nitride film and the oxide semiconductor TFT. The silicon nitride film eliminates the need for hydrogenation treatment on polysilicon and the silicon oxide film prevents hydrogen in the silicon nitride film from diffusing into the oxide semiconductor film.

[0177] Fig.25 The cross-sectional structure of the low-temperature polysilicon TFT 526 and the oxide semiconductor TFT 576 whose sources and drains are in direct contact with each other is shown. Fig.25 The configuration example in includes a silicon nitride film 120 provided over and in contact with portions of the source / drain 107 and the source / drain 105. The silicon nitride film 120 is an interlayer insulating film.

[0178] Fig.25 The configuration example in includes another interlayer insulating film 119 made of silicon oxide between the source / drain 113 (oxide semiconductor film) of the oxide semiconductor TFT 576 and the silicon nitride film 120. The silicon nitride film 120 is covered with the interlayer insulating film 119 and the oxide semiconductor film is separated from the silicon nitride film 120. The junction 150 is located between the interlayer insulating film 119 and the interlayer insulating film 121 (outer than the interlayer insulating film 119).

[0179] The silicon nitride film 120 allows elimination of hydrogenation treatment on the low temperature polysilicon film. The interlayer insulating film 119 functions as a barrier film to prevent hydrogen in the silicon nitride film 120 from diffusing into the oxide semiconductor film.

[0180] Fig.26 Is manufacturing Fig.25 The flowchart of the example of the method of constructing the example is shown in FIG. Steps S221 to S223 are Figure 8 The steps S121 to S123 in the flowchart of are the same as those in the step S124. The step S224 does not include the hydrogenation treatment in the step S124. After the step S224, the method forms a silicon nitride film by CVD and patterns the silicon nitride film by photolithography (S225). As the silicon nitride film is formed, hydrogen is supplied to the low temperature polysilicon film. The steps S226 to S233 are the same as those in the step S234. Figure 8 Steps S125 to S132 in the flowchart are the same.

[0181] Example 10

[0182] Still another configuration example of a low-temperature polysilicon TFT and an oxide semiconductor TFT whose source / drain electrodes are in direct contact with each other is described. Fig. 27 The cross-sectional structure of the low-temperature polysilicon TFT 528 and the oxide semiconductor TFT 578 whose source / drain electrodes are in direct contact with each other is shown. Figure 3 In the configuration example of Embodiment 1 shown in FIG. 1 , the formation order of the low-temperature polysilicon film and the oxide semiconductor film is reversed. The formation order of the low-temperature polysilicon film and the oxide semiconductor film may be reversed from that of other embodiments.

[0183] The oxide semiconductor TFT 578 includes source and drain electrodes 411 and 413, and a channel 409 sandwiched between the source / drain electrodes 411 and 413 in the in-plane direction. The source / drain electrodes 411 and 413 are made of IGZO that reduces resistance. The channel 409 is made of IGZO that does not reduce resistance. The source / drain electrodes 411 and 413 and the channel 409 (semiconductor film) are included in the oxide semiconductor layer. The oxide semiconductor layer is directly formed on the insulating substrate 101. Although Fig. 27 The source / drain 411 and 413 and the channel 409 in the example are in contact with the insulating substrate 101, and another insulating layer (such as a silicon nitride layer) may be provided therebetween.

[0184] The oxide semiconductor TFT 578 also includes a gate 425 and a gate insulating film 417, which are inserted between the gate 425 and the channel 409 in the stacking direction. The channel 409, the gate insulating film 417 and the gate 425 are stacked in this order from the bottom (from the substrate side), and the gate insulating film 417 is in contact with the channel 409 and the gate 425. The gate 425 is made of metal and is included in the metal layer M1. The gate insulating film 417 in this example is made of silicon oxide and is included in the silicon oxide layer SiO_1. Although in Fig. 27 The oxide semiconductor TFT 578 in the example has a top gate structure, but the oxide semiconductor TFT 578 may have a bottom gate structure.

[0185] The low-temperature polysilicon TFT 528 includes a source and a drain 405 and 407, and a channel 403 sandwiched between the source / drain 405 and 407 in the in-plane direction. The source / drain 405 and 407 are made of low-temperature polysilicon that reduces resistance by doping with high-concentration impurities. The channel 403 is made of low-temperature polysilicon that does not reduce resistance. The source / drain 405 and 407 and the channel 403 (semiconductor film) are included in the low-temperature polysilicon layer. The low-temperature polysilicon layer is directly formed on the insulating substrate 101. Although Fig. 27 The source / drain 405 and 407 and the channel 403 in the example are in contact with the insulating substrate 101, and another insulating layer (such as a silicon nitride layer) may be provided therebetween.

[0186] The low temperature polysilicon TFT 528 further includes a gate 423 and a gate insulating film 415, which is inserted between the gate 423 and the channel 403 in the stacking direction. The channel 403, the gate insulating film 415 and the gate 423 are stacked in this order from the bottom (from the substrate side), and the gate insulating film 415 is in contact with the channel 403 and the gate 423. The gate 423 is made of metal and is included in the metal layer M2. The gate insulating film 415 in this example is made of silicon oxide and is included in the silicon oxide layer SiO_2. Although in Fig. 27The low-temperature polysilicon TFT 528 in the example has a top gate structure, and the low-temperature polysilicon TFT 528 may have a bottom gate structure.

[0187] The source / drain 413 of the oxide semiconductor TFT 578 and the source / drain 405 of the low-temperature polysilicon TFT 528 are connected at the junction 450. At the junction 450, a portion of the source / drain 413 of the oxide semiconductor TFT 578 and a portion of the source / drain 405 of the low-temperature polysilicon TFT 528 overlap and stack each other. When viewed from the stacking direction, these portions are stacked and they are in direct contact with each other. Fig. 27 In the example of FIG. 5 , one end of the source / drain 405 of the low-temperature polysilicon TFT 528 is located higher than one end of the source / drain 413 of the oxide semiconductor TFT 578 .

[0188] The interlayer insulating film 419 covers and contacts the channel 403 and source / drain electrodes 405 and 407 of the low-temperature polysilicon TFT 428, and further covers and contacts the oxide semiconductor TFT 578. The interlayer insulating film 419 in this example is made of silicon oxide and is included in the silicon oxide layer SiO_2.

[0189] The interlayer insulating film 421 is provided over the interlayer insulating film 419 and covers the low-temperature polysilicon TFT 528 and the oxide semiconductor TFT 578 (which covers the interlayer insulating film 419 interposed therebetween). The interlayer insulating film 421 in this example is made of silicon oxide and is included in the silicon oxide layer SiO_3.

[0190] The electrode 429 is disposed above the interlayer insulating film 421 and is connected to the source / drain 407 of the low-temperature polysilicon TFT 528 through a via formed in the interlayer insulating films 419 and 421. The through hole inside the via interconnects the electrode 429 and the source / drain 407. The electrode 429 and the through hole are made of the same metal. The electrode 429 is made of metal and is included in the metal layer M3.

[0191] The electrode 427 is disposed above the interlayer insulating film 421 and is connected to the source / drain 411 of the oxide semiconductor TFT 578 through a via formed in the interlayer insulating films 419 and 421. The through hole inside the via interconnects the electrode 427 and the low resistance LTPS film 414 on the source / drain 411. The electrode 427 and the through hole are made of the same metal. The electrode 427 is made of metal and is included in the metal layer M3. The insulating layer may be made of a material other than silicon oxide (such as silicon nitride).

[0192] Fig.28 Is manufacturing Fig. 27Flowchart of an example of a method of constructing an example shown in . The method forms an IGZO layer by sputtering and patterns the IGZO layer by photolithography (S241). Next, the method forms a silicon oxide layer SiO_1 by CVD (S242), further forms a metal layer M1 by sputtering, and patterns the metal layer M1 and the silicon oxide layer SiO_1 together by photolithography (S243).

[0193] Next, the method deposits an amorphous silicon film by CVD and patterns the amorphous silicon film by photolithography (S244). The method crystallizes the amorphous silicon film by excimer laser annealing (ELA) to prepare a (low temperature) polysilicon film, and further reduces the source / drain region of the IGZO layer using the metal layer M1 (gate 425) as a mask (S245).

[0194] Next, the method dopes the source / drain region of the polysilicon film with impurities and activates the impurities. In addition, the method terminates dangling bonds by hydrogenation (S246). Next, the method forms a silicon oxide layer SiO_2 (S247). Next, the method forms a metal layer M2 by sputtering and patterns the metal layer M2 by photolithography (S248). The materials and structures of gates 423 and 425 can be the same as those in Example 1.

[0195] Next, the method forms a silicon oxide layer SiO_3 (S249). Next, the method opens vias in the silicon oxide layers SiO_2 and SiO_3 by anisotropic etching (S250). Next, the method forms a metal layer M3 by sputtering and patterns the metal layer M3 by photolithography (S251). The metal layer M3 includes electrodes 427 and 429, and through holes (coating or filling the inner part of the vias) for connecting the electrodes 427 and 429 to the source / drain 411 of the oxide semiconductor TFT and the source / drain 407 of the low-temperature polysilicon TFT. The materials and structures of the electrodes 427 and 429 and the through holes can be the same as those in Example 1.

[0196] As explained above, the embodiments of the present disclosure are described; however, the present disclosure is not limited to the aforementioned embodiments. Those skilled in the art can easily modify, add or change each element used in the aforementioned embodiments within the scope of the present disclosure. A part of the construction of one embodiment can be replaced with the construction of another embodiment, or the construction of one embodiment can be incorporated into the construction of another embodiment.

Claims

1. A thin film device comprising: Polysilicon components; as well as Oxide semiconductor device, wherein the polysilicon element comprises a first portion made of low-resistance polysilicon, wherein the oxide semiconductor element includes a second portion made of a low-resistance oxide semiconductor, The first portion is included in a polysilicon film, the second portion is included in an oxide semiconductor film, and the polysilicon film and the oxide semiconductor film are directly provided on a common insulating layer, The polysilicon element is a polysilicon thin film transistor. wherein the oxide semiconductor element is an oxide semiconductor thin film transistor, wherein the first portion is included in the source / drain of the polysilicon thin film transistor, and the resistance of the source / drain of the polysilicon thin film transistor is lower than the resistance of the channel of the polysilicon thin film transistor, wherein the second portion is included in a source / drain of the oxide semiconductor thin film transistor, the resistance of the source / drain of the oxide semiconductor thin film transistor is lower than the resistance of a channel of the oxide semiconductor thin film transistor, and The first portion and the second portion are arranged to overlap each other and be connected without a through hole. 2 . The thin film device according to claim 1 , wherein the first portion is in direct contact with the second portion. 3 . The thin film device according to claim 1 , wherein the first portion and the second portion are connected via a metal film interposed therebetween. 4 . The thin film device according to claim 1 , wherein ions are implanted into the first portion and the second portion to reduce contact resistance. 5 . The thin film device according to claim 1 , wherein the first portion is connected to the second portion with a metal silicide film interposed therebetween. 6 . The thin film device according to claim 5 , wherein the metal silicide film is a layer of a mixture of at least one of the component elements of the oxide semiconductor, a silicon element, and a metal element.

7. The thin film device according to claim 1, The polysilicon thin film transistor includes a gate disposed above a channel with a gate insulating film interposed therebetween. wherein the gate is covered with an interlayer insulating film, and Part of the interlayer insulating film covers part of the source / drain of the oxide semiconductor thin film transistor.

8. The thin film device according to claim 1, wherein the polysilicon thin film transistor comprises a second source / drain different from the source / drain of the polysilicon thin film transistor, and The second source / drain is connected to the metal film through a low-resistance oxide semiconductor film made of the same material as the second portion.

9. The thin film device according to claim 1, further comprising: a silicon nitride film covering at least a portion of the polysilicon thin film transistor; as well as A silicon oxide film is provided between the silicon nitride film and the oxide semiconductor thin film transistor.

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