Display device

Abstract

Disclosed is a display device including: a substrate including a display area and a peripheral area located outside the display area, the peripheral area including a pad area; a test circuit unit disposed within the pad area; a cover layer covering the test circuit unit; an output pad disposed within the pad area and arranged between the test circuit unit and the display area; an input pad disposed within the pad area, disposed at an opposite side with respect to the output pad; and a protection layer covering the output pad and the input pad, and on a plane, an end portion of the protection layer is separated from the cover layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0069554, filed on June 12, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device. Background Technology

[0003] With the rapid development of display devices for visually representing various electrical signal information, a variety of flat panel display devices with excellent characteristics such as thinness, light weight, and low power consumption have been researched and developed. These display devices can display images in response to signals applied by driving integrated circuits (ICs).

[0004] Typically, driver ICs can be electrically connected to display devices via chip-on-glass (COG), tape-on-coat (TCP), or chip-on-film (COF) methods. The COG method has a simpler structure than the TCP or COF methods and is therefore widely used.

[0005] In the COG method, after placing the driver IC on the display panel with the circuit pattern formed thereon, the driver IC is heated and pressed, and then directly mounted onto the display panel. Therefore, when mounting the driver IC using the COG method, pressure is applied to the display panel. This can potentially damage the display panel. Summary of the Invention

[0006] According to one or more embodiments, a display device is provided in which the occurrence of damage to the display panel is minimized or reduced when a driver integrated circuit (IC) is mounted using a chip-on-glass (COG) method.

[0007] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practice of the disclosed embodiments.

[0008] According to one or more embodiments, a display device includes: a substrate including a display area and a peripheral area located outside the display area, the peripheral area including a pad area; a test circuit unit disposed within the pad area; a cover layer covering the test circuit unit; an output pad disposed within the pad area and arranged between the test circuit unit and the display area; an input pad disposed within the pad area on a side opposite to the output pad, with the test circuit unit located between the input pad and the output pad; and a protective layer covering the output pad and the input pad, wherein, in a plane, the ends of the protective layer are separated from the cover layer.

[0009] The test circuit unit may include multiple transistors, and the gate electrodes of the multiple transistors may be electrically connected to each other.

[0010] The gate electrode can be configured as a gate line extending in a first direction.

[0011] The display device may also include multiple data lines extending in a second direction perpendicular to the first direction to pass through the display area, wherein each of the multiple transistors is electrically connected to a corresponding data line among the multiple data lines.

[0012] The display device may further include: a driver chip including input bumps and output bumps, and mounted on a pad region; and an adhesive insulating resin layer in which conductive balls are dispersed, the adhesive insulating resin layer being disposed between the pad region and the driver chip, wherein the input bumps are electrically connected to the input pad and the output bumps are electrically connected to the output pad by means of the conductive balls.

[0013] The driver chip can be placed on the cover layer.

[0014] Each of the multiple transistors may also include a source electrode and a drain electrode disposed on a gate electrode, an interlayer insulating layer may be disposed between the gate electrode and the source electrode and the drain electrode, and an input pad and an output pad may be disposed on the interlayer insulating layer.

[0015] Between the end of the protective layer and the cover layer, the interlayer insulation layer can be in direct contact with the adhesive insulating resin layer.

[0016] The display device may further include: a display panel, including a substrate; and an input sensing unit located on the display panel, wherein the input sensing unit includes a first touch insulating layer disposed on the display panel, a bridging wire disposed on the first touch insulating layer, a second touch insulating layer disposed on the bridging wire, and a first sensing electrode and a second sensing electrode disposed on the second touch insulating layer, and the protective layer includes at least one of the first touch insulating layer and the second touch insulating layer.

[0017] The display device may further include: an additional output pad disposed on the protective layer and connected to the output pad; and an additional input pad disposed on the protective layer and connected to the input pad, wherein the additional output pad and the additional input pad may comprise the same material as the first sensing electrode and the second sensing electrode.

[0018] According to one or more embodiments, a display device includes: a display panel; an input sensing unit disposed on the display panel; and a driver chip mounted on the display panel, wherein the display panel includes: a substrate including a display area and a peripheral area located outside the display area, the peripheral area including a pad area; a test circuit unit disposed within the pad area; a cover layer covering the test circuit unit; an output pad disposed within the pad area and arranged between the test circuit unit and the display area; and an input pad disposed on a side opposite to the output pad, with the test circuit unit located between the input pad and the output pad, wherein the driver chip is disposed on the cover layer, an input bump of the driver chip is electrically connected to the input pad, and an output bump of the driver chip is electrically connected to the output pad.

[0019] The display panel may also include a protective layer covering the output pads and input pads, and the ends of the protective layer around the cover layer may be separated from the cover layer.

[0020] The input sensing unit may include: a first touch insulating layer disposed on the display panel; a bridging wire located on the first touch insulating layer; a second touch insulating layer located on the bridging wire; and a first sensing electrode and a second sensing electrode located on the second touch insulating layer. The protective layer may include at least one of the first touch insulating layer and the second touch insulating layer.

[0021] The display panel may further include: an additional output pad disposed on the protective layer and connected to the output pad; and an additional input pad disposed on the protective layer and connected to the input pad, wherein the additional output pad and the additional input pad may comprise the same material as the first sensing electrode and the second sensing electrode.

[0022] The display panel may also include: a thin-film transistor disposed within the display area; an organic light-emitting device electrically connected to the thin-film transistor; and a planarization layer located between the thin-film transistor and the organic light-emitting device, wherein the protective layer may include the same material as the planarization layer.

[0023] The test circuit unit may include multiple transistors, and the gate electrodes of the multiple transistors may be configured as gate lines extending in a first direction.

[0024] The display panel may also include multiple data lines extending in a second direction perpendicular to the first direction to pass through the display area, and each of the multiple transistors may be electrically connected to a corresponding data line among the multiple data lines.

[0025] The display device may also include an adhesive insulating resin layer in which conductive balls are dispersed, the adhesive insulating resin layer being disposed between the pad area and the driver chip, wherein, by using the conductive balls, input bumps can be electrically connected to input pads and output bumps can be electrically connected to output pads.

[0026] Each of the multiple transistors may also include a source electrode and a drain electrode disposed on a gate electrode, an interlayer insulating layer may be disposed between the gate electrode and the source electrode and the drain electrode, and an input pad and an output pad may be disposed on the interlayer insulating layer.

[0027] Between the end of the protective layer and the cover layer, the interlayer insulation layer can be in direct contact with the adhesive insulating resin layer.

[0028] Other aspects, features, and advantages will be apparent from the following drawings, the following description, and the claims. Attached Figure Description

[0029] The above and other aspects, features, and advantages of certain embodiments disclosed will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 This is a plan view illustrating an example of a display device according to an embodiment;

[0031] Figure 2 It is shown Figure 1 A plan view of an example display panel of a display device;

[0032] Figure 3 It is along Figure 2 A sectional view taken by line I-I';

[0033] Figure 4 It is shown Figure 1 A floor plan of area "A";

[0034] Figure 5 It is along Figure 4 A sectional view taken from line II-II';

[0035] Figure 6 It is shown Figure 2 A plan view of area "B"; and

[0036] Figure 7 It is along Figure 6 The sectional view taken from line III-III'. Detailed Implementation

[0037] Because this disclosure allows for various modifications and numerous embodiments, some exemplary embodiments will be shown in the accompanying drawings and described in more detail in the following description. The effects and features of this disclosure, and how they can be obtained, will become apparent from the embodiments described later in more detail with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below, but can be implemented in various forms.

[0038] It will be understood that although terms such as "first," "second," etc., can be used to describe various components, these components should not be limited by these terms. Rather, these terms are used to distinguish one component from another.

[0039] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “one,” and “the” are also intended to include the plural forms.

[0040] It will also be understood that the term “comprising” and / or variations thereof as used herein indicates the presence of the stated feature or component, but does not preclude the presence or addition of one or more other features or components.

[0041] It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, that layer, region, or component may be formed directly or indirectly on said other layer, region, or component. That is, for example, there may be one or more intermediate layers, intermediate regions, or intermediate components.

[0042] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the accompanying drawings may be arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0043] When an embodiment can be implemented differently, the specific process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described sequence.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments of the inventive concept pertain. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the context of the relevant field, and not as having an idealized or overly formal meaning.

[0045] Here, some exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Throughout the drawings, the same or corresponding components may have the same reference numerals.

[0046] Figure 1 This is a plan view illustrating an example of a display device according to an embodiment.

[0047] Reference Figure 1 The display device 10 may include a display panel 100 and an input sensing unit 200 disposed on the display panel 100.

[0048] The display panel 100 can display images. The input sensing unit 200 may include a first sensing electrode 210 and a second sensing electrode 230, and can sense the contact of an external touch input unit (such as a user's hand or pen) to generate an input signal.

[0049] The first sensing electrodes 210 can be connected to each other in the first direction X, and form a plurality of first sensing electrode arrays. In addition, the plurality of first sensing electrode arrays can be separated from each other in the second direction Y, which is perpendicular to the first direction X, and can be arranged parallel to each other.

[0050] The second sensing electrode 230 can be disposed between the first sensing electrode 210 in the first direction X and the second direction Y, and can be connected to each other in directions intersecting with the plurality of first sensing electrode arrays.

[0051] exist Figure 1 In the illustration, each of the first sensing electrode 210 and the second sensing electrode 230 is shown to have a rhomboid shape. However, the embodiment is not limited to this, and each of the first sensing electrode 210 and the second sensing electrode 230 may have any shape of various shapes.

[0052] Figure 2 It is shown Figure 1 A plan view of an example display panel of a display device; Figure 3 It is along Figure 2 A sectional view taken from line I-I'.

[0053] Reference Figure 2 and Figure 3 The display panel 100 may include a display area DA in which an image is displayed and a peripheral area PA located outside the display area DA. For example, the substrate 101 has a display area DA and a peripheral area PA.

[0054] Multiple display elements can be disposed in the display area DA. In the example, the multiple display elements can be organic light-emitting display devices (OLEDs) and can emit red, green, blue, or white light. The peripheral area PA can include pad (also called "soldering pad") areas PADA, to which various electronic devices or printed circuit boards (PCBs) such as driver integrated circuits (ICs) are electrically attached.

[0055] Figure 2This is a plan view showing the appearance of the substrate 101 during the manufacturing process of the display panel 100. In electronic devices (such as the final manufactured display panel 100 or a smartphone including the display panel 100), a portion of the substrate 101 can be bent to minimize or reduce the area of ​​the peripheral region PA that is perceived by the user. For example, the substrate 101 can be bent between the pad region PADA and the display region DA, such that at least a portion of the pad region PADA can overlap with the display region DA. In this case, the direction of bending can be set in such a way that the pad region PADA does not obscure the display region DA, but rather, the pad region PADA is located behind the display region DA. Therefore, the user perceives the display region DA as occupying the display device (see...). Figure 1 Most of the 10).

[0056] In an embodiment, each of the left and right ends of the display area DA can be bent to have an outwardly convex shape. Therefore, it can be recognized that when viewing the display device from the front (see...),... Figure 1 When 10), in the display device (see 10), Figure 1 There are no borders at both ends of 10), and the display area DA can be expanded.

[0057] Figure 3 It is shown Figure 2 The image shows a cross-sectional view of a portion of the display panel 100, illustrating an example in which the OLED 180 is used as a display device. However, embodiments are not limited thereto, and the display panel 100 may include different types of display devices, such as liquid crystal devices.

[0058] In this embodiment, substrate 101 may be a flexible plastic substrate. For example, substrate 101 may include polymeric resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. However, substrate 101 may be modified in various ways such that substrate 101 may include, for example, glass or metal.

[0059] A thin-film transistor (TFT) is disposed in the display area DA of the substrate 101. In addition to the TFT, an OLED 180 electrically connected to the TFT is also disposed in the display area DA of the substrate 101. The pixel electrode 181 of the OLED 180 is electrically connected to the TFT. In an embodiment, the TFT (not shown) may be disposed in the peripheral area PA of the substrate 101. For example, the TFT disposed in the peripheral area PA may be part of a circuit unit for controlling electrical signals applied to the display area DA.

[0060] A thin-film transistor (TFT) may include a semiconductor layer 111, a gate electrode 113, a source electrode 115a, and a drain electrode 115b. The semiconductor layer 111 may include amorphous silicon, polycrystalline silicon, or an organic semiconductor material. To prevent or substantially prevent impurities from penetrating into the substrate 101, a buffer layer 110 comprising an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) may be disposed on the substrate 101, and the semiconductor layer 111 may be disposed on the buffer layer 110.

[0061] A gate electrode 113 may be disposed above the semiconductor layer 111. A source electrode 115a and a drain electrode 115b are electrically connected to each other in response to a signal applied to the gate electrode 113. In embodiments, the gate electrode 113 may comprise at least one material from the group consisting of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may have a single-layer or multi-layer structure. In this case, to obtain insulating properties between the semiconductor layer 111 and the gate electrode 113, a gate insulating layer 120 comprising an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride) may be located between the semiconductor layer 111 and the gate electrode 113.

[0062] Interlayer insulating layer 130 may be disposed on gate electrode 113. Interlayer insulating layer 130 may include inorganic materials (such as silicon oxide, silicon nitride, or silicon oxynitride) and may have a single-layer structure or a multilayer structure.

[0063] Source electrode 115a and drain electrode 115b are disposed on interlayer insulating layer 130. Each of source electrode 115a and drain electrode 115b can be electrically connected to semiconductor layer 111 via contact holes formed in interlayer insulating layer 130 and gate insulating layer 120. Considering conductivity, for example, source electrode 115a and drain electrode 115b can comprise at least one material selected from the group consisting of Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W and Cu, and can have a single-layer structure or a multilayer structure.

[0064] The planarization layer 140 can be disposed on the thin-film transistor TFT. For example, as... Figure 3 As shown, when the OLED 180 is disposed on the thin-film transistor TFT, the planarization layer 140 can cover the thin-film transistor TFT to provide a flat surface. The planarization layer 140 may include organic materials such as acrylic resin, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). Although Figure 3A planarization layer 140 with a single-layer structure is shown, but various modifications are possible so that the planarization layer 140 can have a multi-layer structure.

[0065] An OLED 180, including a pixel electrode 181, a counter electrode 183, and an intermediate layer 185 between the pixel electrode 181 and the counter electrode 183, can be disposed on a planarization layer 140. The intermediate layer 185 may include an emission layer.

[0066] Pixel electrode 181 can be disposed on planarization layer 140. Pixel electrode 181 can contact one of source electrode 115a and drain electrode 115b through an opening in planarization layer 140, and can be electrically connected to thin-film transistor TFT.

[0067] Pixel electrode 181 can be a (semi-)transparent electrode or a reflective electrode. When pixel electrode 181 is a (semi-)transparent electrode, it can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), In₂O₃, indium gallium oxide (IGO), or aluminum-doped zinc oxide (AZO). In an embodiment, when pixel electrode 181 is a reflective electrode, it can include a reflective layer comprising any material of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and mixtures thereof, and a layer comprising ITO, IZO, ZnO, In₂O₃, or AZO. Pixel electrode 181 can include any of the various materials, and various modifications are possible, wherein pixel electrode 181 can have a single-layer structure or a multi-layer structure.

[0068] A pixel defining layer 150 may be disposed on the planarization layer 140. The pixel defining layer 150 may have an opening corresponding to each pixel (i.e., at least the center of the pixel electrode 181 is exposed through its opening), thereby defining the pixel. Furthermore, as... Figure 3 As shown, the pixel defining layer 150 can increase the distance between the end of the pixel electrode 181 and the counter electrode 183 on the pixel electrode 181, thereby preventing or substantially preventing electric arcing at the end of the pixel electrode 181. The pixel defining layer 150 may include an organic material, such as polyimide or HMDSO.

[0069] The intermediate layer 185 of the OLED 180 may comprise a low molecular weight material or a polymer material. When the intermediate layer 185 comprises a low molecular weight material, it may have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and / or an electron injection layer (EIL) are stacked, and may comprise any of various organic materials such as copper phthalocyanine (CuPc), N,N'-di(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), and tris(8-hydroxyquinoline aluminum) (Alq3)). These layers may be formed using methods such as vacuum deposition.

[0070] When the intermediate layer 185 comprises a polymeric material, for example, the intermediate layer 185 may have a structure including an HTL and an EML. In this case, the HTL may comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may comprise polymeric materials such as polyphenylenevinylene (PPV) and polyfluorene. In embodiments, the intermediate layer 185 may be formed using screen printing, inkjet printing, or laser-induced thermal imaging (LITI). The intermediate layer 185 may have any of the various structures.

[0071] The counter electrode 183 is configured to correspond to the display area DA. That is, the counter electrode 183 can be integrally formed to correspond to multiple OLEDs 180. The counter electrode 183 can be a (semi-)transparent electrode or a reflective electrode. When the counter electrode 183 is a (semi-)transparent electrode, the counter electrode 183 can have a layer comprising a metal with a small work function (e.g., any material such as lithium (Li), calcium (Ca), lithium fluoride (LiF) / Ca, LiF / Al, Ag, Mg, and mixtures thereof) and a (semi-)transparent conductive layer (such as ITO, IZO, ZnO, or In2O3). When the counter electrode 183 is a reflective electrode, the counter electrode 183 can have a layer comprising any material such as Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and mixtures thereof. However, the construction and materials of the counter electrode 183 are not limited thereto, and various modifications are possible.

[0072] A capping layer 160 may be disposed on the counter electrode 183. The capping layer 160 can improve the efficiency of light generated in the OLED 180, for example, the efficiency of light extraction to the outside. To improve light efficiency, the capping layer 160 may comprise at least one organic or inorganic material selected from the group consisting of silicon oxide, silicon nitride, zinc oxide, titanium oxide, zirconium oxide, indium tin oxide, indium zinc oxide, Alq3, CuPc, CBP, and α-NPB.

[0073] An encapsulation layer 500 can be disposed on the cap layer 160. The encapsulation layer 500 can protect the OLED 180 from external moisture or oxygen. For this purpose, the encapsulation layer 500 can extend within the display area DA in which the OLED 180 is disposed and within the peripheral area PA outside the display area DA. In an embodiment, as... Figure 3 As shown, the encapsulation layer 500 may have a multi-layer structure. In an embodiment, the encapsulation layer 500 may include a first inorganic encapsulation layer 510, an organic encapsulation layer 520, and a second inorganic encapsulation layer 530.

[0074] In an embodiment, the first inorganic encapsulation layer 510 may cover the capping layer 160 and may include any material of silicon oxide, silicon nitride, and silicon oxynitride. Figure 3 As shown, since the first inorganic encapsulation layer 510 is formed along the structure below it, its top surface will be uneven.

[0075] In an embodiment, because the organic encapsulation layer 520 can cover the first inorganic encapsulation layer 510 and can have sufficient thickness, the top surface of the organic encapsulation layer 520 can be substantially flat throughout the entire display area DA. In an embodiment, the organic encapsulation layer 520 may comprise at least one material selected from the group consisting of polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane.

[0076] In this embodiment, the second inorganic encapsulation layer 530 may cover the organic encapsulation layer 520 and may include any material of silicon oxide, silicon nitride, and silicon oxynitride. The second inorganic encapsulation layer 530 may extend outside the organic encapsulation layer 520 and may contact the first inorganic encapsulation layer 510, such that the organic encapsulation layer 520 may not be exposed to the outside.

[0077] In this way, the encapsulation layer 500 may include a first inorganic encapsulation layer 510, an organic encapsulation layer 520, and a second inorganic encapsulation layer 530. Therefore, through this multilayer structure, even if cracks occur in the encapsulation layer 500, these cracks will not connect between the first inorganic encapsulation layer 510 and the organic encapsulation layer 520, or between the organic encapsulation layer 520 and the second inorganic encapsulation layer 530. Thus, the formation of pathways for external moisture or oxygen to permeate into the display area DA can be prevented or substantially prevented, or the formation of such pathways can be minimized or reduced.

[0078] When forming the encapsulation layer 500, the underlying structure may be damaged. For example, the first inorganic encapsulation layer 510 may be formed using chemical vapor deposition (CVD). When the first inorganic encapsulation layer 510 is formed using CVD, the layers on which the first inorganic encapsulation layer 510 is formed may be damaged. Therefore, when the first inorganic encapsulation layer 510 is formed directly on the capping layer 160, the capping layer 160, which improves the efficiency of light generation in the OLED 180, may be damaged, causing the display device (see...) to... Figure 1 The light efficiency of (10) may deteriorate. Therefore, in an embodiment, to prevent or substantially prevent damage to the capping layer 160 during the formation of the encapsulation layer 500, a protective layer 170 may be located between the capping layer 160 and the encapsulation layer 500. In an embodiment, the protective layer 170 may include LiF.

[0079] Figure 4 It is shown Figure 1 A floor plan of area "A"; Figure 5 It is along Figure 4 The sectional view taken from line II-II'.

[0080] Reference Figure 4 and Figure 5 Input sensing unit (see) Figure 1 The 200) can be directly formed on the display panel (see Figure 1 On 100). For example, the input sensing unit (see 100). Figure 1 The 200) can be directly formed on the encapsulation layer 500. Therefore, the display device (see Figure 1 The thickness of 10) can be reduced. In another example, in the input sensing unit (see...) Figure 1 After the 200 is formed on the substrate (not shown), the substrate (not shown) can be bonded to the encapsulation layer 500.

[0081] The first sensing electrode 210 and the second sensing electrode 230 may include a transparent conductive layer. The transparent conductive layer may include a transparent conductive oxide, such as ITO, IZO, ZnO, or indium tin zinc oxide (ITZO). In an embodiment, the transparent conductive layer may include a conductive polymer, such as any one of PEDOT, metal nanowires, and graphene. In another example, the first sensing electrode 210 and the second sensing electrode 230 may include an opaque metal layer. In an embodiment, for light transmittance, the first sensing electrode 210 and the second sensing electrode 230 may have a mesh shape.

[0082] Two first sensing electrodes 210 that are adjacent to each other in the first direction X can be connected to each other using a connecting portion 220. The connecting portion 220 can be disposed on the same layer as the first sensing electrodes 210. The connecting portion 220 can be integrally formed with the first sensing electrodes 210.

[0083] Two second sensing electrodes 230 that are adjacent to each other in a second direction Y perpendicular to the first direction X can be connected to each other using a bridging wire 240. The bridging wire 240 can be disposed on a different layer from the first sensing electrode 210 and the second sensing electrode 230. In an embodiment, the bridging wire 240 can be disposed below the first sensing electrode 210 and the second sensing electrode 230.

[0084] For example, such as Figure 5 As shown, this is used to improve the encapsulation layer 500 and the input sensing unit (see...). Figure 1 A first touch insulating layer 201, which strengthens the adhesion between the first and second touch insulating layers (200) can be formed on the encapsulation layer 500, and a bridging wire 240 is disposed on the first touch insulating layer 201. Furthermore, a second touch insulating layer 203 can be formed on the bridging wire 240, and a first sensing electrode 210 and a second sensing electrode 230 can be disposed on the second touch insulating layer 203. In this case, the bridging wire 240 and the second sensing electrode 230 can be electrically connected to each other via contact holes (CNTs) formed in the second touch insulating layer 203. In an embodiment, the first touch insulating layer 201 and the second touch insulating layer 203 may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0085] In an embodiment, a third touch insulating layer 205 may be formed on the first sensing electrode 210 and the second sensing electrode 230. In an example, the third touch insulating layer 205 may include at least one selected from acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, polyurethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0086] Because the bridging wire 240 and the connecting portion 220 intersect each other, the width of the bridging wire 240 (measured in the plane) can be minimized or reduced to decrease the parasitic capacitance between the bridging wire 240 and the connecting portion 220. In an embodiment, the bridging wire 240 may comprise a material having a lower resistance than the second sensing electrode 230 to improve sensitivity. For example, the bridging wire 240 may comprise any material of Mo, Ag, Ti, Cu, Al, and their alloys.

[0087] In an embodiment, such as Figure 4 and Figure 5 As shown, the bridging wire 240 is disposed on a layer lower than the layer of the connection portion 220. However, the embodiment is not limited to this; in another embodiment, the bridging wire 240 may be disposed on a layer higher than the layer of the connection portion 220. In this embodiment, two or more bridging wires 240 may be formed.

[0088] In an embodiment, a dummy pattern may be provided between the first sensing electrode 210 and the second sensing electrode 230. Each dummy pattern has a floating state in which it is not connected to the first sensing electrode 210 or the second sensing electrode 230. The dummy pattern can be formed on the same layer as the first sensing electrode 210 and the second sensing electrode 230, thereby reducing the visibility of the boundary region between the first sensing electrode 210 and the second sensing electrode 230.

[0089] Figure 6 It is shown Figure 2 Plan view of area "B". Figure 7 It is along Figure 6 The sectional view taken from line III-III'.

[0090] Reference Figure 6 and Figure 7 The test circuit unit (or test circuit) TCA can be located in the pad area PADA, and the test circuit unit TCA can include multiple transistors TT. The multiple transistors TT can be transistors used to test whether the pixels are working properly.

[0091] In an embodiment, each of the plurality of transistors TT may have a display area (see [link]). Figure 2 Thin-film transistors within the DA (see DA) Figure 3 The structure is the same as that of a TFT. In an embodiment, each of the plurality of transistors TT may include a semiconductor layer 320 comprising amorphous silicon, polycrystalline silicon or organic semiconductor material, a gate electrode 341 on the semiconductor layer 320, a source electrode 361 connected to the semiconductor layer 320 and a drain electrode 362.

[0092] Each of the multiple transistors TT can be electrically connected to extend in the second direction Y to pass through the display area (see Figure 2 The gate electrodes 341 of the multiple data lines DL of the DA) can be connected to each other. That is, the gate electrodes 341 of the multiple transistors TT can be configured as a single gate line extending in the first direction X. Therefore, when an electrical signal is simultaneously (e.g., synchronously) applied to the connected gate electrodes 341 of the multiple transistors TT, a channel is simultaneously (e.g., synchronously) formed in the semiconductor layer 320 of the multiple transistors TT. In this way, when the multiple transistors TT are synchronously turned on, the electrical signal from the test signal line 368 can be transmitted to the multiple data lines DL, and the display area (see Figure 2 The electrical connection in the DA (Data Line 1) to multiple data lines DL (Data Line 2) allows the pixels to emit light to check for defects in the pixels in the display area DA.

[0093] The drain electrode 362 of transistor TT can be connected to the corresponding data line DL via a connection line 343. In an embodiment, the connection line 343 may include the same material as the gate electrode 341 and may be disposed on the same layer as the gate electrode 341. Furthermore, the source electrode 361 of transistor TT can be connected to a test signal line 368 extending in the first direction X. In an example, the source electrode 361 may be an integral component with the test signal line 368.

[0094] like Figure 6 and Figure 7 As shown, multiple output pads 365 and input pads 366 can be arranged in the pad area PADA.

[0095] Multiple output pads 365 can be arranged in the first direction X on the test circuit unit TCA and the display area (see...) Figure 2 Between the DA). Each of the plurality of output pads 365 may be disposed on and in contact with a corresponding connection line 343. In an embodiment, each of the plurality of output pads 365 may comprise the same material as the source electrode 361 and drain electrode 362 of transistor TT, and may be connected to the connection line 343 via a contact hole formed in the interlayer insulating layer 130.

[0096] Multiple input pads 366 may be disposed on the side opposite to multiple output pads 365, and a test circuit unit (TCA) is provided between the multiple input pads 366 and the multiple output pads 365. The multiple input pads 366 may be arranged in a first direction X. In an embodiment, each of the multiple input pads 366 may include the same material as the multiple output pads 365 and may be disposed on the same layer as the multiple output pads 365.

[0097] Output pad 365 and input pad 366 may be covered by protective layer 204. Protective layer 204 may include at least one of a first touch insulating layer 201 and a second touch insulating layer 203. Therefore, here, "first touch insulating layer 201 and second touch insulating layer 203," "first touch insulating layer 201," or "second touch insulating layer 203" may be used to refer to protective layer 204. Figure 7 In the diagram, both the first touch insulating layer 201 and the second touch insulating layer 203 are shown covering the output pad 365 and the input pad 366. However, the embodiment is not limited to this; either the first touch insulating layer 201 or the second touch insulating layer 203 may cover the output pad 365 and the input pad 366. In an embodiment, an additional input pad 374 and an additional output pad 372 may be formed on the second touch insulating layer 203 to overlap with the input pad 366 and the output pad 365.

[0098] An additional input pad 374 can be connected to an input pad 366 via contact holes formed in the first touch insulating layer 201 and the second touch insulating layer 203, and an additional output pad 372 can be connected to an output pad 365 via contact holes formed in the first touch insulating layer 201 and the second touch insulating layer 203. In an embodiment, the additional input pad 374 and the additional output pad 372 may include an input sensing unit (see...) Figure 1 The first sensing electrode of (200) (see Figure 4 210) and the second sensing electrode (see Figure 4 The same material as 230).

[0099] Additional input pads 374 and 372 can be connected to a driver chip 400 mounted on the pad area PADA. The driver chip 400 includes a body 410, an output bump 420, and an input bump 430. Figure 7 In the diagram, driver chip 400 shows one output bump 420 and one input bump 430. However, driver chip 400 may include multiple output bumps 420 and multiple input bumps 430. For example, driver chip 400 may be an integrated circuit (IC) chip.

[0100] Additional input pad 374 can be connected to input bump 430 of driver chip 400, and additional output pad 372 can be connected to output bump 420 of driver chip 400. Therefore, when the display device (see...) Figure 1 10) In actual operation, the electrical signal from the driver chip 400 can be transmitted from the output bump 420 via the output pad 365 and the connection line 343 to the data line DL, and finally to the display area (see...). Figure 2 Multiple pixels in the DA). Regarding the pixels that will be displayed in the display area (see DA). Figure 2 The image information implemented in the DA (Data Access Controller) can be input to the driver chip 400 via the input bump 430. Therefore, in this embodiment, the display device (see...) Figure 1 10) may include another input pad 367 connected to input pad 366. A printed circuit board (PCB) may be electrically connected to the other input pad 367.

[0101] After the anisotropic conductive film, in which conductive balls 440 are dispersed in the adhesive insulating resin layer 450, is inserted between the driver chip 400 and the pad region PADA, the driver chip 400 can be pressed and mounted on the pad region PADA at high temperature. In this case, the conductive balls 440 can send current to the input bump 430 and the additional input pad 374, and can send current to the output bump 420 and the additional output pad 372. Without forming the additional input pad 374 and the additional output pad 372, the input bump 430 and the output bump 420 can be connected to the input pad 366 and the output pad 365 via the conductive balls 440.

[0102] like Figure 7 As shown, when the input bump 430 of the driver chip 400 is electrically connected to the input pad 366 and the output bump 420 of the driver chip 400 is electrically connected to the output pad 365, the driver chip 400 is disposed on the test circuit unit TCA. Therefore, to prevent or substantially prevent damage to the transistor TT during the mounting of the driver chip 400, the test circuit unit TCA may be covered by a cover layer (or cover portion) 142. In an embodiment, the cover layer 142 may be combined with a planarization layer (see...) Figure 3 It is formed together with the formation of 140), and may include a planarization layer (see Figure 3 The same material as 140).

[0103] In an embodiment, when the first touch insulating layer 201 and the second touch insulating layer 203 are formed on the entire pad region PADA to cover the cover layer 142, the first touch insulating layer 201 and the second touch insulating layer 203 on the cover layer 142 are compressed by the conductive balls 440 during the mounting of the driver chip 400. Therefore, damage (such as cracks) may occur in the first touch insulating layer 201 and the second touch insulating layer 203. Furthermore, when moisture penetrates into the cover layer 142 through cracks, the cover layer 142 thermally expands, causing interface separation between the first touch insulating layer 201 and the interlayer insulating layer 130 near the cover layer 142. The penetrated moisture moves to the adjacent output pad 365, causing damage to the display area (see...). Figure 2 To achieve fine dark spots or dark lines in DA).

[0104] Therefore, to prevent or substantially prevent this problem, in an embodiment, a valley V is formed around the cover layer 142 in the pad region PADA. Thus, even when the cover layer 142 expands, interface separation between the first touch insulating layer 201 and the interlayer insulating layer 130 can be avoided. In an embodiment, the valley V may be disposed at least between the test circuit unit TCA and the plurality of output pads 365 and between the test circuit unit TCA and the plurality of input pads 366.

[0105] The valley V can be a region in which a portion of the first touch insulating layer 201 and a portion of the second touch insulating layer 203 are removed, and in the valley V, the interlayer insulating layer 130 can be in direct contact with the adhesive insulating resin layer 450. However, the embodiment is not limited to this. As described above, the first touch insulating layer 201 or the second touch insulating layer 203 can cover the output pad 365 and the input pad 366. In this case, the valley V can be formed by removing a portion of the first touch insulating layer 201 or a portion of the second touch insulating layer 203. In the embodiment, an additional insulating layer in addition to the first touch insulating layer 201 and the second touch insulating layer 203 can be formed to cover the output pad 365 and the input pad 366. In this case, the valley V can be formed by removing the first touch insulating layer 201, the second touch insulating layer 203, and the additional insulating layer.

[0106] To mount the driver chip 400 on the pad area PADA, the driver chip 400 is thermo-pressed. This generates stress in the substrate 101, allowing it to bend under applied force. This stress may concentrate on the concave valleys V. Therefore, cracks may occur in the interlayer insulating layer 130 at points corresponding to the valleys V. The cracks may propagate along the interlayer insulating layer 130, potentially causing damage to the display panel (see...). Figure 2 In the 100). Therefore, in the embodiment, the valley V is formed in the following position: when the driver chip 400 is installed, it can be directed to the display panel (see 100). Figure 2 The position where the minimum stress is applied (100%).

[0107] Table 1 below shows the results of measuring the stress applied to the substrate 101 during the mounting of the driver chip 400, based on the distance between the cover layer 142 and the valley V. Here, the distance between the cover layer 142 and the valley V is the distance between the end of the cover layer 142 and the starting point of the valley V. The cover layer 142 and the valley V, which are separated from each other, refer to the first touch insulating layer 201 and the second touch insulating layer 203 disposed between the cover layer 142 and the valley V.

[0108] Table 1

[0109]

[0110] In Table 1 above, Example 1 shows a case where the valley V is not formed. However, as mentioned above, when the valley V is not formed, small dark spots or lines will appear in the display area (see Table 1). Figure 2 In the DA). Therefore, in the embodiment, a valley V is formed.

[0111] Comparing Examples 2 to 6 with each other, as the distance between the cover layer 142 and the valley V increases, the magnitude of the stress occurring at the location corresponding to the valley V increases. Therefore, as... Figure 7 As shown, the valley V can be formed after the end of the cover layer 142. This means that the first touch insulating layer 201 and the second touch insulating layer 203 are not present between the end of the cover layer 142 and the valley V, and in the plane, the ends of the first touch insulating layer 201 and the ends of the second touch insulating layer 203 are separated from the cover layer 142.

[0112] In this way, when the valley V is located after the end of the cover layer 142, the stress concentrated on the valley V during the mounting of the driver chip 400 can be alleviated by the cover layer 142 formed of organic material. Therefore, even when the valley V, which is used to prevent or substantially prevent the appearance of fine dark spots or dark lines, is formed in the display area (see...), the stress can be reduced. Figure 2 When installing the driver chip 400 in the DA), the display panel (see) Figure 1 Damage in 100% can also be minimized or reduced. Figure 7 An example is shown in which the first touch insulating layer 201 and the second touch insulating layer 203 are not formed on the cover layer 142. However, when the valley V is formed around the cover layer 142, the aforementioned problem does not occur even if damage occurs in the first touch insulating layer 201 and the second touch insulating layer 203 on the cover layer 142. Therefore, when the valley V is formed, the first touch insulating layer 201 and the second touch insulating layer 203 can be formed on the cover layer 142.

[0113] According to embodiments of this disclosure, a display device is provided in which the occurrence of damage to the display panel during the installation of a driver IC can be minimized or reduced.

[0114] It will be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope set forth in the claims.

Claims

1. A display device, the display device comprising: The substrate includes a display area and a peripheral area located outside the display area, the peripheral area including a pad area; The test circuit unit is disposed within the pad area; A cover layer is applied to cover the test circuit unit. An output pad is disposed within the pad area and arranged between the test circuit unit and the display area; An input pad is disposed within the pad area, positioned on the opposite side of the output pad in a second direction, and the test circuit unit is located between the input pad and the output pad. as well as A protective layer covers the output pad and the input pad. Wherein, on the plane, the ends of the protective layer and each of the input pads are separated from the cover layer along the second direction, and The second direction is the direction in which the output pad, the test circuit unit, and the input pad are arranged sequentially.

2. The display device according to claim 1, wherein, The test circuit unit includes multiple transistors, and The gate electrodes of the plurality of transistors are electrically connected to each other.

3. The display device according to claim 2, wherein, The gate electrode is configured as a gate line extending in a first direction perpendicular to the second direction.

4. The display device according to claim 3, further comprising a plurality of data lines extending in the second direction to pass through the display area, wherein, Each of the plurality of transistors is electrically connected to a corresponding data line among the plurality of data lines.

5. The display device according to claim 2, further comprising: The driver chip includes input bumps and output bumps, and is disposed on the pad region; as well as An adhesive insulating resin layer, in which conductive balls are dispersed, is disposed between the pad region and the driver chip. The input bump is electrically connected to the input pad via the conductive ball, and the output bump is electrically connected to the output pad via the conductive ball.

6. The display device according to claim 5, wherein, The driver chip is disposed on the cover layer.

7. The display device according to claim 5, wherein, Each of the plurality of transistors further includes a source electrode and a drain electrode, the source electrode and the drain electrode being disposed on the gate electrode. An interlayer insulating layer is disposed between the gate electrode and the source electrode and the drain electrode, and The input pad and the output pad are disposed on the interlayer insulation layer.

8. The display device according to claim 1, further comprising: Display panel, including the substrate; And an input sensing unit, located on the display panel, The input sensing unit includes: a first touch insulating layer disposed on the display panel; a bridging wire located on the first touch insulating layer; a second touch insulating layer located on the bridging wire; and a first sensing electrode and a second sensing electrode located on the second touch insulating layer. The protective layer includes at least one of the first touch insulating layer and the second touch insulating layer.

9. The display device according to claim 8, further comprising: An additional output pad is disposed on the protective layer and connected to the output pad; And an additional input pad, disposed on the protective layer and connected to the input pad, The additional output pad and the additional input pad are made of the same material as the first sensing electrode and the second sensing electrode.

10. A display device, the display device comprising: Display panel; An input sensing unit is disposed on the display panel; as well as The driver chip is mounted on the display panel, wherein... The display panel includes: The substrate includes a display area and a peripheral area located outside the display area, the peripheral area including a pad area; The test circuit unit is disposed within the pad area; A cover layer is applied to cover the test circuit unit. An output pad is disposed within the pad area and arranged between the test circuit unit and the display area; and An input pad is disposed on the opposite side of the output pad in a second direction, and the test circuit unit is located between the input pad and the output pad, wherein... The driver chip is disposed on the cover layer, and the input bumps of the driver chip are electrically connected to the input pad, and the output bumps of the driver chip are electrically connected to the output pad. On a flat surface, the input pad is separated from the cover layer along the second direction. The second direction is the direction in which the output pad, the test circuit unit, and the input pad are arranged sequentially.

11. The display device according to claim 10, wherein, The display panel also includes a protective layer covering the output pad and the input pad, and the ends of the protective layer around the cover layer are separated from the cover layer.

12. The display device according to claim 11, wherein, The input sensing unit includes: a first touch insulating layer disposed on the display panel; a bridging wire located on the first touch insulating layer; a second touch insulating layer located on the bridging wire; and a first sensing electrode and a second sensing electrode located on the second touch insulating layer. The protective layer includes at least one of the first touch insulating layer and the second touch insulating layer.

13. The display device according to claim 12, wherein, The display panel further includes: an additional output pad disposed on the protective layer and connected to the output pad; and an additional input pad disposed on the protective layer and connected to the input pad. The additional output pad and the additional input pad are made of the same material as the first sensing electrode and the second sensing electrode.

14. The display device according to claim 11, wherein, The display panel further includes: a thin-film transistor disposed within the display area; an organic light-emitting device electrically connected to the thin-film transistor; and a planarization layer located between the thin-film transistor and the organic light-emitting device. The cover layer comprises the same material as the planarization layer.

15. The display device according to claim 10, wherein, The test circuit unit includes multiple transistors, and The gate electrodes of the plurality of transistors are configured as gate lines extending in a first direction perpendicular to the second direction.

16. The display device according to claim 15, wherein, The display panel also includes multiple data lines that extend in the second direction to pass through the display area, and Each of the plurality of transistors is electrically connected to a corresponding data line among the plurality of data lines.

17. The display device of claim 15, further comprising an adhesive insulating resin layer in which conductive balls are dispersed, the adhesive insulating resin layer being disposed between the pad region and the driving chip, and the input bump being electrically connected to the input pad via the conductive balls, and the output bump being electrically connected to the output pad via the conductive balls.

18. The display device according to claim 17, wherein, The display panel further includes a protective layer covering the output pad and the input pad, and the ends of the protective layer surrounding the cover layer are separated from the cover layer. Each of the plurality of transistors further includes a source electrode and a drain electrode, the source electrode and the drain electrode being disposed on the gate electrode. An interlayer insulating layer is disposed between the gate electrode and the source electrode and the drain electrode, and The input pad and the output pad are disposed on the interlayer insulation layer.

19. The display device according to claim 7 or claim 18, wherein, The interlayer insulation layer is in direct contact with the adhesive insulating resin layer between the end of the protective layer and the cover layer.

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