Three-dimensional flash memory device including cell gate patterns and its manufacturing method

Abstract

A three-dimensional flash memory device including cell gate patterns and a method for manufacturing the same are disclosed. The three-dimensional flash memory device is described as including a substrate, a plurality of cell gate patterns and a plurality of molded insulating layers alternately stacked on the substrate, and a vertical channel structure in contact with the side surfaces of the plurality of cell gate patterns and the side surfaces of the plurality of molded insulating layers. Each of the plurality of cell gate patterns may include a cell gate electrode and a barrier pattern adjacent to one side surface of the cell gate electrode. The inner surface of the barrier pattern may include an upper inner surface, a middle inner surface, and a lower inner surface. The middle inner surface of the barrier pattern may face one side surface of the cell gate electrode. The barrier pattern may have a portion protruding toward the cell gate electrode at the junction between the upper inner surface and the middle inner surface of the barrier pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0072284, filed on June 18, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a three-dimensional flash memory device including a cell gate pattern with a barrier pattern and a method for manufacturing the same. Background Technology

[0004] Three-dimensional flash memory devices are semiconductor devices that operate via cell gate electrodes and an electric field applied to the channel layer. If there are sharp points between the cell gate electrode (or cell gate barrier pattern) and the channel layer or charge trap layer, current will leak and the electric field will concentrate on the sharp points, potentially physically damaging the barrier pattern, charge trap layer, and / or tunnel insulation layer at the sharp points. Summary of the Invention

[0005] Embodiments of this disclosure provide a structure including a unit gate electrode having an arcuate or conical corner portion, a unit gate barrier pattern, and / or a barrier pattern, and a method of manufacturing the structure such that the electric field is not concentrated between the unit gate electrode and the channel pattern.

[0006] For example, a method has been proposed in which the nitrogen concentration in the sacrificial insulating layer used to form the unit gate electrode and unit gate barrier patterns is stepped or gradually adjusted to make the shapes of the oxidized barrier patterns different.

[0007] Embodiments of this disclosure provide a method for manufacturing a three-dimensional flash memory device.

[0008] According to an example embodiment, a three-dimensional flash memory device may include: a substrate; a plurality of cell gate patterns and a plurality of molded insulating layers alternately stacked on the substrate; and a vertical channel structure contacting the side surfaces of the plurality of cell gate patterns and the side surfaces of the plurality of molded insulating layers. Each of the plurality of cell gate patterns may include a cell gate electrode and a barrier pattern adjacent to one side surface of the cell gate electrode. The inner surface of the barrier pattern may include an upper inner surface, a middle inner surface, and a lower inner surface. The middle inner surface of the barrier pattern may face the one side surface of the cell gate electrode. The barrier pattern may have a portion protruding toward the cell gate electrode at the junction between the upper inner surface and the middle inner surface of the barrier pattern.

[0009] According to an example embodiment, a three-dimensional flash memory device may include: a substrate; a cell gate pattern and a molded insulating layer stacked on the substrate; and a vertical channel structure adjacent to the side surfaces of the cell gate pattern and the molded insulating layer. The molded insulating layer may include an insulating material. The cell gate pattern may include a cell gate electrode, a conductive inner cell gate barrier pattern, an insulating outer cell gate barrier pattern, and a barrier pattern. The conductive inner cell gate barrier pattern may surround an upper surface, a lower surface, and a side surface of the cell gate electrode. A first surface of the insulating outer cell gate barrier pattern may conformally cover the conductive inner cell gate barrier pattern. An inner surface of the barrier pattern may be located on a second surface of the insulating outer cell gate barrier pattern opposite to the first surface of the insulating outer cell gate barrier pattern. The inner surface of the barrier pattern may have an uneven shape including recessed portions. The outer surface of the barrier pattern may have a convex outer surface.

[0010] According to an example embodiment, a three-dimensional flash memory device may include: a substrate; a plurality of cell gate patterns and a plurality of molded insulating layers alternately stacked on the substrate; and a vertical channel structure contacting the side surfaces of the plurality of cell gate patterns and the side surfaces of the plurality of molded insulating layers. The plurality of molded insulating layers may include an insulating material. Each of the plurality of cell gate patterns may include a cell gate electrode and a barrier pattern surrounding one side surface of the cell gate electrode. The inner surface of the barrier pattern may include an upper inner surface, a middle inner surface, and a lower inner surface. The upper and lower inner surfaces of the inner surface of the barrier pattern may each have an uneven shape. Attached Figure Description

[0011] Figure 1 This is a longitudinal cross-sectional view of a three-dimensional flash memory device according to an embodiment.

[0012] Figures 2A to 2N This illustrates various embodiments of a cell gate pattern and a vertical channel structure. Figure 1 An enlarged view of area "A" in the image.

[0013] Figure 3A and Figures 3B to 8 These are longitudinal and enlarged views illustrating methods for forming a three-dimensional flash memory device according to various embodiments. Detailed Implementation

[0014] Figure 1 This is a longitudinal cross-sectional view showing a three-dimensional flash memory device according to an embodiment of the present disclosure.

[0015] Reference Figure 1The three-dimensional flash memory device may include a substrate 10 and a surface insulating layer 20, a lower select gate pattern 30, a lower interlayer insulating layer 25, a cell stack CS, a cover insulating layer 65, a vertical channel structure 70, an upper interlayer insulating layer 85, a via plug 90, and a bit line 95 stacked on the substrate 10. The three-dimensional flash memory device may also include a raised source region 15 located between the substrate 10 and the vertical channel structure 70.

[0016] The substrate 10 may include at least one of a single-crystal silicon wafer, a bonded silicon wafer, an epitaxially grown silicon layer, a silicon-on-insulator (SOI) wafer, a deposited polycrystalline silicon layer, a compound semiconductor such as a silicon-germanium (SiGe) layer or a silicon-carbon (SiC) layer, and other semiconducting materials.

[0017] The surface insulating layer 20 may include an insulator conformally formed on the surface of the substrate 10. For example, the surface insulating layer 20 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and combinations thereof. In embodiments, the surface insulating layer 20 may include an oxidized silicon layer. For example, the surface insulating layer 20 may be formed by partially oxidizing the surface of the substrate 10.

[0018] A lower select gate pattern 30 may be disposed between a surface insulating layer 20 and an underlying interlayer insulating layer 25. The lower select gate pattern 30 may include a lower select gate electrode 31 and a lower select gate barrier pattern 32. The lower select gate barrier pattern 32 may conformally cover or surround the upper, lower, and side surfaces of the lower select gate electrode 31. The lower select gate electrode 31 may have a substantially flat top surface, a substantially flat bottom surface, and a substantially flat side surface. The lower select gate barrier pattern 32 may also have a substantially flat top surface, a substantially flat bottom surface, and a substantially flat outer surface. The lower select gate electrode 31 may include a conductor, and the lower select gate barrier pattern 32 may include a conductive barrier material and / or an insulating barrier material.

[0019] An interlayer insulating layer 25 may be formed between the lower selected gate pattern 30 and the cell stack CS. The interlayer insulating layer 25 may include silicon oxide.

[0020] The cell stack CS may include alternately stacked cell gate patterns 40 (also referred to as gate patterns) and molded insulating layers 60 (also referred to as molded layers). Each cell gate pattern 40 may include a cell gate electrode 41 (also referred to as gate electrode 41), a cell gate barrier pattern 42 (also referred to as gate barrier pattern), and a barrier pattern 50.

[0021] The cell gate barrier pattern 42 may conformally cover or surround the top, bottom, and side surfaces of the cell gate electrode 41. The cell gate electrode 41 may have a substantially flat top surface, a substantially flat bottom surface, and substantially flat side surfaces. In an embodiment, the cell gate electrode 41 may have arcuate side surfaces. The cell gate barrier pattern 42 may also have a substantially flat top surface, a substantially flat bottom surface, and a substantially flat outer surface. In an embodiment, the cell gate barrier pattern 42 may have arcuate side surfaces. The cell gate electrode 41 may include a metal such as tungsten, and the cell gate barrier pattern 42 may include a conductive barrier pattern such as titanium nitride (TiN) and / or an insulating barrier pattern such as aluminum oxide (Al2O3).

[0022] Barrier pattern 50 may be formed on both side surfaces of cell gate barrier pattern 42. Barrier pattern 50 may be disposed between cell gate barrier pattern 42 of cell gate pattern 40 and vertical channel structure 70. Barrier pattern 50 may include an insulator such as silicon oxide.

[0023] A molded insulating layer 60 may be situated between cell gate patterns 40 and may include silicon oxide. A cover insulating layer 65 may be formed on the cell stack CS. The cover insulating layer 65 may include silicon oxide. Compared to the molded insulating layer 60, the cover insulating layer 65 and the underlying interlayer insulating layer 25 may be formed to be relatively thick.

[0024] The vertical channel structure 70 may abut (e.g., contact) the side surfaces of the overlay insulating layer 65, the cell stack CS, and the lower interlayer insulating layer 25, and may be electrically connected to the substrate 10. For example, the vertical channel structure 70 may vertically penetrate the stacked overlay insulating layer 65, the cell stack CS, and the lower interlayer insulating layer 25 to connect to a raised source region 15 rising from the substrate 10. The raised source region 15 may include an epitaxial growth layer. The vertical channel structure 70 may include a central gap fill pattern 71, a channel pattern 73 surrounding the central gap fill pattern 71, and via pads 77 located on the central gap fill pattern 71. The outer surface of the via pads 77 may contact and be electrically connected to the channel pattern 73. The central gap fill pattern 71 may be formed in a column shape, the channel pattern 73 may be cylindrical, and the via pad 77 may be disc-shaped or column-shaped. The central gap fill pattern 71 may include an insulator such as silicon oxide. The channel pattern 73 may include multiple layers of insulating and semiconductor layers. For example, the channel pattern 73 may include a silicon nitride layer, a silicon oxide layer, and a polysilicon layer. The via pad 77 may include N-doped polysilicon doped with N-type impurities such as phosphorus (P) or arsenic (As). In embodiments, the via pad 77 may also include a metal silicide layer or a metal nitride layer. For example, the lower or outer portion of the via pad 77 may include polysilicon, and the upper or inner portion may include a metal silicide layer or a metal nitride layer. The metal silicide layer may include at least one of tungsten silicide (WSi), cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), and various other metal silicides. The metal nitride layer may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), aluminum nitride (AlN), and various other metal nitrides. In a top view, the vertical channel structure 70 may have a circular shape. Therefore, in a top view, the channel pattern 73 may have a record shape, and the central gap filling pattern 71 may have a circular shape.

[0025] An upper interlayer insulating layer 85 may cover or surround the upper interlayer insulating layer 65 and the vertical channel structure 70. The upper interlayer insulating layer 85 may include silicon oxide. A via plug 90 may be connected to a via pad 77 of the vertical channel structure 70 by passing vertically through the upper interlayer insulating layer 85. The via plug 90 may include at least one of a metal, a metal nitride, and a metal silicide. A bit line 95 may be formed in a line shape on the upper interlayer insulating layer 85. The bit line 95 may be electrically connected to the vertical channel structure 70 through the via plug 90.

[0026] Figures 2A to 2N This is an illustration of various embodiments for showing the cell gate pattern 40 and the vertical channel structure 70. Figure 1 An enlarged view of area "A" in the image.

[0027] Reference Figure 2A According to an embodiment, the cell gate pattern 40 may include a cell gate electrode 41, a cell gate barrier pattern 42, and a barrier pattern 50a. The cell gate barrier pattern 42 may include an inner cell gate barrier pattern 43 (also referred to as a conductive barrier layer 43) and an outer cell gate barrier pattern 44 (also referred to as an insulating barrier layer 44). The inner cell gate barrier pattern 43 may conformally cover or surround the outer surface (e.g., top, side, and bottom surface) of the cell gate electrode 41. The inner cell gate barrier pattern 43 may include a conductive material. For example, the inner cell gate barrier pattern 43 may include a diffusion barrier material such as titanium nitride (TiN). The outer cell gate barrier pattern 44 may conformally cover or surround the outer surface (e.g., top, side, and bottom surface) of the inner cell gate barrier pattern 43. The outer cell gate barrier pattern 44 may include an insulating barrier material with a high work function (e.g., aluminum oxide (Al2O3)). The barrier pattern 50a may be disposed adjacent to one side surface of the cell gate electrode 41.

[0028] The channel pattern 73 may include a charge trapping layer 74, a tunnel insulating layer 75, and a channel layer 76. The charge trapping layer 74 may be formed on the outer surface of the barrier pattern 50a and the outer surface of the molded insulating layer 60. The charge trapping layer 74 may include an insulator with a relatively high dielectric constant to trap electrons. For example, the charge trapping layer 74 may include silicon nitride. The tunnel insulating layer 75 may include an insulator with a relatively low work function, allowing electrons to tunnel through. For example, the tunnel insulating layer 75 may include silicon oxide. The channel layer 76 may include an electron-movable semiconducting material. For example, the channel layer 76 may include an intrinsic semiconductor layer such as undoped polysilicon. In embodiments, the channel layer 76 may include P-doped polysilicon or N-doped polysilicon, wherein the P-doped polysilicon is doped with a P-type impurity including boron (B), gallium (Ga), or indium (In), and the N-doped polysilicon is doped with an N-type impurity including at least one of phosphorus (P), arsenic (As), and antimony (Sb). The channel layer 76 may be formed as a side surface surrounding the central gap filling pattern 71. The tunnel insulation layer 75 may be formed as an outer surface surrounding the channel layer 76. The charge trapping layer 74 may be formed as an outer surface surrounding the tunnel insulation layer 75.

[0029] The inner surface of the barrier pattern 50a may include an upper inner surface 50iu (also referred to as the upper sidewall surface 50iu), an intermediate inner surface 50im (also referred to as the intermediate sidewall surface 50im), and a lower inner surface 50il (also referred to as the lower sidewall surface 50il). The inner surface of the barrier pattern 50a may face the gate electrode 41 and may be opposite to the outer sidewall of the barrier pattern 50a. The upper inner surface 50iu may have a downward slope from the unit gate electrode 41 or the unit gate barrier pattern 42 to the charge trapping layer 74 of the channel pattern 73 of the vertical channel structure 70. The intermediate inner surface 50im may be substantially vertically flat. The lower inner surface 50il may have an upward slope from the unit gate electrode 41 or the unit gate barrier pattern 42 toward the charge trapping layer 74 of the channel pattern 73 of the vertical channel structure 70. For example, the upper inner surface 50iu, the middle inner surface 50im, and the lower inner surface 50il can be inclined, such that the middle inner surface 50im is laterally recessed. The upper inner surface 50iu, the middle inner surface 50im, and the lower inner surface 50il of the barrier pattern 50a can correspond to the interface between the barrier pattern 50a and the unit gate barrier pattern 42, or the outer surface of the unit gate barrier pattern 42. Therefore, the interface between the barrier pattern 50a and the unit gate barrier pattern 42, or the outer surface of the unit gate barrier pattern 42, can have an upper portion with a downward slope, a substantially vertical and flat middle portion, and a lower portion with a downward slope.

[0030] Since the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44 of the cell gate barrier pattern 42 have conformal profiles, the side interfaces 42iu, 42im and 42il between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44 may also include an upper side interface 42iu with a downward slope, a substantially vertical and flat middle side interface 42im and a lower side interface 42il with an upward slope, so as to be parallel to the upper inner surface 50iu, the middle inner surface 50im and the lower inner surface 50il of the barrier pattern 50a. The upper interface 42iu, middle interface 42im, and lower interface 42il between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44 can correspond to the upper outer surface (also called the upper region of the outer wall), the middle outer surface (also called the middle region of the outer wall), and the lower outer surface (also called the lower region of the outer wall) of the inner cell gate barrier pattern 43 (also called the conductive barrier), and the upper inner surface, the middle inner surface, and the lower inner surface of the outer cell gate barrier pattern 44, respectively. Additionally, the side interfaces 41iu, 41im, and 41il between the cell gate electrode 41 and the cell gate barrier pattern 42 can also include an upper interface 41iu with a downward slope, a substantially vertical and flat middle interface 41im, and a lower interface 41il with an upward slope, parallel to the side interfaces 42iu, 42im, and 42il, respectively. The side interfaces 41iu, 41im, and 41il between the unit gate electrode 41 and the unit gate barrier pattern 42 may correspond to the outer surface of the unit gate electrode 41, the inner surface of the unit gate barrier pattern 42, or the inner surface of the inner unit gate barrier pattern 43. The unit gate electrode 41 may include a side surface along the side interfaces 41iu, 41im, and 41il between the unit gate electrode 41 and the unit gate barrier pattern 42. The upper segment of said one side surface of the unit gate electrode 41 may extend along the upper side interface 41iu. The middle segment of said one side surface of the unit gate electrode 41 may extend along the middle side interface 41im. The lower segment of said one side surface of the unit gate electrode 41 may extend along the lower side interface 41il.

[0031] The first surface (e.g., the inner surface) of the outer cell gate barrier pattern 44 (also referred to as the insulating barrier layer 44) may cover or surround the inner cell gate barrier pattern 43. The first surface of the outer cell gate barrier pattern 44 may have an upper side surface, an intermediate side surface, and a lower side surface corresponding to the upper inner side surface 50iu, the intermediate inner side surface 50im, and the lower inner side surface 50il of the barrier barrier pattern 50a, respectively. The second surface of the outer cell gate barrier pattern 44 may be opposite to the first surface of the outer cell gate barrier pattern 44.

[0032] The outer surface 50R (also referred to as the outer wall) of the barrier pattern 50a may protrude convexly toward the channel pattern 73 of the vertical channel structure 70. The outer surface 50R of the barrier pattern 50a may be arc-shaped. The outer surface 74R of the charge trap layer 74, the outer surface 75R of the tunnel insulation layer 75, and the outer surface 76R of the channel layer 76 may be partially recessed along the outer surface 50R of the barrier pattern 50a. The radius of curvature of the outer surface 74R of the charge trap layer 74 may be greater than the radius of curvature of the outer surface 50R of the barrier pattern 50a, the radius of curvature of the outer surface 75R of the tunnel insulation layer 75 may be greater than the radius of curvature of the outer surface 74R of the charge trap layer 74, and the radius of curvature of the outer surface 76R of the channel layer 76 may be greater than the radius of curvature of the outer surface 75R of the tunnel insulation layer 75 (50R < 74R < 75R < 76R). The outer surface 50R of the barrier pattern 50a may correspond to the interface between the barrier pattern 50a and the charge trap layer 74 or the inner surface of the charge trap layer 74. The outer surface 74R of the charge trap layer 74 may correspond to the interface between the charge trap layer 74 and the tunnel insulating layer 75 or the inner surface of the tunnel insulating layer 75. The outer surface 75R of the tunnel insulating layer 75 may correspond to the interface between the tunnel insulating layer 75 and the channel layer 76 or the inner surface of the channel layer 76. The outer surface 76R of the channel layer 76 may correspond to the interface between the channel layer 76 and the central gap filling pattern 71 or the outer surface of the central gap filling pattern 71.

[0033] The profile of the barrier pattern 50a may resemble the cross-section of a concave lens. For example, the upper horizontal width W1u and lower horizontal width W1l of the barrier pattern 50a may be thicker than the middle horizontal width W1m of the barrier pattern 50a (W1u>W1m, W1l>W1m). The upper horizontal width W1u and lower horizontal width W1l of the barrier pattern 50a may be substantially the same or similar. The upper horizontal width W1u and lower horizontal width W1l of the barrier pattern 50a may be measured at a level close to the interface between the barrier pattern 50a and the molded insulating layer 60. The middle horizontal width W1m of the barrier pattern 50a may be measured at the middle of the barrier pattern 50a (e.g., approximately half its vertical height).

[0034] Reference Figure 2BAccording to the embodiment, the barrier pattern 50b of the cell gate pattern 40 may include an upper inner surface 50iu and an upper outer surface 50ou with downward slopes, a substantially vertically flat middle inner surface 50im and a middle outer surface 50om, and a lower inner surface 50il and a lower outer surface 50ol with upward slopes. The upper outer surface 50ou, the middle outer surface 50om, and the lower outer surface 50ol of the barrier pattern 50b may correspond to the upper inner surface, the middle inner surface, and the lower inner surface of the charge trap layer 74, respectively. Therefore, the charge trap layer 74 may have an upper inner surface with downward slopes, a substantially vertically flat middle inner surface, and a lower inner surface with upward slopes. The upper outer surface 50ou, the middle outer surface 50om, and the lower outer surface 50ol of the barrier pattern 50b may correspond to the interface between the barrier pattern 50b and the charge trap layer 74. Therefore, the side interface between the barrier pattern 50b and the charge trapping layer 74 can have an upper side interface with a downward slope, a substantially vertical and flat middle side interface, and a lower side interface with an upward slope. The upper horizontal width W2u and lower horizontal width W2l of the charge trapping layer 74 of the channel pattern 73 adjacent to the barrier pattern 50b can be thicker or wider than the middle horizontal width W2m of the charge trapping layer 74 (W2u>W2m, W2l>W2m). The upper horizontal width W2u and lower horizontal width W2l of the charge trapping layer 74 can be substantially the same or similar (W2u≈W2l). The upper horizontal width W2u and lower horizontal width W2l of the charge trapping layer 74 can be measured at the same level as the side interface between the barrier pattern 50b and the molded insulating layer 60. The middle horizontal width W2m of the charge trapping layer 74 can be measured at half the vertical height of the barrier pattern 50b. Other components can be further referenced. Figure 2A To understand.

[0035] Reference Figure 2C According to an embodiment, the barrier pattern 50c of the cell gate pattern 40 may include an upper inner surface 50iu with a downward slope, a substantially vertically flat middle inner surface 50im, a lower inner surface 50il with an upward slope, and an arcuate outer surface 50R that protrudes convexly toward the channel pattern 73 of the vertical channel structure 70. Figure 2AIn contrast, the connection points between the upper inner surface 50iu and the middle inner surface 50im of the barrier pattern 50c, and between the lower inner surface 50il and the middle inner surface 50im of the barrier pattern 50c, may have inflection points (IU, IL). Inflection points IU and IL may have a step difference. The side interfaces 42iu, 42im, and 42il between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44, and the side interfaces 41iu, 41im, and 41il between the cell gate electrode 41 and the cell gate barrier pattern 42, may each have inflection points IU and IL. Other components can be further referenced. Figure 2A and Figure 2B To understand.

[0036] Reference Figure 2D According to the embodiment, the barrier pattern 50d of the cell gate pattern 40 includes a substantially vertically flat upper inner surface 50iu, a substantially vertically flat middle inner surface 50im, and a substantially vertically flat lower inner surface 50il. Therefore, the side interfaces 42iu, 42im, and 42il between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44 can also be substantially vertically flat, and the side interfaces 41iu, 41im, and 41il between the cell gate electrode 41 and the cell gate barrier pattern 42 can also be substantially vertically flat. (Refer to...) Figure 2D The connection points between the upper inner surface 50iu and the middle inner surface 50im of the barrier pattern 50d, the connection points between the lower inner surface 50il and the middle inner surface 50im of the barrier pattern 50d, the connection points between the side interfaces 42iu, 42im and 42il between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44, and the connection points between the side interfaces 41iu, 41im and 41il between the cell gate electrode 41 and the cell gate barrier pattern 42 may also have inflection points IU and IL, respectively. The barrier pattern 50d may include an arcuate outer surface 50R that protrudes from the channel pattern 73 toward the vertical channel structure 70. The average width W3u between the upper inner surface 50iu and the outer surface 50R of the barrier pattern 50d is greater than the average width W3m between the middle inner surface 50im and the outer surface 50R (W3u>W3m). The average width W3l between the lower inner surface 50il and the outer surface 50R of the barrier pattern 50d may be greater than the average width W3m between the middle inner surface 50im and the outer surface 50R (W3l>W3m). The average width W3u between the upper inner surface 50iu and the outer surface 50R of the barrier pattern 50d and the average width W3l between the lower inner surface 50il and the outer surface 50R of the barrier pattern 50d may be substantially the same or similar to each other (W3u≈W3l). Other components may be further referenced. Figures 2A to 2C Understand.

[0037] Refer to Figure 2E , according to the embodiment, the blocking barrier pattern 50e of the unit gate pattern 40 may include an upper inner surface 50iu having a downward slope, a substantially vertical flat intermediate inner surface 50im, and a lower inner surface 50il having an upward slope. The side interfaces 42iu, 42im, and 42il between the inner unit gate barrier pattern 43 and the outer unit gate barrier pattern 44 of the unit gate barrier pattern 42 may include an upper side interface 42iu having a downward slope, a vertical flat intermediate side interface 42im, and a lower side interface 42il having an upward slope. The intermediate side interface 42im may be vertically flat. The side interface 41i between the unit gate electrode 41 and the unit gate barrier pattern 42 may be substantially arc-shaped. For example, the average horizontal width W4u between the upper inner surface 50iu of the blocking barrier pattern 50e and the unit gate electrode 41 may be less than the average horizontal width W4m between the intermediate inner surface 50im of the blocking barrier pattern 50e and the unit gate electrode 41 (W4u < W4m). The average horizontal width W4l between the lower inner surface 50il of the blocking barrier pattern 50e and the unit gate electrode 41 is less than the average horizontal width W4m between the intermediate inner surface 50im of the blocking barrier pattern 50e and the unit gate electrode 41 (W4l < W4m). The average horizontal width W4u between the upper inner surface 50iu of the blocking barrier pattern 50e and the unit gate electrode 41 and the average horizontal width W4l between the lower inner surface 50il of the blocking barrier pattern 50e and the unit gate electrode 41 may be substantially the same or similar to each other. In the embodiment, the side interfaces 42iu, 42im, and 42il between the inner unit gate barrier pattern 43 and the outer unit gate barrier pattern 44 of the unit gate barrier pattern 42 may also be substantially arc-shaped.

[0038] Refer to Figure 2F , according to the embodiment, the blocking barrier pattern 50f of the unit gate pattern 40 may include an arc-shaped inner surface �0is and an arc-shaped outer surface 50R. The upper horizontal width W5u and the lower horizontal width W5l of the blocking barrier pattern 50f may be greater than the intermediate horizontal width W5m of the blocking barrier pattern 50f (W5u > W5m, W5l > W5m). The upper horizontal width W5u and the lower horizontal width W5l may be substantially the same or similar to each other. The side interface 42i between the inner unit gate barrier pattern 43 and the outer unit gate barrier pattern 44 of the unit gate barrier pattern 42 may be substantially parallel or concentric with the inner surface 50is of the blocking barrier pattern 50f. The side interface 41i between the unit gate electrode 41 and the unit gate barrier pattern 42 may also be substantially parallel or concentric with the side interface 42i between the inner unit gate barrier pattern 43 and the outer unit gate barrier pattern 44 of the unit gate barrier pattern 42.

[0039] Reference Figure 2G According to an embodiment, the barrier pattern 50g of the cell gate pattern 40 includes an upper inner surface 50iu with steps, a lower inner surface 50il with steps, and a substantially vertically flat intermediate inner surface 50im. For example, the upper inner surface 50iu and the lower inner surface 50il may have a tortuous or meandering shape or an uneven shape to protrude toward or be recessed from the cell gate electrode 41. The intermediate inner surface 50im may be substantially vertically flat. The barrier pattern 50g may include an arcuate outer surface 50R to protrude toward the vertical channel structure 70. The side interfaces 42iu, 42im, and 42il between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44 of the cell gate barrier pattern 42, and the upper inner surface 50iu, the intermediate inner surface 50im, and the lower inner surface 50il of the barrier pattern 50g may each have the same shape or be similar to each other. The side interfaces 41iu, 41im, and 41il between the unit gate electrode 41 and the unit gate barrier pattern 42 may have the same shape as the upper inner surface 50iu, the middle inner surface 50im, and the lower inner surface 50iu of the barrier barrier pattern 50g, or the side interfaces 42iu, 42im, and 42il between the inner unit gate barrier pattern 43 and the outer unit gate barrier pattern 44 of the unit gate barrier pattern 42, or be similar to the upper inner surface 50iu, the middle inner surface 50im, and the lower inner surface 50iu of the barrier barrier pattern 50g, or the side interfaces 42iu, 42im, and 42il between the inner unit gate barrier pattern 43 and the outer unit gate barrier pattern 44 of the unit gate barrier pattern 42. The upper horizontal width W6u and the lower horizontal width W6l of the barrier barrier pattern 50g may be greater than the middle horizontal width W6m of the barrier barrier pattern 50g (W6u>W6m, W6l>W6m). The upper horizontal width W6u and lower horizontal width W6l of the barrier pattern 50g may be substantially the same or similar to each other. As mentioned above, the upper horizontal width W6u and lower horizontal width W6l of the barrier pattern 50g can be measured at a level closer to the interface between the barrier pattern 50g and the molded insulating layer 60. The middle horizontal width W6m of the barrier pattern 50g can be measured at the middle portion of the barrier pattern 50g (e.g., at approximately half the vertical height).

[0040] Reference Figure 2HAccording to the embodiment, the side interfaces 41iu, 41im, and 41il between the unit gate electrode 41 and the unit gate barrier pattern 42 of the unit gate pattern 40 can be substantially flat. For example, the side interfaces 41iu, 41im, and 41il between the unit gate electrode 41 and the unit gate barrier pattern 42 may include an upper side interface 41iu with a downward slope, a substantially vertically flat middle side interface 41im, and a lower side interface 41il with an upward slope. The contours of the inner surfaces 50iu, 50im, and 50il of the barrier pattern 50g can be smoothly relaxed by the unit gate barrier pattern 42.

[0041] Reference Figure 2I According to the embodiment, the side interfaces 42iu, 42im, and 42il between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44 of the cell gate barrier pattern 42 of the cell gate pattern 40 can be substantially flat. For example, the side interfaces 42iu, 42im, and 42il between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44 of the cell gate barrier pattern 42 may include an upper side interface 42iu with a downward slope, a substantially vertical and flat middle side interface 42im, and a lower side interface 42il with an upward slope. The contours of the inner surfaces 50iu, 50im, and 50il of the barrier pattern 50g can be smoothly relaxed through the outer cell gate barrier pattern 44 of the cell gate barrier pattern 42.

[0042] Reference Figure 2J According to an embodiment, the barrier pattern 50h of the cell gate pattern 40 may include an upper inner surface 50iu with a downward slope, a substantially vertically flat middle inner surface 50im, a lower inner surface 50il with an upward slope, and a substantially vertically flat outer surface. The outer surface of the barrier pattern 50h may correspond to the outer surface 74S of the charge trapping layer 74 of the channel pattern 73 of the vertical channel structure 70. For example, the charge trapping layer 74, tunnel insulating layer 75, channel layer 76, and central gap filling pattern 71 of the channel pattern 73 of the vertical channel structure 70 may each have substantially vertically flat outer surfaces 74S, 75S, 76S, and 71S, respectively. Therefore, the upper horizontal width W7u and the lower horizontal width W7l of the barrier pattern 50h may be thicker than the middle horizontal width W7m of the barrier pattern 50h (W7u>W7m, W7l>W7m). The upper horizontal width W7u and the lower horizontal width W7l of the barrier pattern 50h can be substantially the same or similar.

[0043] Reference Figure 2KAccording to an embodiment, the barrier pattern 50i of the cell gate pattern 40 includes an upper inner surface 50iu and a lower inner surface 50il having multiple stepped shapes, a substantially vertically flat middle inner surface 50im, and an outer surface. For example, the upper inner surface 50iu and the lower inner surface 50il may have tortuous or meandering shapes or multiple stepped shapes. For example, the charge trapping layer 74, tunnel insulating layer 75, channel layer 76, and central gap filling pattern 71 of the channel pattern 73 of the vertical channel structure 70 may each have substantially vertically flat outer surfaces 74S, 75S, 76S, and 71S, respectively. Figure 2A and Figure 2B The inventive concept can be applied, in whole or in part, to the embodiments described with reference to the other accompanying drawings. Figures 2B to 2K In the diagram, elements not shown can be referenced via cross-reference. Figure 2A Please refer to the accompanying diagrams for further understanding.

[0044] Reference Figure 2L According to an embodiment, the inner surface of the barrier pattern 50j may include protruding portions Pu and P1 that protrude toward the cell gate electrode 41 or the cell gate barrier pattern 42. For example, the barrier pattern 50j may have a first protruding portion Pu that slightly protrudes toward the portion between the upper inner surface 50iu and the intermediate inner surface 50im, and a second protruding portion P1 that slightly protrudes toward the portion between the lower inner surface 50il and the intermediate inner surface 50im. The protruding portions (Pu and P1) may be very fine. The upper inner surface 50iu and the lower inner surface 50il may be inclined. The interface between the inner cell gate barrier pattern 43 and the outer cell gate barrier pattern 44 of the cell gate barrier pattern 42 may also have protruding portions Pu and P1 along the contour of the inner surface of the barrier pattern 50j. The interface between the cell gate electrode 41 and the cell gate barrier pattern 42 may also have protruding portions Pu and P1. In an embodiment, the interface between the unit gate electrode 41 and the unit gate barrier pattern 42 may have a substantially stepped profile.

[0045] Reference Figure 2M According to the embodiment, the inner surface of the barrier pattern 50k may have protrusions Pu and Pl that protrude toward the unit gate electrode 41 or the unit gate barrier pattern 42, and may include a vertically flat upper inner surface 50iu, a vertically flat middle inner surface 50im and a vertically flat lower inner surface 50il.

[0046] Reference Figure 2NAccording to the embodiment, the inner surface of the barrier pattern 50l may have a plurality of protrusions Pu and a plurality of protrusions P1. The interface between the inner unit gate barrier pattern 43 and the outer unit gate barrier pattern 44 of the unit gate barrier pattern 42 may also have a plurality of protrusions Pu and a plurality of protrusions P1 along the contour of the inner surface of the barrier pattern 50l. The interface between the unit gate electrode 41 and the unit gate barrier pattern 42 may also have a plurality of protrusions Pu and a plurality of protrusions P1. In the embodiment, the interface between the unit gate electrode 41 and the unit gate barrier pattern 42 may have a substantially stepped contour.

[0047] Because according to Figures 2L to 2N In the embodiment shown, the protruding portions Pu and Pl of the inner surfaces of the barrier patterns 50j, 50k and 50l can be formed toward the unit gate electrode 41, so that no sharp portion is formed between the unit gate electrode 41 and the vertical channel structure 70, and thus no electric field concentration effect occurs between the unit gate electrode 41 and the vertical channel structure 70.

[0048] Figure 3A and Figures 3B to 6 This is a longitudinal cross-sectional view illustrating a method for forming a three-dimensional flash memory device according to an embodiment. Figure 3A , Figure 4A , Figure 5A and Figure 6 It is a longitudinal cross-sectional view, and Figure 3B , Figure 4B and Figure 5B This is an enlarged view of region "A".

[0049] Reference Figure 3A and Figure 3BA method for forming a three-dimensional flash memory device according to an embodiment may include: performing multiple deposition processes to form a surface insulating layer 20, a lower sacrificial insulating layer 35, a lower interlayer insulating layer 25, a molded stacked layer MS, and a cover insulating layer 65 on a substrate 10; and performing photolithography and etching processes to form channel vias CH. For example, the method may include performing an oxidation process or a deposition process to form the surface insulating layer 20 on the substrate 10. For example, the substrate 10 may include monocrystalline silicon. The lower sacrificial insulating layer 35 may include a material different from the material of the surface insulating layer 20 to have etch selectivity with the surface insulating layer 20. For example, the lower sacrificial insulating layer 35 may include silicon nitride. The lower interlayer insulating layer 25 may include a material different from the material of the lower sacrificial insulating layer 35 to have etch selectivity with the lower sacrificial insulating layer 35. For example, the lower interlayer insulating layer 25 may include silicon oxide. The molded stacked layer MS may include a plurality of sacrificial insulating layers 45 and a plurality of molded insulating layers 60 alternately stacked on the lower interlayer insulating layer 25. For example, the sacrificial insulating layer 45 may include silicon nitride, and the molded insulating layer 60 may include silicon oxide. Therefore, the sacrificial insulating layer 45 and the molded insulating layer 60 may have excellent etch selectivity. Compared to the molded insulating layer 60, the cover insulating layer 65 may be formed as relatively thick on the molded stacked layer MS. The cover insulating layer 65 may include the same material as the molded insulating layer 60 (e.g., silicon oxide). A channel via CH may pass through the cover insulating layer 65, the molded stacked layer MS, the lower interlayer insulating layer 25, the lower sacrificial insulating layer 35, and the surface insulating layer 20 to expose a portion of the substrate 10. In a top view, the channel via CH may be circular. Each of the sacrificial insulating layers 45 in the molded stacked layer MS may include silicon nitride (Si). x N y (where x and y are positive real numbers), and can have various concentration distributions. For example, each sacrificial insulating layer 45 can have a Si-rich lower layer 45l, an N-rich intermediate layer 45m, and a Si-rich upper layer 45u.

[0050] Compared to the N-rich intermediate layer 45m, the Si-rich lower layer 45l and Si-rich upper layer 45u can have relatively low nitrogen (N) concentrations (i.e., relatively high silicon (Si) concentrations). Therefore, compared to the Si-rich lower layer 45l and Si-rich upper layer 45u, the N-rich intermediate layer 45m can have relatively high nitrogen (N) concentrations (i.e., relatively low silicon (Si) concentrations). In embodiments, the lower boundary 45il between the lower layer 45l and the intermediate layer 45m and / or the upper boundary 45iu between the intermediate layer 45m and the upper layer 45u can be invisible. For example, the lower boundary 45il and the upper boundary 45iu may be substantially non-existent when the concentration profiles of the lower layer 45l, the intermediate layer 45m, and the upper layer 45u gradually change. In embodiments, the lower boundary 45il and the upper boundary 45iu may be substantially present when the concentration profiles of the lower layer 45l, the intermediate layer 45m, and the upper layer 45u become stepped or discrete. The sacrificial insulating layer 45 can be formed by repeatedly performing multiple deposition processes. For example, a Si-rich lower layer 45l can be formed using a first deposition process where the N source is relatively scarce, an N-rich intermediate layer 45m can be formed using a second deposition process where the N source is relatively abundant, and a Si-rich upper layer 45u can be formed using a third deposition process where the N source is relatively scarce. In an embodiment, during the process of forming the sacrificial insulating layer 45, the Si-rich lower layer 45l, the N-rich intermediate layer 45m, and the Si-rich upper layer 45u can be formed sequentially according to the gradual change in the N source supply.

[0051] Reference Figure 4A and Figure 4BThe method may include forming a raised source region 15 and forming a barrier pattern 50. Forming the raised source region 15 may include performing an epitaxial growth process to form an epitaxial growth layer on a substrate 10 exposed in a channel hole CH. Thus, the raised source region 15 may include an epitaxial layer comprising a single-crystal silicon layer, a silicon-germanium (SiGe) layer, a silicon-carbon (SiC) layer, or other single-crystal silicon layers. The top level of the raised source region 15 may be positioned at a level higher than the top surface of the lower sacrificial insulating layer 35. Thus, the raised source region 15 and the lower sacrificial insulating layer 35 may be in contact with each other. Forming the barrier pattern 50 may include oxidizing a portion of the sacrificial insulating layer 45 of the molded stacked layer MS exposed in the channel hole CH. An in-situ vapor generation (ISSG) oxidation process or a plasma oxidation process may be performed to partially oxidize the sacrificial insulating layer 45. In the oxidation process, oxygen radicals may penetrate into the sacrificial insulating layer 45 to directly bond with dangling bonds of silicon atoms and may be replaced by nitrogen atoms bonded to silicon. For example, since the Si-rich lower layer 45l and Si-rich upper layer 45u are relatively silicon-rich layers, the ratio of oxygen free radicals directly bonded to dangling bonds of silicon atoms can be relatively higher than that in the N-rich intermediate layer 45m. Furthermore, since the N-rich intermediate layer 45m is relatively nitrogen-rich, the ratio of oxygen free radicals replaced by nitrogen atoms can be relatively higher than that in the Si-rich lower layer 45l and Si-rich upper layer 45u. Therefore, during the oxidation process, the lower horizontal width W1l of the barrier pattern 50 formed by oxidizing the Si-rich lower layer 45l can become thicker towards the bottom, and the upper horizontal width W1u of the barrier pattern 50 formed by oxidizing the Si-rich upper layer 45u can become thicker towards the top. In the N-rich intermediate layer 45m, oxygen and nitrogen atoms are replaced, and since oxygen atoms can be released from the sacrificial insulating layer 45 to the outside, the N-rich intermediate layer can expand relatively less. Furthermore, oxygen atoms can penetrate deeper through the interface between the sacrificial insulating layer 45 and the molded insulating layer 60. Therefore, the closer the Si-rich lower layer 45l and Si-rich upper layer 45u are to the molded insulating layer 60, the easier they are to oxidize, and the horizontal widths W1u and W1l can be increased. The outer surface 50o of the barrier pattern 50 can protrude towards the channel hole CH. For example, the outer surface 50o of the barrier pattern 50 can be arc-shaped.

[0052] Reference Figure 5A and Figure 5BThe method may include forming a vertical channel structure 70 in a via CH. Forming the vertical channel structure 70 may include: performing an atomic layer deposition process to conformally form a channel pattern 73 on the inner wall and bottom of the via CH; performing a gap-filling process to form a central gap-filling pattern 71 in the via CH; and forming a via pad 77 on the central gap-filling pattern 71 by performing an etching, deposition, and chemical mechanical polishing (CMP) process. The channel pattern 73 may include a charge trapping layer 74, a tunnel insulating layer 75, and a channel layer 76. The charge trapping layer 74 may be conformally formed on a molded insulating layer 60 and a barrier pattern 50. The charge trapping layer 74 may have a conformal profile along the side surface of the molded insulating layer 60 and the outer surface 50o of the barrier pattern 50. For example, the interface between the charge trapping layer 74 and the molded insulating layer 60 may be substantially vertically flat, and the interface between the charge trapping layer 74 and the barrier pattern 50 may be arcuate. The charge trap layer 74 may have an arcuate outer surface 74R corresponding to the outer surface 50o of the barrier pattern 50. The charge trap layer 74 may include a relatively high-k dielectric material such as silicon nitride. A tunnel insulating layer 75 may be conformally formed on the charge trap layer 74. The tunnel insulating layer 75 may have an arcuate outer surface 75R corresponding to the arcuate outer surface 74R of the charge trap layer 74. The tunnel insulating layer 75 may include a relatively easy-to-tunnel and durable insulating material such as silicon oxide. A channel layer 76 may be conformally formed on the tunnel insulating layer 75. The channel layer 76 may have an arcuate outer surface 76R corresponding to the arcuate outer surface 75R of the tunnel insulating layer 75. A central gap fill pattern 71 may be formed on the channel layer 76 to fill the channel via CH. The central gap fill pattern 71 may include a material with excellent filling properties such as silicon oxide. Via pads 77 may be directly electrically connected to the channel layer 76. The via pad 77 may include at least one of N-doped polysilicon, metal silicide, metal nitride, and metal.

[0053] Reference Figure 6 and Figure 2B The method may include removing the sacrificial insulating layer 45 and forming a cell gate pattern 40 in the empty space defined by removing the sacrificial insulating layer 45. A wet etchant such as phosphoric acid (H3PO4) may be used to remove the sacrificial insulating layer 45. The cell gate pattern 40 may include a cell gate electrode 41 and a cell gate barrier pattern 42 formed by performing an atomic layer deposition process. The cell gate barrier pattern 42 may include an inner cell gate barrier pattern 43 and an outer cell gate barrier pattern 44. (See also...) Figure 2B The cell gate pattern 40 is described in detail.

[0054] like Figures 2A to 2NAs shown, depending on the process conditions, the element shape can be formed to be the same as or similar to various unit gate electrodes 41, unit gate barrier patterns 42, barrier patterns 50a-50l and vertical channel structures 70.

[0055] Figure 7A and Figure 7B This is a longitudinal cross-sectional view illustrating a method for forming a three-dimensional flash memory device according to an embodiment. First, referring to... Figure 3A and Figure 7A The sacrificial insulating layer 45 may include unit sacrificial insulating layers 45a to 45g having various N concentrations. The unit sacrificial insulating layers 45a to 45g may include unit sacrificial insulating layers 45a to 45c wherein the N concentration decreases downwards from that of the unit sacrificial insulating layer 45d having the highest N concentration, and unit sacrificial insulating layers 45e to 45g wherein the N concentration decreases upwards from that of the unit sacrificial insulating layer 45d. Although the accompanying drawings show the sacrificial insulating layer 45 comprising seven unit sacrificial insulating layers 45a to 45g, in embodiments, the sacrificial insulating layer 45 may include more unit sacrificial insulating layers 45a to 45g. See also... Figure 4A and Figure 7B The method may include performing an oxidation process to form a barrier pattern 50. Also refer to... Figure 2G The interface between the barrier pattern 50 and the unit sacrificial insulating layers 45a to 45g may have a stepped profile depending on the N concentration. The outer surface of the barrier pattern 50 may be arcuate. In an embodiment, the interface between the barrier pattern 50 and the unit sacrificial insulating layers 45a to 45g may be substantially arcuate. In an embodiment, the outer surface of the barrier pattern 50 may also have a stepped profile. The method may then include performing a reference... Figure 5A and Figure 6 The described process is to form a product with... Figures 2A to 2N The various unit gate electrodes 41, unit gate barrier patterns 42, barrier patterns 50a to 50l, and vertical channel structures 70 shown are the same or similar elements.

[0056] Figure 8 This is a vertical cross-sectional view illustrating a method for forming a three-dimensional flash memory device according to an embodiment.

[0057] Reference Figure 8 In order to execute the reference Figure 3A and Figures 3B to 4A and Figure 4B After the described process forms the barrier pattern 50 and the channel hole CH, the method may further include performing a local etching process to partially remove the outer portion of the barrier pattern 50 that protrudes toward the channel hole CH. During this process, the outer surface of the barrier pattern 50 may be substantially vertically flat.

[0058] The three-dimensional flash memory device according to the disclosed embodiments may include a cell gate electrode having arcuate side surfaces. The three-dimensional flash memory device according to the disclosed embodiments may include a cell gate barrier pattern and a barrier pattern having a concave arcuate inner side surface and a convex arcuate outer side surface. The three-dimensional flash memory device according to the disclosed embodiments may include a channel pattern having a concave arcuate outer surface. Therefore, in the three-dimensional flash memory device according to the embodiments, the electric field is not concentrated between the cell gate electrode and the channel pattern, and the electric field can be widely dispersed. In the channel pattern, the tunneling of charge or electrons is widely dispersed rather than concentrated in a portion, thereby improving the physical and electrical reliability of the channel pattern and the effective lifetime of the device.

[0059] Although exemplary embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that the present disclosure may be implemented in other specific forms without departing from the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the above exemplary embodiments are not limiting in all respects but rather illustrative.

Claims

1. A three-dimensional flash memory device, comprising: Substrate; Multiple cell gate patterns and multiple molded insulating layers are alternately stacked on the substrate; as well as A vertical channel structure is provided, which contacts the side surfaces of the plurality of cell gate patterns and the side surfaces of the plurality of molded insulating layers, wherein: Each of the plurality of unit gate patterns includes a unit gate electrode and a barrier pattern disposed adjacent to one side surface of the unit gate electrode. The inner surface of the barrier pattern includes an upper inner surface, a middle inner surface, and a lower inner surface. The inner middle surface of the barrier pattern faces one side surface of the unit gate electrode. The outer wall of the barrier pattern has a convex arcuate surface, and The barrier pattern has a portion protruding toward the cell gate electrode at the connection point between the upper inner surface of the barrier pattern and the middle inner surface of the barrier pattern.

2. The three-dimensional flash memory device according to claim 1, wherein, Each of the plurality of cell gate patterns includes an insulating outer cell gate barrier pattern, the insulating outer cell gate barrier pattern being located between the cell gate electrode and the barrier barrier pattern. The first surface of the insulating outer cell gate barrier pattern covers the upper section, the lower section, and the middle section of one side surface of the cell gate electrode. The first surface of the insulating outer unit gate barrier pattern has an upper inner surface, a middle inner surface, and a lower inner surface that correspond to the upper inner surface, the middle inner surface, and the lower inner surface of the barrier barrier pattern, respectively. The insulating outer cell gate barrier pattern has a portion protruding toward the cell gate electrode at the connection point between the upper inner surface and the middle inner surface of the insulating outer cell gate barrier pattern.

3. The three-dimensional flash memory device according to claim 1, wherein, Each of the plurality of cell gate patterns includes a conductive inner cell gate barrier pattern, the conductive inner cell gate barrier pattern being located between the cell gate electrode and the barrier barrier pattern. The conductive inner cell gate barrier pattern covers the upper section, the lower section, and the middle section of one side surface of the cell gate electrode. The outer wall of the gate barrier pattern of the conductive inner unit faces the inner surface of the barrier barrier pattern. The conductive inner cell gate barrier pattern has an upper outer surface, a middle outer surface, and a lower outer surface that correspond to the upper inner surface, the middle inner surface, and the lower inner surface of the barrier barrier pattern, respectively. The conductive inner cell gate barrier pattern has a portion protruding toward the cell gate electrode at the connection point between the upper outer surface of the conductive inner cell gate barrier pattern and the middle outer surface of the conductive inner cell gate barrier pattern.

4. The three-dimensional flash memory device according to claim 1, wherein, The upper inner surface of the barrier pattern has a first slope. The lower inner surface of the barrier pattern has a second slope, and The first slope and the second slope have symmetrical shapes.

5. The three-dimensional flash memory device according to claim 4, in, The upper inner surface and the lower inner surface of the barrier pattern each have a concave-convex shape.

6. The three-dimensional flash memory device according to claim 1, in, Along the inner surface of the barrier pattern, the barrier pattern has a stepped difference at the connection point between the upper inner surface of the barrier pattern and the middle inner surface of the barrier pattern.

7. The three-dimensional flash memory device according to claim 1, in, The inner middle surface of the barrier pattern is vertically flat.

8. The three-dimensional flash memory device according to claim 1, in, The inner surface of the barrier pattern has a concave surface.

9. The three-dimensional flash memory device according to claim 1, in, The average width between the upper inner surface and the outer surface of the barrier pattern is greater than the average width between the middle inner surface and the outer surface of the barrier pattern.

10. The three-dimensional flash memory device according to claim 1, in, The side surface of the unit gate electrode is convex and arc-shaped.

11. A three-dimensional flash memory device, comprising: Substrate; A cell gate pattern and a molded insulating layer are stacked on the substrate. The molded insulating layer comprises an insulating material. The unit gate pattern includes a unit gate electrode, a conductive inner unit gate barrier pattern, an insulating outer unit gate barrier pattern, and a barrier barrier pattern. The conductive inner cell gate barrier pattern surrounds the upper surface, lower surface, and side surface of the cell gate electrode. The first surface of the insulating outer cell gate barrier pattern conformally covers the conductive inner cell gate barrier pattern. The inner surface of the barrier pattern is located on the second surface of the insulating outer cell gate barrier pattern, which is opposite to the first surface of the insulating outer cell gate barrier pattern. The inner surface of the barrier pattern has a concave-convex shape including recessed portions, and The outer surface of the barrier pattern is convex and arc-shaped; and A vertical channel structure that is adjacent to the side surface of the cell gate pattern and the side surface of the molded insulating layer.

12. The three-dimensional flash memory device according to claim 11, wherein, The inner surface of the barrier pattern includes an upper inner surface with a downward slope, a middle inner surface with a vertical slope, and a lower inner surface with an upward slope. The upper inner surface and the lower inner surface of the barrier pattern have an uneven shape. The inner middle surface of the barrier pattern is flat.

13. The three-dimensional flash memory device according to claim 11, wherein, The first surface of the insulating outer cell gate barrier pattern has a portion recessed towards the cell gate electrode, and The second surface of the insulating outer cell gate barrier pattern protrudes toward the barrier pattern.

14. A three-dimensional flash memory device, comprising: Substrate; Multiple cell gate patterns and multiple molded insulating layers are alternately stacked on the substrate. The plurality of molded insulating layers include insulating material. Each of the plurality of cell gate patterns includes a cell gate electrode and a barrier pattern surrounding one side surface of the cell gate electrode. The inner surface of the barrier pattern includes an upper inner surface, a middle inner surface, and a lower inner surface. The upper inner surface and the lower inner surface of the inner surface of the barrier pattern each have a concave-convex shape. The outer surface of the barrier pattern is convex and arc-shaped; and A vertical channel structure that contacts the side surfaces of the plurality of cell gate patterns and the side surfaces of the plurality of molded insulating layers.

15. The three-dimensional flash memory device according to claim 14, wherein, The average width between the unit gate electrode and the upper inner surface of the barrier pattern is less than the average width between the unit gate electrode and the middle inner surface of the barrier pattern.

16. The three-dimensional flash memory device according to claim 14, wherein, A portion of the inner surface of the barrier pattern is concave and arc-shaped. The vertical trench structure includes: a gap-filling pattern, a trench layer, a tunnel insulation layer, and a charge trapping layer, wherein the trench layer surrounds the gap-filling pattern, the tunnel insulation layer surrounds the trench layer, and the charge trapping layer surrounds the tunnel insulation layer. The charge trap layer is in direct contact with the outer surface of the barrier pattern, and The charge trap layer is spaced apart from the insulating outer cell gate barrier pattern of the cell gate pattern.

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