Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device may include: horizontal patterns, which are arranged on peripheral circuit structures and spaced apart from each other; memory structures, which are respectively arranged on the horizontal patterns, each memory structure including a three-dimensional arrangement of memory cells. The through-insulating patterns and the separation structure may isolate the horizontal patterns from each other. The through-vias may extend through the through-insulating patterns to connect the logic circuits of the peripheral circuit structures to the memory structures.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority benefit of Korean Patent Application No. 10-2019-0075814 filed on June 25, 2019 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a three-dimensional semiconductor memory device and a method for manufacturing the same, and in particular, to a highly integrated three-dimensional semiconductor memory device and a method for manufacturing the same. Background Art

[0004] A higher integration of semiconductor devices is needed to meet consumer demand for excellent performance and low prices. In the case of semiconductor devices, since their integration is an important factor in determining product prices, it is particularly necessary to increase the integration. The integration of two-dimensional or planar semiconductor devices is usually highly dependent on the area occupied by the unit memory cell, and is therefore greatly affected by the level of fine pattern formation technology. However, the expensive processing equipment required to increase the fineness of the pattern sets a practical limit to increasing the integration of two-dimensional or planar semiconductor devices. Therefore, a three-dimensional semiconductor memory device including a three-dimensionally arranged memory cell has been proposed recently. Summary of the invention

[0005] Embodiments of the inventive concept are directed to a three-dimensional semiconductor memory device having increased integration density.

[0006] Embodiments of the inventive concept also relate to methods of manufacturing three-dimensional semiconductor memory devices.

[0007] According to some embodiments, a three-dimensional semiconductor memory device includes: horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other; memory structures disposed on the horizontal patterns, respectively, each memory structure including a three-dimensional arrangement of memory cells. A through-insulating pattern and a separation structure may isolate the horizontal patterns from each other. A through-via may extend through the through-insulating pattern to connect a logic circuit of the peripheral circuit structure to the memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments described herein.

[0009] Figure 1 is a diagram illustrating a substrate on which a three-dimensional semiconductor memory device according to an embodiment of the inventive concept is integrated.

[0010] Figure 2 is a perspective view schematically illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0011] Figure 3 is a schematic plan view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0012] Figure 4A , Figure 4B and Figure 4C are plan views schematically illustrating some examples of cell array structures in a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0013] Figure 5A , Figure 5B and Figure 5C is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0014] Fig. 6A , Figure 6B , Figure 6C and Fig.6D are along Figure 5A 1 and 2 are taken along lines II′, II-II′, III-III′, and IV-IV′ to illustrate cross-sectional views of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0015] Fig. 7A and Figure 7B are along Figure 5A 1 and 2-2' are taken to illustrate cross-sectional views of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0016] Fig. 8A , Figure 8B and Figure 8C are along Figure 5A 1 and 2 are taken along lines II′, II-II′, and IV-IV′ to illustrate cross-sectional views of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0017] Fig.9A is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0018] Fig. 9B is along Fig.9A A cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept is shown taken along line V-V'.

[0019] Fig. 10A is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0020] Fig. 10B is along Fig. 10AA cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept is shown taken along line VI-VI′.

[0021] Fig. 10C and Fig. 10D is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept.

[0022] Fig.11A is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0023] Fig. 11B and Fig. 11C is along Fig.11A A cross-sectional view of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept is shown taken along line VII-VII'.

[0024] Fig. 12A and Fig. 12B is along Figure 5A 1 and 2 are taken along lines II-II′ and III-III′ to illustrate cross-sectional views of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0025] Fig.13A , Fig. 13B and Fig. 13C is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0026] Fig.14 is a plan view schematically illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0027] Fig.15 is a flowchart illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0028] FIG. 16A to FIG. 23A and FIG. 16B to FIG. 23B is a diagram illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0029] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment, and should not be interpreted as defining or limiting the range of values ​​or characteristics covered by the example embodiments. For example, the relative thickness and positioning of layers, regions and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0030] A three-dimensional semiconductor memory device and a method of manufacturing the same according to embodiments of the inventive concept will be described in more detail below with reference to the accompanying drawings.

[0031] Figure 1 is a diagram illustrating a substrate on which a three-dimensional semiconductor memory device is integrated according to an embodiment of the inventive concept.

[0032] Reference Figure 1 The semiconductor substrate 1 (eg, a wafer) may include chip regions 10 and scribe line regions 20 respectively located between the chip regions 10, and semiconductor chips are respectively formed by the chip regions 10. The chip regions 10 may be oriented in two different directions (eg, Figure 1 1 and 2 (in the first direction D1 and the second direction D2 shown in FIG. 1 ). Each chip area 10 may be surrounded by a scribe area 20. A corresponding scribe area 20 may be provided between each pair of adjacent chip areas 10 (adjacent to each other in the first direction D1 and the second direction D2). The scribe area 20 may be a linearly extending area, which indicates where the wafer 1 (after semiconductor devices are formed in the chip area 10) can be cut so as to separate the resulting semiconductor devices from each other (i.e., to form semiconductor chips corresponding to the semiconductor devices formed in the chip area 10). In some examples, the scribe area 20 may not be formed with circuits (e.g., transistors) required for the resulting semiconductor device to operate (e.g., no transistors, wiring, etc. at all, or only dummy structures such as one or more dummy transistors, wiring, etc.).

[0033] The semiconductor substrate 1 may be a bulk silicon wafer, a silicon-on-insulator (SOI) wafer, a germanium wafer, a germanium-on-insulator (GOI) wafer, a silicon-germanium wafer, or a thin wafer including an epitaxial layer formed by a selective epitaxial growth (SEG) process. The top (and / or the entirety) of the semiconductor substrate 1 may include a crystalline semiconductor material (e.g., those semiconductor materials mentioned herein).

[0034] According to an embodiment of the inventive concept, a three-dimensional semiconductor memory device including three-dimensionally arranged memory cells may be formed on each chip region 10 of a semiconductor substrate 1 .

[0035] Figure 2 is a perspective view schematically illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0036] Reference Figure 2 , Figure 3 , Figure 4A , Figure 4B and Figure 4C, a three-dimensional semiconductor memory device according to an embodiment of the inventive concept may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS. A through via TVS of the cell array structure CS may connect the cell array structure CS to the peripheral circuit structure PS. When viewed in a plan view, the cell array structure CS including a through hole region THR having a through insulating pattern 105 and having a through via TVS formed therein may cover the peripheral circuit structure PS.

[0037] In some embodiments, a variety of peripheral logic circuits, such as row and column decoders, page buffers, control circuits, and other peripheral logic circuits (e.g., formed by interconnected peripheral transistors) may be formed in the peripheral circuit structure PS. The peripheral transistors of the peripheral circuit structure PS may be integrated on the semiconductor substrate 1. For example, the source / drain regions of the peripheral logic circuits may be formed by portions of the semiconductor substrate 1 doped with charge carrier impurities (e.g., acceptor and / or donor dopants).

[0038] The cell array structure CS may include a cell array including a plurality of memory cells arranged in three dimensions. The cell array structure CS may include one or more mats MT, each of which is formed in a corresponding mat region MTR. Each mat MT may be controlled separately from other mats MT in the corresponding semiconductor device, so that concurrent access operations may be performed on several mats MT at the same time. Each mat MT may include a plurality of memory blocks BLK0, BLK1, ..., BLKn. Each memory block BLK0, BLK1, ..., BLKn may include a plurality of memory cells arranged in three dimensions.

[0039] For example, each memory block BLK0, BLK1, ..., BLKn may include a plurality of horizontal patterns stacked in sequence, a plurality of vertical patterns arranged to cross the horizontal patterns in a vertical direction, and a memory element between the side surfaces of the horizontal patterns and the vertical patterns. Each horizontal pattern may be formed of or include at least one conductive material (e.g., doped silicon or metal) and may be arranged in the form of a line or a plate.

[0040] Figure 3 is a schematic plan view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0041] refer to Figure 2 , Figure 3 , Figure 4A , Figure 4B and 4C The peripheral circuit structure PS and the cell array structure CS described and illustrated (and alternatives described herein) may be provided at each chip region 10 of the semiconductor substrate 1 .

[0042] At each chip region 10, a peripheral circuit structure PS (for example, see Figure 2 )'s row decoder ROW DEC and column decoder COL DEC, page buffer PBR and control circuit.

[0043] The cell array structure CS is formed (see, for example, Figure 2 ) may be disposed in each chip region 10. The plurality of pads MT may be arranged in the first direction D1 and the second direction D2. In one embodiment, the plurality of pads MT may be disposed on horizontal patterns 100a, 100b, 100a', and 100b' spaced apart from each other in the first direction D1 and the second direction D2, respectively.

[0044] A plurality of pads MT may be provided to cover a peripheral circuit structure PS including a peripheral logic circuit (see, for example, Figure 2 According to an embodiment of the inventive concept, the peripheral logic circuit of the peripheral circuit structure PS (eg, see Figure 2 ) can be arranged under the pad MT to reduce the constraints on its layout.

[0045] Figure 4A , Figure 4B and Figure 4C are plan views schematically illustrating some examples of cell array structures in a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0046] Reference Figure 4A , the cell array structure CS may include a plurality of pad regions MTR. The pad regions MTR may be spaced apart from each other in the first direction D1 and the second direction D2.

[0047] Horizontal patterns 100a, 100b, 100a', and 100b' may be respectively disposed in the pad region MTR, and memory structures including a plurality of three-dimensionally arranged memory cells may be respectively disposed on the horizontal patterns 100a, 100b, 100a', and 100b'.

[0048] The through hole regions THR (a plurality of through vias TVS are formed in each through hole region THR) may be disposed between pad regions MTR adjacent to each other in the first direction D1 and between pad regions MTR adjacent to each other in the second direction D2. The through hole regions THR may be spaced apart from each other in the first direction D1 and the second direction D2. The through hole regions THR may correspond to and be defined by corresponding through insulation patterns 105.

[0049] The separation structures DIT may be respectively disposed to extend between adjacent through hole regions THR. The horizontal patterns 100a, 100b, 100a', and 100b' adjacent to each other may be physically separated from each other and electrically disconnected from each other by the penetrating insulating patterns 105 and the separation structures DIT.

[0050] Reference Figure 4A and Figure 4B , in each chip region 10, the cell array structure CS may include a plurality of pad regions MTR. The pad regions MTR may be spaced apart from each other in the first direction D1 and the second direction D2.

[0051] Horizontal patterns 100a, 100b, 100a', and 100b' may be respectively disposed in the pad region MTR, and memory structures including a plurality of three-dimensionally arranged memory cells may be respectively disposed on the horizontal patterns 100a, 100b, 100a', and 100b'.

[0052] The through vias TVS may be disposed between the pad regions MTR adjacent to each other in the first direction D1 and between the pad regions MTR adjacent to each other in the second direction D2. The through vias TVS may be spaced apart from each other in the first direction D1 and the second direction D2.

[0053] The separation structures DIT may be respectively disposed between the through vias TVS adjacent to each other.

[0054] The separation structure DIT and a portion of the one or more through insulation patterns 105 may be disposed in the scribe line region 20 , and may also be disposed in the chip region 10 .

[0055] In one embodiment, when viewed in a plan view, each of the horizontal patterns 100a, 100b, 100a' and 100b' may be completely surrounded by the corresponding through-insulating pattern 105 and the separation structure DIT. Therefore, the horizontal patterns 100a, 100b, 100a' and 100b' adjacent to each other may be electrically disconnected from each other by the through-insulating pattern 105 and the separation structure DIT.

[0056] In one embodiment, each horizontal pattern 100a, 100b, 100a' and 100b' may have a first width W1 between two relative through-insulation patterns 105 on opposite sides of the horizontal pattern, and may have a second width W2 between two relative separation structures DIT (on these opposite sides of the horizontal pattern), and the second width W2 may be greater than the first width W1. Figure 4B An example of such different widths W1 and W2 measured in a first direction D1 is highlighted (and similarly different widths in a second direction D2 are shown, although not labeled).

[0057] according to Figure 4C The embodiment shown in the figure may omit reference Figure 4A and Figure 4B The described penetration insulating pattern 105. Specifically, the horizontal patterns 100a, 100b, 100a' and 100b' may be separated from each other by the separation structure DIT. In some examples, when viewed in a plan view, each of the horizontal patterns 100a, 100b, 100a' and 100b' may be completely surrounded by the separation structure DIT.

[0058] Reference FIG. 5A to FIG. 14 The through via TVS and the separation structure DIT according to an embodiment of the inventive concept are described in more detail.

[0059] Figure 5A , Figure 5B and Figure 5C is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Fig. 6A , Figure 6B , Figure 6C and Fig.6D are along Figure 5A The I-I' line, II-II' line, III-III' line and IV-IV' line of the embodiment of the present invention are intercepted to show the cross-sectional view of the three-dimensional semiconductor memory device according to the embodiment of the present invention. It should be understood that the cross-sectional views and related plan views in many drawings of the present application may not be precisely associated with each other to better convey the various features of the embodiment. For example, the number of repetitive structures of a particular element shown in the plan view may be different from the number of these repetitive structures of the particular element shown in the corresponding cross-sectional view. In addition, when an alternative structure of a cross-sectional view is shown via another cross-sectional view, this alternative structure may not be reflected in the plan view corresponding to the cross-sectional view showing this alternative structure.

[0060] Reference Figure 5A , Fig. 6A , Figure 6B and Figure 6C , a peripheral circuit structure PS including a peripheral transistor PTR may be disposed on and / or within the semiconductor substrate 1 , and a cell array structure CS may be disposed on the peripheral circuit structure PS.

[0061] Specifically, the peripheral circuit structure PS may include a peripheral transistor PTR integrated on (eg, on a top surface and / or within) the semiconductor substrate 1 and a lower insulating gap-filling layer 50 disposed to cover the peripheral transistor PTR.

[0062] The semiconductor substrate 1 may be a silicon wafer, a silicon germanium wafer, a germanium wafer, or a single crystal epitaxial layer grown on a single crystal silicon wafer. The semiconductor substrate 1 may include an active region defined by a device isolation layer 11 .

[0063] As described above, the peripheral logic circuit formed by the interconnected peripheral transistors PTR may include row and column decoders, page buffers, and control circuits. The peripheral transistors PTR may include NMOS transistors and PMOS transistors, low voltage transistors and high voltage transistors, and may be integrated on and / or within the semiconductor substrate 1. The peripheral circuit wiring 33 may be electrically connected to the peripheral transistors PTR through the peripheral contact plugs 31. For example, the peripheral contact plugs 31 and the peripheral circuit wiring 33 may be coupled to corresponding transistors among the NMOS transistors and the PMOS transistors constituting the peripheral transistors PTR.

[0064] The lower insulating gap-filling layer 50 may be provided to cover the peripheral gate electrode, the peripheral contact plug 31 and the peripheral circuit wiring 33. The lower insulating gap-filling layer 50 may include a plurality of stacked insulating layers. For example, the lower insulating gap-filling layer 50 may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer and / or a low-k dielectric layer.

[0065] The cell array structure CS may be disposed on the lower insulating gap-filling layer 50, and may include a plurality of pad regions MTR, through hole regions THR disposed between adjacent pad regions MTR, and dummy regions DR disposed between adjacent pad regions MTR and between adjacent through hole regions THR. The pad regions MTR may be disposed to be spaced apart from each other in the first direction D1 and the second direction D2, as previously described with reference to Figure 3 , Figure 4A and Figure 4B described.

[0066] The cell array structure CS may include memory structures respectively disposed in the pad regions MTR, through vias TVS respectively disposed in the through hole regions THR, and at least one separation structure DIT disposed in each dummy region DR.

[0067] Each memory structure may include a horizontal pattern 100 a or 100 b in each pad region MTR, a stack ST on the horizontal pattern 100 a or 100 b , and a vertical structure VS penetrating the stack ST.

[0068] Each through-hole TVS may be formed to extend through a through-insulating pattern 105 disposed between the horizontal patterns 100a and 100b. Each through-hole may include a through-plug TPLG and a sidewall spacer SS disposed to connect the peripheral circuit wiring 33 to the connection line CL. A group of through-hole TVS may be disposed in a corresponding through-hole region THR. In terms of a plan view, each through-hole region THR may have a boundary corresponding to a corresponding through-insulating pattern 105 (defined herein by a corresponding through-insulating pattern 105). When viewed in a plan view, at least one through-hole region THR may be disposed between a pair of stacks ST spaced apart from each other. In one embodiment, the through-hole region THR may be disposed between a pair of stacks ST spaced apart from each other in a first direction D1. The through-hole regions THR may be spaced apart from each other in a second direction D2.

[0069] The separation structure DIT may include a dummy plug DPLG and a dummy spacer DS disposed between the dummy plug DPLG and the horizontal pattern 100 a or 100 b .

[0070] More specifically, the horizontal patterns 100a and 100b may be disposed on the lower insulating gap-filling layer 50 of the peripheral circuit structure PS. The horizontal patterns 100a and 100b may be disposed in the pad region MTR, respectively, and a stack ST may be disposed on each of the horizontal patterns 100a or 100b.

[0071] The horizontal pattern 100a or 100b may be formed of or include at least one semiconductor material (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or aluminum gallium arsenide (AlGaAs)). The horizontal pattern 100a or 100b may be formed to have one of a polycrystalline, amorphous, and single crystal structure. As an example, the horizontal pattern 100a or 100b may be formed of a polycrystalline silicon layer doped with n-type impurities. As another example, the horizontal pattern 100a or 100b may be formed of or include at least one conductive material. The horizontal pattern 100a or 100b may include a cell array region CAR and a connection region CNR.

[0072] The stack ST may be formed in both the cell array region CAR and the connection region CNR. Each stack ST may include an insulating layer ILD and an electrode EL alternately stacked in a third direction D3 (e.g., a vertical direction) perpendicular to the first direction D1 and the second direction D2. The electrode EL of each stack ST may be stacked to form a stepped structure in an edge region (i.e., the connection region CNR) of each pad region MTR.

[0073] When measured in the first direction D1, as the distance from the horizontal pattern 100a or 100b increases, the length of the electrode EL of each stack ST can be reduced. Each electrode EL can have a pad portion located at its opposite end, and the pad portion of each electrode EL can be exposed by another electrode directly located thereon. The pad portion of the electrode EL can be located at different positions in the horizontal direction and the vertical direction. The electrode EL can be formed by at least one conductive material (for example, doped semiconductor material, metal silicide, metal material or metal nitride) or include at least one conductive material. The insulating layer ILD can be formed by silicon oxide or include silicon oxide.

[0074] Reference Fig. 6A , Figure 6B and Fig.6D , the vertical structure VS may be disposed to penetrate the stack ST in each pad region MTR and may be connected to the horizontal pattern 100a or 100b. When viewed in a plan view, the vertical structure VS may be arranged in a specific direction or may be arranged in a zigzag shape.

[0075] The vertical structure VS may include a semiconductor material (e.g., silicon (Si), germanium (Ge), or a mixture thereof). In some embodiments, the vertical structure VS may be formed of or include a doped semiconductor material or an intrinsic semiconductor material. The vertical structure VS including the semiconductor material may be used as a channel of a transistor constituting a NAND cell string (thus, each vertical structure VS may constitute a vertical channel of a corresponding vertically arranged NAND cell string).

[0076] The vertical insulation patterns VP may be disposed between the stack ST and the vertical structure VS. Each of the vertical insulation patterns VP may extend in the third direction D3 and surround a side surface of a corresponding vertical structure VS. Fig.6D In the embodiment shown in , the vertical insulation pattern VP extends in the third direction D3 and surrounds the side surface of the upper semiconductor pattern USP. The vertical insulation pattern VP may be shaped like a hollow tube or macaroni with its top and bottom opened.

[0077] The vertical insulating pattern VP may be formed of a single film or a plurality of films. In some embodiments, the vertical insulating pattern VP may be part of a data storage layer. For example, the vertical insulating pattern VP may include a tunnel insulating layer, a charge storage layer, and a blocking insulating layer, which are used as data storage layers of a NAND flash memory device. For example, the charge storage layer may be a trap insulating layer, a floating gate electrode, or an insulating layer including conductive nanodots. More specifically, the charge storage layer may be formed of and / or include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, or a stacked trap layer. The tunnel insulating layer may be one of the materials having a band gap greater than the band gap of the charge storage layer, and the blocking insulating layer may be at least one of a high-k dielectric material such as aluminum oxide and hafnium oxide. Alternatively, the vertical insulating pattern VP may include a thin film for a phase change memory or for a variable resistance memory.

[0078] Reference Fig.6D , in each pad region MTR, the common source plug CPLG may penetrate the stack ST in the third direction D3 and may contact the horizontal pattern 100a or 100b. A sidewall insulating spacer SP may be interposed between the common source plug CPLG and the stack ST. During a read or program operation of the three-dimensional NAND flash memory device, a source voltage may be applied to the horizontal pattern 100a or 100b through the common source plug CPLG.

[0079] In some embodiments, the three-dimensional semiconductor memory device may be a three-dimensional NAND flash memory device whose NAND cell string is integrated on the horizontal pattern 100a or 100b. In other words, the stack ST, the vertical structure VS, and the vertical insulating pattern VP including the data storage layer may form a memory cell, which is three-dimensionally arranged on the horizontal pattern 100a or 100b. In the stack ST, the electrode EL may be a word line (connected to be activated by a row decoder) and may form a gate electrode of a memory cell transistor of a cell string of the NAND flash memory device.

[0080] In one embodiment, the penetration insulating pattern 105 in the through hole region THR may be disposed between the horizontal patterns 100a and 100b. As an example, the penetration insulating pattern 105 may be disposed between the horizontal patterns 100a and 100b adjacent to each other in the first direction D1. The penetration insulating pattern 105 may contact the lower insulating gap-filling layer 50 and may contact the side surfaces of the horizontal patterns 100a and 100b adjacent to each other.

[0081] An upper insulating gap-filling layer 150 may be disposed on the horizontal pattern 100a or 100b and the through insulating pattern 105 to cover ends of the electrodes EL forming the step structure. A first interlayer insulating layer 160 may be disposed to cover top surfaces of the vertical structures VS.

[0082] The cell contact plugs PLG may be provided to penetrate the first interlayer insulating layer 160 and the upper insulating gap-filling layer 150 , and may be coupled to end portions of the electrodes EL, respectively.

[0083] The bit line BL may be disposed on the first interlayer insulating layer 160 and may extend in the second direction D2 to cross the stack ST. The bit line BL may be electrically connected to the vertical structure VS through a bit line contact plug BPLG.

[0084] The through plugs TPLG may be disposed to penetrate the first interlayer insulating layer 160, the upper insulating gap-filling layer 150, the through insulating pattern 105, and an upper portion of the lower insulating gap-filling layer 50, and may be coupled to the peripheral circuit wiring 33. Each of the through plugs TPLG may be surrounded by a sidewall spacer SS formed of an insulating material.

[0085] The through plugs TPLG may be respectively connected to the cell contact plugs PLG through the connection lines CL on the first interlayer insulating layer 160. Therefore, the through plugs TPLG may electrically connect the electrodes EL of the stack ST to the peripheral circuit wirings 33.

[0086] In some embodiments, at least two separation structures DIT may be disposed between the horizontal patterns 100a and 100b adjacent to each other in the first direction D1. The separation structures DIT may be disposed between adjacent through via TVS groups (adjacent to each other in the second direction D2), and the separation structures DIT may be spaced apart from each other in the first direction D1.

[0087] The separation structure DIT may be in contact with the penetration insulating pattern 105. Therefore, in the dummy region DR, the separation structure DIT may separate the horizontal patterns 100a and 100b from each other. The dummy horizontal pattern 100d may be disposed between each adjacent separation structure DIT. The dummy horizontal pattern 100d may be separated from the horizontal patterns 100a and 100b and may be disposed on the lower insulating gap filling layer 50. The dummy horizontal pattern 100d may be formed of the same material layer as the horizontal patterns 100a and 100b (e.g., patterned from the horizontal semiconductor layer 100).

[0088] The bottom surface of the separation structure DIT may be located at a height higher than the bottom surface of the through-plug TPLG. The bottom surface of the separation structure DIT may be in contact with the lower insulating gap-filling layer 50. The bottom surface of the separation structure DIT may be located at a height equal to or lower than the bottom surface of the horizontal pattern 100a or 100b. The top surface of the separation structure DIT may be located at the same height as the top surface of the through-plug TPLG.

[0089] Each separation structure DIT may include a dummy plug DPLG and a dummy spacer DS surrounding the dummy plug DPLG. The dummy plug DPLG may include: a vertical portion P1 disposed to penetrate the first interlayer insulating layer 160 and the upper insulating gap filling layer 150 in the third direction D3; and a horizontal portion P2 disposed between the horizontal patterns 100a and 100b to horizontally connect the vertical portions P1 to each other (eg, Figure 6C In one embodiment, the dummy plug DPLG may be formed of or include the same conductive material as the through plug TPLG (eg, formed of a material deposited during the same deposition process). FIG. 6A to FIG. 6C In the exemplary separation structure DIT shown in FIG. 1 , the vertical portions P1 of the dummy plugs DPLG are spaced apart from each other in the second direction D2, and the horizontal portions P2 of the dummy plugs DPLG extend in the second direction D2. However, it should be appreciated that for horizontal patterns (e.g., Figures 4A-4C The partition structure DIT between the dummy plugs 100a and 100a' in the figure may adopt an alternative orientation (e.g., rotated 90 degrees). In each dummy plug DPLG, the diameter A1 of the vertical portion P1 may be greater than or substantially equal to the diameter B1 of the through plug TPLG. In each dummy plug DPLG, the width A2 of the horizontal portion P2 in the first direction D1 may be greater than the width A1 of the vertical portion P1. As an example, the maximum width A2 of the horizontal portion may be at least 1.5 times, for example, about 1.5 times to 5 times, the maximum width A1 of the vertical portion P1.

[0090] In each dummy plug DPLG, a side surface of the horizontal portion P2 adjacent to the horizontal patterns 100a and 100b may be rounded or inclined. In each dummy plug DPLG, a top surface of the vertical portion P1 may be located at the same height as a top surface of the through-plug TPLG. In each dummy plug DPLG, a bottom surface of the horizontal portion P2 may be located at a height higher than a bottom surface of the through-plug TPLG.

[0091] The surface of the dummy plug DPLG may be surrounded by a dummy spacer DS made of an insulating material. The dummy spacer DS may extend from an area between the horizontal patterns 100a and 100b and the side surface of the dummy plug DPLG to another area between the through insulating pattern 105 and the side surface of the dummy plug DPLG. A portion of the dummy spacer DS may be disposed between the bottom surface of the dummy plug DPLG and the lower insulating gap-filling layer 50. The dummy spacer DS may be formed of the same insulating material as the sidewall spacer SS surrounding the through plug TPLG or include the same insulating material as the sidewall spacer SS surrounding the through plug TPLG (e.g., formed of a material deposited during the same deposition process).

[0092] Since a plurality of separation structures DIT are disposed separately from each other in the first direction D1, the horizontal patterns 100a and 100b can be completely separated from each other by other separation structures DIT. For example, in the case where one separation structure DIT does not contact the penetration insulating pattern 105, other separation structures DIT adjacently arranged in the first direction can be disposed to contact adjacent penetration insulating patterns 105 to ensure that the horizontal patterns 100a and 100b can be completely separated from each other.

[0093] In some embodiments, an example in which three separation structures DIT are provided is shown, but the number of separation structures DIT is not limited to this example. In one embodiment, only one separation structure DIT may be provided, extending between adjacent through-hole regions THR (e.g., extending between adjacent through-insulation patterns 105 and connected to adjacent through-insulation patterns 105).

[0094] The second interlayer insulating layer 170 may be disposed on the first interlayer insulating layer 160 to cover the bit lines BL and the connection lines CL. The second interlayer insulating layer 170 may directly cover the top surface of the separation structure DIT.

[0095] according to Figure 5B In the embodiment shown in FIG. 1 , the penetration insulating pattern 105 may be arranged to penetrate a portion of the stepped structure of the stacked ST. A plurality of separation structures DIT may be arranged between adjacent penetration insulating patterns 105 (in Figure 5B adjacent to each other in the second direction D2), and some of the separation structures DIT may penetrate the step structure of the stack ST.

[0096] according to Figure 5C In the embodiment shown in , the separation structure DIT may penetrate a portion of the stepped structure of the stack ST and may be connected to the penetrating insulation patterns 105 adjacent to each other in the second direction D2.

[0097] In the following, for the sake of simplicity, Figure 5A and FIG. 6A to FIG. 6DElements having the same features as those of the described three-dimensional semiconductor memory device may be identified by the same reference numerals without repeated description.

[0098] Fig. 7A and 7B is a cross-sectional view showing Fig. 6A and Figure 6B An alternative structure of the embodiment, and corresponding to respectively along Figure 5A sectional views taken along lines II' and II-II' of FIG. 1 are used to illustrate a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0099] Reference Fig. 7A and 7B , the peripheral circuit structure PS may further include an etch stop layer 60 covering the top surface of the peripheral circuit wiring 33. The etch stop layer 60 may be formed between different portions 50, 50' of the lower insulating gap-filling layer. The etch stop layer 60 may be formed of an insulating material having an etching selectivity with respect to the lower insulating gap-filling layer 50. The through plug TPLG may be provided to penetrate the lower insulating gap-filling layer 50' and the etch stop layer 60, and may contact the peripheral circuit wiring 33.

[0100] The metal plate pattern 101 may be disposed between the lower insulating gap filling layer 50' and the horizontal patterns 100a and 100b, respectively. The metal plate pattern 101 may contact the bottom surface of the horizontal patterns 100a and 100b. The metal plate pattern 101 may overlap the horizontal patterns 100a and 100b and may be spaced apart from each other. Similar to the horizontal patterns 100a and 100b described herein, the metal plate patterns 101 may be spaced apart from each other by penetrating the insulating pattern 105 and the separation structure DIT.

[0101] The metal plate pattern 101 may be formed of or include at least one of a metal material (e.g., tungsten, copper, aluminum, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a transition metal (e.g., titanium, tantalum, etc.), or a metal silicide material. In one embodiment, a predetermined voltage generated by a voltage generator during operation of the three-dimensional semiconductor memory device may be applied to the metal plate pattern 101.

[0102] The separation structure DIT may penetrate the horizontal patterns 100a and 100b and the metal plate pattern 101 in the third direction D3. A dummy metal pattern 101d spaced apart from the metal plate pattern 101 may be disposed between adjacent separation structures DIT. The dummy metal pattern 101d may be disposed between the dummy horizontal pattern 100d and the lower insulating gap-filling layer 50'.

[0103] Fig. 8A , Figure 8B and Figure 8C is a cross-sectional view showing Fig. 6A and Figure 6B An alternative structure of the embodiment, and corresponding to respectively along Figure 5A 1 and 2 are cross-sectional views taken along lines II', II-II', and IV-IV' to illustrate a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0104] Reference Fig. 8A , Figure 8B and Figure 8C , stacked STs spaced apart from each other may be disposed on the lower insulating gap-filling layer 50 , and first and second horizontal patterns 100 a / 100 b and 110 a / 110 b may be sequentially stacked between each stacked ST and the lower insulating gap-filling layer 50 .

[0105] The first horizontal pattern 100a / 100b and the second horizontal pattern 110a / 110b may be disposed in each pad region MTR and may be separated and spaced apart from each other. An insulating layer may be disposed between the first horizontal pattern 100a / 100b and the second horizontal pattern 110a / 110b, and the first horizontal pattern 100a / 100b and the second horizontal pattern 110a / 110b may contact each other.

[0106] The first horizontal pattern 100a / 100b and the second horizontal pattern 110a / 110b may be formed of a semiconductor material and may have one of a polycrystalline, amorphous, and single crystal structure. As an example, the first horizontal pattern 100a / 100b and the second horizontal pattern 110a / 110b may be formed of a polycrystalline silicon layer doped with n-type impurities. The concentration of the n-type impurities in the first horizontal pattern 100a / 100b may be different from the concentration of the n-type impurities in the second horizontal pattern 110a / 110b.

[0107] The vertical structure VS may be disposed to penetrate the stack ST and the second horizontal patterns 110 a and 110 b in each pad region MTR, and may be connected to the first horizontal pattern 100 a or 100 b .

[0108] Reference Figure 8C, in each pad region MTR, a source conductive pattern SCP may be disposed between the first horizontal pattern 100a / 100b and the second horizontal pattern 110a / 110b. The source conductive pattern SCP may extend along and parallel to the bottom surface of the stack ST. The source conductive pattern SCP may contact a portion of the side surface of the vertical structure VS including a semiconductor material. The source conductive pattern SCP may form a common source line operably connected to a cell string formed by the vertical structure VS (e.g., electrically connected to a NAND cell string).

[0109] The bottom surface of the source conductive pattern SCP may be in contact with the first horizontal pattern 100a or 100b, and the top surface of the source conductive pattern SCP may be in contact with the second horizontal patterns 110a and 110b. In one embodiment, an insulating layer (not shown) may be provided between the source conductive pattern SCP and the first horizontal pattern 100a or 100b. The source conductive pattern SCP may be formed of a semiconductor layer doped with an n-type dopant. A portion of the second horizontal patterns 110a and 110b may penetrate the source conductive pattern SCP.

[0110] The through insulating pattern 105 may penetrate the first and second horizontal patterns 100a / 100b and 110a / 110b adjacent to each other. The through insulating pattern 105 may contact the lower insulating gap-filling layer 50 and may contact side surfaces of the first and second horizontal patterns 100a / 100b and 110a / 110b adjacent to each other.

[0111] The separation structure DIT may be arranged to penetrate the first horizontal pattern 100a / 100b and the second horizontal pattern 110a / 110b in the dummy region DR. Each separation structure DIT may include a dummy plug DPLG and a dummy spacer DS surrounding the dummy plug DPLG. The dummy plug DPLG may include: a vertical portion P1 arranged to penetrate the first interlayer insulating layer 160 and the upper insulating gap filling layer 150 in the third direction D3; and a first horizontal portion P2 and a second horizontal portion P3 arranged in the first horizontal pattern 100a / 100b and the second horizontal pattern 110a / 110b to horizontally connect the vertical portions P1 to each other. The dummy spacer DS may conformally cover the vertical portion P1 and the first horizontal portion P2 and the second horizontal portion P3 of the dummy plug DPLG.

[0112] Fig.9A is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 9B is along Fig.9A A cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept is shown taken along line V-V'.

[0113] Reference Fig.9A and Fig. 9B , the horizontal pattern 100a or 100b may be disposed in each pad region MTR of the cell array structure CS, and the through via TVS may be disposed in the through hole region THR. In addition, the separation structure DIT may be disposed in each dummy region DR.

[0114] Each separation structure DIT may be disposed between adjacent through-insulation patterns 105 (eg, between Fig.9A The horizontal patterns 100a and 100b (for example, in the second direction D2) extend between and contact each other. Fig.9A A plurality of separation structures DIT are arranged side by side between the structures (adjacent to each other in the first direction D1).

[0115] The separation structures DIT may be spaced apart from each other in the first direction D1 , and the dummy horizontal pattern 100 d may be disposed between adjacent separation structures DIT.

[0116] Each separation structure DIT may extend in the second direction D2 and may be connected to the penetration insulating pattern 105. Each separation structure DIT may include a dummy spacer DS that contacts the horizontal pattern 100a or 100b in the first direction D1 and contacts the penetration insulating pattern 105 in the second direction D2. The dummy spacer DS may include a vertical portion P1 extending in the third direction D3 and a horizontal portion P2 that horizontally connects the vertical portions P1 to each other. In each dummy spacer DS, a diameter A2 of the vertical portion P1 may be smaller than a diameter B1 of the through-plug TPLG. Here, the vertical portion P1 and the horizontal portion P2 may be formed of an insulating material. In addition, each separation structure DIT may include an air gap AG in the horizontal portion P2.

[0117] Fig. 10A is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 10B is along Fig. 10A A cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept is shown taken along line VI-VI′.

[0118] Reference Fig. 10A and Fig. 10B , a single separation structure DIT can be formed between adjacent through-insulation patterns 105 (in Fig. 10A and 100b (in the second direction D2) and may be located between adjacent horizontal patterns 100a and 100b (in the second direction D2). Fig. 10A between the two adjacent to each other in the first direction D1).

[0119] The separation structure DIT may include a dummy plug DPLG and a dummy spacer DS surrounding the dummy plug DPLG. The dummy plug DPLG may include vertical portions P1 spaced apart from each other in the first and second directions D1 and D2 and share a single horizontal portion P2 horizontally connecting the vertical portions P1 together.

[0120] Fig. 10C and Fig. 10D is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept. Fig. 10C and Fig. 10D Alternative locations and configurations of a single discrete structure DIT (disposed between adjacent through-via TVS groups) are shown, and it should be understood that Fig. 10B The features in the cross-sectional views represent this alternative and repeated descriptions may be omitted.

[0121] Reference Fig. 10C The separation structure DIT may include a plurality of vertical portions P1 and one horizontal portion P2 to which the vertical portions P1 are connected together, and a width of the horizontal portion P2 in the first direction D1 may be greater than a width of the through insulating pattern 105 .

[0122] Reference Fig. 10D , the separation structure DIT including a plurality of vertical portions P1 and one horizontal portion P2 may penetrate a portion of the stepped structure of the stack ST.

[0123] The separation structures DIT may be respectively disposed between the groups of the through vias TVS, and here, the separation structures DIT may be staggered along the second direction D2.

[0124] Fig.11A is a plan view illustrating a portion of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 10B and Fig. 11C is along Fig.11A A cross-sectional view of a three-dimensional semiconductor memory device according to some embodiments of the inventive concept is shown taken along line VII-VII'.

[0125] Reference Fig.11A and Fig. 10B, each separation structure DIT may include a dummy plug DPLG and a dummy spacer DS surrounding the dummy plug DPLG. The dummy plug DPLG may be formed of or include the same conductive material as the through plug TPLG, and the dummy spacer DS may be formed of or include an insulating material. Here, the dummy plug DPLG may penetrate the first interlayer insulating layer 160 and the upper insulating gap filling layer 150 in the third direction D3, and may include a vertical portion P1 and a horizontal portion P2, wherein the top surface of the vertical portion P1 is shaped as a line extending in the second direction D2, and the horizontal portion P2 protrudes from the vertical portion P1 in the horizontal direction. When measured in the first direction D1, the width of the horizontal portion P2 may be greater than the width of the vertical portion P1. The horizontal portion P2 may have a rounded side surface, and the dummy spacer DS may be disposed between the horizontal portion P2 and the horizontal pattern 100a or 100b.

[0126] Fig. 11C Shown with Fig. 10B Compared to alternative structures. Fig. 11C In the embodiment shown in , each separation structure DIT may be arranged to continuously penetrate the first interlayer insulating layer 160, the upper insulating gap filling layer 150 and the horizontal semiconductor layer 100, and may be a linear pattern extending in the second direction D2 and connected to the through-hole TVS adjacent thereto. Here, the separation structure DIT may include a columnar pattern formed of an insulating material (i.e., without a conductive material, as in Fig. 9B described above).

[0127] Fig. 12A and Fig. 12B is along Figure 5A 1 and 2 are taken along lines II-II′ and III-III′ to illustrate cross-sectional views of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0128] Reference Fig. 12A and Fig. 12B , the separation structure DIT may include a dummy plug DPLG and a dummy spacer pattern DSP disposed between the dummy plug DPLG and the horizontal pattern 100a or 100b. Here, the dummy spacer pattern DSP may be disposed between the horizontal portion P2 of the dummy plug DPLG and the side surface of the horizontal pattern 100a or 100b.

[0129] Fig.13A , Fig. 13B and Fig. 13C is a cross-sectional view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0130] Reference Fig.13A and Fig. 13B, the dummy stack DST may be disposed on the horizontal semiconductor layer 100 between the pad regions MTR. Similar to the stack ST, the dummy stack DST may include dummy electrodes DEL and insulating layers ILD vertically alternately stacked on the horizontal semiconductor layer 100.

[0131] The dummy stack DST may be disposed on the through-insulating pattern 105 in the through-hole region THR. The through-plug TPLG may penetrate the dummy stack DST and the through-insulating pattern 105. The sidewall spacer SS may be disposed between the through-plug TPLG and the dummy stack DST. The separation structure DIT may penetrate the dummy stack DST in the dummy region DR. Each separation structure DIT may include a dummy plug DPLG and a dummy spacer DS surrounding the dummy plug DPLG. The vertical portion P1 of the dummy plug DPLG may penetrate the dummy stack DST, and the horizontal portion P2 may be disposed between the dummy stack DST and the lower insulating gap-filling layer 50.

[0132] Reference Fig. 13C , the dummy stack DST may include sacrificial layers SL and insulating layers ILD vertically alternately stacked on the horizontal semiconductor layer 100. The sacrificial layer SL may be formed at the same height as the electrode EL of the stack ST. The sacrificial layer SL may be formed of a sacrificial layer (not shown) used in the process of forming the electrode EL (e.g., replaced by the electrode EL).

[0133] Fig.14 is a plan view schematically illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0134] Reference Fig.14 , the stack ST may include a cell array region in which the vertical structure VS is disposed and a connection region having a step structure.

[0135] A first through hole region THR1, a second through hole region THR2, and a third through hole region THR3 may be provided, each of which includes a through hole region penetrating the horizontal semiconductor layer 100 (as described herein) and including a plurality of through vias TVS ( Fig.14The first through-via TVS1 may penetrate the area between the vertical structure VS and the stepped structure of the stacked ST. The second through-via TVS2 may penetrate a portion of the stepped structure of the stacked ST. In addition, the third through-via TVS3 may be disposed between the vertical structures VS that penetrate the stacked ST. In other words, the third through-via TVS3 may be disposed in a portion of the cell array region in which the memory cell is disposed. As described above, the first through-via TVS1, the second through-via TVS2, and the third through-via TVS3 may include a through-plug TPLG that connects the cell array structure CS to the peripheral circuit structure PS. The separation structure DIT may be disposed between adjacent stacked STs to separate adjacent horizontal patterns 100a and 100b from each other. The separation structure DIT may be configured to have the same structure as described herein, for example, with reference to FIG. 5A to FIG. 13C The same structure as any of those separate structures DIT described.

[0136] Fig.15 is a flowchart illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. FIG. 16A to FIG. 23A and FIG. 16B to FIG. 23B is a diagram illustrating a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. FIG. 16A to FIG. 23A shows a vertical cross section of a portion having a through hole formed thereon, FIG. 16B to FIG. 23B A vertical cross section of a portion on which a separation structure is formed is shown.

[0137] Reference Figure 4A , Fig.15 , Fig.16A and Fig. 16B , a peripheral circuit structure PS may be formed on the semiconductor substrate 1 (in S10 ).

[0138] The semiconductor substrate 1 may include a chip region and a scribe line region, as previously described with reference to Figure 1 The semiconductor substrate 1 may be a crystalline silicon (or other crystalline semiconductor) wafer.

[0139] The formation of the peripheral circuit structure PS may include: forming a peripheral transistor PTR in and / or on the semiconductor substrate 1; forming peripheral interconnect structures 31 and 33 to provide electrical connections to and between the peripheral transistors PTR; and forming a lower insulating gap filling layer 50 (e.g., including several interlayer dielectric layers of the peripheral circuit structure PS to insulate the respective peripheral interconnect structures 31 and 33 from each other). A peripheral logic circuit may be formed by interconnecting several peripheral transistors PTR, for example, through the peripheral interconnect structures 31 and 33. In addition, the peripheral interconnect structures 31 and 33 may connect the peripheral logic circuit to, for example, Fig. 6AIt should be understood that the peripheral interconnect structures 31 and 33 and the peripheral transistors PTR shown in the drawings are simplified for illustrative purposes, and that many more peripheral transistors PTR and more complex electrical interconnections therebetween will typically be implemented.

[0140] Row and column decoders, page buffers, and control circuits (constituting a peripheral logic circuit formed by interconnected peripheral transistors PTR) may be formed at each chip region of the semiconductor substrate 1. As an example, the formation of the peripheral logic circuit may include forming a device isolation layer 11 in a trench formed in the semiconductor substrate 1 (the device isolation layer 11 defines an active region in the semiconductor substrate 1). Each peripheral transistor may be formed by sequentially forming a peripheral gate insulating layer and a peripheral gate electrode on the semiconductor substrate 1, and implanting impurities into portions of the semiconductor substrate 1 on both sides of the peripheral gate electrode to form corresponding source / drain regions of the peripheral transistor PTR within the semiconductor substrate 1. Gate spacers may be formed on the side surfaces of the peripheral gate electrode.

[0141] The formation of the peripheral interconnect structures 31 and 33 may include: forming a peripheral contact plug 31 penetrating a portion of the lower insulating gap-filling layer 50 ; and forming a peripheral circuit wiring 33 connected to the peripheral contact plug 31 .

[0142] After forming the peripheral transistor PTR and the peripheral interconnect structure, an additional layer of lower insulating gap-filling layer 50 may be formed to cover the entire top surface of semiconductor substrate 1. Lower insulating gap-filling layer 50 may have a planarized top surface and may be patterned to expose the top surface of an edge portion of semiconductor substrate 1.

[0143] The lower insulating gap-filling layer 50 may include a single insulating layer or a plurality of stacked insulating layers, and may include, for example, one or more silicon oxide layers, one or more silicon nitride layers, one or more silicon oxynitride layers, and / or one or more low-k dielectric layers.

[0144] After forming the peripheral circuit structure PS, the horizontal semiconductor layer 100 may be formed to cover the peripheral circuit structure PS (in S20 ).

[0145] Specifically, the horizontal semiconductor layer 100 may be formed on the lower insulating gap-filling layer 50. The horizontal semiconductor layer 100 may be formed of a semiconductor material and may have a single crystal or polycrystalline structure. A portion of the horizontal semiconductor layer 100 may be made conductive by doping the horizontal semiconductor layer 100 with a charge carrier dopant. Through the selective doping of the horizontal semiconductor layer 100, wiring may be formed therein to interconnect various elements of the cell array structure CS. In some examples, the selective doping of the horizontal semiconductor layer 100 may form source / drain regions of transistors formed on and / or in the horizontal semiconductor layer 100.

[0146] The horizontal semiconductor layer 100 may be formed on the top surface of the semiconductor substrate 1 using a deposition process. The horizontal semiconductor layer 100 may be epitaxially grown on the top surface of the semiconductor substrate 1. In one embodiment, when viewed in a plan view, the horizontal semiconductor layer 100 may be formed to extend in a first direction D1 and a second direction D2 that intersect each other, and may cover a plurality of chip regions 10 (e.g., see FIG. 1 ) of the semiconductor substrate 1. Figure 1 ). In each chip region 10 (see, for example, Figure 1 ), the horizontal semiconductor layer 100 may include a plurality of pad regions MTR and through hole regions THR therebetween.

[0147] As an example, the horizontal semiconductor layer 100 may be formed by depositing a polysilicon layer on the semiconductor substrate 1. In one embodiment, the polysilicon layer may be doped with impurities of the first conductivity type during its deposition process. Alternatively, the horizontal semiconductor layer 100 may be formed by depositing an undoped polysilicon layer and then doping the undoped polysilicon layer with impurities of the first conductivity type.

[0148] In one embodiment, since the horizontal semiconductor layer 100 is formed by a blanket deposition process, the horizontal semiconductor layer 100 may be formed to cover the top surface and side surfaces of the lower insulating gap-filling layer 50 and the top surface of the edge portion of the semiconductor substrate 1. Thus, the horizontal semiconductor layer 100 may be in contact with the semiconductor substrate 1 in the edge portion of the semiconductor substrate 1. The top surface of the horizontal semiconductor layer 100 (at least the top surface of the horizontal semiconductor layer 100 formed in the chip region 10) may be substantially flat (for example, due to a planarization process such as CMP performed after blanket deposition or epitaxial growth of the horizontal semiconductor layer 100 material).

[0149] Next, a penetrating insulating pattern 105 may be formed to penetrate a portion of the horizontal semiconductor layer 100 (in S30 ).

[0150] Specifically, after forming the horizontal semiconductor layer 100, the portion of the horizontal semiconductor layer 100 between the pad regions MTR may be etched to form an opening exposing the lower insulating gap-filling layer 50. The opening may be formed between the pad regions MTR. Thereafter, an insulating material may be deposited in the opening formed in the horizontal semiconductor layer 100 to form a through insulating pattern 105. Thus, the through insulating pattern 105 may be formed to penetrate the portion of the horizontal semiconductor layer 100 between the pad regions MTR.

[0151] Reference Figure 4A , Fig.15 , Fig.17A and Fig. 17B, the stack structure 110 may be formed to cover the top surface of the horizontal semiconductor layer 100 (in S40 ).

[0152] The stacked structure 110 may include a sacrificial layer SL and an insulating layer ILD that are alternately and repeatedly stacked. In the stacked structure 110, the sacrificial layer SL may have substantially the same thickness. The sacrificial layer SL and the insulating layer ILD may be formed by a thermal chemical vapor deposition (thermal CVD) process, a plasma enhanced CVD process, or an atomic layer deposition (ALD) process. Since the stacked structure 110 is formed by a deposition process, the stacked structure 110 may extend from the top surface of the horizontal semiconductor layer 100 to the top surface of the semiconductor substrate 1.

[0153] In the stacked structure 110, the sacrificial layer SL may be formed of a material that can be selectively etched and removed without significantly etching the insulating layer ILD. In one embodiment, the sacrificial layer SL and the insulating layer ILD may have a high etching selectivity in a wet etching process using a chemical solution, or may have a low etching selectivity in a dry etching process using an etching gas. As an example, the sacrificial layer SL and the insulating layer ILD may be formed of an insulating material having an etching selectivity relative to each other. For example, the sacrificial layer SL may be formed of a silicon nitride layer, and the insulating layer ILD may be formed of a silicon oxide layer.

[0154] Reference Figure 4A , Fig.15 , Fig.18A and Fig.18B , a patterning process may be performed on the stack structure 110 to form a mold structure 120 in each pad region MTR (in S50 ).

[0155] The mold structure 120 may be formed by performing a trimming process on the stacked structure 110. Here, the trimming process may include the following steps: forming a mask pattern (not shown) on the stacked structure; etching a portion of the stacked structure; reducing the horizontal area of ​​the mask pattern; and removing the mask pattern; here, before the step of removing the mask pattern, the steps of etching a portion of the stacked structure and reducing the horizontal area of ​​the mask pattern may be repeated several times. As a result of the trimming process, each mold structure 120 may have a step structure in the edge portion of each pad region MTR. At the same time, the outermost portion of the mold structure 120 close to the edge portion of the semiconductor substrate 1 may extend to cover the side surface of the peripheral circuit structure PS and contact the edge portion of the semiconductor substrate 1.

[0156] An upper insulating gap-filling layer 150 may be formed on the horizontal semiconductor layer 100 on which the mold structure 120 is formed. The formation of the upper insulating gap-filling layer 150 may include depositing a thick insulating layer to cover the mold structure 120 and performing a planarization process on the insulating layer. The upper insulating gap-filling layer 150 may be formed of an insulating material having an etching selectivity with respect to the sacrificial layer SL.

[0157] Reference Figure 4A , Fig.19A , Fig.19B , Fig. 20A and Fig. 20B , a plurality of vertical structures may be formed to penetrate each mold structure (in S60 ).

[0158] Specifically, refer to Fig.19A and Fig.19B After forming the upper insulating gap-filling layer 150, a hard mask layer MP may be formed, the hard mask layer MP having openings exposing some portions of each mold structure 120. The hard mask layer MP may be formed of or include at least one of a silicon-containing material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or polysilicon), a carbon-containing material (e.g., an amorphous carbon layer (ACL) or a spin-on hard mask (SOH)), a metal material (e.g., tungsten), or an organic material.

[0159] In some embodiments, in the edge portion of the semiconductor substrate 1 , the hard mask layer MP may be formed to cover the top surface of the semiconductor substrate 1 , and may be in contact with the horizontal semiconductor layer 100 and the top surface of the edge portion of the semiconductor substrate 1 .

[0160] Next, the portion of the mold structure 120 exposed by the opening of the hard mask layer MP may be anisotropically etched to form a vertical hole VH exposing the horizontal semiconductor layer 100 in each mold structure 120. When viewed in a plan view, the vertical holes VH may be arranged in a specific direction (e.g., linearly) or may be arranged in a zigzag shape. Here, the anisotropic etching process for the mold structure 120 may be, for example, a plasma etching process, a reactive ion etching (RIE) process, an inductively coupled plasma reactive ion etching (ICP-RIE) process, or an ion beam etching (IBE) process.

[0161] In one embodiment, when the anisotropic etching process is performed using high power plasma, positive charges caused by ions and / or radicals in the plasma may be accumulated or charged on the surface of the horizontal semiconductor layer 100 exposed through the vertical hole VH.

[0162] In addition, according to an embodiment of the present invention, during the manufacture of a three-dimensional semiconductor device, the semiconductor substrate 1 can be placed on a support member (not shown) of a semiconductor manufacturing system, and during the anisotropic etching process of forming the vertical hole VH, a ground voltage from the support member can be applied to the semiconductor substrate 1.

[0163] Since the portions of the horizontal semiconductor layer 100 in the pad region MTR are connected to each other and meet the top surface of the edge portion of the semiconductor substrate 1 during the anisotropic etching process using plasma, the positive charges accumulated in the horizontal semiconductor layer 100 during the formation of the vertical hole VH may be discharged through the semiconductor substrate 1. For example, the horizontal semiconductor layers 100 formed in each pad region MTR are connected to each other through other portions of the horizontal semiconductor layer 100. For example, each portion of the horizontal semiconductor layer 100 formed in each pad region MTR in some or all of the chip regions 10 may have an electrical path to the same discharge position (e.g., at the top surface of the edge portion of the semiconductor substrate 1).

[0164] Since the ground voltage is applied to the horizontal semiconductor layer 100 (a single continuous layer throughout the semiconductor substrate 1 ) during the formation of the vertical hole VH, an arc phenomenon may be prevented from occurring in the horizontal semiconductor layer 100 due to positive charges accumulated in the horizontal semiconductor layer 100 .

[0165] In addition, in the case where the hard mask layer MP includes an amorphous carbon layer (ACL), negative charges may be accumulated or charged in the amorphous carbon layer during the anisotropic etching process using plasma. In this case, since the hard mask layer MP is in contact with the semiconductor substrate 1 and the horizontal semiconductor layer 100 in the edge portion of the semiconductor substrate 1, the negative charges in the hard mask layer MP may be discharged through the semiconductor substrate 1. For example, the hard mask layers MP formed in each pad region MTR are connected to each other through other portions of the hard mask layer MP. For example, each portion of the hard mask layer MP formed in each pad region MTR in some or all of the chip regions 10 may have an electrical path to the same discharge position (e.g., at the top surface of the edge portion of the semiconductor substrate 1).

[0166] Next, refer to Fig. 20A and Fig. 20B , a vertical structure VS may be formed in the vertical hole VH. As described above, the vertical structure VS may be formed of or include at least one of a semiconductor or a conductive material.

[0167] The formation of the vertical structure VS may include forming a semiconductor spacer that exposes the horizontal semiconductor layer 100 and covers the side surface of the opening and forming a semiconductor body portion connected to the horizontal semiconductor layer 100. The vertical structure VS may include a semiconductor material (e.g., silicon (Si), germanium (Ge) or a mixture thereof) and may be a doped semiconductor material or an intrinsic semiconductor material. The vertical structure VS may be connected to the horizontal semiconductor layer 100. In addition, a conductive pad (e.g., Fig.6D The conductive pad may be an impurity region doped with impurities or may be formed of a conductive material.

[0168] In addition, before forming the vertical structure VS in the vertical hole VH, a vertical insulation pattern VP may be formed in the vertical hole VH. The vertical insulation pattern VP may be formed of a single film or a plurality of films. In some embodiments, the vertical insulation pattern VP may be a part of a data storage layer.

[0169] Next, refer to Figure 4A , Fig. 20A and Fig. 20B After forming the vertical structure VS, the sacrificial layer SL of the mold structure 120 may be replaced with the electrode EL (in S70). Therefore, a stack ST may be formed on the horizontal semiconductor layer 100, and here, each stack ST may include a vertically stacked electrode EL. In some examples, some portions of the sacrificial layer SL of the mold structure 120 may not be etched and remain after removing other portions of the sacrificial layer SL (e.g., forming a vertical structure VS). FIG. 13A to FIG. 13C The virtual stack DST).

[0170] More specifically, after forming the vertical structure VS, the mold structure 120 may be patterned to form a groove spaced apart from the vertical structure VS and having a line shape. As a result of forming the groove, side surfaces of the insulating layer ILD and the sacrificial layer SL of the mold structure 120 may be exposed.

[0171] Next, the sacrificial layer SL exposed by the trench may be removed to form a gate region between the insulating layers ILD. The gate region may be formed by isotropically etching the sacrificial layer SL using an etching recipe selected to have an etching selectivity with respect to the insulating layer ILD, the vertical structure VS, and the horizontal semiconductor layer 100. For example, in the case where the sacrificial layer SL is a silicon nitride layer and the insulating layer ILD is a silicon oxide layer, the etching step may be performed by an isotropic etching process using an etching solution including phosphoric acid.

[0172] Next, an electrode EL may be formed in the gate region. The electrode EL may be formed to partially or completely fill the gate region. Each electrode EL may include a barrier metal layer and a metal layer deposited sequentially. As a result of forming the electrode EL, a stack ST may be formed on each pad region MTR of the horizontal semiconductor layer 100, and the stack ST may have a stepped structure on an edge portion of each pad region MTR.

[0173] Reference Figure 4A , Fig.21A , Fig. 21B , Fig.22A and Fig. 22B , horizontal patterns 100 a and 100 b spaced apart from each other may be formed on each pad region MTR (in S80 ).

[0174] Specifically, refer to Fig.21A and Fig. 21B , a first interlayer insulating layer 160 may be formed to cover the stack ST and the upper insulating gap-filling layer 150. A through hole TH may be formed between adjacent stack STs to penetrate the first interlayer insulating layer 160, the upper insulating gap-filling layer 150, and the through insulating pattern 105 and expose the peripheral circuit wiring 33.

[0175] During the formation of the through hole TH, a dummy hole DH may be formed in a dummy region DR disposed between adjacent pad regions MTR and between adjacent through hole regions THR. The width of the dummy hole DH may be less than or equal to the width of the through hole TH. The dummy holes DH may be formed to be spaced apart from each other in the first direction D1 and the second direction D2.

[0176] The through hole TH and the dummy hole DH may be formed by anisotropically etching the first interlayer insulating layer 160, the upper insulating gap-filling layer 150, the penetration insulating pattern 105, and the lower insulating gap-filling layer 50. The through hole TH and the dummy hole DH may be formed simultaneously using the same etching mask. When the through hole TH is formed simultaneously with the dummy hole DH, a portion of the horizontal semiconductor layer 100 may remain on the dummy region DR, and in this case, the horizontal semiconductor layer 100 on the dummy region DR may be used as an etching stop layer. Thus, the dummy hole DH may expose the horizontal semiconductor layer 100.

[0177] Reference Fig.22A and Fig. 22BAfter forming the through hole TH and the dummy hole DH, the portion of the horizontal semiconductor layer 100 exposed by the dummy hole DH may be subjected to an isotropic etching process. Therefore, the lower portion of the dummy hole DH may be expanded to form an expanded dummy hole DEH in the dummy region DR. Each expanded dummy hole DEH extends between adjacent penetration insulating patterns 105 and exposes the adjacent penetration insulating patterns 105 (e.g., extends between and exposes the adjacent penetration insulating patterns 105 in the second direction D2—e.g., corresponding to Figure 5A The distance between the dummy holes DH in the first direction D1 may be greater than the distance between the dummy holes DH in the second direction D2. In this example, the expanded dummy hole DEH may connect to the adjacent dummy holes DH arranged in the second direction D2, but may not connect to the adjacent dummy holes arranged in the first direction D1 (e.g., corresponding to Figure 5A In other examples, the expanded dummy holes DEH may connect adjacent dummy holes DH arranged in the first direction D1 and adjacent dummy holes DH arranged in the second direction D2 (eg, corresponding to Fig. 10A DIT shown in ).

[0178] The process of etching the horizontal semiconductor layer 100 may be performed using a chemical physical etching method such as reactive ion etching (RIE), a wet etching method using an etchant, a chemical pyrolytic etching method such as gas phase etching (GPE), and a combination of these methods.

[0179] The extended dummy hole DEH may be formed by isotropically etching the horizontal semiconductor layer 100 until the penetration insulating pattern 105 is exposed in the dummy region DR. Therefore, the horizontal semiconductor layer 100 may be divided into a plurality of horizontal patterns 100a and 100b. For example, the horizontal pattern 100a or 100b may be formed on each pad region MTR. When forming the extended dummy hole DEH, a portion of the horizontal semiconductor layer 100 may remain between adjacent extended dummy holes DEH to form a dummy horizontal pattern 100d.

[0180] Next, a spacer layer 200 may be formed on the inner surfaces of the through hole TH and the extended dummy hole DEH. The spacer layer 200 may conformally cover the side surfaces and bottom surfaces of the through hole TH and the extended dummy hole DEH. The spacer layer 200 may cover the top surface of the peripheral circuit wiring 33 exposed by the through hole TH and the surfaces of the horizontal patterns 100a and 100b exposed by the extended dummy hole DEH.

[0181] Next, refer to Figure 4A , Fig.23A and Fig. 23B, an anisotropic etching process may be performed on the spacer layer 200 to form a sidewall spacer SS that covers the side surface of the through hole TH and exposes the peripheral circuit wiring 33 .

[0182] When forming the sidewall spacer SS, a dummy spacer DS may be formed in the extended dummy hole DEH. The sidewall spacer SS may be formed simultaneously with the dummy spacer DS (e.g., patterned by the same spacer layer 200). In some examples, the spacer layer 200 may be etched at the bottom of the extended dummy hole DEH to expose a portion of the lower insulating gap-filling layer 50 at the bottom of the extended dummy hole DEH ( Fig. 23B dummy spacers DS are formed by using a dummy spacer DS (not shown).

[0183] Next, refer to Figure 4A and Fig.23A , a through via TVS may be formed between adjacent pad regions MTR in the through hole region THR (in S90 ).

[0184] Specifically, a conductive material may be formed to fill the through hole TH in which the sidewall spacer SS is formed, and the dummy hole DH and the extended dummy hole DEH in which the dummy spacer DS is formed. Thus, a through plug TPLG may be formed in the through hole TH in which the sidewall spacer SS is formed, and a dummy plug DPLG may be formed in the dummy hole DH and the extended dummy hole DEH. The through plug TPLG may be connected to the peripheral circuit wiring 33, and the dummy plug DPLG may be surrounded by the dummy spacer DS. The dummy plug DPLG may not be connected to the peripheral logic circuit (not connected to any wiring in the peripheral circuit structure PS). In some examples, the dummy plug DPLG may be electrically floating. In other examples, the dummy plug DPLG may be connected to a voltage source (e.g., a reference voltage source such as ground or a bias voltage source such as Vbb or Vcc).

[0185] Next, the bit lines BL and the connection lines CL described above may be formed on the first interlayer insulating layer 160. Thereafter, a cutting or sawing machine may be used to cut the bit lines BL and the connection lines CL along the scribe line regions 20 (eg, see FIG. 2 ). Figure 1 ) cutting the semiconductor substrate 1, thus, the three-dimensional semiconductor device formed on the semiconductor substrate 1 can be divided into a plurality of semiconductor chips (for example, each semiconductor chip corresponds to a semiconductor device cut out from the chip region 10).

[0186] According to an embodiment of the inventive concept, during a manufacturing process using high frequency power, a horizontal semiconductor layer including a plurality of pad regions is formed of a single layer and can be grounded. Thus, in the process of manufacturing a three-dimensional semiconductor memory device using high frequency power, an arc phenomenon caused by positive charges accumulated in the horizontal semiconductor layer can be prevented.

[0187] After the high-frequency power process, a single horizontal semiconductor layer can be divided into a plurality of horizontal patterns corresponding to the pad regions. In other words, the horizontal patterns can be respectively arranged in the pad regions. In addition, the horizontal patterns can be electrically and physically separated from each other (e.g., to form separated pad regions MTR) by penetrating the insulating pattern and the separation structure. Therefore, the operation of the three-dimensional semiconductor device (e.g., a three-dimensional semiconductor device including a NAND flash memory cell) can be independently performed at each separated horizontal pattern (e.g., independent concurrent memory access to the pad MT at each pad region MTR).

[0188] While example embodiments of the inventive concept have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. A three-dimensional semiconductor memory device, comprising: horizontal patterns disposed on the peripheral circuit structure and spaced apart from each other in a first direction parallel to a top surface of the substrate; Memory structures are respectively arranged on the horizontal patterns, each of the memory structures comprising three-dimensionally arranged memory cells; penetrating insulating patterns, each of which is disposed between adjacent horizontal patterns and spaced apart from each other in a second direction crossing the first direction, each of which is adjacent to a side surface of the horizontal pattern, a through plug extending through a corresponding through-insulation pattern to electrically connect the memory structure to the peripheral circuit structure; as well as a separation structure disposed between the horizontal patterns and extending between the penetration insulating patterns in the second direction and connected to the penetration insulating patterns, wherein the horizontal pattern is a part of the first material layer, and Each of the penetration insulating patterns penetrates the first material layer and has an opposing boundary extending between the side surfaces of the horizontal patterns, and the opposing boundary has a portion defined by the first material layer.

2. The three-dimensional semiconductor memory device according to claim 1, wherein: A bottom surface of the separation structure is located at a higher height than a bottom surface of the through-plug.

3. The three-dimensional semiconductor memory device according to claim 1, wherein: The separation structure includes an insulator that contacts at least one horizontal pattern and contacts the penetration insulating pattern.

4. The three-dimensional semiconductor memory device according to claim 3, further comprising: a sidewall spacer surrounding a side surface of the through plug, Wherein, the sidewall spacer comprises the same insulating material as the insulator.

5. The three-dimensional semiconductor memory device according to claim 1, wherein: The separation structure comprises: a dummy plug including the same conductive material as the through plug and extending in a third direction perpendicular to the first direction and the second direction; and A dummy spacer surrounds the dummy plug.

6. The three-dimensional semiconductor memory device according to claim 5, wherein: A top surface of the dummy plug is located at the same height as a top surface of the through plug.

7. The three-dimensional semiconductor memory device according to claim 1, wherein: The separation structure comprises: a dummy plug disposed between the horizontal patterns; and a dummy spacer disposed between the dummy plug and the horizontal pattern, wherein the dummy plug includes a horizontal portion extending in the second direction and a vertical portion extending from the horizontal portion in a third direction perpendicular to the first direction and the second direction, and The width of the horizontal portion is at least 1.5 times the width of the vertical portion when measured in the first direction.

8. The three-dimensional semiconductor memory device according to claim 7, wherein: A portion of the dummy spacer extends from a region between the horizontal portion and the horizontal pattern to a region between the horizontal portion and the through insulating pattern.

9. The three-dimensional semiconductor memory device according to claim 7, wherein: A portion of the dummy spacer is disposed between a bottom surface of the dummy plug and a top surface of the peripheral circuit structure.

10. The three-dimensional semiconductor memory device according to claim 7, wherein: The horizontal portion of the dummy plug has a rounded side surface.

11. The three-dimensional semiconductor memory device according to claim 1, wherein: The separation structure comprises: dummy plugs, each of the dummy plugs comprising: vertical portions extending in a vertical direction and spaced apart from each other in the second direction; and a shared horizontal portion connecting the vertical portions in the second direction; and A dummy spacer surrounds the dummy plug.

12. The three-dimensional semiconductor memory device according to claim 11, wherein: The width of the vertical portion is greater than the diameter of the through-plug when measured in the first direction.

13. The three-dimensional semiconductor memory device according to claim 1, wherein: Each of the memory structures comprises: a stack comprising electrodes vertically stacked on each of the horizontal patterns, the stack having a stepped structure in an edge region of each of the horizontal patterns; and A vertical structure, penetrating the stack, Wherein, the penetration insulation pattern is arranged between adjacent stacked stepped structures.

14. The device according to claim 1, wherein The opposing boundaries of the through insulation patterns extend in the first direction.

15. The device according to claim 1, wherein Each of the opposite boundaries of the through insulation pattern has a surface portion contacting the first material layer.

16. A three-dimensional semiconductor memory device, comprising: A horizontal pattern, disposed on the peripheral circuit structure; Memory structures are respectively arranged on the horizontal patterns, each of the memory structures comprising three-dimensionally arranged memory cells; a penetrating insulating pattern disposed between adjacent horizontal patterns and adjacent to side surfaces of the horizontal patterns; a through-plug penetrating a corresponding through-insulation pattern and electrically connecting the memory structure to the peripheral circuit structure; as well as a plurality of separation structures arranged side by side between the horizontal patterns and extending between and contacting the penetration insulating patterns; as well as Dummy horizontal patterns are discretely formed between adjacent pairs of through-insulation patterns and adjacent pairs of separation structures, The dummy horizontal patterns are in contact with adjacent pairs of penetration insulation patterns and adjacent pairs of separation structures.

17. The three-dimensional semiconductor memory device according to claim 16, wherein: At least some of the separation structures are formed of an insulating material that abuts side surfaces of the corresponding horizontal patterns.

18. A three-dimensional semiconductor memory device, comprising: A peripheral circuit structure, comprising a substrate and a peripheral logic circuit formed on the substrate; horizontal patterns disposed on the peripheral circuit structure and spaced apart from each other in a first direction; Memory structures are respectively arranged on the horizontal patterns, each of the memory structures comprising three-dimensionally arranged memory cells; as well as Separation structure, set between adjacent horizontal patterns, Wherein, the separation structure comprises: a dummy plug disposed between the horizontal patterns; and a dummy spacer disposed between the dummy plug and the horizontal pattern, wherein the dummy plug includes a horizontal portion extending in a second direction intersecting the first direction and a vertical portion extending from the horizontal portion in a third direction perpendicular to the first direction and the second direction, and The width of the horizontal portion is at least 1.5 times the width of the vertical portion when measured in the first direction.

19. The three-dimensional semiconductor memory device according to claim 18, wherein: When viewed in a plan view, the separation structure is disposed to surround and electrically isolate at least one horizontal pattern.

20. The three-dimensional semiconductor memory device according to claim 18, in, Each of the memory structures comprises a first stack comprising electrodes stacked vertically on a corresponding horizontal pattern, wherein the three-dimensional semiconductor memory device further comprises a dummy stack, the dummy stack being spaced apart from the first stack and comprising a horizontal layer disposed at the same height as the electrode of the first stack, and Wherein, the separation structure penetrates the dummy stack.

21. The three-dimensional semiconductor memory device according to claim 18, further comprising: first through insulating patterns and second through insulating patterns disposed between and in contact with side surfaces of adjacent horizontal patterns; as well as a through plug penetrating the first through insulation pattern and the second through insulation pattern to operably connect the memory structure to the peripheral circuit structure, The separation structure extends between the first through insulation pattern and the second through insulation pattern and contacts the first through insulation pattern and the second through insulation pattern.

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