Semiconductor device and manufacturing method

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing. A semiconductor device and method are provided, whereby a series of spacers are formed in a first region and a second region of a substrate. The series of spacers in the first region are patterned, while the series of spacers in the second region are protected so as to separate the properties of the spacers in the first region from the properties of the spacers in the second region.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor devices and methods of manufacturing. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry has been increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate, the substrate comprising a first fin in a first region and a second fin in a second region; a first gate stack located above the first fin and a second gate stack located above the second fin; a first plurality of spacers adjacent to the first gate stack, the first plurality of spacers having a first width, wherein at least two spacers of the first plurality of spacers have side walls that are in physical contact with the first gate stack; and a second plurality of spacers adjacent to the second gate stack, the second plurality of spacers having a second width greater than the first width, wherein a first spacer of the second plurality of spacers separates the second gate stack from each other spacer within the second plurality of spacers.

[0005] According to another embodiment of the present disclosure, a semiconductor device is provided, comprising: a spacer stack adjacent to a first gate stack above a first semiconductor fin, wherein a width of each spacer in the spacer stack is no greater than a top spacer in the spacer stack, the spacer stack having a first width and being located in a core region of a semiconductor substrate; and a first plurality of spacers adjacent to a second gate stack above a second semiconductor fin, at least one spacer of the first plurality of spacers having an "L" shape, the first plurality of spacers having a second width greater than the first width.

[0006] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: blanket depositing a first material adjacent to a first dummy gate electrode over a first semiconductor fin and adjacent to a second dummy gate electrode over a second semiconductor fin; blanket depositing a second material adjacent to the first material; patterning the first material and the second material to form a first spacer and a second spacer adjacent to the first dummy gate electrode and a third spacer and a fourth spacer adjacent to the second dummy gate electrode, wherein the patterning is at least partially performed using one or more anisotropic etching processes; removing the first dummy gate electrode and the second dummy gate electrode; etching the first material of the first spacer to expose sidewalls of the second material of the second spacer and form a spacer stack, the sidewalls being perpendicular to the main surface of the first semiconductor fin, wherein etching the first material does not etch the third spacer or the fourth spacer; forming a first gate electrode adjacent to the spacer stack; and forming a second gate electrode adjacent to the third spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure may be best understood through the following detailed description. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0008] Figure 1 A semiconductor substrate having a core region and an I / O region is shown in accordance with some embodiments.

[0009] Figures 2A-2D A cross-sectional view of a core region and an I / O region is shown in accordance with some embodiments.

[0010] Figures 3A-3D The formation of a spacer according to some embodiments is shown.

[0011] Figures 4A-4D The formation of an interlayer dielectric according to some embodiments is shown.

[0012] Figures 5A-5D Patterning of spacers according to some embodiments is shown.

[0013] Figures 6A-6D Dielectric removal is shown in accordance with some embodiments.

[0014] Figures 7A-7D The formation of a gate stack according to some embodiments is shown.

[0015] Figures 8A-8B The formation of four spacers is shown in accordance with some embodiments.

[0016] Figures 9A-9B A first patterning of four spacers is shown in accordance with some embodiments.

[0017] Figures 10A-10B A second patterning of four spacers is shown in accordance with some embodiments.

[0018] Figures 11A-11B A third patterning of four spacers is shown for forming a spacer pile in accordance with some embodiments.

[0019] Figures 12A-12B Patterning of a single spacer is shown in accordance with some embodiments.

[0020] Figures 13A-13B Patterning of two spacers is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted and formed, and may also include an embodiment in which additional features may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another (or multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0023] Embodiments will now be described with respect to specific structures, such as FinFET devices of 16 nanometer and higher technology generations. However, embodiments are not so limited and may be used in a variety of applications beyond those specifically discussed below.

[0024] Reference now Figure 1, showing a substrate 101 including a core region 103 and an I / O region 105 (for clarity, the substrate 101 is shown in FIG. Figure 1 1 , but is generally continuous as a semiconductor wafer. Within the core region 103, the device may be connected to a first voltage source (e.g., a first high voltage) and a first ground (e.g., a first low voltage source), and may include logic devices, memory devices, combinations of these devices, etc. for performing the desired functions of the semiconductor device 100. Within the I / O region 105, the device may be connected to a second voltage source (e.g., a second high voltage) different from the first voltage source (e.g., a higher voltage source) and a second ground (e.g., a second low voltage source) that is the same as or different from the first ground, and may include devices for sending signals to and receiving signals from the semiconductor device 100. However, any suitable region and any suitable functionality may be utilized.

[0025] The substrate 101 may be a silicon substrate, but other substrates such as semiconductor on insulator (SOI), strained SOI, and silicon germanium on insulator may be used. The substrate 101 may be a p-type semiconductor, but in other embodiments, the substrate 101 may be an n-type semiconductor.

[0026] In other embodiments, substrate 101 may be selected as a material that will particularly improve the performance (e.g., improve carrier mobility) of a device formed from substrate 101. For example, in some embodiments, the material of substrate 101 may be selected as an epitaxially grown semiconductor material layer, such as epitaxially grown silicon germanium, which helps improve some measures of performance of devices formed from epitaxially grown silicon germanium. However, while the use of these materials can improve some performance characteristics of the device, the use of these same materials may affect other performance characteristics of the device.

[0027] A plurality of first fin field effect transistors (FinFETs) 107 are formed in the core region 103. For the sake of clarity, Figure 1 Only one such device is shown in FIG. In a device formed in the core region 103, fewer fins may be implemented to form a corresponding transistor, and the spacing between adjacent gates (and therefore, the width of the intermediate source / drain regions) may be smaller than in other regions (eg, the I / O region 105).

[0028] A plurality of second FinFETs 108 are formed in the I / O region 105. For clarity, Figure 1Only one such device is shown in FIG. 1 . In a device formed in the I / O region 105, more fins may be implemented to form corresponding transistors, and the spacing between adjacent gates (and therefore, the width of the intermediate source / drain regions) may be greater than in other regions (e.g., the core region 103). The structures in the I / O region 105 may be formed simultaneously with the corresponding structures in the core region 103.

[0029] In the final formation of the first isolation region 111, a portion of the substrate 101 may be formed as an initial step. A masking layer ( Figure 1 The masking layer 101 is formed by a process (not shown separately) and a suitable etching process to remove portions of the substrate 101. For example, the masking layer can be a hard mask including silicon nitride formed by a process such as chemical vapor deposition (CVD), but other materials (e.g., oxides, oxynitrides, silicon carbide, combinations of these materials, etc.) and other processes (e.g., plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or even silicon oxide followed by nitridation) can also be used. Once the masking layer is formed, the masking layer can be patterned by a suitable photolithography process to expose those portions of the substrate 101 that will be removed.

[0030] However, as will be appreciated by those skilled in the art, the above-described processes and materials for forming the masking layer are not the only methods that may be used to protect portions of the substrate 101 while exposing other portions of the substrate 101. Any suitable process (e.g., a patterned and developed photoresist) may be used to expose the portion of the substrate 101 to be removed. All such methods are fully intended to be included within the scope of the present embodiment.

[0031] Once the masking layer has been formed and patterned, portions of substrate 101 may be removed. Exposed substrate 101 may be removed by a suitable process such as reactive ion etching (RIE) to remove portions of substrate 101, but any suitable process may be used. In an embodiment, portions of substrate 101 may be removed from the surface of substrate 101 to less than about A first depth of, for example, about

[0032] However, as will be appreciated by those skilled in the art, the above process is only one possible process and is not meant to be the only embodiment. Instead, any suitable process that can remove portions of substrate 101 and any suitable process including any number of masking and removal steps can be used.

[0033] In addition, the masking and etching process additionally forms fins 113 from those portions of the substrate 101 that remain unremoved. For convenience, the fins 113 are shown in the figure as being separated from the substrate 101, but a separate physical indication may or may not exist. As described below, these fins 113 can be used to form the channel region of a multi-gate FinFET transistor. Although Figure 1 Only two fins 113 formed from the substrate 101 are shown, but any number of fins 113 may be used.

[0034] The fins 113 may be formed so that they have a width of about 5 nm to about 80 nm (e.g., about 30 nm) at the surface of the substrate 101. In addition, the fins 113 may be patterned by any suitable method. For example, one or more photolithography processes (including double patterning or multi-patterning processes) may be used to pattern the fins 113. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing patterns to be created with, for example, smaller pitches than would otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 113.

[0035] Once the fins 113 have been formed, a dielectric material may be deposited and may be recessed to form the first isolation region 111. The dielectric material may be an oxide material, a high density plasma (HDP) oxide, etc. After optional cleaning and lining steps, the dielectric material may be formed using a chemical vapor deposition (CVD) method (e.g., a HARP process), a high density plasma CVD method, or other suitable formation methods known in the art.

[0036] The deposition process may fill or overfill the area around the fin 113, and the excess material may then be removed from the fin 113 by a suitable process such as chemical mechanical polishing (CMP), etching, combinations of these, etc. In an embodiment, the removal process also removes any dielectric material located above the fin 113, such that removing the dielectric material will expose the surface of the fin 113 for further processing steps.

[0037] Once planarized, the dielectric material may then be recessed from the surface of the fin 113. The recessing may be performed to expose at least a portion of the sidewalls of the fin 113 adjacent to the top surface of the fin 113. The dielectric material may be recessed using a wet etch by immersing the top surface of the fin 113 in an etchant such as HF, although other etchants (e.g., HF) may be used. 2) and other methods (e.g., reactive ion etching, using 3 / NF 3 The dielectric material may be recessed to a depth of about 100 mm from the surface of the fin 113. to approximately The distance between Additionally, the recessing may also remove any remaining dielectric material located above the fins 113 to ensure that the fins 113 are exposed for further processing.

[0038] However, as one of ordinary skill in the art will appreciate, the above steps may be only a portion of the overall process flow for filling and recessing the dielectric material. For example, a lining step, a cleaning step, an annealing step, a gap filling step, a combination of these steps, etc. may also be utilized. All possible processing steps are fully intended to be included within the scope of the present embodiment.

[0039] After forming the first isolation region 111, a dummy gate dielectric 115 and a dummy gate electrode 117 may be formed over each fin 113, the dummy gate electrode 117 being located over the dummy gate dielectric 115. In an embodiment, the dummy gate dielectric 115 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other method known in the art and used to form a gate dielectric. Depending on the technique of gate dielectric formation, the thickness of the dummy gate dielectric 115 on the top of the fin 113 may be different from the thickness of the gate dielectric on the sidewalls of the fin 113.

[0040] The dummy gate dielectric 115 may include a material such as silicon dioxide or silicon oxynitride having a thickness ranging from about 3 angstroms to about 100 angstroms (e.g., about 10 angstroms). The dummy gate dielectric 115 may be formed of a high dielectric constant (high-k) material (e.g., a relative dielectric constant greater than about 5), such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxynitride (HfON) or zirconium oxide (ZrO 2 ) or a combination thereof, wherein the equivalent oxide thickness is about 0.5 angstroms to about 100 angstroms, such as about 10 angstroms or less. In addition, any combination of silicon dioxide, silicon oxynitride and / or high-k materials may also be used for the dummy gate dielectric 115.

[0041] The dummy gate electrode 117 may include a conductive or non-conductive material and may be selected from the group consisting of polysilicon, but any suitable material or combination of materials may be used. The dummy gate electrode 117 may be deposited by chemical vapor deposition (CVD), sputtering deposition, or other techniques known in the art and used to deposit conductive materials. The thickness of the dummy gate electrode 117 may be about 1000 Å. To date The top surface of the dummy gate electrode 117 may have a non-flat top surface and may be flattened before patterning or gate etching of the dummy gate electrode 117. At this time, ions may or may not be introduced into the dummy gate electrode 117. For example, ions may be introduced by ion implantation technology.

[0042] Once formed, the dummy gate electrode 117 may be patterned. The patterned dummy gate electrode 117 defines a plurality of channel regions on each side of the fin 113 beneath the dummy gate dielectric 115. The patterned dummy gate electrode 117 may be formed by depositing and patterning a gate mask 119 on the dummy gate electrode 117 using, for example, deposition and photolithography techniques known in the art. The gate mask 119 may include commonly used masking and sacrificial materials such as, but not limited to, silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, and may be deposited to about 1000 Å. To date The dummy gate electrode 117 may be etched using a dry etching process to form a patterned dummy gate electrode 117 .

[0043] Figures 2A-2D Shown along Figure 1 Various cross-sectional views of the cutting lines shown. For example, Figure 2A A cross-sectional view along line AA of a first FinFET 107 along a fin 113 in the core region 103 is shown (eg, a “fin cut” view), while Figure 2B A cross-sectional view along line BB of the first FET 107 along a cut adjacent to the fin 113 is shown (eg, a “non-fin cut” view). Similarly, Figure 2C A cross-sectional view of a second FinFET 108 located within the I / O region 105 along line CC (eg, a “fin cut” view) is shown. Figure 2D A cross-sectional view along line DD (eg, a "non-fin cut" view) of a second FinFET 108 located within the I / O region 105 along a cut adjacent to the fin 113 is shown. In these figures, the substrate 101 has been removed for clarity.

[0044] In addition, if Figures 2A-2DIt can be seen that the width of the dummy gate electrode 117 may be different in the device formed in the core region 103 and the device formed in the I / O region 105. For example, in the core region 103, the first width W1 of the dummy gate electrode 117 may be about To date Between, for example In the I / O region 105, the second width W2 of the dummy gate electrode 117 may be approximately To date Between, for example However, any suitable width may be used.

[0045] Figures 3A-3D Shows that along with Figures 2A-2D A cross-sectional view similar to the cut line is shown, and additionally shows a first spacer 301 and a second spacer 303 formed adjacent to the dummy gate electrode 117 in the core region 103 and the I / O region 105. In an embodiment, the material of the first spacer 301 may include a silicon-based material, such as SiN, SiON, SiOCN, SiC, SiOC, SiO 2 , SiC, etc., or in other embodiments, may include metal-based materials such as SiGeO, SiAsO, GeO x , AsO x 、SiP、SiPO、SiTiO、TiO x , CuO x 、CoO x etc., and can be formed into approximately Appointment In an embodiment, the first spacer 301 may be formed by initially using a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, a treatment such as oxidation, a combination of these processes, etc. However, any suitable material, thickness, and formation method may be used.

[0046] The second spacer 303 may be formed above the first spacer 301 and may be used to provide a different material having different etching characteristics than the first spacer 301. Thus, in an embodiment where the first spacer 301 is SiN, the material of the second spacer 303 may be SiOCN, but in other embodiments, the second spacer 303 may be a silicon-based material, such as SiN, SiON, SiC, SiOC, SiO 2, SiC, etc., or in other embodiments, may include metal-based materials such as SiGeO, SiAsO, GeOx, AsOx, SiP, SiPO, SiTiO, TiOx, CuOx, CoOx, etc. In an embodiment, the second spacer 303 may be formed using a deposition process (e.g., physical vapor deposition, chemical vapor deposition, atomic layer deposition, a combination of these, etc.) and has a thickness of about 1000 nm. To date However, any suitable material, thickness, and formation method may be used.

[0047] Figures 3A-3D It is further shown that once the material of the first spacer 301 and the second spacer 303 has been blanket deposited, the material of the first spacer 301 and the second spacer 303 can be patterned to form the first spacer 301 and the second spacer 303. In an embodiment, the material of the first spacer 301 and the second spacer 303 is patterned using one or more anisotropic etching processes (e.g., reactive ion etching) to remove the first spacer 301 and the second spacer 303 from the horizontal surface of the structure. However, any suitable patterning process may be used.

[0048] In addition, although Figures 3A-3D Only the first spacer 301 and the second spacer 303 are shown in the figure, but the embodiment is not limited to the presence of only two spacers. Instead, any suitable number of spacers can be formed adjacent to the dummy gate electrode 117. For example, the number of separate spacers having different materials can be between three spacers and ten spacers.

[0049] In an embodiment, a patterning process of one or more anisotropic etching processes for removing the first spacer 301 and the second spacer 303 from the horizontal surface of the structure may also be used to recess the portion of the first isolation region 111 exposed by the patterning process. Therefore, the first isolation region 111 not covered by the patterned dummy gate electrode 117 and the patterned first spacer 301 and the patterned second spacer 303 may be recessed to a level lower than the portion of the first isolation region 111 covered, thereby forming a crown or fin shape within the first isolation region 111. However, in other embodiments, the first isolation region 111 is not recessed, and any suitable patterning of the first isolation region 111 is fully intended to be included within the scope of the embodiments.

[0050] Figures 3A-3DAlso shown is the removal of the fin 113 from those areas not protected by the patterned dummy gate electrode 117, the first spacer 301, and the second spacer 303, and the regrowth of the source / drain regions 305. The fin 113 may be removed from those areas not protected by the patterned dummy gate electrode 117, the first spacer 301, and the second spacer 303 by reactive ion etching (RIE) using the patterned dummy gate electrode 117, the first spacer 301, and the second spacer 303 as a hard mask, or by any other suitable removal process. Removal may continue until the fin 113 is coplanar with the surface of the first isolation region 111 (as shown) or below the surface.

[0051] In some embodiments, the removal of material from the fins 113 will be non-uniform between the core region 103 and the I / O region 105. For example, the removal of material from the fins 113 within the I / O region 105 may occur at an increased rate relative to the removal of material from the fins 113 in the core region 103. As a result, the openings formed by the removal will extend deeper in the I / O region 105 than in the core region 103. However, in other embodiments, the openings may extend to similar depths.

[0052] Once these portions of the fins 113 are removed, the source / drain regions 305 may be regrown in contact with each fin 113. In an embodiment, the source / drain regions 305 may be regrown, and in some embodiments, the source / drain regions 305 may be regrown to form a stressor that transfers stress to the channel region of the fin 113 located below the patterned dummy gate electrode 117. In embodiments where the fins 113 include silicon and the FinFET is a p-type device, the source / drain regions 305 may be regrown with a material (e.g., silicon) or other material (e.g., silicon germanium) having a different lattice constant than the channel region by a selective epitaxial growth process. The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, etc., and may last from about 5 minutes to about 120 minutes, for example, about 30 minutes.

[0053] In an embodiment, the source / drain regions 305 may be formed to have approximately To date The thickness between and above the first isolation region 111 is about To date Between (e.g. about ). In the present embodiment, the source / drain region 305 may be formed to have a height between about 5 nm and about 250 nm, for example, about 100 nm, higher than the upper surface of the first isolation region 111. In addition, due to uneven etching, the height of the source / drain region 305 in the I / O region 105 may be greater than the height of the source / drain region 305 in the core region 103. For example, the height of the source / drain region 305 in the I / O region 105 may be about 100 nm. To date Between, for example The height of the source / drain region 305 in the core region 103 may be approximately To date Between, for example

[0054] However, although specific sizes and shapes are described herein, these sizes and shapes are intended to be illustrative and are not intended to be limiting. On the contrary, any suitable size and shape of the source / drain region 305 can be utilized, and in the manufacturing process, the size and shape may be affected by many parameters. For example, the size and shape of the source / drain region 305 may be affected by the following parameters: the size and spacing of the gate stack (e.g., different gate stacks between the core region 103 and the I / O region 105 will result in different widths of their respective source / drain regions 305), the type of etching used to make room for the source / drain region 305, the parameters used during the epitaxial growth of the source / drain region 305, etc. All of these parameter differences and their corresponding effects on the size and shape of the source / drain region 305 are fully intended to be included within the scope of the embodiment.

[0055] Once the source / drain region 305 is formed, dopants can be injected into the source / drain region 305 by injecting appropriate dopants to supplement the dopants in the fin 113. For example, p-type dopants (e.g., boron, gallium, indium, etc.) can be injected to form a PMOS device. Alternatively, n-type dopants (e.g., phosphorus, arsenic, antimony, etc.) can be injected to form an NMOS device. These dopants can be injected using the patterned dummy gate electrode 117, the first spacer 301, and the second spacer 303 as masks. It should be noted that a person of ordinary skill in the art will recognize that many other processes, steps, etc. can be used to inject dopants. For example, a person of ordinary skill in the art will recognize that various combinations of spacers and liners can be used to perform multiple implants to form source / drain regions with specific shapes or characteristics suitable for specific purposes. Any of these processes can be used to inject dopants, and the above description is not meant to limit the present embodiment to the above steps.

[0056] Figures 4A-4D shows along with Figures 2A-2D A cross-sectional view similar to the cut line is shown, and additionally shows the deposition of a contact etch stop layer 401 and an interlayer dielectric (ILD) layer 403 over the source / drain regions 305. The contact etch stop layer 401 is used to protect the underlying structure from damage caused by further processing and to provide a control point for further etching processing. In one embodiment, the contact etch stop layer 401 can be formed from silicon nitride using plasma enhanced chemical vapor deposition (PECVD), but other materials (e.g., nitrides, oxynitrides, carbides, borides, combinations thereof, etc.) and alternative techniques for forming the contact etch stop layer 401 (e.g., low pressure CVD (LPCVD), PVD, etc.) can be used instead. The thickness of the contact etch stop layer 401 can be about 1000 Å. to approximately between, for example approximately

[0057] The ILD layer 403 may include a material such as borophosphosilicate glass (BPSG), but any suitable dielectric may be used. The ILD layer 403 may be formed using a process such as PECVD, but other processes such as LPCVD may be used instead. The ILD layer 403 may be formed to a thickness of about to approximately between.

[0058] Figures 4A-4D It is further shown that once the ILD layer 403 has been formed, the ILD layer 403 and the contact etch stop layer 401 can be planarized with the first spacer 301, the second spacer 303, and the dummy gate electrode 117. In an embodiment, the ILD layer 403, the contact etch stop layer 401, the first spacer 301, and the second spacer 303 can be planarized using, for example, a planarization process (e.g., a chemical mechanical polishing process), but any suitable process can be used. The planarization process is also used to remove the gate mask 119.

[0059] Figures 5A-5D shows along with Figures 2A-2D 1 and 10. A cross-sectional view of a similar cut line is shown and additionally illustrates the removal of the dummy gate electrode 117 in both the core region 103 and the I / O region 105. In an embodiment, the dummy gate electrode 117 may be removed using, for example, one or more wet or dry etching processes that utilize an etchant that is selective to the material of the dummy gate electrode 117. However, any suitable removal process or processes may be used.

[0060] Figures 5A-5DIt is further shown that once the dummy gate electrode 117 has been removed from both the core region 103 and the I / O region 105, a mask 501 may be disposed over the structures within the I / O region 105 to protect the structures within the I / O region 105. In an embodiment, the mask 501 may be a photosensitive material, such as a polymer-based photoresist, which is dispensed and then patterned using, for example, an exposure and development process to protect the I / O region 105 while exposing the core region 103. However, the mask 501 may be formed using any suitable material (e.g., a hard mask material) and any suitable process (e.g., a deposition and patterning process).

[0061] Once mask 501 is formed and the structures within I / O region 105 are protected, Figure 5A-5B It is shown that in the core region 103, the first spacer 301 is patterned to remove those portions of the first spacer 301 aligned along the sidewalls of the second spacer 303 without removing those portions of the first spacer 301 covered by the second spacer 303, and to form a first spacer remainder 503. In an embodiment, the patterning of the first spacer 301 can be performed using, for example, one or more etching processes (e.g., chemical etching, plasma etching, wet cleaning, combinations of these, etc.) using an etchant that is selective to the material of the first spacer 301 without significantly etching the material of the second spacer 303.

[0062] In an embodiment, the removal process for forming the first spacer remainder 503 completely removes the first spacer 301 from the adjacent sidewalls of the second spacer 303, so that the first spacer remainder 503 is connected and aligned with the sidewalls of the second spacer 303. Therefore, the width of the first spacer remainder 503 can be equal to the deposition thickness of the second spacer 303 (e.g., arrive However, in other embodiments, the first spacer 301 may remain adjacent to the sidewalls of the second spacer 303 (but with a reduced thickness), or may be etched such that the first spacer remainder 503 is recessed in a direction parallel to the top surface of the fin 113.

[0063] By removing a portion of the first spacer 301 and forming the first spacer remainder 503, the number of spacers ("a") located in the core region 103 can be reduced to be lower than the number of spacers ("b") located in the I / O region 105, such that ba ≥ 1. In addition, for those structures in the core region 103, the thickness of the combination of spacers (e.g., the second spacer 303 and the first spacer 301) can be reduced (e.g., ) without reducing the thickness of the combination of spacers within the I / O region 105 (e.g., ). Therefore, the capacitance and leakage risk in the I / O region 105 operating at a relatively high voltage can be reduced without reducing the performance of the devices located in the core region 103.

[0064] Additionally, in some embodiments, the patterning of the first spacer 301 and the formation of the first spacer remainder 503 may also remove a portion of the first isolation region 111 within the core region 103 below the dummy gate electrode 117. In an embodiment, the first isolation region 111 may be removed such that the recess 505 is formed with a curved concave surface of the first isolation region 111 without forming a corresponding recess in the I / O region 105 (because the I / O region 105 is still protected by the presence of the mask 501). In an embodiment, the first depth D formed by the recess 505 is 1 Can be in about To date Between, for example and may have a first width W 1 However, any suitable dimensions may be used.

[0065] Figures 6A-6D shows along with Figures 2A-2D A cross-sectional view similar to the cut line is shown, and additionally shows the removal of a portion of the dummy gate dielectric 115 in the core region 103. Such removal forms a dummy gate dielectric remainder 601 within the core region 103, which is removed by the presence of the mask 501 (see Figure 5C-5D ), the dummy gate dielectric 115 is not contacted by the process and remains intact within the I / O region 105. In an embodiment, the dummy gate dielectric 115 can be patterned using, for example, one or more etching processes (e.g., chemical etching, plasma etching, wet cleaning, combinations of these, etc.) using an etchant that is selective to the material of the dummy gate dielectric 115 without significantly etching the material of the second spacer 303 or the first spacer remainder 503.

[0066] In one embodiment, the removal process used to form the dummy gate dielectric remainder 601 removes material of the dummy gate dielectric 115 such that the dummy gate dielectric remainder 601 is connected to and aligned with the sidewalls of the second spacer 303 and / or the first spacer remainder 503. Therefore, the width of the dummy gate dielectric remainder 601 can be equal to the deposited thickness of the second spacer 303 (e.g., at arrive However, in other embodiments, the dummy gate dielectric remainder 601 may be etched such that the dummy gate dielectric remainder 601 is recessed in a direction parallel to the top surface of the fin 113 .

[0067] Figure 6C-6D It is also shown that once the dummy gate dielectric remainder 601 is formed, the mask 501 can be removed to expose the I / O region 105 for further processing. In an embodiment where the mask 501 is a photoresist, an ashing process can be used to remove the mask 501, thereby increasing the temperature of the mask 501 to cause thermal decomposition of the photoresist, after which the decomposed material can be easily removed. However, in other embodiments, an etching process can be used to remove the mask 501, and any suitable removal process can be used.

[0068] Figures 7A-7D shows along with Figures 2A-2D 1 and 1 , and additionally illustrate the formation of a first gate stack 701 in the area left by removing the dummy gate electrode 117. In an embodiment, the process of forming the first gate stack 701 may begin by depositing a series of layers. In an embodiment, the series of layers may include an interface layer, a first dielectric material, a first metal material, and a first p-metal work function layer (for clarity, Figures 7A-7D Each layer is not shown separately).

[0069] Optionally, the interfacial layer may be formed before forming the first dielectric material. In an embodiment, the interfacial layer may be a material such as silicon dioxide formed by a process such as in-situ steam generation (ISSG), or a deposition process such as chemical vapor deposition or atomic layer deposition. In another embodiment, the interfacial layer may be a material such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta 2 O 5 , combinations of these materials, etc., wherein the first thickness of the high-k material is about To date Between, for example In embodiments utilizing a deposition process, the interface layer may be conformally formed, whereas in embodiments utilizing ISSG, the interface layer may be formed along the bottom of the opening without extending along the sidewalls.

[0070] Once the interface layer is formed, a first dielectric material may be formed as a capping layer over the interface layer. In an embodiment, the first dielectric material is a dielectric such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta 2 O 5 , combinations of these materials, etc., the first dielectric material is deposited by a process such as atomic layer deposition, chemical vapor deposition, etc. The first dielectric material may be deposited to about To date A second thickness between, but any suitable material and thickness may be used.

[0071] Optionally, a first metal material or a metal gate cap layer may be formed adjacent to the first dielectric material as a barrier layer, and may be formed of a metal material such as TaN, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these materials, etc. The first metal material may be deposited to about 1000 Å using a deposition process (e.g., atomic layer deposition, chemical vapor deposition, sputtering, etc.). To date A third thickness between , but any suitable deposition process or thickness may be used.

[0072] The first p-metal work function layer can be formed adjacent to the first metal material, and in certain embodiments, can be similar to the first metal material. For example, the first p-metal work function layer can be formed of materials such as W, Al, Cu, TiN, Ti, TiAlN, Ta, TaN, Co, Ni, TaC, TaCN, TaSiN, TaSi 2 、NiSi 2 、Mn、Zr、ZrSi 2 , TaN, Ru, AlCu, Mo, MoSi 2 , metal materials such as WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these materials, etc. In addition, a deposition process (such as atomic layer deposition, chemical vapor deposition, sputtering, etc.) can be used to deposit the first p-metal work function layer to about To date A fourth thickness between , but any suitable deposition process or thickness may be used.

[0073] Once the first p-metal work function layer is formed, a first n-metal work function layer may be deposited. In an embodiment, the first n-metal work function layer may be a material such as W, Cu, AlCu, TiAlC, TiAlN, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. For example, the first n-metal work function layer may be deposited to about 1000 Å using an atomic layer deposition (ALD) process, a CVD process, or the like. to about Between (e.g. about However, any suitable material and process may be used to form the first n-metal work function layer.

[0074] An adhesion layer and a fill material are also deposited within the first gate stack 701. Once the first n-metal work function layer is formed, an adhesion layer may be formed to help bond the upper fill material to the lower first n-metal work function layer and provide a nucleation layer for the formation of the fill material. In an embodiment, the adhesion layer may be a material such as titanium nitride, or may be a material similar to the first n-metal work function layer, and may be formed to about 1000 W using a similar process (e.g., ALD). to approximately The seventh thickness is between, for example, about However, any suitable materials and processes may be used.

[0075] Once the adhesion layer is formed, a fill material is deposited to fill the remainder of the opening with the adhesion layer. In an embodiment, the fill material may be a material such as tungsten, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these materials, and the like, and may be formed using a deposition process such as electroplating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations of these processes, and the like. Additionally, the fill material may be deposited to about To date Between (e.g. about ) in thickness. However, any suitable material may be used.

[0076] Figures 7A-7DIt is further shown that after the fill material has been deposited to fill and overfill the openings, the material can be planarized to form the first gate stack 701. In an embodiment, the material can be planarized using, for example, a chemical mechanical polishing process, but any suitable process, such as grinding or etching, can be used. Although not explicitly shown for clarity, the interface layer can be planar along the bottom surface of the first gate stack 701; the first dielectric material, the first metal material, the first p-metal work function layer, the first n-metal work function layer, and the adhesion layer can have a "U" shape; and the fill material can fill the remainder of the space of the first gate stack 701. However, any suitable shape or combination of shapes can be used for the various layers of the first gate stack 701.

[0077] By forming the first gate stack 701, the first gate stack 701 in the core region 103 is in contact with each spacer (e.g., the second spacer 303 and the first spacer remaining portion 503). However, in the I / O region 105, the first gate stack 701 is in physical contact with the first spacer 301, but the first spacer 301 separates the second spacer 303 from the first gate stack 701.

[0078] at last, Figures 7A-7D The formation of a first contact 703 to the source / drain region 305 is shown. In an embodiment, an opening is formed through the ILD layer 403 and the contact etch stop layer 401 to expose a portion of the source / drain region 305. Optionally, a silicide contact may be formed before forming the first contact 703. The silicide contact may include titanium, nickel, cobalt, or erbium to reduce the Schottky barrier height of the contact. However, other metals, such as platinum, palladium, etc., may also be used. Silicidation may be performed by blanket deposition of an appropriate metal layer, followed by an annealing step, which reacts the metal with the exposed silicon of the underlying layer. The unreacted metal is then removed, for example, using a selective etching process. The thickness of the silicide contact may be between about 5nm and about 50nm.

[0079] By patterning the spacers in the core region 103 without patterning the spacers in the I / O region 105, the capacitance between the first gate stack 701 and its corresponding contact can be adjusted for each device. Therefore, the capacitance issues associated with the larger voltages applied to the devices in the I / O region 105 can be handled without the need to make similar changes to the devices in other regions such as the core region 103. Therefore, the reduction in electrical performance and yield due to leakage current of these devices can be reduced or eliminated. Similarly, the process window used between the first contact 703 and the first gate stack 701 can be increased.

[0080] In an embodiment, the first contact 703 can be a conductive material, such as Al, Cu, W, Co, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations of these materials, etc., but any suitable material can be deposited into the opening using a deposition process such as sputtering, chemical vapor deposition, electroplating, chemical plating, etc. to fill and / or overfill the opening. Once filled or overfilled, a planarization process such as chemical mechanical polishing (CMP) can be used to remove any deposited material outside the opening. However, any suitable material and formation process can be used. In addition, the thickness of the first contact 703 can be about 1000 nm. To date between.

[0081] Figures 8A-8B Another embodiment using more than two spacers (eg, more than a first spacer 301 and a second spacer 303) is shown, wherein Fig. 8A Shows Figure 3A A close-up view of the box marked 800 in FIG. Figure 8B Shows Figure 3C A close-up view of the frame marked as 800 in FIG. In this embodiment, the first spacer 301 and the second spacer 303 are as described above with respect to Figures 3A-3D However, in addition to the first spacer 301 and the second spacer 303, a third spacer 801 and a fourth spacer 803 are formed.

[0082] In an embodiment, the third spacer 801 may include a silicon-based material, such as SiN, SiON, SiOCN, SiC, SiOC, SiO2, SiC, etc., or in other embodiments, may include a metal-based material, such as SiGeO, SiAsO, GeO x , AsO x 、SiP、SiPO、SiTiO、TiO x , CuO x 、CoO x etc., and can be formed at about To date In an embodiment, the third spacer 801 may be formed by initially using a deposition process such as physical vapor deposition, chemical vapor deposition, a treatment such as oxidation, a combination of these, etc. However, any suitable material, thickness, and formation method may be used.

[0083] Once the third spacer 801 is formed, a fourth spacer 803 may be formed over the third spacer 801. The fourth spacer 803 may be formed over the third spacer 801 and may be used to provide a different material with different etching characteristics than the third spacer 801. Thus, the fourth spacer 803 may be a silicon-based material, such as SiN, SiON, SiOCN, SiC, SiOC, SiO 2 , SiC, etc., or in other embodiments, may include metal-based materials such as SiGeO, SiAsO, GeO x , AsO x 、SiP、SiPO、SiTiO、TiO x , CuO x 、CoO x In an embodiment, the fourth spacer 803 may be formed using a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, a combination of these, etc., and has a thickness of about 1000 Å. To date However, any suitable material, thickness, and formation method may be used.

[0084] Figures 8A-8B It is further shown that once the materials of the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803 are blanket deposited, the materials of the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803 can be patterned to form the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803. In an embodiment, the materials of the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803 are patterned using one or more anisotropic etching processes (e.g., reactive ion etching) to remove the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803 from the horizontal surface of the structure. However, any suitable patterning process may be used.

[0085] As can be seen, after patterning the materials of the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803, each spacer (e.g., the first spacer 301, the second spacer 303, and the third spacer 801) except the last deposited spacer (e.g., the fourth spacer 803) has an "L" shape after the patterning process. In addition, the last deposited spacer (e.g., the fourth spacer 803) does not have an "L" shape, but has vertical sidewalls in this view.

[0086] Figures 9A-9BThe removal process of etching the first spacer 301 in the core region 103 and forming the first spacer remainder 503 without etching the first spacer 301 in the I / O region 105 is shown (so that the number of spacers on the device in the core region 103 is less than the number of spacers on the device in the I / O region 105). In an embodiment, the removal process may be as described above with respect to Figures 5A-5D The removal process is performed, for example, by protecting the I / O region 105 and using an anisotropic etching process to remove portions of the first spacer 301 while stopping the etching on the second spacer 303. However, any suitable process may be used.

[0087] If desired, once the first spacer remainder 503 is formed, the first gate stack 701 may be formed adjacent to the first spacer remainder 503 and the second spacer 303 (within the core region 103) and adjacent to the spacers (e.g., the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803) within the I / O region 105. In an embodiment, the first gate stack 701 may be formed as described with respect to Figures 7A-7D The first gate stack 701 is formed. However, any suitable materials and processes may be used.

[0088] If the first gate stack 701 is not formed at this time, Figures 10A-10B Another removal process is shown for etching the second spacer 303 and forming the second spacer remainder 1001. In an embodiment, the removal process for forming the first spacer remainder 503 completely removes the second spacer 303 from the adjacent sidewalls of the third spacer 801, while stopping on the third spacer 801, such that the second spacer remainder 1001 is connected to and aligned with the sidewalls of the third spacer 801. However, in other embodiments, the second spacer 303 may remain adjacent to the sidewalls of the third spacer 801 (but with a reduced thickness), or may be etched such that the second spacer remainder 1001 is recessed in a direction parallel to the top surface of the fin 113.

[0089] By forming the second spacer remaining portion 1001 in the core region 103, the width of the second spacer remaining portion 1001 may be equal to the width of the third spacer 801 (width 第二间隔体剩余部分 -width 第三间隔体 =0), and the width of the third spacer 801 may be greater than the width of the fourth spacer (width 第三间隔体 -width 第四间隔体 >0). However, in the I / O region, where there is no patterning of the spacers, the width of each spacer is greater than the width of the subsequently deposited upper spacer (width 下间隔体 -width 上间隔体 >0). However, any suitable width may be used.

[0090] Furthermore, if desired at this stage of manufacturing, once the second spacer remainder 1001 is formed, the first gate stack 701 may be formed adjacent to the first spacer remainder 503 and the second spacer remainder 1001 (within the core region 103) and adjacent to the spacers (e.g., the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803) within the I / O region 105. In an embodiment, the first gate stack 701 may be formed as described above with respect to Figures 7A-7D The first gate stack 701 is formed. However, any suitable materials and processes may be used.

[0091] If the first gate stack 701 is not formed at this time, Figures 11A-11B Another removal process is shown for etching the third spacer 801 and forming the third spacer remainder 1101. In an embodiment, the removal process for forming the third spacer remainder 1101 completely removes the third spacer 801 from the adjacent sidewalls of the fourth spacer 803, so that the third spacer remainder 1101 is connected to and aligned with the sidewalls of the fourth spacer 803. However, in other embodiments, the third spacer 801 can remain adjacent to the sidewalls of the fourth spacer 803 (but with a reduced thickness), or can be etched so that the third spacer remainder 1101 is recessed in a direction parallel to the top surface of the fin 113.

[0092] By forming a plurality of spacers (e.g., the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803), and then sequentially etching at least some of the spacers (e.g., the first spacer 301, the second spacer 303, and the third spacer 801), a spacer stack 1103 is formed by the remaining portions of the multilayer spacer after the spacer removal, wherein the spacer stack 1103 includes the fourth spacer 803, the third spacer remaining portion 1101, the second spacer remaining portion 1001, and the first spacer remaining portion 503. In the present embodiment, the remaining portions (e.g., the third spacer remaining portion 1101, the second spacer remaining portion 1001, and the first spacer remaining portion 503) at the bottom of the spacer stack 1103 may have the same thickness as the material as originally deposited, while the top of the spacer stack (e.g., the unetched fourth spacer 803) has a much greater thickness in the same direction, for example, having a thickness of about 1000Å to about 1000Å. To date The thickness between If the thickness or the thickness of the spacer stack 1103 is too thin, the operating voltage window cannot be enlarged, while if the thickness or the thickness of the spacer stack 1103 is too large, it will affect the transistor density, resulting in fewer transistors included in the same surface area.

[0093] Once the spacer stack 1103 is formed, the first gate stack 701 may be formed adjacent to the spacer stack 1103 (within the core region 103) and adjacent to the spacers (e.g., the first spacer 301, the second spacer 303, the third spacer 801, and the fourth spacer 803) within the I / O region 105. In an embodiment, the first gate stack 701 may be formed as described above with respect to Figures 7A-7D The first gate stack 701 is formed. However, any suitable materials and processes may be used.

[0094] In addition, although the first gate stack 701 is described as being formed only after the last deposited gate spacer is exposed (e.g., after the third spacer remainder 1101 is formed), this is intended to be illustrative and not intended to limit the embodiments. Instead, the first gate stack 701 can be formed at any point after the first spacer remainder 503 is formed, such as before the second spacer remainder 1001 is formed or before the third spacer remainder 1101 is formed. Any suitable combination of spacers and spacer remainders can be used to modify the capacitance between the first gate stack 701 and the first contact 703.

[0095] For example, Figures 12A-12B Additional examples of spacer combinations that may be used are shown, Fig. 12A The core area is shown in Fig. 7A In the embodiment at the position highlighted by the dashed box labeled 1200, Fig. 12B Shown in Figure 7C 1200 is highlighted by a dotted box. In the embodiment, the fourth spacer 803 is made of SiON x The third spacer 801 is formed by SiN x The second spacer 303 is formed of SiOCN, and the first spacer 301 is formed of SiO 2 Furthermore, in the core region 103 but not in the I / O region 105 , at least a portion of the first spacer 301 is removed, so that the first gate stack 701 is formed adjacent to the second spacer 303 .

[0096] Figures 13A-13B Shown with Figures 12A-12B A similar embodiment, wherein Fig.13A The core area is shown in Fig. 7A In the embodiment at the position highlighted by the dashed box labeled 1200, Fig. 13B Shown in Figure 7C In the embodiment at the position highlighted by the dotted box marked as 1200. In this embodiment, Figures 12A-12B Similar to the embodiment described above, the fourth spacer 803 is made of SiONx The third spacer 801 is formed by SiN x The second spacer 303 is formed of SiOCN, and the first spacer 301 is formed of SiO 2 However, in the present embodiment, not only the first spacer 301 is etched, but also the second spacer 303 is etched and patterned. Therefore, in the core region 103 but not in the I / O region 105, at least a portion of the first spacer 301 and the second spacer 303 is removed, so that the first gate stack 701 is formed adjacent to the third spacer 801.

[0097] In an embodiment, a semiconductor device includes: a substrate, the substrate including a first fin in a first region and a second fin in a second region; a first gate stack located above the first fin and a second gate stack located above the second fin; a first plurality of spacers adjacent to the first gate stack, the first plurality of spacers having a first width, wherein at least two spacers of the first plurality of spacers have sidewalls that physically contact the first gate stack; and a second plurality of spacers adjacent to the second gate stack, the second plurality of spacers having a second width greater than the first width, wherein a first spacer in the second plurality of spacers separates the second gate stack from each other spacer in the second plurality of spacers. In an embodiment, the first spacer in the second plurality of spacers has an "L"-shaped structure. In an embodiment, each spacer in the first plurality of spacers has the first width. In an embodiment, the first plurality of spacers includes at least three spacers, and wherein each spacer in the first plurality of spacers has a sidewall that physically contacts the first gate stack. In an embodiment, a second spacer in the second plurality of spacers has the first width. In an embodiment, the semiconductor device further comprises: a first gate dielectric, the first gate dielectric is located between the first plurality of spacers and the first fin, the first gate dielectric has the first width; and a second gate dielectric, the second gate dielectric is located between the second gate stack and the second fin. In an embodiment, the first region is a core region and the second region is an I / O region, wherein the first plurality of spacers has a different layer than the second plurality of spacers, and wherein the first gate stack is connected to a first voltage source and the second gate stack is connected to a second voltage source different from the first voltage source.

[0098] In another embodiment, a semiconductor device includes: a spacer stack adjacent to a first gate stack above a first semiconductor fin, wherein each spacer within the spacer stack has a width no greater than a top spacer within the spacer stack, the spacer stack having a first width and being located in a core region of a semiconductor substrate; and a first plurality of spacers adjacent to a second gate stack above a second semiconductor fin, at least one of the first plurality of spacers having an "L" shape, the first plurality of spacers having a second width greater than the first width. In an embodiment, each material within the first plurality of spacers is also within the spacer stack. In an embodiment, each spacer within the spacer stack has the first width. In an embodiment, at least one spacer within the spacer stack is recessed from an adjacent spacer within the spacer stack. In an embodiment, the width of the first gate stack is less than the width of the second gate stack. In an embodiment, the semiconductor device further includes a shallow trench isolation adjacent to the first semiconductor fin, the first gate stack extending into a recess of the shallow trench isolation. In an embodiment, the spacer stack includes at least four spacers.

[0099] In yet another embodiment, a method of manufacturing a semiconductor device includes: blanket depositing a first material over a first semiconductor fin adjacent to a first dummy gate electrode and over a second semiconductor fin adjacent to a second dummy gate electrode; blanket depositing a second material adjacent to the first material; patterning the first material and the second material to form a first spacer and a second spacer adjacent to the first dummy gate electrode and a third spacer and a fourth spacer adjacent to the second dummy gate electrode, wherein the patterning is performed at least in part using one or more anisotropic etching processes; removing the first dummy gate electrode and the second dummy gate electrode; etching the first material of the first spacer to expose sidewalls of the second material of the second spacer and forming a spacer stack, the sidewalls being perpendicular to a major surface of the first semiconductor fin, wherein etching the first material does not etch the third spacer or the fourth spacer; forming a first gate electrode adjacent to the spacer stack; and forming a second gate electrode adjacent to the third spacer. In an embodiment, the method further includes: depositing a third material adjacent to the second material; and etching the second material to expose sidewalls of the third material and forming the spacer stack. In an embodiment, the method further comprises: depositing a fourth material adjacent to the third material; and etching the third material to expose the sidewalls of the fourth material and form the spacer stack. In an embodiment, the method further comprises: after etching the first material, etching a first gate dielectric over the first semiconductor fin without etching a second gate dielectric over the second semiconductor fin. In an embodiment, the first semiconductor fin is located in a core region of a semiconductor substrate and the second semiconductor fin is located in an I / O region of the semiconductor substrate. In an embodiment, the method further comprises recessing a shallow trench isolation region after etching the first material.

[0100] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can be variously changed, replaced and transformed herein without departing from the spirit and scope of the present invention.

[0101] Example 1. A semiconductor device, comprising: a substrate, the substrate comprising a first fin in a first region and a second fin in a second region; a first gate stack located above the first fin and a second gate stack located above the second fin; a first plurality of spacers adjacent to the first gate stack, the first plurality of spacers having a first width, wherein at least two spacers of the first plurality of spacers have sidewalls that are in physical contact with the first gate stack; and a second plurality of spacers adjacent to the second gate stack, the second plurality of spacers having a second width greater than the first width, wherein a first spacer of the second plurality of spacers separates the second gate stack from each other spacer within the second plurality of spacers.

[0102] Example 2. The semiconductor device of Example 1, wherein the first spacer of the second plurality of spacers has an “L” shaped structure.

[0103] Example 3. The semiconductor device of Example 1, wherein each spacer of the first plurality of spacers has the first width.

[0104] Example 4. The semiconductor device of Example 1, wherein the first plurality of spacers includes at least three spacers, and wherein each spacer within the first plurality of spacers has a sidewall in physical contact with the first gate stack.

[0105] Example 5. The semiconductor device of Example 1, wherein a second spacer of the second plurality of spacers has the first width.

[0106] Example 6. The semiconductor device according to Example 1 further includes: a first gate dielectric, the first gate dielectric is located between the first plurality of spacers and the first fin, the first gate dielectric has the first width; and a second gate dielectric, the second gate dielectric is located between the second gate stack and the second fin.

[0107] Example 7. A semiconductor device according to Example 1, wherein the first region is a core region and the second region is an I / O region, wherein the first plurality of spacers has a different layer from the second plurality of spacers, and wherein the first gate stack is connected to a first voltage source and the second gate stack is connected to a second voltage source different from the first voltage source.

[0108] Example 8. A semiconductor device, comprising: a spacer stack adjacent to a first gate stack above a first semiconductor fin, wherein the width of each spacer in the spacer stack is no greater than that of a top spacer in the spacer stack, the spacer stack having a first width and being located in a core region of a semiconductor substrate; and a first plurality of spacers adjacent to a second gate stack above a second semiconductor fin, at least one spacer of the first plurality of spacers having an "L" shape, the first plurality of spacers having a second width greater than the first width.

[0109] Example 9. The semiconductor device of Example 8, wherein each material within the first plurality of spacers is also within the spacer stack.

[0110] Example 10. The semiconductor device of Example 8, wherein each spacer within the spacer stack has the first width.

[0111] Example 11. The semiconductor device of Example 8, wherein at least one spacer within the spacer stack is recessed from an adjacent spacer within the spacer stack.

[0112] Example 12. The semiconductor device of Example 8, wherein a width of the first gate stack is smaller than a width of the second gate stack.

[0113] Example 13. The semiconductor device of Example 8 further includes a shallow trench isolation adjacent to the first semiconductor fin, the first gate stack extending into a recess of the shallow trench isolation.

[0114] Example 14. The semiconductor device of Example 8, wherein the spacer stack includes at least four spacers.

[0115] Example 15. A method for manufacturing a semiconductor device, the method comprising: blanket depositing a first material adjacent to a first dummy gate electrode over a first semiconductor fin and adjacent to a second dummy gate electrode over a second semiconductor fin; blanket depositing a second material adjacent to the first material; patterning the first material and the second material to form a first spacer and a second spacer adjacent to the first dummy gate electrode and a third spacer and a fourth spacer adjacent to the second dummy gate electrode, wherein the patterning is performed at least in part using one or more anisotropic etching processes; removing the first dummy gate electrode and the second dummy gate electrode; etching the first material of the first spacer to expose sidewalls of the second material of the second spacer and form a spacer stack, the sidewalls being perpendicular to the main surface of the first semiconductor fin, wherein etching the first material does not etch the third spacer or the fourth spacer; forming a first gate electrode adjacent to the spacer stack; and forming a second gate electrode adjacent to the third spacer.

[0116] Example 16. The method of Example 15, further comprising: depositing a third material adjacent to the second material; and etching the second material to expose sidewalls of the third material and form the spacer stack.

[0117] Example 17. The method of Example 16, further comprising: depositing a fourth material adjacent to the third material; and etching the third material to expose sidewalls of the fourth material and form the spacer stack.

[0118] Example 18. The method of Example 15, further comprising: after etching the first material, etching a first gate dielectric over the first semiconductor fin without etching a second gate dielectric over the second semiconductor fin.

[0119] Example 19. The method of Example 15, wherein the first semiconductor fin is located in a core region of a semiconductor substrate, and the second semiconductor fin is located in an I / O region of the semiconductor substrate.

[0120] Example 20. The method of Example 15, further comprising recessing a shallow trench isolation region after etching the first material.

Claims

1. A semiconductor device, comprising: a substrate including a first fin in a first region and a second fin in a second region; a first gate stack located above the first fin and a second gate stack located above the second fin; a first plurality of spacers adjacent to the first gate stack, the first plurality of spacers having a first width, wherein at least two spacers of the first plurality of spacers have sidewalls in physical contact with the first gate stack; and a second plurality of spacers adjacent to the second gate stack, the second plurality of spacers having a second width greater than the first width, wherein a first spacer in the second plurality of spacers spaces the second gate stack apart from every other spacer in the second plurality of spacers; The first plurality of spacers includes at least four spacers, and each spacer in the first plurality of spacers has a sidewall physically contacting the first gate stack.

2. The semiconductor device according to claim 1, wherein The first spacer of the second plurality of spacers has an “L” shaped structure.

3. The semiconductor device according to claim 1, wherein Each spacer of the first plurality of spacers has the first width.

4. The semiconductor device according to claim 1, wherein: A second spacer of the second plurality of spacers has the first width.

5. The semiconductor device according to claim 1, further comprising: a first gate dielectric, the first gate dielectric being located between the first plurality of spacers and the first fin, the first gate dielectric having the first width; as well as A second gate dielectric is disposed between the second gate stack and the second fin.

6. The semiconductor device according to claim 1, wherein The first region is a core region and the second region is an I / O region, wherein the first plurality of spacers have a different layer from the second plurality of spacers, and wherein the first gate stack is connected to a first voltage source and the second gate stack is connected to a second voltage source different from the first voltage source.

7. A semiconductor device comprising: a spacer stack adjacent to a first gate stack above a first semiconductor fin, wherein each spacer within the spacer stack has a width no greater than a top spacer within the spacer stack, the spacer stack having a first width and being located in a core region of a semiconductor substrate, and wherein the spacer stack includes at least four spacers, each spacer within the spacer stack having a sidewall in physical contact with the first gate stack; and A first plurality of spacers is adjacent to a second gate stack over a second semiconductor fin, at least one spacer of the first plurality of spacers having an "L" shape, the first plurality of spacers having a second width greater than the first width.

8. The semiconductor device according to claim 7, wherein: Each material located within the first plurality of spacers is also located within the spacer stack.

9. The semiconductor device according to claim 7, wherein: Each spacer within the spacer stack has the first width.

10. The semiconductor device according to claim 7, wherein: At least one spacer within the spacer stack is recessed from an adjacent spacer within the spacer stack.

11. The semiconductor device according to claim 7, wherein: A width of the first gate stack is smaller than a width of the second gate stack. 12 . The semiconductor device according to claim 7 , further comprising a shallow trench isolation adjacent to the first semiconductor fin, wherein the first gate stack extends into a recess of the shallow trench isolation.

13. A method for manufacturing a semiconductor device, the method comprising: blanket depositing a first material over the first semiconductor fin adjacent to the first dummy gate electrode and over the second semiconductor fin adjacent to the second dummy gate electrode; blanket depositing a second material adjacent to the first material; depositing a third material adjacent to the second material; depositing a fourth material adjacent to the third material; patterning the first material and the second material to form first and second spacers adjacent to the first dummy gate electrode and third and fourth spacers adjacent to the second dummy gate electrode, wherein the patterning is performed at least in part using one or more anisotropic etching processes; removing the first dummy gate electrode and the second dummy gate electrode; etching the first material of the first spacer to expose sidewalls of the second material of the second spacer, etching the second material to expose sidewalls of the third material, etching the third material to expose sidewalls of the fourth material, and forming a spacer stack, the sidewalls being perpendicular to a major surface of the first semiconductor fin, wherein etching the first material, the second material, and the third material does not etch the third spacer or the fourth spacer; forming a first gate electrode adjacent to the spacer stack; and A second gate electrode is formed adjacent to the third spacer.

14. The method according to claim 13, further comprising: After etching the first material, a first gate dielectric over the first semiconductor fin is etched without etching a second gate dielectric over the second semiconductor fin.

15. The method according to claim 13, wherein: The first semiconductor fin is located in a core region of a semiconductor substrate, and the second semiconductor fin is located in an I / O region of the semiconductor substrate.

16. The method of claim 13, further comprising recessing a shallow trench isolation region after etching the first material.

Images