Vertical semiconductor device

Abstract

A vertical semiconductor device may include a stacked structure, a channel structure, and a lower connection structure. The stacked structure may include an insulating layer and a gate electrode that are alternately and repeatedly stacked. The stacked structure may be spaced apart from the upper surface of a substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected to the channel and the substrate. The sidewall of the lower connection structure may include a protrusion that is disposed at a central portion of the sidewall in a vertical direction starting from the upper surface of the substrate. The vertical semiconductor device may have high reliability.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0076579 filed on June 26, 2019, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to vertical semiconductor devices and methods of manufacturing the same. Background Art

[0004] A vertical NAND flash memory device may include a lower connection structure for electrically connecting a lower sidewall of a channel and a substrate. However, the lower connection structure may be difficult to have a stable structure. Therefore, the vertical NAND flash memory device may have poor reliability due to the lower connection structure. Summary of the invention

[0005] Example embodiments provide a vertical semiconductor device including excellent electrical characteristics.

[0006] Example embodiments provide a method of manufacturing a vertical semiconductor device including excellent electrical characteristics.

[0007] According to example embodiments, a vertical semiconductor device is provided, which may include a stacked structure, a channel structure, and a lower connection structure. The stacked structure may include an insulating layer and a gate electrode that are alternately and repeatedly stacked. The stacked structure may be spaced apart from the upper surface of the substrate. The channel structure may include a charge storage structure and a channel. The channel structure may pass through the stacked structure. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected to the channel and the substrate. The sidewall of the lower connection structure may include a protrusion, which is disposed at a central portion of the sidewall starting from the upper surface of the substrate in the vertical direction.

[0008] According to example embodiments, a vertical semiconductor device is provided, which may include a supporting layer, a stacking structure, a channel structure, and a lower connection structure. The supporting layer may be spaced apart from the upper surface of the substrate. The stacking structure may be formed on the supporting layer. The stacking structure may include an insulating layer and a gate electrode stacked alternately and repeatedly. The channel structure may pass through the stacking structure and the supporting layer, and may extend to the upper surface of the substrate. The channel structure may include a charge storage structure and a channel. The lower connection structure may be formed on the substrate. The lower connection structure may be electrically connected to the channel and the substrate. The end of the lower connection structure disposed at the center portion in the vertical direction starting from the upper surface of the substrate may protrude from the end of each of the lower connection structure formed on the bottom of the supporting layer and the lower connection structure formed on the upper surface of the substrate.

[0009] According to example embodiments, a vertical semiconductor device is provided, which may include a stacked structure, a channel structure, and a lower connection structure. The stacked structure may include an insulating layer and a gate electrode stacked alternately and repeatedly. The stacked structure may be spaced apart from the upper surface of the substrate. The channel structure may pass through the stacked structure and may extend to the upper surface of the substrate. The channel structure may include a charge storage structure and a channel. The lower connection structure may contact the substrate to fill the gap between the surface of the substrate and the stacked structure. The lower connection structure may be electrically connected to the channel and the substrate. The lower connection structure may include a channel connection pattern and a protection pattern. In the same etching process, the protection pattern may include a material whose etching rate is lower than the etching rate of the channel connection pattern.

[0010] According to example embodiments, a vertical semiconductor device is provided, which may include a stacked structure, a channel structure, and a lower connection structure. The stacked structure may include an insulating layer and a gate electrode stacked alternately and repeatedly. The stacked structure may be spaced apart from the upper surface of the substrate. The channel structure may pass through the stacked structure and may extend to the upper surface of the substrate. The channel structure may include a charge storage structure and a channel. The lower connection structure may contact the substrate to fill the gap between the surface of the substrate and the stacked structure. The lower connection structure may be electrically connected to the channel and the substrate. The channel may include an upper channel and a lower channel. The upper channel and the lower channel may be spaced apart from each other in the vertical direction. The lower connection structure may be electrically connected to the upper channel and the lower channel.

[0011] According to example embodiments, a method for manufacturing a vertical semiconductor device is provided. In the method, a first sacrificial layer may be formed on a substrate. A molding structure may be formed on the first sacrificial layer. The molding structure may include an insulating layer and a second sacrificial layer stacked alternately and repeatedly. A channel structure may be formed to pass through the molding structure, and the channel structure may extend to the upper surface of the substrate. The channel structure may include a charge storage structure and a channel. The first sacrificial layer may be removed to form a gap between the surface of the substrate and the stacked structure. A lower connection structure may be formed to fill the gap. The lower connection structure may be electrically connected to the channel and the substrate. The lower connection structure may include a channel connection pattern and a protection pattern.

[0012] In a vertical semiconductor device according to example embodiments, a sidewall of the lower connection structure may include a protrusion, and the protrusion may be disposed at a central portion of the sidewall of the lower connection structure in a vertical direction from an upper surface of the substrate. A contact interface portion (e.g., a seam) of the lower connection structure filling a gap between a surface of the substrate and the stacked structure may not be exposed by the sidewall of the lower connection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0014] Figures 1 to 37 Represents non-limiting example embodiments as described herein.

[0015] Figures 1 to 3 are cross-sectional views and plan views illustrating a vertical semiconductor device according to example embodiments;

[0016] Figures 4 to 6 are enlarged cross-sectional views showing portions of a vertical semiconductor device according to example embodiments, respectively;

[0017] Figures 7 to 24 are cross-sectional views and plan views illustrating a method of manufacturing a vertical semiconductor device according to example embodiments;

[0018] Fig.25 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments;

[0019] Fig.26 and Fig. 27 is a cross-sectional view showing stages of a method of manufacturing a vertical semiconductor device according to example embodiments;

[0020] Fig.28 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments;

[0021] Figure 29 to Figure 33 are enlarged cross-sectional views of portions of a vertical semiconductor device according to example embodiments, respectively;

[0022] Fig.34 and Fig.35 is a cross-sectional view illustrating stages of a method of manufacturing a vertical semiconductor device according to example embodiments; and

[0023] Fig.36 and Fig.37 are cross-sectional views and plan views illustrating stages of a method of manufacturing a vertical semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0024] Hereinafter, a direction substantially parallel to the upper surface of the substrate is defined as a first direction. A direction substantially parallel to the upper surface of the substrate and perpendicular to the first direction is defined as a second direction. A direction substantially perpendicular to the upper surface of the substrate is defined as a vertical direction.

[0025] Figures 1 to 3 are cross-sectional views and plan views illustrating a vertical semiconductor device according to example embodiments. Figures 4 to 6 are respectively enlarged cross-sectional views illustrating portions of a vertical semiconductor device according to example embodiments.

[0026] In particular, Figure 1 Including along Figure 3 A cross-sectional view taken along path I-I'. Figure 2 Including along Figure 3 A cross-sectional view taken along path II-II'. Figures 4 to 6 Each of the Figure 1 and Figure 2 An enlarged cross-sectional view of portion "A".

[0027] refer to Figures 1 to 3 The vertical semiconductor device may include a lower connection structure 160, a support layer 106, a stack structure 172, and a channel structure 190 formed on a substrate 100. The vertical semiconductor device may further include a common source pattern 182, an insulating spacer 180, and the like.

[0028] The substrate 100 may include a semiconductor material such as silicon, germanium or silicon-germanium, or a III-V compound such as GaP, GaAs, GaSb, etc. In some example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0029] The lower connection structure 160 may be electrically connected to the substrate 100 and the channel 136 included in the channel structure 190. Therefore, the bottom of the lower connection structure 160 may directly contact the substrate 100. The lower connection structure 160 will be described in detail later.

[0030] The support layer 106 may be formed on the lower connection structure 160. In example embodiments, a portion of the support layer 106 may cover a portion of a sidewall of the lower connection structure 160.

[0031] When the first gap (156a, refer to Fig.15 ), the support layer 106 may support a structure formed on the support layer 106. The support layer 106 may include, for example, polysilicon.

[0032] The lower insulating layer 108 may be formed on the support layer 106. The lower insulating layer 108 may have a flat upper surface. The lower insulating layer 108 may include silicon oxide.

[0033] The stack structure 172 may be formed on the lower insulating layer 108. The stack structure 172 may include insulating layers 120 and gate electrodes 170 that are alternately and repeatedly stacked. One of the insulating layers 120 may be formed on an uppermost portion of the stack structure 172.

[0034] For example, the gate electrode 170 included in the stack structure 172 may be used as one of a gate electrode of a ground selection transistor, a gate electrode of a unit transistor among a plurality of unit transistors, and a gate electrode of a string selection transistor.

[0035] In example embodiments, the gate electrode 170 may include a barrier layer (not shown) and a gate conductive layer. The gate conductive layer may include a metal having excellent gap filling characteristics and low resistance. The gate conductive layer may include, for example, tungsten, titanium, tantalum, platinum, etc., and the barrier layer may include, for example, a metal nitride such as tungsten nitride, titanium nitride, tantalum nitride, etc.

[0036] The channel structure 190 may pass through the stacked structure 172, the lower insulating layer 108, and the support layer 106, and the channel structure 190 may extend to the upper portion of the substrate 100. The channel structure 190 may be formed in a channel hole 126 extending through the stacked structure 172, the lower insulating layer 108, and the support layer 106 to the upper portion of the substrate 100 (refer to Fig. 9 )middle.

[0037] In example embodiments, the channel hole 126 may have a sidewall slope such that the width of the channel hole 126 may gradually decrease from top to bottom. Therefore, the channel structure 190 may have a sidewall slope such that the width of the channel structure 190 may gradually decrease from top to bottom.

[0038] The channel structure 190 may include a charge storage structure 135, a channel 136, and a filling pattern 138. The channel structure 190 may further include a capping pattern 140 contacting the channel 136. The capping pattern 140 may be formed in an upper portion of the channel hole 126.

[0039] The charge storage structure 135 may include a tunnel insulating pattern 134, a charge storing pattern 132, and a blocking pattern 130 sequentially stacked from an outer wall of a channel 136. The tunnel insulating pattern 134 and the blocking pattern 130 may include silicon oxide, and the charge storing pattern 132 may include silicon nitride.

[0040] The charge storage structure 135 may be formed on an upper sidewall of the channel hole 126 located higher than the bottom of the support layer 106. In addition, the charge storage structure 135 may partially remain at a lower portion of the channel hole 126 in the substrate 100. That is, the charge storage structure 135 may have a cut shape at a portion adjacent to the lower connection structure 160.

[0041] The channel 136 may have a cylindrical shape in the channel hole 126. The channel 136 may contact the charge storage structure 135 and the lower connection structure 160. The channel 136 may include polysilicon.

[0042] A filling pattern 138 may be formed on the channel 136 to fill the inner space of the channel hole 126. The filling pattern 138 may include an insulating material. The insulating material may include, for example, silicon oxide.

[0043] A capping pattern 140 may be formed on the filling pattern 138. The capping pattern 140 may include, for example, polysilicon. The capping pattern 140 may function as a pad pattern for contacting an upper wiring (not shown).

[0044] A first insulating interlayer 146 may also be formed on the capping pattern 140 and the stack structure 172 .

[0045] The common source pattern 182 may pass through the first interlayer insulating layer 146, the stack structure 172, the support layer 106, and the lower insulating layer 108. A bottom of the common source pattern 182 may contact an upper surface of the substrate 100.

[0046] In example embodiments, the common source pattern 182 may have a line shape extending in the first direction. In this case, the common source pattern 182 may be formed in the trench 148 (refer to FIG. 1 ) that passes through the first insulating interlayer 146, the stacked structure 172, the lower insulating layer 108, and the support layer 106 and exposes the substrate 100. Fig.12 The groove 148 may extend in the first direction.

[0047] That is, the lower connection structure 160, the support layer 106, the lower insulating layer 108, and the stack structure 172 may be formed between the common source patterns 182. Therefore, the lower connection structure 160, the support layer 106, the lower insulating layer 108, and the stack structure 172 may have a line shape extending in the first direction.

[0048] The common source pattern 182 may include, for example, a barrier metal layer (not shown) and a metal pattern. The barrier metal layer may include a metal nitride, such as tungsten nitride, titanium nitride, tantalum nitride, etc. In addition, the metal pattern may include, for example, a metal with low resistance, such as tungsten, titanium, tantalum, platinum, etc.

[0049] The insulating spacer 180 may be formed on the sidewall of the common source pattern 182 . In example embodiments, the insulating spacer 180 may include silicon oxide. That is, the insulating spacer 180 may be formed on the sidewall of the trench 148 .

[0050] The stacked structure 172, the lower insulating layer 108, the supporting layer 106, and the lower connection structure 160 may contact the insulating spacer 180. Therefore, the gate electrode 170 and the common source pattern 182, the supporting layer 106 and the common source pattern 182, and the lower connection structure 160 and the common source pattern 182 may be insulated from each other by the insulating spacer 180.

[0051] like Figure 1 As shown, a portion of the sidewall of the lower connection structure 160 may be covered by the support layer 106. The sidewall of the lower connection structure 160 may not directly contact the insulating spacer 180. Figure 2 A portion of the sidewall of the lower connection structure 160 on which the support layer 106 is not formed is shown. In this portion, the sidewall of the lower connection structure 160 may directly contact the insulating spacer 180.

[0052] In some example embodiments, the common source pattern 182 may have a contact plug shape. In this case, the common source pattern 182 may be formed in the trench 148 extending in the first direction (refer to Fig.12 Although not shown, a common source line may be further formed under the contact plug.

[0053] The first gap 156a may be defined by the bottom of the support layer 106, the upper surface of the substrate 100, and the channel 136. The first gap 156a may be communicated with the lower portion of the groove 148. In addition, a lower connection structure 160 may be formed in the first gap 156a. The lower connection structure 160 may include a channel connection pattern 160a and a protection pattern 160b.

[0054] The channel connection pattern 160a may be conformally formed on the bottom of the support layer 106, the lower sidewall of the channel 136, and the upper surface of the substrate 100. In this case, the channel connection pattern 160a formed on the bottom of the support layer 106 and the channel connection pattern 160a formed on the upper surface of the substrate 100 may not contact each other at the central portion of the first gap 156a in the vertical direction. Therefore, the channel connection pattern 160a may not include a seam at the central portion.

[0055] The channel connection pattern 160a may have conductivity. That is, the channel connection pattern 160a may include a conductive material. Therefore, the substrate 100 and the channel 136 may be electrically connected through the channel connection pattern 160a.

[0056] In example embodiments, the channel connection pattern 160a may include polysilicon doped with conductive impurities. For example, the channel connection pattern 160a may be doped with N-type impurities such as phosphorus and arsenic.

[0057] In some examples, the channel connection pattern 160 a may be doped with P-type impurities such as boron.

[0058] The protection pattern 160 b may be formed on the channel connection pattern 160 a. The protection pattern 160 b may fill a space between the channel connection pattern 160 a formed on the support layer 106 and the channel connection pattern 160 a formed on the substrate 100.

[0059] The protection pattern 160b may be conformally formed on the surface of the channel connection pattern 160a. That is, the protection pattern 160b formed on the channel connection pattern 160a on the support layer 106 and the protection pattern 160b formed on the channel connection pattern 160a on the substrate 100 may contact each other at the central portion of the first gap in the vertical direction. Therefore, the protection pattern 160b may include a seam S therein. However, the seam S may not be exposed on the sidewall of the lower connection structure 160.

[0060] In the lower connection structure 160 , the end of the protection pattern 160 b may protrude from the end of the channel connection pattern 160 a toward the trench (ie, in the second direction) in the lateral direction.

[0061] In the etching process, the protection pattern 160b may include a material having a lower etching rate than the channel connection pattern 160a. In example embodiments, in the etching process for forming the channel connection pattern 160a, the etching rate of the channel connection pattern 160a may be higher than twice that of the protection pattern 160b.

[0062] In example embodiments, the protection pattern 160b may include a material that may be etched at a different etching rate together with the channel connection pattern 160a in the same etching process. For example, the channel connection pattern 160a may include polysilicon doped with N-type impurities.

[0063] In example embodiments, the protection pattern 160b may include undoped polysilicon or polysilicon doped with P-type impurities. Alternatively, the protection pattern 160b may include polysilicon doped with N-type impurities at a concentration lower than that of the channel connection layer.

[0064] In some example embodiments, the protection pattern 160b may include polysilicon doped with non-conductive impurities, such as C, O, N, Cl, etc.

[0065] In some example embodiments, the protection pattern 160 b may include a material that may be etched in an etching process different from that of the channel connection pattern 160 a .

[0066] In example embodiments, the protection pattern 160b may include an insulating layer. For example, the protection pattern 160b may include silicon oxide, SiOC, SiON, or the like.

[0067] In example embodiments, in the first gap, a thickness of the protection pattern 160 b in the vertical direction may be smaller than a total thickness of the channel connection pattern 160 a in the vertical direction.

[0068] In example embodiments, a grain size of the protection pattern 160 b may be smaller than a grain size of the channel connection pattern 160 a .

[0069] Therefore, the lower connection structure 160 may include channel connection patterns 160 a and protection patterns 160 b interposed between the channel connection patterns 160 a .

[0070] In the cross-sectional view of a portion of the sidewall of the lower connection structure 160, the channel connection pattern 160a, the protection pattern 160b and the channel connection pattern 160a may be stacked. In addition, the protection pattern 160b may protrude from the channel connection pattern 160a in the second direction. Therefore, the end of the protection pattern 160b may correspond to the protrusion.

[0071] That is, in the sidewall of the lower connection structure 160, an end portion of the lower connection structure 160 disposed at a central portion in the vertical direction may protrude in the second direction from an end portion of the lower connection structure 160 contacting each of the bottom of the support layer 106 and the upper surface of the substrate 100. The sidewall of the lower connection structure 160 may include a protrusion.

[0072] In an example embodiment, if Figure 4 As shown, the upper and lower surfaces of the protection pattern 160b may have inclined surfaces so that the protection pattern 160b has a sharp shape toward the end in the second direction. Therefore, the height of the protection pattern 160b in the vertical direction may gradually decrease toward the end of the protection pattern 160b in the second direction.

[0073] In an example embodiment, if Figure 5 As shown, the end of the protection pattern 160b may have a rounded shape.

[0074] In an example embodiment, if Figure 6 As shown, the upper and lower surfaces of the protection pattern 160b may be flat, and the end portion may have a vertical slope. Therefore, the protection pattern 160b may have the same height in the vertical direction according to its position.

[0075] In a vertical semiconductor device, the channel connection pattern 160a formed in the first gap 156a may not form a contact interface (i.e., a seam) in the first gap 156a. On the other hand, the protection pattern 160b may include a seam S at the central portion of the first gap 156a in the vertical direction. However, the seam S may be disposed inside the protection pattern 160b and may not be exposed by the sidewall of the lower connection structure 160. When over-etching of the channel connection pattern 160a occurs due to exposing the gap and filling another material (e.g., a conductive material) in the gap and the etched portion, electrical failures and reliability failures may occur. However, the seam may not be exposed by the sidewall of the lower connection structure 160, thereby reducing electrical failures and reliability failures.

[0076] Figures 7 to 24 are cross-sectional views and plan views illustrating a method of manufacturing a vertical semiconductor device according to example embodiments.

[0077] Each cross-section is along Figure 3 The path I-I' is intercepted. Fig.17 yes Fig.16 An enlarged view of the "A" section, and Fig.19 yes Fig.18 Magnified view of section "A".

[0078] refer to Figure 7 and Figure 8 , a first sacrificial pattern 104 may be formed on the substrate 100, and a support layer 106 may be formed on the first sacrificial pattern 104. A lower insulating layer 108 may be formed on the support layer 106. A molding structure 124 may be formed on the lower insulating layer 108.

[0079] In example embodiments, a liner layer (not shown) may be further formed on the surface of the substrate 100. For example, the liner layer may include silicon oxide.

[0080] The first sacrificial pattern 104 may be formed by forming a first sacrificial layer on the substrate 100 and patterning the first sacrificial layer.

[0081] The first sacrificial pattern 104 may include a material having a high etch selectivity with respect to the support layer 106 and the insulating layer 120 formed thereon. In example embodiments, the first sacrificial pattern 104 may include a material having a high etch selectivity with respect to silicon oxide and polysilicon. The first sacrificial pattern 104 may include, for example, silicon nitride.

[0082] In example embodiments, in the patterning of the first sacrificial layer, the first sacrificial layer located on a portion of the trench for forming the common source pattern 182 may be etched to form a first sacrificial pattern 104 including a first opening 112a. That is, the first opening 112a may be formed in a portion of the trench for forming the common source pattern 182. The surface of the substrate 100 may be exposed by the bottom of the first opening 112a.

[0083] In some example embodiments, after forming the first sacrificial layer, the patterning process may not be performed. Therefore, the first sacrificial layer may not include the first opening 112a. In this case, the subsequent same process may be performed to form a Figure 2 A cross-sectional view of a semiconductor device is shown.

[0084] In example embodiments, a support layer 106 may be formed on an upper surface of the first sacrificial pattern 104 to fill the first opening 112 a . Thus, the support layer 106 may contact a surface of the substrate 100 and a portion of a sidewall of the first sacrificial pattern 104 .

[0085] When the first sacrificial pattern 104 is removed by a subsequent process, the support layer 106 may support the lower insulating layer 108 and the mold structure 124 thereon. In example embodiments, the support layer 106 may include, for example, polysilicon.

[0086] The lower insulating layer 108 may be formed on the support layer 106. The lower insulating layer 108 may be formed to have a flat upper surface. The lower insulating layer 108 may include silicon oxide.

[0087] The second sacrificial layers 122 and the insulating layers 120 may be alternately and repeatedly formed on the lower insulating layer 108 to form the molding structure 124. One of the insulating layers 120 may be formed on the uppermost portion of the molding structure 124.

[0088] In example embodiments, the lower insulating layer 108 and the insulating layer 120 may include oxide, eg, silicon oxide, and the second sacrificial layer 122 may include, eg, silicon nitride.

[0089] refer to Fig. 9 , the insulating layer 120, the second sacrificial layer 122, the lower insulating layer 108, the supporting layer 106, and the first sacrificial pattern 104 may be etched by an anisotropic etching process to form a channel hole 126 exposing the surface of the substrate 100. In example embodiments, the channel hole 126 may extend to a portion below the upper surface of the substrate 100.

[0090] A charge storage structure 135 , a channel 136 , and a filling pattern 138 may be formed in each channel hole 126 .

[0091] Specifically, a charge storage structure layer may be formed on the sidewall and bottom of the channel hole 126 and the upper surface of the mold structure 124. The charge storage structure layer may include a blocking layer, a charge storage layer, and a tunnel insulating layer stacked in sequence. For example, the blocking layer, the charge storage layer, and the tunnel insulating layer may include silicon oxide, silicon nitride, and silicon oxide, respectively.

[0092] A channel layer may be conformally formed on the charge storage structure layer. The channel layer may include polysilicon.

[0093] Thereafter, a filling insulating layer may be formed on the channel layer to fill the remaining portion of the channel hole 126. Then, the filling insulating layer, the channel layer, and the charge storage structure layer may be planarized until the upper surface of the molding structure 124 may be exposed.

[0094] Through the planarization process, the charge storage structure 135 and the channel 136 may be sequentially stacked on the sidewalls of the channel hole 126 and the upper surface of the substrate 100. A filling pattern 138 may be formed on the channel 136 to fill the inside of the channel 136. The charge storage structure 135 may include a blocking pattern 130, a charge storage pattern 132, and a tunnel insulating pattern 134.

[0095] refer to Fig.10 and Fig.11 , the upper portion of the filling pattern 138 and the channel 136 may be removed to form a recess, and a capping pattern 140 may be formed in the recess. The capping pattern 140 may include, for example, polysilicon. Thus, a preliminary channel structure 188 may be formed in each channel hole 126. Thereafter, a first insulating interlayer 146 may be formed on the molding structure 124 and the capping pattern 140.

[0096] refer to Fig.12 and Fig.13 , the first insulating interlayer 146, the second sacrificial layer 122, the insulating layer 120, and the lower insulating layer 108 may be etched by an anisotropic etching process to form a primary trench exposing the upper surface of the support layer. The primary trench may extend in the first direction. The primary trench may have a first width in the second direction. In example embodiments, the first width may be greater than the thickness of the first sacrificial pattern 104 formed on the substrate 100.

[0097] A first spacer layer may be formed on the sidewalls and bottom of the preliminary trench and on the first insulating interlayer 146. The first spacer layer may be anisotropically etched to form a first spacer 150. The first spacer 150 may be formed on the sidewalls of the preliminary trench. In example embodiments, the first spacer 150 may include polysilicon.

[0098] Subsequently, the support layer 106 exposed by the bottom of the preliminary trench may be anisotropically etched to form the trench 148. The first sacrificial pattern 104 may be exposed by the bottom of the trench 148.

[0099] The first spacer 150 may cover the sidewalls of the lower insulating layer 108 and the molding structure 124 exposed by the trench 148. Thus, the insulating layer 120, the second sacrificial layer 122, and the lower insulating layer 108 may not be exposed by the trench 148.

[0100] refer to Fig.14 , the initial first gap 156 may be formed by removing the first sacrificial pattern 104 exposed by the bottom of the trench 148. The removal process may include an isotropic etching process, for example, a wet etching process.

[0101] In the removal process of the first sacrificial pattern 104 , other layers except the first sacrificial pattern 104 , such as oxide, polysilicon, etc., may not be removed. A bottom of the support layer 106 and a portion of a sidewall of the barrier pattern 130 may be exposed by the initial first gap 156 .

[0102] refer to Fig.15 , the blocking pattern 130, the charge storage pattern 132, and the tunnel insulating pattern 134 exposed by the initial first gap 156 may be sequentially removed. Thus, the initial first gap 156 may be transformed into the first gap 156a. In addition, the preliminary channel structure 188 may be transformed into the channel structure 190.

[0103] The first gap 156 a and the groove 148 may communicate with each other.

[0104] The lower outer wall of the channel 136 may be exposed by the first gap 156a. In addition, the upper surface of the substrate 100 may be exposed by the first gap 156a.

[0105] In example embodiments, a liner layer may be formed on the substrate 100. In this case, the liner layer may be removed together through an etching process of the barrier pattern 130 and the tunnel insulating pattern 134 exposed by the preliminary first gap 156.

[0106] When the wet etching process is performed, a portion of the charge storage structure 135 directly exposed by the initial first gap 156 may be etched, and the charge storage structure 135 may be further etched in a vertical direction from the initial first gap 156 .

[0107] In the first gap 156a, the portion between the upper surface of the substrate 100 and the bottom of the support layer 106 is referred to as a first portion, and the etched portion of the charge storage structure 135 is referred to as a second portion. For example, the second height of the second portion in the vertical direction may be greater than the first height of the first portion in the vertical direction. The first height may be substantially the same as the thickness of the first sacrificial pattern 104, so that the first height may be less than the first width.

[0108] refer to Fig.16 and Fig.17 , the first spacer 150 formed on the sidewall of the trench 148 may be removed (refer to Fig.15 ). The removal process of the first spacer 150 may include an isotropic etching process.

[0109] Thereafter, the sidewalls of the trench 148 and the surface of the first gap 156a (see Fig.15 ), a channel connection layer 158 a is conformally formed on the upper surface of the substrate 100 and the first insulating interlayer 146 .

[0110] The channel connection layer 158a may be formed to not completely fill the first portion of the first gap 156a. That is, in the first gap 156a, the channel connection layer 158a formed on the bottom of the support layer 106 and the channel connection layer 158a formed on the substrate 100 may not contact each other at the center portion of the first gap 156a in the vertical direction. Therefore, the channel connection layer 158a may not include a contact interface in the first gap 156a. In addition, the channel connection layer 158a may be formed to not completely fill the groove 148.

[0111] The channel link layer 158 a may be formed to completely fill the second portion of the first gap 156 a .

[0112] That is, the channel connection layer 158a may be formed to have a first thickness less than ½ of the first height. In addition, the first thickness may be greater than ½ of the width of the charge storage structure in the second direction.

[0113] The channel connection layer 158 a may fill the second portion so that the channel 136 may be electrically connected to the substrate 100 through the channel connection layer 158 a .

[0114] In example embodiments, the channel connection layer 158a may include polysilicon doped with conductive impurities. For example, the channel connection layer 158a may be doped with N-type impurities such as phosphorus and arsenic.

[0115] In some example embodiments, the channel connection layer 158 a may be doped with P type impurities such as boron.

[0116] refer to Fig.18 and Fig.19 , a protection layer 158 b may be conformally formed on the channel connection layer 158 a .

[0117] The protective layer 158 b may be formed to completely fill the first portion of the first gap 156 a . In addition, the protective layer 158 b may be formed to not completely fill the trench 148 .

[0118] That is, the protective layer 158b formed conformally on the upper surface of the channel connection layer 158a may contact itself at the central portion of the first gap 156a in the vertical direction. Therefore, the first portion may be completely filled with the protective layer 158b. In addition, the seam S may be formed at the contact portion of the protective layer 158b. The protective layer 158b may be deposited on the bottom of the groove 148 so that the entrance portion of the first gap 156a may be filled with the protective layer 158b. Therefore, the seam S may be positioned inside the protective layer 158b at the central portion of the first gap 156a in the vertical direction.

[0119] That is, the protective layer 158b may be formed to have a thickness greater than 1 / 2 of the height of the gap between the channel connection layers 158a formed at the first portion in the vertical direction. In addition, the protective layer 158b may be formed to have a thickness less than 1 / 2 of the width in the second direction between the channel connection layers 158a formed on the facing sidewalls of the trench 148.

[0120] In example embodiments, in the etching process of the channel connection layer 158a, the protection layer 158b may use a material whose etching rate is lower than the etching rate of the channel connection layer 158a. For example, in the process of etching the channel connection layer 158a, the etching rate of the channel connection layer 158a may be higher than twice the etching rate of the protection layer 158b.

[0121] In example embodiments, the channel connection layer 158 a and the protection layer 158 b may respectively include materials having different etching rates in the same etching process.

[0122] For example, the channel connection layer 158 a may include polysilicon doped with N-type impurities.

[0123] In example embodiments, the protective layer 158b may include undoped polysilicon. Alternatively, the protective layer 158b may include polysilicon doped with N-type impurities having a concentration lower than that of the channel connection layer 158a. In the etching process, the etching rate of the undoped polysilicon or the polysilicon lightly doped with N-type impurities may be lower than the etching rate of the polysilicon doped with N-type impurities of the channel connection layer 158a.

[0124] In some example embodiments, the protective layer 158 b may include polysilicon doped with P-type impurities. In an etching process, polysilicon doped with impurities having different conductivity types may have different etching rates from each other.

[0125] In some example embodiments, the protective layer 158b may include polysilicon doped with non-conductive impurities. For example, the non-conductive impurities may include C, O, N, Cl, etc. In the etching process, the polysilicon doped with conductive impurities and the polysilicon doped with non-conductive impurities may have different etching rates from each other.

[0126] In some example embodiments, the channel connection layer 158a and the protection layer 158b may include materials that can be etched by different etching processes, respectively. When the channel connection layer 158a is etched, the protection layer 158b may be etched less than the channel connection layer 158a. In example embodiments, the protection layer 158b may include an insulating layer. For example, the protection layer 158b may include silicon oxide, SiOC, SiON, etc.

[0127] refer to Fig. 20 and Fig.21 , the protective layer 158b and the channel connection layer 158a formed on the sidewall and bottom of the trench 148 and the first insulating interlayer 146 may be sequentially removed to form a lower connection structure 160 filling the first gap 156a. The lower connection structure 160 may include a channel connection pattern 160a and a protective pattern 160b. In addition, the substrate 100 may be exposed through the bottom of the trench 148.

[0128] First, if Fig. 20 As shown, the protective layer 158b formed on the sidewall and bottom of the trench 148 and the first insulating interlayer 146 may be removed. In this case, the protective layer 158b may remain in the first gap 156a. In example embodiments, the protective layer 158b may be removed by an isotropic etching process. The isotropic etching process may include an isotropic dry etching process.

[0129] In the etching process, the protective layer 158b has a relatively low etching rate, so that the etching amount can be easily controlled. In the etching process, the seam located in the protective layer 158b may not be exposed.

[0130] Afterwards, if Fig.21 As shown, the channel connection layer 158a formed on the sidewall and bottom of the trench 148 and the first insulating interlayer 146 may be removed (see Fig. 20 ). Therefore, the insulating layer 120 and the second sacrificial layer 122 may be exposed through the sidewalls of the trench 148. The channel connection layer 158a may be removed by an isotropic etching process. The isotropic etching process may include an isotropic dry etching process.

[0131] In the removal process of the channel connection layer 158a, the protection layer 158b may be slightly etched or may be etched to have an etching rate lower than that of the channel connection layer 158a. That is, the channel connection layer 158a formed at the first portion of the first gap 156a may be etched faster than the protection layer 158b.

[0132] Through the above process, the lower connection structure 160 may be formed in the first gap 156a, and the lower connection structure 160 may include a channel connection pattern 160a and a protection pattern 160b between portions of the channel connection pattern 160a. In this case, in a cross-sectional view of a portion of the sidewall of the lower connection structure 160, the channel connection pattern 160a, the protection pattern 160b, and the channel connection pattern 160a may be stacked. In addition, the protection pattern 160b may protrude from the channel connection pattern 160a in the second direction.

[0133] In addition, after the etching process is performed, the seams S included in the protection pattern 160b may not be exposed by the sidewalls of the lower connection structure 160. Therefore, defects due to the exposure of the seams S may be reduced.

[0134] In example embodiments, the etching process of the channel connection layer 158a may use an etchant such as HBr, Cl 2 、F 2 , HCl, ClF 3 etc. gas.

[0135] According to the etching process, the shape of the sidewall of the lower connection structure 160 may be changed. For example, the sidewall of the lower connection structure 160 may have a shape as shown in FIG. Figure 4 , Figure 5 and Figure 6 One of the shapes shown.

[0136] When the channel connection layer 158a is etched, the protection layer 158b may be partially etched to form a Figure 4 and Figure 5 The lower connecting structure 160 is one of the shapes shown. In the exemplary embodiment, as shown in FIG. Figure 4 As shown, the upper and lower surfaces of the protection pattern 160b may have inclined surfaces so that the protection pattern 160b has a sharp shape toward the end in the second direction. Figure 5 As shown, the end of the protection pattern 160b may have a rounded shape.

[0137] When the channel connection layer 158a is etched, the protection layer 158b may be slightly etched to form a Figure 6The lower connecting structure 160 of the shape shown. In the exemplary embodiment, as Figure 6 As shown, the upper and lower surfaces of the protection pattern 160b may be flat, and the end portion may have a vertical slope. Therefore, the protection pattern 160b may have the same height in the vertical direction according to its position.

[0138] For example, the channel connection layer 158a may include polysilicon doped with N-type impurities, and the protective layer 158b may include undoped polysilicon, polysilicon doped with P-type impurities, or polysilicon doped with N-type impurities at a concentration lower than the doping concentration of the channel connection layer. In this case, the protective layer 158b and the channel connection layer 158a may be removed by an isotropic dry etching process using an etching gas including a halogen gas. For example, the etching gas may include HBr, Cl 2 、F 2 , HCl, ClF 3 wait.

[0139] The channel 136 may be electrically connected to the substrate 100 through a lower connection structure 160 .

[0140] refer to Fig. 22 , the second sacrificial layer 122 exposed by the sidewall of the trench 148 is removed to form a second gap 162 between the insulating layers 120. A portion of the outer wall of the barrier pattern 130 may be exposed through the second gap 162. The removal process of the second sacrificial layer 122 may include a wet etching process.

[0141] refer to Fig.23 A second barrier layer (not shown) may be conformally formed on surfaces of the trench 148 and the second gap 162 , and a gate electrode layer may be formed on the second barrier layer to fill the second gap 162 .

[0142] In example embodiments, the gate electrode layer may include a barrier layer (not shown) and a gate conductive layer stacked in sequence. The gate conductive layer may include a metal with low resistance, such as tungsten, titanium, tantalum, platinum, etc., and the barrier layer may include a metal nitride, such as tungsten nitride, titanium nitride, tantalum nitride, etc.

[0143] Thereafter, the gate electrode layer may be partially removed to form a gate electrode 170 filling the second gap 162. In example embodiments, the gate electrode layer formed in the trench 148 may be removed. The removal process may include a wet etching process. The gate electrode 170 may extend in the first direction.

[0144] Thus, a stack structure 172 including the insulating layers 120 and the gate electrodes 170 that are alternately and repeatedly stacked may be formed, and the stack structure 172 may extend in the first direction.

[0145] refer to Fig.24 , an insulating spacer layer may be formed on the sidewalls of the trench 148. The insulating spacer layer may be anisotropically etched so that the substrate may be exposed by the bottom of the trench. Therefore, an insulating spacer 180 may be formed on the sidewalls of the trench 148. The insulating spacer 180 may include silicon oxide.

[0146] Thereafter, a conductive layer may be formed on the first insulating interlayer 146 to fill the trench 148. The conductive layer may be planarized until the upper surface of the first insulating interlayer 146 may be exposed to form a common source pattern 182. The common source pattern 182 may include, for example, a barrier metal layer and a metal pattern. The barrier metal layer may include a metal nitride, such as tungsten nitride, titanium nitride, tantalum nitride, etc. The metal pattern may include a metal with low resistance, such as tungsten, titanium, tantalum, platinum, etc.

[0147] Although not shown, an upper insulating interlayer may be formed on the first insulating interlayer 146 , the common source pattern 182 , and the insulating spacer 180 , and then an upper wiring may be formed to be electrically connected to each of the capping pattern 140 , the common source pattern 182 , and the gate electrode 170 .

[0148] Fig.25 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments.

[0149] The vertical semiconductor device may have a cell-peripheral-on-chip (COP) structure in which a peripheral circuit may be formed under a memory cell. That is, a peripheral circuit for driving a memory cell may be formed on a substrate disposed under the memory cell.

[0150] refer to Fig.25 A circuit pattern serving as a peripheral circuit may be formed on the lower substrate 200. A lower wiring 209 may be formed to be electrically connected to the circuit pattern. A lower insulating interlayer 210 may be formed to cover the circuit pattern.

[0151] The lower substrate 200 may be divided into a field region in which the device isolation pattern 202 is formed and an active region in which the device isolation pattern 202 is not formed.

[0152] The circuit pattern may include a transistor 204 , a resistor, a capacitor, etc. The transistor 204 may include a gate and a source / drain.

[0153] The lower wiring 209 may include a lower contact plug 206 and a conductive line 208. The lower wiring 209 may be formed in multiple layers. The lower insulating interlayer 210 may include silicon oxide.

[0154] The lower wiring 209 may be formed in the lower insulating interlayer 210. An uppermost portion of the lower insulating interlayer 210 may be flat.

[0155] A lower conductive pattern 212 may be formed on the lower insulating interlayer 210. In example embodiments, the lower conductive pattern 212 may be used as a common source line. In example embodiments, the lower conductive pattern 212 may include a metal or a metal silicide. For example, the lower conductive pattern 212 may include tungsten, copper, aluminum, tungsten silicide, cobalt silicide, etc.

[0156] A base layer 216 may be formed on the lower conductive pattern 212. The base layer 216 may include, for example, a polysilicon layer or a single crystal silicon layer.

[0157] In example embodiments, the base layer 216 may serve as an upper substrate.

[0158] A structure is formed on the base layer 216, and the structure is similar to Figures 1 to 3 In addition to the common source pattern, the structure formed on the base layer 216 can be Figures 1 to 3 The structures shown are essentially the same.

[0159] In example embodiments, a common source pattern may be formed below the base layer 216, and the common source pattern may have a line shape. Therefore, in this case, the insulating spacer and the common source pattern may not be formed in the trench 148. That is, the insulating pattern 186 may be formed in the trench 148. The insulating pattern 186 may include silicon oxide. In example embodiments, a contact plug contacting the common source pattern may be formed in the trench 148.

[0160] Fig.26 and Fig. 27 are cross-sectional views illustrating stages of a method of manufacturing a vertical semiconductor device according to example embodiments.

[0161] refer to Fig.26 , a circuit pattern constituting a peripheral circuit may be formed on the lower substrate 200. A lower wiring 209 may be formed to be electrically connected to the circuit pattern, and a lower insulating interlayer 210 may be formed to cover the circuit pattern. A lower conductive pattern 212 and a base layer 216 may be sequentially formed on the lower insulating interlayer 210.

[0162] Before forming the circuit pattern, a trench isolation process may be performed on the lower substrate 200 to form a field region in which the device isolation pattern 202 is formed and an active region in which the device isolation pattern 202 is not formed.

[0163] In example embodiments, after forming the lower insulating interlayer 210 , an upper surface of the lower insulating interlayer 210 may be planarized.

[0164] refer to Fig. 27 , can be performed on the base layer 216 with reference Figures 6 to 23Thus, a substrate layer 216 may be formed on the substrate layer 216. Fig.23 The structure shown.

[0165] Reference again Fig.25 , the insulating layer may be formed to completely fill the trench 148, and the insulating layer may be planarized to form an insulating pattern 186 in the trench 148. The insulating layer may include silicon oxide. Thus, it is possible to manufacture Fig.25 The semiconductor device shown.

[0166] Fig.28 is a cross-sectional view illustrating a vertical semiconductor device according to example embodiments. Figure 29 to Figure 33 are respectively enlarged cross-sectional views of portions of a vertical semiconductor device according to example embodiments.

[0167] Figure 29 to Figure 33 This is an enlarged view of the lower connection structure and channel structure. Fig.29 yes Fig.28 Magnified view of part B.

[0168] Each vertical semiconductor device can be connected to a reference Figure 1 The vertical semiconductor devices described are essentially the same.

[0169] refer to Fig.28 and Fig.29 In the vertical semiconductor device, the lower connection structure 160 may be electrically connected to the channel 136 a included in the channel structure 190 and the substrate 100 .

[0170] In an example embodiment, the channel 136a may have a cylindrical shape having a partially cut portion in the channel hole 126 (refer to Fig. 9 ). In particular, the channel 136a may have a cut portion at a portion facing the lower connection structure 160. In example embodiments, a portion of the channel 136a may remain below the bottom of the lower connection structure 160 in the channel hole 126. That is, the channel 136a may include an upper channel and a lower channel. The upper channel and the lower channel may be spaced apart from each other in a vertical direction, and the lower connection structure may electrically connect the upper channel and the lower channel.

[0171] In example embodiments, a bottom of the upper trench may have the same height as a top of the cut portion of the charge storage structure 135, or be higher than the top of the cut portion of the charge storage structure 135. A top surface of the lower trench may have the same height as a bottom of the cut portion of the charge storage structure 135, or be lower than the bottom of the cut portion of the charge storage structure 135.

[0172] The lower connection structure 160 may contact the bottom of the upper channel and the top surface of the lower channel, respectively. The lower connection structure 160 may not contact the outer wall of the channel 136a. Therefore, the contact area between the channel 136a and the lower connection structure 160 may be reduced. The channel 136a may be physically separated from itself by the cutting portion, and the channel 136a may be electrically connected by the lower connection structure 160.

[0173] At least a portion of the contact channel of the lower connection structure 160 may include polysilicon doped with impurities. In example embodiments, the lower connection structure 160 may include polysilicon doped with N-type impurities such as phosphorus, arsenic, etc. The impurities of the lower connection structure 160 may diffuse into the channel 136a adjacent to the lower connection structure 160. However, the contact area between the channel 136a and the lower connection structure 160 may be reduced, so that the area of ​​the diffusion source of the impurities of the lower connection structure 160 may be reduced. Therefore, the diffusion of impurities to the upper portion of the channel 136a may be reduced, and the diffusion of impurities may be easily controlled.

[0174] In example embodiments, a gate induced drain leakage (GIDL) transistor may be formed on the lower connection structure 160 to erase data of a cell in a vertical semiconductor device. When impurities included in the lower connection structure 160 excessively diffuse into the channel 136a or the diffusion of the impurities is not controlled, it may be difficult to maintain the characteristics of the GIDL transistor. However, in example embodiments, the diffusion of the impurities may be easily controlled, so that the characteristic distribution of the GIDL transistor may be uniformly maintained.

[0175] In some example embodiments, Fig.30 As shown, the channel 136b may have a cylindrical shape in the channel hole 126, and a portion of the channel 136b may have a relatively thin width. In particular, the channel 136b may have a relatively thin width at a portion facing the lower connection structure 160.

[0176] That is, the channel 136b may include an upper channel, a lower channel, and a connecting portion. The connecting portion may be formed between the upper channel and the lower channel, and the connecting portion may connect the upper channel and the lower channel. The width of the connecting portion may be less than the width of each of the upper channel and the lower channel. When the connecting portion is formed, the channel 136b may have a cylindrical shape without a cutting portion.

[0177] The lower connection structure 160 may contact a portion of the channel 136b having a relatively narrow width, that is, an outer wall of a connection portion of the channel 136b. Since the width of the channel 136b has a relatively thin width at a contact portion between the channel 136b and the lower connection structure 160, the width of a diffusion path of impurities of the lower connection structure 160 may be reduced. Therefore, diffusion of impurities to the upper portion of the channel 136b may be reduced, and diffusion of impurities may be easily controlled.

[0178] In example embodiments, the lower connection structure 160 may be one channel connection pattern including polysilicon doped with impurities.

[0179] In some example embodiments, Fig.31 and Fig.32 As shown, the lower connection structure 160 may include a channel connection pattern 160a and a protection pattern 160b, as shown in FIG. Figure 1 shown.

[0180] In some example embodiments, Fig.33 As shown, the charge storage structure 135 may have a cut portion adjacent to the lower connection structure 160. In addition, the heights of the cut portions of the tunnel insulating pattern 134, the charge storage pattern 132, and the blocking pattern 130 included in the charge storage structure 135 may be different from each other. In the etching process of the layers included in the charge storage structure 135, the etching rates of the tunnel insulating layer, the charge storage layer, and the blocking layer may be different.

[0181] In an example embodiment, if Fig.33 As shown, the charge storage pattern 132 may protrude from the tunnel insulation pattern 134 and the barrier pattern 130. That is, the upper portion of the cut portion of the charge storage pattern 132 may protrude downward from the upper portion of the cut portion of each of the tunnel insulation pattern 134 and the barrier pattern 130. In addition, the lower portion of the cut portion of the charge storage pattern 132 may protrude upward from the lower portion of the cut portion of each of the tunnel insulation pattern 134 and the barrier pattern 130. Therefore, the top of the cut portion of the charge storage pattern 132 may be lower than the top of the cut portion of each of the tunnel insulation pattern 134 and the barrier pattern 130. In addition, the bottom of the cut portion of the charge storage pattern 132 may be higher than the bottom of the cut portion of each of the tunnel insulation pattern 134 and the barrier pattern 130.

[0182] In some example embodiments, although not shown, the tunnel insulating pattern 134 and the blocking pattern 130 may protrude from the charge storing pattern 132. That is, a top of a cut portion of the charge storing pattern 132 may be higher than a top of a cut portion of each of the tunnel insulating pattern 134 and the blocking pattern 130. In addition, a bottom of a cut portion of the charge storing pattern 132 may be lower than a bottom of a cut portion of each of the tunnel insulating pattern 134 and the blocking pattern 130.

[0183] Fig.34 and 35 are cross-sectional views illustrating stages of a method of manufacturing a vertical semiconductor device according to example embodiments.

[0184] Fig.28 , Fig.29 and Fig.31 The method for manufacturing the vertical semiconductor device shown in FIG. 1 is described. Except for the lower connection structure and the channel, the vertical semiconductor device can be manufactured by the same method as in reference Figures 7 to 24 The process shown is essentially the same process for fabricating each vertical semiconductor device.

[0185] First, execute and reference Figures 7 to 15 The same process as shown is used to form Fig.15 The structure shown.

[0186] refer to Fig.34 , the outer wall of the lower portion of the channel exposed by the first gap 156a may be further etched so that the channel 136a may have a cut portion formed by the first gap 156a. Therefore, the sidewall of the fill pattern 138 may be exposed by the first gap 156a. During the etching process, the insulating layer and the sacrificial layer may be slightly etched. That is, in the etching process, the polysilicon may be selectively etched, while the silicon oxide layer and the silicon nitride layer may be slightly etched. The etching process may include an isotropic etching process. In the etching process, the etching source may use an etching gas or an etching solution.

[0187] refer to Fig.35 , a channel connection layer may be formed to completely fill the first gap 156a. The channel connection layer may be formed to fill the cut portion of the channel 136a, so that the channel 136a may be electrically connected through the channel connection layer.

[0188] In example embodiments, a process for forming a channel connection layer may be performed in-situ or ex-situ with an etching process for a portion of the channel 136 a .

[0189] Thereafter, the channel connection layer formed on the sidewall and bottom of the trench 148 and the first insulating interlayer 146 may be removed to form a lower connection structure 160 filling the first gap 156 a .

[0190] A portion of the lower connection structure 160 contacting the trench 136a may include polysilicon doped with impurities. In example embodiments, the lower connection structure 160 may include polysilicon doped with N-type impurities such as phosphorus, arsenic, or the like.

[0191] Subsequently, by executing the reference Figure 22 to Figure 24 The process shown can produce Fig.28 A vertical semiconductor device with a structure as shown.

[0192] In some example embodiments, reference may be performed Fig.34 The process shown can then be performed with reference to Figures 16 to 24 However, when executing reference Fig.16 In the process shown in FIG. 1 , a channel connection layer may be formed to fill the cut portion of the channel. In this case, a semiconductor device including a semiconductor device having Fig.31 A vertical semiconductor device with a lower connection structure 160 of the shape shown.

[0193] As described above, when a subsequent process is performed after forming the channel connection layer, excessive diffusion of impurities of the channel connection layer into the channel can be reduced.

[0194] Fig.36 and Fig.37 are cross-sectional views and plan views illustrating stages of a method of manufacturing a vertical semiconductor device according to example embodiments.

[0195] Figure 30 to Figure 32 The method for manufacturing the vertical semiconductor device shown in FIG. 1 is described. Except for the lower connection structure and the channel, each vertical semiconductor device can be manufactured by the same method as reference. Figures 7 to 24 The process shown is basically the same as the one shown.

[0196] First, execute and reference Figures 7 to 15 The same process as shown is used to form Fig.15 The structure shown.

[0197] Next, refer to Fig.36 , the outer wall of the lower portion of the channel exposed by the first gap 156 a may be further etched so that the channel 136 b may have a relatively thin thickness at a portion facing the first gap 156 a .

[0198] refer to Fig.37 , a channel connection layer may be formed to completely fill the first gap 156a. The channel connection layer may contact a portion of the channel 136b having a relatively thin thickness. Therefore, the channel 136b may be electrically connected through the channel connection layer.

[0199] Afterwards, you can execute the reference Fig.35 The process shown can then be performed with reference to Figure 22 to Figure 24 In this case, it is possible to manufacture Fig.30 A vertical semiconductor device is shown.

[0200] In some example embodiments, reference may be performed Fig.36 The process shown can then be performed with reference to Figures 16 to 24 In this case, it is possible to manufacture Fig.32 A vertical semiconductor device is shown.

[0201] As is conventional in the art, embodiments can be described and illustrated according to the blocks that perform the described one or more functions. These blocks can be referred to as units or modules, etc., and are physically implemented by analog and / or digital circuits, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hard-wired circuits, etc., and can be optionally driven by firmware and / or software. For example, the circuit can be implemented in one or more semiconductor chips, or implemented on substrate supports such as printed circuit boards. The circuit constituting a block can be implemented by dedicated hardware, or by a processor (for example, one or more programmed microprocessors and associated circuits), or by a combination of dedicated hardware that performs some functions of the block and a processor that performs other functions of the block. Without departing from the scope of the present disclosure, each block of the embodiment can be physically divided into two or more interacting and discrete blocks. Similarly, without departing from the scope of the present disclosure, the blocks of the embodiment can be physically combined into more complex blocks. An aspect of the embodiment can be implemented by instructions stored in a non-transitory storage medium and executed by a processor.

[0202] The above is an illustration of exemplary embodiments and should not be construed as limiting thereof. Although some exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the means-plus-function clause is intended to cover the structures described herein that perform the functions, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is an illustration of various exemplary embodiments and should not be construed as being limited to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

Claims

1. A vertical semiconductor device, comprising: A stack structure comprising insulating layers and gate electrodes that are alternately and repeatedly stacked, the stack structure being spaced apart from an upper surface of a substrate; a channel structure, comprising a charge storage structure and a channel, wherein the channel structure passes through the stacked structure; as well as a lower connection structure formed on the substrate, the lower connection structure being electrically connected to the channel and the substrate, wherein The side wall of the lower connection structure includes a protrusion, and the protrusion is provided at a central portion of the side wall in a vertical direction from the upper surface of the substrate, in: The channel structure includes a plurality of channel structures, and The lower connection structure contacts a surface of the substrate, and the lower connection structure fills a gap between the upper surface of the substrate and the stack structure and a portion between lower portions of the channel structures.

2. The vertical semiconductor device according to claim 1, wherein: The lower connection structure includes a protection pattern and a channel connection pattern having conductivity, and an end portion of the protection pattern corresponds to the one protrusion.

3. The vertical semiconductor device according to claim 2, wherein: The channel connection pattern is conformally formed on an upper surface of the gap, a sidewall of the channel, and a lower surface of the gap, and wherein the protection pattern is disposed between the channel connection pattern formed on the upper surface of the gap and the channel connection pattern formed on the lower surface of the gap.

4. The vertical semiconductor device according to claim 2, wherein: The protection pattern includes a material having an etching rate lower than an etching rate of the channel connection pattern in the same etching process.

5. The vertical semiconductor device according to claim 2, wherein: The channel connection pattern includes polysilicon doped with conductive impurities.

6. The vertical semiconductor device according to claim 5, wherein: The protection pattern includes undoped polysilicon.

7. The vertical semiconductor device according to claim 5, wherein: The protection pattern includes an insulating material or polysilicon doped with non-conductive impurities.

8. The vertical semiconductor device according to claim 2, wherein: The upper and lower surfaces of the protection pattern have inclined surfaces, and the protection pattern has a sharp shape toward an end thereof in the second direction.

9. The vertical semiconductor device according to claim 2, wherein: Seams are included in the protection pattern. 10 . The vertical semiconductor device of claim 1 , further comprising a supporting layer between the lower connection structure and the stacked structure. 11 . The vertical semiconductor device of claim 1 , further comprising an insulating spacer covering sidewalls of the stack structure and the lower connection structure, and a common source pattern contacting the insulating spacer and the substrate and extending in the first direction.

12. The vertical semiconductor device of claim 1, wherein: The channel structure is formed in a channel hole extending through the stack structure to an upper portion of the substrate, and The charge storage structure is formed on an upper sidewall of the channel hole that is higher than the lower connection structure, and the channel contacts the charge storage structure and the lower connection structure and has a cylindrical shape.

13. The vertical semiconductor device according to claim 1, wherein: The channel includes an upper channel and a lower channel which are spaced apart from each other in a vertical direction, and the lower connection structure is electrically connected to the upper channel and the lower channel.

14. The vertical semiconductor device according to claim 1, wherein: The channel includes an upper channel, a lower channel, and a connection portion, wherein the connection portion connects the upper channel and the lower channel, and a width of the connection portion is smaller than a width of each of the upper channel and the lower channel.

15. The vertical semiconductor device of claim 1, further comprising: a circuit pattern formed on a lower substrate; a lower insulating intermediate layer covering the circuit pattern; as well as a lower conductive pattern formed on the lower insulating interlayer, wherein The substrate is disposed on the lower conductive pattern.

16. The vertical semiconductor device according to claim 1, wherein: The upper surface and the lower surface of the one protrusion have inclined surfaces, and the one protrusion has a sharp shape toward an end thereof in the second direction.

17. A vertical semiconductor device comprising: a support layer spaced apart from the upper surface of the substrate; a stacked structure formed on the support layer, the stacked structure comprising insulating layers and gate electrodes stacked alternately and repeatedly; a channel structure, which passes through the stacked structure and the support layer and extends to the upper surface of the substrate, the channel structure comprising a charge storage structure and a channel; as well as a lower connection structure formed on the substrate, the lower connection structure being electrically connected to the channel and the substrate, wherein an end portion of the lower connection structure disposed at a central portion in a vertical direction from the upper surface of the substrate protrudes from an end portion of each of the lower connection structure formed on the bottom of the support layer and the lower connection structure formed on the upper surface of the substrate to form a protrusion, in: The channel structure includes a plurality of channel structures, and The lower connection structure contacts a surface of the substrate, and the lower connection structure fills a gap between the upper surface of the substrate and the stack structure and a portion between lower portions of the channel structures.

18. The vertical semiconductor device according to claim 17, wherein: The lower connection structure includes a channel connection pattern and a protection pattern, and an end portion of the protection pattern corresponds to the one protrusion.

19. A vertical semiconductor device comprising: a stack structure comprising insulating layers and gate electrodes stacked alternately and repeatedly, the stack structure being spaced apart from an upper surface of a substrate; a channel structure, which passes through the stacked structure and extends to the upper surface of the substrate, the channel structure comprising a charge storage structure and a channel; as well as a lower connection structure that contacts the substrate to fill a gap between a surface of the substrate and the stacked structure, and the lower connection structure is electrically connected to the channel and the substrate, wherein The lower connection structure includes a channel connection pattern and a protection pattern, and the protection pattern includes a material whose etching rate is lower than that of the channel connection pattern in the same etching process, and The side wall of the lower connection structure includes a protrusion, and the protrusion is provided at a central portion of the side wall in a vertical direction from the upper surface of the substrate, in: The channel structure includes a plurality of channel structures, and The lower connection structure contacts a surface of the substrate, and the lower connection structure fills a gap between the upper surface of the substrate and the stack structure and a portion between lower portions of the channel structures.

20. The vertical semiconductor device of claim 19, wherein: An end portion of the protection pattern protrudes from an end portion of the channel connection pattern in the lower connection structure to form the one protrusion.

21. The vertical semiconductor device of claim 19, wherein: The channel connection pattern is conformally formed on an upper surface of the gap, a sidewall of the channel, and a lower surface of the gap, and wherein the protection pattern is interposed between the channel connection pattern formed on the upper surface of the gap and the channel connection pattern formed on the lower surface of the gap.

22. The vertical semiconductor device of claim 19, wherein: Seams are included in the protection pattern.

23. The vertical semiconductor device of claim 19, wherein: The protection pattern includes undoped polysilicon.

24. The vertical semiconductor device of claim 19, wherein: The channel includes an upper channel and a lower channel which are spaced apart from each other in a vertical direction, and the lower connection structure is electrically connected to the upper channel and the lower channel.

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