semiconductor devices

Abstract

This application relates to semiconductor devices. In order to reduce the on-resistance while suppressing the increase in characteristic variation of a vertical MOSFET with a superjunction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions arranged at predetermined intervals in the n-type drift region below the p-type base region, a plurality of trenches with the bottom surface reaching a deeper position than the p-type base region and arranged between adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed in the p-type base region on the side of the gate electrodes.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2019-120692, filed on June 28, 2019, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a semiconductor device including a vertical MOSFET (vertical metal-oxide-semiconductor field-effect transistor) with a trench gate, and more particularly to an efficient technique for a semiconductor device including a so-called superjunction structure (hereinafter referred to as the SJ structure) having a p-type column region formed such that it protrudes from the bottom of the p-type base region toward the n-type drift region. Background Technology

[0004] A semiconductor device having an SJ structure includes, for example: a semiconductor substrate including an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions coupled to the p-type base region and arranged at predetermined intervals in the n-type drift region, a gate electrode arranged between adjacent p-type column regions and formed in a trench reaching the bottom surface of the p-type base region, and an n-type source region formed in the p-type base region on the side of the gate electrode.

[0005] An example of a semiconductor device having this SJ structure is described in Japanese Unexamined Patent Application Publication No. 2017-168501 (Patent Document 1). In the same document, a vertical MOSFET is disclosed having a plurality of p-type column regions formed in a strip shape, and a strip gate electrode arranged in a plan view between adjacent p-type column regions. Summary of the Invention

[0006] The inventors of this application discovered the following problem when attempting to further reduce the on-resistance of vertical MOSFETs, including those with SJ structures.

[0007] When the on-resistance of the vertical MOSFET with the so-called SJ structure described in Patent Document 1 is further reduced, it is effective to decrease the spacing of the periodic p-type column regions and increase the concentration of the n-type drift region or p-type column region. However, the breakdown voltage and standard on-resistance of the vertical MOSFET become more sensitive to changes in the size of the p-type column region and the n-type drift region, thus leading to an increase in the characteristic variation of the vertical MOSFET.

[0008] Other issues and novel features will become apparent from the description in the specification and drawings.

[0009] The semiconductor device according to an embodiment of the present disclosure includes: a semiconductor substrate including an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions arranged at predetermined intervals in the n-type drift region at a lower portion of the base region, a plurality of trenches with the bottom surface reaching a deeper position than the p-type base region and arranged between adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches through a gate insulating film, and an n-type source region formed in the p-type base region on the side of the gate electrodes.

[0010] By using the semiconductor device according to the embodiment, the on-resistance can be reduced while suppressing the increase in characteristic variation of the vertical MOSFET including the SJ structure. Attached Figure Description

[0011] Figure 1 This is a plan view of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0012] Figure 2 It is by Figure 1 The enlarged plan view of the unit region shown by the dashed line in the figure.

[0013] Figure 3 yes Figure 2 A cross-sectional view of the main part of the unit cell UC in the diagram.

[0014] Figure 4 This is an enlarged plan view of a cell region of a comparative example of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0015] Figure 5 yes Figure 4 A cross-sectional view of the main part of the unit cell UC in the diagram.

[0016] Figure 6 This is a graph showing the relationship between the breakdown voltage BVdss and the standard on-resistance Rsp of a vertical MOSFET according to embodiments and comparative examples.

[0017] Figure 7 This is an enlarged plan view of a cell region of a first modified example of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0018] Figure 8 yes Figure 7 A cross-sectional view of the main part of the unit cell UC in the diagram.

[0019] Figure 9 This is an enlarged plan view of a cell region of a second modified example of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0020] Figure 10 yes Figure 9 A cross-sectional view of the main part of the unit cell UC in the diagram.

[0021] Figure 11 This is an enlarged plan view of a cell region of a third modified example of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0022] Figure 12 yes Figure 11 A cross-sectional view of the main part of the unit cell UC in the diagram.

[0023] Figure 13 This is a cross-sectional view showing the main parts of the manufacturing process of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0024] Figure 14 It shows Figure 13 A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0025] Figure 15 It shows Figure 14 A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0026] Figure 16 It shows Figure 15 A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0027] Figure 17 It shows Figure 16 A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0028] Figure 18 It shows Figure 17 A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0029] Figure 19 It shows Figure 18 A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0030] Figure 20 It shows Figure 19 A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0031] Figure 21 It shows Figure 20A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0032] Figure 22 It shows Figure 21 A cross-sectional view of the main parts of the manufacturing process for a semiconductor device with a vertical MOSFET structure.

[0033] Figure 23 This is an enlarged plan view of a cell region of a fourth modified example of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0034] Figure 24 This is an enlarged plan view of a cell region of a fifth modified example of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0035] Figure 25 This is an enlarged plan view of a cell region of a sixth modified example of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0036] Figure 26 This is an enlarged plan view of a cell region of a seventh modified example of a semiconductor device having a vertical MOSFET structure according to an embodiment.

[0037] Figure 27 This is an enlarged plan view of a cell region of an eighth modified example of a semiconductor device having a vertical MOSFET structure according to an embodiment. Detailed Implementation

[0038] Referring to the accompanying drawings, a semiconductor device according to an embodiment will be described in detail. In the specification and drawings, identical or corresponding structural elements are designated by the same reference numerals, and repeated descriptions thereof are omitted. Furthermore, at least some embodiments and each modification can be arbitrarily combined with each other. Additionally, in each cross-sectional view, diagonal lines indicating that the space is not a cavity may be omitted to make the drawings easier to read. If a cavity is indicated, it should be separately specified as a cavity in the specification.

[0039] The symbols “-” and “+” indicate the relative density of n- or p-type impurities. For example, in the case of n-type impurities, the impurity density is ranked in the order of lowest “n--”, “n-”, “n”, “n+” and highest “n++”.

[0040] (First Embodiment) will refer to Figures 1 to 3 To describe the semiconductor device according to this embodiment. For example... Figure 1As shown, a semiconductor device with a vertical MOSFET has a gate pad 101 and a source pad 102 on the main surface of a semiconductor substrate 100. Reference numeral 103 schematically shows the cell region of the vertical MOSFET located below the source pad 102.

[0041] Figure 2 It is by Figure 1 The image shows an enlarged plan view of the unit region 103, indicated by the dashed lines. Multiple p-type column regions 104 and multiple trench gates (i.e., gate electrodes) 105 are arranged in parallel along the Y direction. In this embodiment, the spacing Pcol of the p-type column regions 104 and the spacing Ptr of the trench gates 105 are respectively set at certain intervals, and preferably, the spacing Pcol is twice the spacing Ptr. Furthermore, assuming the width of the trench gate 105 in the X direction is Wtr, the unit cell UC is designed such that when along the lines connecting adjacent p-type column regions 104, there is always an overlap with the trench gate 105 by more than twice the width Wtr.

[0042] like Figure 3 As shown, the p-type base region 106 and the p+ type base contact region 107 are repeatedly formed parallel to each other in the X direction at a distance from Ptr between adjacent trench gates 105.

[0043] Figure 3 yes Figure 2 A cross-sectional view of AA. Each unit cell UC of the vertical MOSFET includes: an n-type drift region 108 formed by an n-type epitaxial layer in the semiconductor substrate 100, an n+-type drain region 109 formed by an n+-type semiconductor layer with high impurity concentration at the bottom of the n-type drift region 108, and a drain electrode 110 electrically coupled to the bottom of the n+-type drain region 109.

[0044] In the p-type base region 106, an n+ type source region 111 formed of an n+ type semiconductor layer with a high impurity concentration is formed. In the Z direction, which is the thickness direction of the semiconductor substrate 100, the n+ source region 111 is formed shallower than the p-type base region 106, and the p-type column region 104 is formed deeper than the p-type base region 106. Between adjacent p-type column regions 104, a trench gate 105 is formed to fill two trenches formed by etching the surface of the n-drift region 108. A gate insulating film 112 is formed at the interface between the n-drift region 108 and the trench gate 105. An insulating film 113 is formed on the upper surface of the n-drift region 108 to cover the trench gate 105 and the n+ type source region 111, and a source electrode 114 is formed on the upper surface of the insulating film 113.

[0045] The source electrode 114 is formed between adjacent trench gates 105 that are deeper than the n+ type source region 111 and shallower than the p-type base region 106 through a strip-shaped contact hole CH1 formed in the insulating film 113, and is coupled to the p+ type base contact region 107. Furthermore, the source electrode 114 is coupled to the p+ type base contact region 107 formed on the p-type column region 104 through a strip-shaped contact hole CH2 formed in the insulating film 113.

[0046] To compare the configuration of the vertical MOSFET according to the first embodiment described above, Figure 4 and Figure 5 It shows the relationship with Figure 2 and Figure 3 The comparison example of the vertical MOSFET shown is illustrated. Incidentally, Figure 5 yes Figure 4 BB cross-section diagram. Figure 4 and Figure 5 The vertical MOSFET shown is configured such that the p-type column regions 104 are always arranged between adjacent trench gates 105. That is, between adjacent p-type column regions 104, only one strip trench gate 105 is arranged in the plan view in this configuration.

[0047] On the other hand, according to the first embodiment, the vertical MOSFET and Figure 4 and Figure 5 Compared to the comparative example, a wider current path can be ensured by reducing the occupancy of the p-type column region 104 per unit cell UC in the planar diagram. Furthermore, even when the repetition interval Ptr of the trench gate 105 is reduced to increase gate density, the on-resistance can be reduced without requiring excessively high impurity concentrations in the p-type column region and drift region, as the repetition interval Pcol of the p-type column region and drift region (also known as the n-type column region) can ensure a distance twice that of the interval Ptr.

[0048] Figure 6 The relationship between the charge imbalance rate (the balance of charge in the p-type and n-type column regions) and the breakdown voltage BVdss and the standard on-resistance Rsp is shown when the charge in the p-type and n-type column regions are equal, thus obtaining the maximum breakdown voltage of the vertical MOSFET.

[0049] exist Figure 4 and Figure 5 In the vertical MOSFET of the comparative example shown, it is necessary to reduce Pcol / Ptr, and the p-type and n-type column regions need to be highly concentrated to reduce the standard on-resistance Rsp, while maintaining a charge imbalance margin that meets or exceeds a certain breakdown voltage. Therefore, the problem arises where the breakdown voltage and standard on-resistance Rsp become more sensitive to the charge imbalance rate.

[0050] On the other hand, the vertical MOSFET structure of the first embodiment can significantly reduce the standard on-resistance Rsp without increasing the breakdown voltage BVdss and the sensitivity of the standard on-resistance Rsp to the charge imbalance rate. Therefore, the vertical MOSFET structure not only improves basic performance but also better resists manufacturing variations, thereby increasing product yield.

[0051] (First Modification Example) Figure 7 and Figure 8 A first modified example of the first embodiment is shown. Compared to the first embodiment, the change in the first modified example is that the repeating interval of the trench gate 105 has two types of intervals, Ptr1 and Ptr2, and if the repeating interval of the p-type column region 104 and the trench gate 105 is Pcol, then the interval Pcol has a summation relationship between intervals Ptr1 and Ptr2. Incidentally, Figure 8 This is the CC section view in the figure.

[0052] Because the semiconductor device of the first modified example has this relationship, the design flexibility of the unit cell is greater than that of the first embodiment, and the distance between the p-type column region 104 and the trench gate 105 can be increased, so that the influence of the p-type column region 104 on the channel resistance can be suppressed. Furthermore, since the distance between the PN junction of the p-type column region and the n-type column region (i.e., the n-type drift region 108) and the trench gate 105 can be increased, the coupling of the increased electric field amplitude at the lower part of the PN junction and the trench gate 105 can be mitigated, thereby improving the breakdown voltage.

[0053] (Second Modification Example) Figure 9 and Figure 10 A second modified example of the first embodiment is shown. Compared to the first embodiment, the second modified example differs in that a trench gate 105 with a minimum trench width Wtr is formed using a honeycomb structure in the plan view to increase gate density, and p-type column regions 104 are arranged in an interleaved manner in the plan view. Even in this configuration, the relationship between the trench gate 105 and the p-type column regions 104 is designed such that there is always an overlap with more than twice the width Wtr of the trench gate 105, assuming a line connecting adjacent p-type column regions 104. Incidentally, Figure 10 yes Figure 9 DD cross-section diagram.

[0054] exist Figure 10 In this process, a trench gate 105 is formed with a width W in the X direction and a width Wtr in the Y direction between adjacent p-type column regions. The trench gate 105 is designed such that the width W is more than twice the width Wtr.

[0055] Compared to the first embodiment, the second modified example has a higher density of trench gates 105 in a single cell UC. Therefore, since the channel density can be increased, the on-resistance of the vertical MOSFET can be reduced. Furthermore, even with the design resulting in a high trench gate density, a wide current path can be ensured because the occupancy of the p-type column region per cell in the planar view can be reduced. Therefore, the on-resistance can be reduced without excessively increasing the impurity concentration in the p-type column region and the n-type drift region.

[0056] (Third Modification Example) Figure 11 and Figure 12 A third modified example of the first embodiment is shown. Compared to the first embodiment, the third modified example differs in that the trench gate 105 with a minimum trench width Wtr is formed in a grid structure in the plan view to increase gate density, and the p-type column regions 104 are arranged in an interleaved manner in the plan view. Even in this configuration, the relationship between the trench gate 105 and the p-type column regions 104 is designed such that there is always an overlap with more than twice the width Wtr of the trench gate 105, assuming a line connecting adjacent p-type column regions 104. Figure 12 yes Figure 11 EE cross-section diagram.

[0057] exist Figure 12 In this process, a trench gate 105 is formed with a width W in the X direction and a width Wtr in the Y direction between adjacent p-type column regions. The trench gate 105 is designed such that the width W is more than twice the width Wtr.

[0058] In the configuration of the third modified example, the density of the trench gate 105 in the unit cell UC is higher than that in the first embodiment. Therefore, since the trench density can be increased, the on-resistance of the vertical MOSFET can be reduced. Furthermore, even with a high trench gate density, a wide current path can be ensured because the occupancy of the p-type column region in the unit cell can be reduced in the planar view. Therefore, the on-resistance can be reduced without excessively increasing the impurity concentration in the p-type column region and the n-type drift region.

[0059] The following describes a method for manufacturing a semiconductor device including a vertical MOSFET according to an embodiment of the present invention.

[0060] like Figure 13 As shown, for example, a semiconductor substrate 100 having an epitaxial layer EP is prepared on a silicon substrate SB that includes a crystal plane (100) of an n-type high-concentration semiconductor layer.

[0061] Next, as Figure 14As shown, a hard mask HM1, consisting of a photoresist film 11 and an insulating film 10, is formed on the upper surface of the epitaxial layer EP.

[0062] Next, as Figure 15 As shown, the upper surface of the epitaxial layer EP exposed from the hard mask HM1 is etched to form a trench 12 for the trench gate.

[0063] Next, after removing the hard mask HM1, as... Figure 16 As shown, after the trench 12 is filled with the insulating film 13, insulating films 14, 15, and 16 are sequentially formed on the upper surface of the epitaxial layer EP. For example, silicon oxide films formed by a CVD method are used as insulating films 14 and 16. Silicon nitride films formed by a CVD method are used as insulating film 15.

[0064] Next, as Figure 17 As shown, a hard mask HM2, consisting of a photoresist film 17 and an insulating film 16, is formed using conventional photolithography and etching techniques. The hard mask HM2 is then used as a mask to introduce impurities, for example, implanting p-type impurity ions, such as boron, into the epitaxial layer EP to form p-type column regions 104.

[0065] Next, after removing the hard mask HM2, insulating film 15, and insulating film 14, as follows Figure 18 As shown, for example, a gate insulating film 112 is formed on the surface of the epitaxial layer EP, including the surface of the trench 12, by a thermal oxidation process.

[0066] Next, as Figure 19 As shown, a trench gate 105 is formed to embed in a trench 12. The trench gate 105 is formed, for example, from a polysilicon film doped with n-type impurities, and is selectively formed in the trench 12 by depositing the polysilicon film on the entire surface of the semiconductor substrate 100 and then etching back by chemical-mechanical polishing (i.e., CMP).

[0067] Next, as Figure 20 As shown, p-type impurities, such as boron, are selectively ion-implanted into the epitaxial layer EP to form a p-type base region 106. The p-type base region 106 is formed between adjacent trench gates 105 and is coupled to a p-type column region 104, and is also formed at a location shallower than the bottom surface of the trench gates 105.

[0068] Next, as Figure 21 As shown, an n-type impurity, such as arsenic, is selectively ion-implanted into the epitaxial layer EP to form an n+ source region 111. The n+ source region 111 is formed on the surface of the p-type base region 106 and is located at the end of the trench gate 105.

[0069] Next, an insulating film 113 is formed on the entire surface of the semiconductor substrate 100. Then, the insulating film 113 is patterned using a photoresist film 18 via conventional photolithography and etching techniques to form contact holes CH1 and CH2 within the insulating film 113. Contact holes CH1 and CH2 are formed between adjacent trench gates 105 and on the p-type column region 104, respectively. Furthermore, the bottom surfaces of contact holes CH1 and CH2 are formed to reach the p-type base region 106 by partially etching the surface of the epitaxial layer EP.

[0070] Next, by ion implantation of p-type impurities using photoresist film 18 and insulating film 113 as masks, a p+ type base contact region 107 is formed in the p-type base region 106 exposed from contact holes CH1 and CH2. Then, after removing the photoresist film 18, as... Figure 22 As shown, a source electrode 114 containing, for example, aluminum as the main component is formed, and a drain electrode 110 having a multilayer structure made of, for example, Au / Cu / Ni is formed on the lower surface of the semiconductor substrate 100, thereby completing the vertical MOSFET.

[0071] Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from its essential points.

[0072] For example, while the present invention has shown an n-trench vertical MOSFET, the present invention can also be applied to a p-trench vertical MOSFET. In this case, the source region, drain region, base region (also called the channel formation region), and conductivity type of the semiconductor layer constituting the drift region can be reversed.

[0073] also, Figure 2 and Figure 7 The bar-shaped p-type column area 104 shown can be in the form of... Figures 23 to 26 The diagram shows an n-type drift zone arranged in an interlaced or grid-like pattern in a plan view. Figures 23 to 26 This is a plan view showing the semiconductor device in the fourth to eighth modified examples.

[0074] In this case, such as Figures 23 to 26 As shown, the occupancy rate of p-type column area 104 in the plan view is... Figure 23 and Figure 25 The staggered arrangement shown is the lowest, and its impact on reducing on-resistance is higher due to the increased width of the current path. Furthermore, even in... Figure 24 and Figure 26 In the case of the square grid arrangement shown, since the width of the current path is greater than... Figure 2 and Figure 7The strip arrangement shown in the figure has a significant impact on reducing on-resistance.

[0075] On the other hand, since the depletion relief required to obtain a high breakdown voltage is more preferably achieved by a short distance between the p-type column regions and the uniform relationship of the PN junction formed by the p-type column regions and the n-type column regions (n-type drift regions), it becomes the opposite of the relief of reduced on-resistance, and is suitable for high breakdown voltage in the order of strip arrangement, square grid arrangement and staggered arrangement.

[0076] like Figure 27 As shown, the p-type column region 104 cannot be directly coupled to the bottom surface of the p-type base region 106. In this case, although the p-type column region 104 becomes a state where the p-type column region 104 is surrounded by the n-type drift region 108 and subsequently the potential floats, the thickness T1 of the n-type region between the p-type base region 106 and the p-type column region 104 can be set to a thickness sufficient to suppress the supporting barrier of the hole from the p-type base region 106 to the p-type column region 104. During actual operation of the vertical MOSFET, as a preferred value, the thickness T1 of the n-type region between the p-type base region 106 and the p-type column region 104 can be set to, for example, about 0.5 μm.

[0077] This configuration can help improve the breakdown voltage of the vertical MOSFET because it can be compared to... Figure 3 The structure shown optimizes the distribution of the depletion layer.

Claims

1. A semiconductor device including a vertical MOSFET, the vertical MOSFET comprising: a semiconductor substrate having a drift region of a semiconductor layer of a first conductivity type; a base region of a semiconductor layer of a second conductivity type opposite to the first conductivity type, the base region being formed on a surface of the drift region; a plurality of column regions of the semiconductor layer of the second conductivity type, the plurality of column regions being arranged in the drift region at a predetermined interval; a plurality of trenches formed in the drift region, the plurality of trenches each having a bottom surface deeper than the base region, the plurality of trenches including a first trench and a second trench, the first trench and the second trench each being disposed between two adjacent column regions of the plurality of column regions in a plan view such that: i) the first trench and the second trench are parallel to the two adjacent column regions; and ii) the first trench and the second trench are disposed between the two adjacent column regions in the plan view but do not overlap the two adjacent column regions; a plurality of gate electrodes formed so as to be embedded in the plurality of trenches through a gate insulating layer formed on each surface of the plurality of trenches; and a plurality of source regions of the semiconductor layer of the first conductivity type formed in the base region, the plurality of source regions being formed on each side of the plurality of gate electrodes, wherein the plurality of gate electrodes includes two gate electrodes, wherein the two gate electrodes are disposed adjacent to each other in the plan view without any column region being disposed therebetween, wherein the plurality of column regions and the plurality of gate electrodes are arranged in a strip shape in a first direction in the plan view, and wherein the plurality of column regions are separated from a bottom surface of the base region by a predetermined distance in a thickness direction of the semiconductor substrate, the thickness direction being perpendicular to the first direction.

2. The semiconductor device according to claim 1, wherein a bottom surface of the plurality of column regions is located at a position deeper in the drift region than the bottom surface of the plurality of trenches.

3. The semiconductor device according to claim 1, wherein an interval of the adjacent plurality of column regions is set to be more than twice an interval of the adjacent plurality of gate electrodes.

4. A semiconductor device comprising: a semiconductor substrate having a drift region of a semiconductor layer of a first conductivity type; a base region of a semiconductor layer of a second conductivity type opposite to the first conductivity type, the base region being formed on a surface of the drift region; a plurality of column regions of the semiconductor layer of the second conductivity type, the plurality of column regions being arranged in the drift region at a predetermined interval; a plurality of trenches, a bottom surface of the plurality of trenches reaching a position deeper than the base region, the plurality of trenches including a first trench and a second trench, the first trench and the second trench each being disposed between two adjacent column regions of the plurality of column regions in a plan view such that: i) the first trench and the second trench are parallel to the two adjacent column regions; and ii) the first trench and the second trench are disposed between the two adjacent column regions in the plan view but do not overlap the two adjacent column regions. ​ ​ ​ a plurality of gate electrodes formed so as to be embedded in the plurality of trenches by a gate insulating layer formed on each surface of the plurality of trenches; and a plurality of source regions of the semiconductor layer of the first conductivity type formed in the base region, the plurality of source regions formed on each side of the plurality of gate electrodes, wherein the plurality of gate electrodes are arranged in a strip shape along a first direction in a plan view, and wherein the plurality of column regions are arranged in a staggered shape along the first direction in a plan view, wherein the plurality of gate electrodes include two gate electrodes, wherein the two gate electrodes are disposed adjacent to each other without any column region disposed therebetween in a plan view, wherein the plurality of column regions and the plurality of gate electrodes are arranged in a strip shape along a first direction in a plan view, and wherein the plurality of column regions are spaced apart from a bottom surface of the base region by a predetermined distance in a thickness direction of the semiconductor substrate, the thickness direction being perpendicular to the first direction.

5. The semiconductor device according to claim 4, wherein bottom surfaces of the plurality of column regions arranged in the staggered shape are located at a position deeper than the bottom surfaces of the plurality of trenches in the drift region.

6. A semiconductor device comprising: a semiconductor substrate having a drift region of a semiconductor layer of a first conductivity type; a base region of a semiconductor layer of a second conductivity type opposite to the first conductivity type, the base region formed on a surface of the drift region; a plurality of column regions of the semiconductor layer of the second conductivity type, the plurality of column regions arranged at a predetermined interval in the drift region; a plurality of trenches, bottom surfaces of the plurality of trenches reaching a position deeper than the base region, the plurality of trenches including a first trench and a second trench, the first trench and the second trench each disposed between two adjacent column regions of the plurality of column regions in a plan view such that: i) the first trench and the second trench are parallel to the two adjacent column regions; and ii) the first trench and the second trench are disposed between the two adjacent column regions in the plan view without overlapping the two adjacent column regions; a plurality of gate electrodes formed so as to be embedded in the plurality of trenches by a gate insulating layer formed on each surface of the plurality of trenches; and a plurality of source regions of the semiconductor layer of the first conductivity type formed in the base region, the plurality of source regions formed on each side of the plurality of gate electrodes, wherein the plurality of gate electrodes are arranged in a strip shape along a first direction in a plan view, and wherein the plurality of column regions are arranged in a grid shape along the first direction in a plan view, wherein the plurality of gate electrodes include two gate electrodes, wherein the two gate electrodes are disposed adjacent to each other without any column region disposed therebetween in a plan view, wherein the plurality of column regions and the plurality of gate electrodes are arranged in a strip shape along a first direction in a plan view, and wherein the plurality of column regions are spaced apart from a bottom surface of the base region by a predetermined distance in a thickness direction of the semiconductor substrate, the thickness direction being perpendicular to the first direction. ​ 7. The semiconductor device of claim 6, wherein a bottom surface of the plurality of column regions arranged in the grid shape is located at a deeper position in the drift region than the bottom surface of the plurality of trenches.

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