Electronic device comprising an electronic module

Abstract

An electronic device is provided. The electronic device includes an electronic module, outputting and / or receiving light, and an electronic panel divided into a first area overlapping the electronic module, a second area surrounding at least a portion of the first area, and a third area adjacent to the second area. The electronic panel includes a base substrate, a plurality of pixels disposed on the base substrate and displaying an image in the second area, an encapsulation layer disposed on the base substrate and covering the plurality of pixels, and a boundary pattern located in the first area. The boundary pattern has an undercut shape.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0081486, filed on July 5, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to an electronic device, and more specifically, to an electronic device including an electronic module and a method of manufacturing the same. Background Technology

[0003] An electronic device may include a display unit for displaying an image and a sensing unit for detecting external input. The display unit may be an organic light-emitting diode (OLED) display panel, which has lower power consumption, higher brightness, and faster response time than some other types of display panels.

[0004] Electronic devices may include electronic modules that receive external signals and / or externally provide output signals. A housing encloses the electronic modules along with a display panel to constitute an electronic device. Summary of the Invention

[0005] An electronic device includes an electronic module for outputting and / or receiving light. The electronic device also includes an electronic panel, which, when viewed in a plane, is divided into a first region superimposed on the electronic module, a second region surrounding at least a portion of the first region, and a third region adjacent to the second region. The electronic panel includes: a substrate; a plurality of pixels disposed on the substrate and displaying an image in the second region; an encapsulation layer disposed on the substrate and covering the plurality of pixels; and a boundary pattern disposed in the first region. When viewed in cross-section, the boundary pattern has an undercut shape.

[0006] In some embodiments, the first region may include a central region and a patterned region that at least partially surrounds the central region. A boundary pattern may be separated from the central region and may be positioned along the patterned region.

[0007] In some embodiments, the boundary pattern may have a closed line shape that at least partially surrounds the central region.

[0008] In some embodiments, the encapsulation layer may include a first inorganic layer, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer. The first inorganic layer may not be superimposed on the central region.

[0009] In some embodiments, the second inorganic layer may be at least partially superimposed on the central region.

[0010] In some embodiments, the second inorganic layer may have a higher visible light transmittance than the first inorganic layer.

[0011] In some embodiments, the electronic device may further include a window disposed on the encapsulation layer and an anti-reflective layer disposed between the window and the electronic panel. The anti-reflective layer may include an aperture corresponding to a central region. The aperture may have a visible light transmittance greater than that of any other portion of the anti-reflective layer.

[0012] In some embodiments, the aperture may have a smaller degree of polarization than any other part of the antireflective layer.

[0013] In some embodiments, the hole can penetrate the anti-reflective layer.

[0014] In some embodiments, the electronic device may further include a sensing unit disposed on the encapsulation layer. The sensing unit may include a plurality of conductive patterns and a plurality of sensing insulating layers disposed between the plurality of conductive patterns. When viewed in a plane, the sensing insulating layers may at least partially overlap with the central region.

[0015] In some embodiments, the electronic device may further include a planarization pattern disposed below the sensing unit. When viewed in a plane, the planarization pattern may at least partially overlap with the central region.

[0016] In some embodiments, the boundary pattern may include a first, second, and third layer stacked sequentially. When viewed in cross-section, the side surface of the third layer may protrude from the side surface of the second layer.

[0017] In some embodiments, the third layer may include a material different from that of the second layer.

[0018] In some embodiments, the boundary pattern may be conductive.

[0019] In some embodiments, each of the plurality of pixels may include a light-emitting element disposed in the second region. A thin-film transistor may be connected to the light-emitting element. The boundary pattern may be disposed on the same layer as the control electrode, input electrode, and / or output electrode of the thin-film transistor.

[0020] An electronic device includes an electronic module and an electronic panel. In a plan view, the electronic panel is divided into a high-transmittance region at least partially superimposed on the electronic module and an effective region at least partially surrounding the high-transmittance region. The high-transmittance region includes a central region separated from the effective region. The electronic panel includes: a plurality of pixels providing light to the effective region; a boundary pattern disposed in the high-transmittance region, which, in the plan view, is separated from and surrounds the central region; and an encapsulation layer at least partially covering the plurality of pixels, the encapsulation layer including a first inorganic layer, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer, the second inorganic layer having a visible light transmittance greater than that of the first inorganic layer. In a plan view, the first inorganic layer may be separated from the central region.

[0021] In some embodiments, each of the plurality of pixels may include a light-emitting element disposed in an effective region and a thin-film transistor connected to the light-emitting element. The boundary pattern may be disposed on the same layer as the input electrode, output electrode, and / or control electrode of the thin-film transistor. The boundary pattern may include the same material as the input electrode, output electrode, and / or control electrode.

[0022] In some embodiments, the boundary pattern may have an undercut shape when viewed in cross-section.

[0023] In some embodiments, when in a planar view, the boundary pattern may have a closed line shape that at least partially surrounds the central region.

[0024] In some embodiments, in a plan view, the second inorganic layer may be at least partially superimposed on the central region.

[0025] A method of manufacturing an electronic device includes forming a boundary pattern and a plurality of pixels on a substrate. A first inorganic layer is formed covering the plurality of pixels and the boundary pattern. A cleaning solution is provided to clean the first inorganic layer. An organic layer and a second inorganic layer are formed on the first inorganic layer. The step of cleaning the first inorganic layer includes peeling a portion of the first inorganic layer from the boundary pattern.

[0026] In some embodiments, the first inorganic layer may have a lower visible light transmittance than the second inorganic layer.

[0027] In some embodiments, the boundary pattern may include a first layer, a second layer, and a third layer stacked sequentially. The second layer may be undercut relative to the third layer. Attached Figure Description

[0028] A more complete understanding of the present disclosure and its many accompanying aspects will be readily obtained when considered in conjunction with the accompanying drawings, as the present disclosure becomes better understood by referring to the following detailed description, in which:

[0029] Figure 1A This is an assembly perspective view illustrating some example embodiments of an electronic device according to the concept of the present invention;

[0030] Figure 1B It is shown Figure 1A An exploded perspective view of an electronic device;

[0031] Figure 2 This is a block diagram illustrating some exemplary embodiments of an electronic device according to a concept of the present invention;

[0032] Figure 3A This is a plan view illustrating some example embodiments of a display unit according to a concept of the present invention;

[0033] Figure 3B This is a plan view illustrating a sensing unit according to some exemplary embodiments of the concept of the present invention;

[0034] Figure 4A It shows along Figure 1B A cross-sectional view of the electronic panel taken by line I-I';

[0035] Figures 4B to 4E This is a simplified plan view of an electronic panel that partially illustrates some exemplary embodiments of the concept according to the present invention;

[0036] Figure 5A It is shown Figure 4A An enlarged view of section XX';

[0037] Figure 5B This is an enlarged cross-sectional view of an electronic panel that partially illustrates some exemplary embodiments of the concept according to the present invention;

[0038] Figures 6A to 6E This is a cross-sectional view illustrating a method for forming a boundary pattern according to some exemplary embodiments of the present invention;

[0039] Figure 7 This is an exploded perspective view illustrating some exemplary embodiments of an electronic device according to the concept of the present invention;

[0040] Figure 8A and Figure 8B These are cross-sectional views illustrating some exemplary embodiments of an electronic device according to the concept of the present invention; and

[0041] Figures 9A to 9L This is a cross-sectional view illustrating a method of manufacturing an electronic device according to some example embodiments of the concept of the present invention. Detailed Implementation

[0042] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" or "combined to" another component, that component may be directly disposed on, directly connected to or directly combined with the other component, or there may be at least one intermediate component between them.

[0043] In the specification and accompanying drawings, the same reference numerals may indicate the same or corresponding components. Additionally, in the accompanying drawings, the thickness, proportions, and dimensions of components may be exaggerated to effectively explain the technical content.

[0044] It will be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be named a second component without departing from the scope of the invention, and vice versa. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0045] Additionally, terms such as “below,” “under,” “above,” and “above” are used herein to explain the relationship of one component to other components shown in the accompanying drawings. Relative terms are intended to include different orientations other than those depicted in the drawings.

[0046] It should be understood that the terms “comprising,” “including,” “having,” etc., are used to describe the presence of the stated features, wholes, steps, operations, components, elements, or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, components, elements, or combinations thereof. Conversely, the phrase “consisting of” is intended to exclude the presence or addition of one or more other features, wholes, steps, operations, components, elements, or combinations thereof.

[0047] The inventive concept will now be described below with reference to the accompanying drawings.

[0048] Figure 1A This is an assembly perspective view illustrating some example embodiments of an electronic device according to the concept of the present invention. Figure 1B It is shown Figure 1A An exploded perspective view of an electronic device. Figure 2 This is a block diagram illustrating some exemplary embodiments of an electronic device according to the present invention. Reference will be made below. Figure 1A , Figure 1B and Figure 2 This invention is explained in terms of its concept.

[0049] An electronic device EA can be activated by an electrical signal. The electronic device EA can be implemented in various ways. For example, an electronic device EA may include a tablet computer, a laptop computer, a desktop computer, a smart TV, etc. In this embodiment, a smartphone is shown as an example of an electronic device EA.

[0050] like Figure 1A As shown, the electronic device EA can display an image IM on its front surface FS. The front surface FS can be defined by a plane of a first directional axis DR1 and a second directional axis DR2. The front surface FS includes a transmissive region TA configured to transmit light through it and a border region BZA adjacent to the transmissive region TA. The border region BZA can be configured to block light.

[0051] Electronic device EA displays image IM in transmission region TA. Image IM can be a static image and / or a dynamic image. Figure 1A The image shows a clock and several icons as an example of an IM (Instant Messaging) image.

[0052] The transmission region TA can have a substantially rectangular shape extending along a first directional axis DR1 and a second directional axis DR2. However, this is shown exemplarily, and the shape of the transmission region TA is not limited to a specific embodiment, but can have various shapes.

[0053] The border region BZA is adjacent to the transmission region TA. The border region BZA may at least partially surround the transmission region TA. However, this is shown exemplarily, and the border region BZA may be configured to be adjacent to only one side of the transmission region TA or may be omitted entirely. The electronic device EA according to embodiments of the present invention is not necessarily limited to a specific embodiment, but may include various embodiments.

[0054] The normal direction of the front surface FS can correspond to the thickness direction of the electronic device EA, and the thickness direction can correspond to the third directional axis DR3. In this embodiment, the front and rear surfaces (e.g., top and bottom surfaces) of each component are defined based on the direction along which the displayed image IM is located. The front and rear surfaces are opposite each other on the third directional axis DR3.

[0055] The directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are relative concepts and may represent other directions. The first direction, the second direction, and the third direction are defined herein as referring to the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively, and are assigned the same reference numerals.

[0056] The electronic device EA according to the present invention can sense user input TC externally applied to the electronic device EA. User input TC may include touch, light, heat, pressure, or various other types of input from the user's body. In addition, the electronic device EA can sense not only inputs in contact with the electronic device EA, but also inputs that are adjacent to or adjacent to the electronic device EA.

[0057] In this embodiment, the user's input TC is shown as the user's hand applied to the front surface FS. However, this is shown exemplarily, and the user's input TC can be provided in various types as discussed above. Depending on the structure of the electronic device EA, the electronic device EA can sense the user's input TC applied to its side or rear surface, but the inventive concept is not necessarily limited thereto.

[0058] An electronic device EA may include a window WM, an electronic panel EP, a circuit board DC, an electronic module EM, and a housing HU (e.g., a housing unit). The window WM and the housing HU are combined to define the appearance of the electronic device EA.

[0059] A window WM is disposed on an electronic panel EP and covers the front surface IS of the electronic panel EP. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multi-layer or single-layer structure. For example, the window WM may have a stacked structure in which multiple plastic films are bonded by adhesives or a stacked structure in which a glass substrate is bonded to the plastic films by adhesives.

[0060] The window WM includes the externally exposed front surface FS. The front surface of an electronic device EA may be defined by the front surface FS of the window WM.

[0061] For example, the transmission region TA can be an optically transparent region. The transmission region TA can have a shape corresponding to the shape of the effective region AA. For example, the transmission region TA may overlap the entire surface of the effective region AA or at least a portion of the effective region AA. The image IM displayed in the effective region AA of the electronic panel EP can be viewed through the transmission region TA.

[0062] The border region BZA can be a region where the transmittance of visible light is relatively less than that of the transmission region TA. The border region BZA defines the shape of the transmission region TA. The border region BZA may be adjacent to the transmission region TA and may at least partially surround the transmission region TA.

[0063] The border area BZA can have a certain color. When the window WM is set as a glass substrate or a plastic substrate, the border area BZA is a colored layer printed or deposited on a surface of the glass substrate or plastic substrate. Alternatively, the border area BZA can be formed by coloring a relevant area of ​​the glass substrate or plastic substrate.

[0064] The border region BZA can at least partially cover the peripheral region NAA of the electronic panel EP and can suppress the visibility of the peripheral region NAA. However, this is shown exemplarily, and according to an embodiment of the present invention, the border region BZA can be omitted from the window WM.

[0065] The electronic panel EP can display an image IM and detect user input TC. The electronic panel EP has a front surface IS including an active area AA and a peripheral area NAA. The active area AA can be an area activated according to an electrical signal.

[0066] In this embodiment, the effective region AA can be the region in which the image IM is displayed and the user's input TC is also detected. At least a portion of the transmission region TA overlaps with the effective region AA. Therefore, the user can identify the image IM through the transmission region TA, or the user's input TC can be provided through the transmission region TA. However, this is shown exemplarily. The effective region AA can be configured such that the region displaying the image IM is separated from the region detecting the user's input TC, but the inventive concept is not limited thereto.

[0067] The peripheral region NAA can be the area covered by the border region BZA. The peripheral region NAA is adjacent to the active region AA. The peripheral region NAA can at least partially surround the active region AA. The peripheral region NAA can include drive lines or drive circuitry that drive the active region AA.

[0068] The peripheral area NAA may include pads (or "solder pads"), one or more electronic components, or various signal lines that provide electrical signals to the active area AA. The peripheral area NAA may be covered by the border area BZA and therefore may not be visible.

[0069] In this embodiment, the electronic panel EP is assembled in a flat state where both its effective area AA and peripheral area NAA are positioned toward the window WM. However, this is shown exemplarily, and the peripheral area NAA of the electronic panel EP can be partially bent. In this case, a portion of the peripheral area NAA can be bent toward the rear surface of the electronic device EA, thus reducing the area of ​​the border area BZA on the front surface FS of the electronic device EA. Optionally, the electronic panel EP can be assembled in a state where a portion of the effective area AA is also bent. Optionally, according to embodiments of the present invention, the peripheral area NAA can be omitted from the electronic panel EP.

[0070] Reference Figure 1A , Figure 1B and Figure 2An electronic panel EP may include a display unit DU and a sensing unit SU. The display unit DU may be a component that essentially generates an image IM. The image IM generated from the display unit DU is visible to the user through a transmission area TA.

[0071] The sensing unit SU detects user input TC that has been externally applied. As discussed above, the sensing unit SU can detect user input TC provided to the window WM.

[0072] A high-transmittance region HA (or a first region) can be defined on the electronic panel EP. Compared to the effective region AA (or a second region), the high-transmittance region HA can have a higher transmittance of visible light per unit area. For example, the high-transmittance region HA can have the highest transmittance of visible light at the central portion of its path used as the light received by the electronic module EM. A further detailed description is provided below.

[0073] In a plan view, the high-transmittance region HA is defined as the location where the high-transmittance region HA at least partially overlaps with the electronic module EM, as will be discussed below. The high-transmittance region HA can be an area that at least partially overlaps not only with the light receiving portion or light output portion of the electronic module EM, but also with the main parts constituting the electronic module EM, such as the body or housing.

[0074] The high-transmittance region HA can have various shapes. In this embodiment, although the high-transmittance region HA is shown as having a circular shape for the sake of simplicity, the high-transmittance region HA can have various shapes, such as an elliptical shape, a polygonal shape, or any other shape including curved edges and / or straight edges.

[0075] At least a portion of the high-transmittance region HA can be surrounded by the effective region AA. In this embodiment, the high-transmittance region HA is separated from the peripheral region NAA (or the third region). The high-transmittance region HA is shown as being defined within the effective region AA such that the entire edge of the high-transmittance region HA is surrounded by the effective region AA. According to this embodiment, in the assembled state of the electronic device EA, the high-transmittance region HA can be defined at a position that at least partially overlaps with the transmittance region TA and is separated from the border region BZA.

[0076] The circuit board DC can be connected to the electronic panel EP. The circuit board DC may include a flexible board CF and a main board MB. The flexible board CF may include an insulating film and conductive connecting wires mounted on the insulating film. The conductive connecting wires are coupled to the pad PD and electrically connect the circuit board DC to the electronic panel EP.

[0077] In this embodiment, the flexible board CF can be assembled in a bent state. Therefore, the main board MB can be disposed on the rear surface of the electronic panel EP and can be stably accommodated in the space of the housing HU. In this embodiment, the flexible board CF can be omitted, and in this case, the main board MB can be directly bonded to the electronic panel EP.

[0078] The motherboard MB may include signal lines and electronic components. The electronic components may be integrated with the signal lines for electrical connection to the electronic panel EP. The electronic components generate various electrical signals (such as signals for generating an image IM and / or for detecting user input TC) and / or process the detected signals. The motherboard MB may be configured with multiple components corresponding to the electrical signals generated and processed, but the inventive concept is not limited thereto.

[0079] According to an embodiment of the present invention, for an electronic device EA, a driving circuit that provides an electrical signal to the effective area AA can be directly mounted on the electronic panel EP. In this case, the driving circuit can be mounted as a chip or can be integrated with a pixel (see...). Figure 3A The circuit board DC is formed together with the PX. Therefore, the circuit board DC can have a reduced area or can be omitted. The electronic device EA conceived according to the present invention is not limited to a specific embodiment, but can include various embodiments.

[0080] The electronic module EM is positioned below the window WM. In a plan view, the electronic module EM can be at least partially superimposed on the high-transmission area HA. ​​The electronic module EM can receive user input TC transmitted through the high-transmission area HA or can provide output through the high-transmission area HA. ​​According to the present invention, the electronic module EM can be configured to be at least partially superimposed on the effective area AA, thus preventing an increase in the area of ​​the border area BZA.

[0081] Return to reference Figure 2 The electronic device EA may include an electronic panel EP, a power module PM, a first electronic module EM1, and a second electronic module EM2. The electronic panel EP, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other. Figure 2 An exemplary illustration shows the display unit DU and the sensing unit SU among the components of an electronic panel EP.

[0082] The first electronic module EM1 and the second electronic module EM2 may each include different functional modules to operate the electronic device EA. The first electronic module EM1 may be directly mounted on the motherboard electrically connected to the electronic panel EP, or it may be mounted on a separate board electrically connected to the motherboard via connectors or the like.

[0083] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, a voice input module AIM, a memory MM, and an external interface IF. One or more of the above modules may not be mounted on the motherboard, but may be electrically connected to the motherboard via a flexible circuit board.

[0084] The control module (CM) controls the overall operation of the electronic device (EA). The control module (CM) can be a microprocessor. For example, the control module (CM) can activate or deactivate the electronic panel (EP). Based on touch signals received from the electronic panel (EP), the control module (CM) can control other modules, such as the image input module (IIM) or the voice input module (AIM).

[0085] The wireless communication module TM can communicate wirelessly with other terminals using Bluetooth or WiFi. The wireless communication module TM can use general communication systems to send and receive voice signals. The wireless communication module TM may include a transmitter TM1 that modulates and transmits the signal to be transmitted, and a receiver TM2 that demodulates the received signal.

[0086] The Image Input Module (IIM) processes image signals and converts them into image data that can be displayed on the Electronic Panel (EP). The Audio Input Module (AIM) receives external audio signals via a microphone in recording mode or voice recognition mode and converts the received audio signals into electronic voice data.

[0087] The external interface IF is used as an interface to connect to an external charger, wired / wireless data port, or card (e.g., memory card, SIM / UIM card) socket.

[0088] The second electronic module EM2 may include a sound output module AOM, a light emitting module LM, a light receiving module LRM, and a camera module CMM. These components can be directly mounted on the motherboard, mounted on a separate board and electrically connected to the electronic panel EP via connectors, or electrically connected to the first electronic module EM1.

[0089] The audio output module AOM converts and outputs audio data received from the wireless communication module TM or stored in the memory MM.

[0090] An optical emitting module (LM) generates and outputs light. The LM can output infrared light. For example, the LM may include an LED element. An optical receiving module (LRM) detects the infrared light. The LRM can be activated when infrared light at a certain level or higher is detected. The LRM may include a CMOS sensor. After the infrared light is output from the LM, it can be reflected from external materials (e.g., a user's finger or face), and the LRM can then receive the reflected infrared light. A camera module (CMM) captures external images.

[0091] An electronic module EM according to an embodiment of the present invention may include one or more of a first electronic module EM1 and a second electronic module EM2. For example, the electronic module EM may include one or more of a camera, a speaker, an optical sensor, and a thermal sensor. The electronic module EM can detect external objects received through a high-transmission region HA or can externally provide sound signals such as speech through the high-transmission region HA. Furthermore, the electronic module EM may include multiple components, but the present invention is not limited thereto.

[0092] An electronic module EM superimposed on a high-transmittance region HA can easily identify external objects through the high-transmittance region HA, or the output signal generated from the electronic module EM can be easily transmitted to the outside. An electronic device EA according to an embodiment of the present invention may further include a transparent member disposed between the electronic module EM and the electronic panel EP. The transparent member may be an optically transparent film that allows user input TC transmitted through the high-transmittance region HA to pass through the transparent member and enter the electronic module EM. The transparent member may be attached to the rear surface of the electronic panel EP, or it may be disposed between the electronic panel EP and the electronic module EM without a separate adhesive layer between the electronic panel EP and the electronic module EM. An electronic device EA according to an embodiment of the present invention may have various structures, but the present invention is not limited thereto.

[0093] According to the present invention, in a plan view, the electronic module EM can be assembled to at least partially overlap with the transmission region TA. Therefore, the area of ​​the border region BZA can be prevented from increasing due to accommodating the electronic module EM, resulting in a preferred design.

[0094] Figure 3A A plan view of a display unit illustrating some example embodiments of the concept according to the present invention is shown. Figure 3B A plan view illustrating some example embodiments of a sensing unit according to a concept of the present invention is shown. Reference will be made below. Figure 3A and 3B Describe the concept of the invention. (Refer to...) Figure 1A , Figure 1Band Figure 2 The same components discussed are assigned the same reference numerals, and repeated descriptions will be omitted. It will be understood that, where certain details are not provided, they may be at least similar to those provided elsewhere in the specification for the corresponding elements.

[0095] like Figure 3A As shown, the display unit DU includes a substrate BS, multiple pixels PX, multiple signal lines GL, DL and PL, a power pattern VDD, and multiple display pads DPD.

[0096] The effective region AA and the peripheral region NAA can be regions disposed on the substrate BS. The substrate BS can include an insulating substrate. For example, the substrate BS can be formed of a glass substrate, a plastic substrate, or a combination thereof.

[0097] Optionally, the substrate BS may also include a metal substrate. The substrate BS may be flexible to allow a user to fold the substrate BS, or it may be rigid. According to the present invention, the substrate BS is not necessarily limited to a specific embodiment, but may include various embodiments, as long as the substrate BS is suitably configured to place components such as pixels PX or signal lines GL, DL, and PL thereon.

[0098] Signal lines GL, DL, and PL are connected to pixel PX and transmit electrical signals to pixel PX. The scan line GL, data line DL, and power line PL are exemplarily shown among the signal lines included in the display unit DU. However, this is only shown as an example. Signal lines GL, DL, and PL may also include one or more initialization voltage lines and transmit control lines, but the inventive concept is not limited thereto.

[0099] Pixel PX can be set in the effective area AA. In this embodiment, an example of the signal circuit for one pixel among a plurality of pixels PX is shown. Pixel PX may include a first thin-film transistor TR1, a capacitor CPP, a second thin-film transistor TR2, and a light-emitting element ELD.

[0100] The first thin-film transistor TR1 is connected to the scan line GL and the data line DL. The capacitor CPP is connected to the first thin-film transistor TR1 and the power line PL. The second thin-film transistor TR2 is connected to the first thin-film transistor TR1, the capacitor CPP, and the light-emitting element ELD. The first thin-film transistor TR1, the capacitor CPP, and the second thin-film transistor TR2 can control the operation of the light-emitting element ELD.

[0101] A light-emitting element (ELD) can emit light at a certain amplitude for a specific time period, and this amplitude and time period correspond to the data signal transmitted via a data line (DL). For example, an ELD can include an organic light-emitting device, a quantum dot light-emitting device, an electrophoretic device, or an electrowetting device.

[0102] The light-emitting element ELD is connected to the power terminal VSS and receives a power signal (referred to herein as the second power signal) that is different from the power signal supplied from the power line PL (referred to herein as the first power signal). The light-emitting element ELD can generate light corresponding to the difference between the second power signal and the electrical signal supplied from the second thin-film transistor TR2. However, this is shown exemplarily. Each of the plurality of pixels PX may include electronic components having various constructions and arrangements, but the inventive concept is not necessarily limited thereto.

[0103] Pixel PX is disposed around the high-transmittance region HA. In this embodiment, the boundary between the high-transmittance region HA and the effective region AA can have a closed line shape. In this embodiment, the boundary between the high-transmittance region HA and the effective region AA is exemplarily shown as having a circular shape.

[0104] The power pattern VDD is disposed in the peripheral area NAA. In this embodiment, the power pattern VDD is associated with multiple power lines PL. Because the display unit DU includes the power pattern VDD, the pixel PX can be provided with the same first power signal.

[0105] The display pad (DPD) may include a first pad P1 and a second pad P2. Multiple first pads P1 may be provided, and multiple first pads P1 may be connected to corresponding data lines DL. The second pad P2 may be associated with the power pattern VDD and thus electrically connected to the power line PL. The display unit DU may provide the pixel PX with an electrical signal externally supplied via the display pad DPD. In addition to the first pads P1 and the second pads P2, the display pad DPD may also include other pads for receiving electrical signals, but the inventive concept is not limited thereto.

[0106] Reference Figure 3B The sensing unit SU is shown to have a shape corresponding to the shape of the display unit DU. In this embodiment, the sensing unit SU may be disposed on the display unit DU. However, this is shown exemplarily. The sensing unit SU may be disposed below the display unit DU or embedded in the display unit DU, but the position of the sensing unit SU is not limited to the specific embodiment.

[0107] The sensing unit SU can detect user input (see...) Figure 1AThe sensing unit SU includes multiple first sensing electrodes TE1, multiple second sensing electrodes TE2, multiple lines TL1, TL2 and TL3, and multiple sensing pads T1, T2 and T3 to obtain information about the location or intensity of the external input TC.

[0108] The first sensing electrode TE1 and the second sensing electrode TE2 are disposed in the effective area AA. Based on the change in capacitance between the first sensing electrode TE1 and the second sensing electrode TE2, the sensing unit SU can obtain information about the user's input TC.

[0109] The first sensing electrodes TE1 are arranged along a first direction DR1, and each of the first sensing electrodes TE1 extends along a second direction DR2. Each of the first sensing electrodes TE1 may include a first main pattern SP1, a first adjacent pattern SP1H, and a first connecting pattern CP1.

[0110] A first main pattern SP1 is disposed in the effective area AA. The first main pattern SP1 is separated from the high-transmittance area HA. ​​The first main pattern SP1 has a certain shape and a first area. In this embodiment, the first main pattern SP1 may have a rhomboid shape. However, this is shown exemplarily. The first main pattern SP1 may have various shapes, and its shape is not necessarily limited to the specific embodiment.

[0111] The first adjacent pattern SP1H is configured to be adjacent to the high-transmittance region HA. According to this embodiment, the sensing unit SU can be removed at the portion overlapping with the high-transmittance region HA. The first adjacent pattern SP1H has a second area smaller than the first area of ​​the first main pattern SP1. The first adjacent pattern SP1H can have a shape obtained by removing the portion overlapping with the high-transmittance region HA from a rhombus shape that can be identical to the rhombus shape of the first main pattern SP1.

[0112] In this embodiment, the first connecting pattern CP1 extends along the second direction DR2. The first connecting pattern CP1 is connected to the first main pattern SP1. The first connecting pattern CP1 can be disposed between two first main patterns SP1 and can connect the two first main patterns SP1. Optionally, the first connecting pattern CP1 is disposed between the first main pattern SP1 and the first adjacent pattern SP1H and connects the first main pattern SP1 and the first adjacent pattern SP1H.

[0113] The second sensing electrodes TE2 are arranged along the second direction DR2, and each of the second sensing electrodes TE2 extends along the first direction DR1. Each of the second sensing electrodes TE2 may include a second main pattern SP2, a second adjacent pattern SP2H, and a second connecting pattern CP2.

[0114] The second main pattern SP2 is separated from the high-transmittance region HA. The second main pattern SP2 can also be separated from the first main pattern SP1. In this embodiment, the separation between the first main pattern SP1 and the second main pattern SP2 can be shown in a cross-sectional view. The first main pattern SP1 and the second main pattern SP2 can be electrically insulated from each other, thus allowing for independent transmission and reception of electrical signals.

[0115] In this embodiment, the second main pattern SP2 may have the same shape as the first main pattern SP1. For example, the second main pattern SP2 may have a rhombus shape. However, this is shown exemplarily. The second main pattern SP1 may have various shapes, and its shape is not necessarily limited to the specific embodiment.

[0116] The second adjacent pattern SP2H is positioned adjacent to the high-transmittance region HA. The second adjacent pattern SP2H has a smaller area than the second main pattern SP2. The second adjacent pattern SP2H may have a shape obtained by removing the portion overlapping with the high-transmittance region HA from a rhombus shape that is identical to the rhombus shape of the second main pattern SP2.

[0117] In this embodiment, the second connecting pattern CP2 extends along the first direction DR1. The second connecting pattern CP2 is connected to the second main pattern SP2. The second connecting pattern CP2 is disposed between the two second main patterns SP2 and connects the two second main patterns SP2. Optionally, the second connecting pattern CP2 is disposed between the second main pattern SP2 and the second adjacent pattern SP2H and connects the second main pattern SP2 and the second adjacent pattern SP2H.

[0118] Sensing lines TL1, TL2, and TL3 are disposed in the peripheral area NAA. Sensing lines TL1, TL2, and TL3 may include a first sensing line TL1, a second sensing line TL2, and a third sensing line TL3.

[0119] The first sensing line TL1 is connected to the corresponding first sensing electrode TE1. In this embodiment, the first sensing line TL1 is connected to the lower end of the opposite end of the first sensing electrode TE1.

[0120] The second sensing line TL2 is correspondingly connected to one end of the second sensing electrode TE2. In this embodiment, the second sensing line TL2 is correspondingly connected to the left end of the opposite end of the second sensing electrode TE2.

[0121] The third sensing line TL3 is correspondingly connected to the upper end of the opposite end of the first sensing electrode TE1. According to the present invention, the first sensing electrode TE1 is connected to the corresponding first sensing line TL1 and the corresponding third sensing line TL3. Therefore, for the first sensing electrode TE1, whose length is relatively greater than the length of the second sensing electrode TE2, it is possible to maintain uniform sensitivity. However, this is only shown exemplarily. In embodiments of the present invention, the third sensing line TL3 can be omitted from the sensing unit SU, but the present invention is not limited thereto.

[0122] Sensing pads T1, T2, and T3 are disposed in the peripheral region NAA. Sensing pads T1, T2, and T3 may include a first sensing pad T1, a second sensing pad T2, and a third sensing pad T3. The first sensing pad T1 is connected to a corresponding first sensing line TL1 and provides an external signal to a first sensing electrode TE1. The second sensing pad T2 is connected to a corresponding second sensing line TL2 and is electrically connected to a second sensing electrode TE2, and the third sensing pad T3 is connected to a corresponding third sensing line TL3 and is electrically connected to a first sensing electrode TE1.

[0123] According to the present invention, the high-transmittance region HA is positioned where it is surrounded by the effective region AA. As a result, the area of ​​the border region BZA can be prevented from being affected by the electronic module (see [reference]). Figure 1B The increase is caused by the EM. In addition, since the sensing electrodes TE1 and TE2 or the pixel PX, which are arranged adjacent to the high-transmittance region HA, are electrically connected via the high-transmittance region HA, the display characteristics or sensitivity of the effective area AA can be prevented from being reduced due to the provision of the high-transmittance region HA.

[0124] Figure 4A It shows the following along Figure 1B A cross-sectional view of the electronic panel taken by line I-I'. Figures 4B to 4E A plan view of an electronic panel, partially illustrating some exemplary embodiments of the concept according to the present invention, is shown. Reference will be made below. Figures 4A to 4E Describe the concept of the invention. (Refer to...) Figures 1A to 3B The same components discussed are assigned the same reference numerals, and repeated descriptions will be omitted. It will be understood that, where certain details are not provided, they may be at least similar to those provided elsewhere in the specification for the corresponding elements.

[0125] For the sake of simplicity, Figure 4A Exemplary examples show a substrate BS, a thin-film transistor TR, a light-emitting element ELD, multiple insulating layers 10, 20, 30, 40, 50, 60 and 70, multiple adjacent patterns SP1H and SP2H, a connecting pattern CP2, and hole signal lines HSL1, HSL2 and HSL3 selected from an electronic panel EP.

[0126] The insulating layers 10 to 70 may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, a sixth insulating layer 60, and a seventh insulating layer 70 stacked in sequence. Each of the first insulating layers 10 to the seventh insulating layer 70 may include one or more of organic and inorganic materials, and may have a single-layer or multi-layer structure.

[0127] In this embodiment, the substrate BS can be optically transparent. For example, the substrate BS can have a visible light transmittance equal to or greater than about 90%.

[0128] A first insulating layer 10 is disposed on the substrate BS and at least partially covers the front surface of the substrate BS. The first insulating layer 10 may include one or more of a barrier layer and a buffer layer. Therefore, the first insulating layer 10 can prevent pixels (see...) from... Figure 3A The PX receives oxygen or moisture introduced through the substrate BS, or may have low surface energy to stably form the pixel PX on the substrate BS.

[0129] In this embodiment, the first insulating layer 10 may be optically transparent. For example, the first insulating layer 10 may have a visible light transmittance equal to or greater than about 90%.

[0130] Thin-film transistors (TRs) and light-emitting elements (ELDs) constitute a pixel (see...) Figure 3A (PX). Thin-film transistor TR can correspond to the second thin-film transistor of pixel PX (see PX). Figure 3A TR2).

[0131] The thin-film transistor TR may include a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP is disposed on the first insulating layer 10.

[0132] Semiconductor patterns SP include semiconductor materials. For example, semiconductor patterns SP may include group III elements, group V elements, and compound or oxide semiconductors of group III and group V elements.

[0133] A semiconductor pattern SP can be divided into a channel region CA, an input region IA, and an output region OA that spans the channel region CA and is separated from the input region IA. The channel region CA, the input region IA, and the output region OA are connected to each other to have a single, integrated shape.

[0134] When viewed in a plane, the channel region CA can be a region that at least partially overlaps with the control electrode CE. The input region IA and the output region OA can have a charge mobility relatively greater than that of the channel region CA. Charge in the semiconductor pattern SP can move from the input region IA to the output region OA through the channel region CA.

[0135] A control electrode CE is disposed on a second insulating layer 20. The second insulating layer 20 is disposed on a first insulating layer 10 and covers a semiconductor pattern SP. When viewed in cross-section, the control electrode CE can be separated from the semiconductor pattern SP by crossing the second insulating layer 20. Alternatively, the control electrode CE can be disposed on the first insulating layer 10, and the semiconductor pattern SP can be disposed on the second insulating layer 20.

[0136] The input electrode IE and the output electrode OE are disposed on the third insulating layer 30. The third insulating layer 30 is disposed on the second insulating layer 20 and at least partially covers the control electrode CE.

[0137] The input electrode IE penetrates the second insulating layer 20 and the third insulating layer 30 and is bonded to the input region IA. The output electrode OE is separated from the input electrode IE and is bonded to the output region OA. Each of the input electrode IE and the output electrode OE may include a conductive material. The input electrode IE provides charge to the input region IA, and the output electrode OE transfers the charge that has moved to the output region OA to the light-emitting element ELD.

[0138] According to this embodiment, the input electrode IE and output electrode OE can be omitted from the thin-film transistor TR. For example, the thin-film transistor TR can be formed only by the control electrode CE and the semiconductor pattern SP. In this case, the input region IA and the output region OA can be used as the input electrode IE and the output electrode OE, and the input electrode IE and the output electrode OE can be used as connection electrodes to connect the thin-film transistor TR to other signal lines or other components. According to embodiments of the present invention, the thin-film transistor TR can be arranged in various structures, but the present invention is not limited thereto.

[0139] The light-emitting element (ELD) may include a first electrode E1, a second electrode E2, an emission pattern EMP, and a control layer EL. The first electrode E1 is disposed on a fourth insulating layer 40. The fourth insulating layer 40 is disposed on a third insulating layer 30 and covers the thin-film transistor TR. The first electrode E1 is coupled to the output electrode OE and electrically connected to the thin-film transistor TR.

[0140] The second electrode E2 is disposed on the fifth insulating layer 50 located on the fourth insulating layer 40. The fifth insulating layer 50 may include one or more organic and inorganic materials, and may have a single-layer or multi-layer structure.

[0141] The second electrode E2 can have a region covering the entire surface of at least the effective region AA. Therefore, multiple light-emitting elements (ELDs) can collectively include a single second electrode E2. However, this is shown exemplarily. A second electrode E2 can be provided for each pixel PX, so multiple second electrodes E2 can correspond to multiple first electrodes E1, but the inventive concept is not necessarily limited thereto.

[0142] The fifth insulating layer 50 may have an opening defined to expose at least a portion of the first electrode E1. An emission pattern EMP may be disposed within the opening. The emission pattern EMP may comprise a luminescent material composed of fluorescent or phosphorescent materials. The luminescent material may comprise organic or inorganic luminescent materials, but the inventive concept is not limited thereto.

[0143] A control layer EL is disposed between the first electrode E1 and the second electrode E2. The control layer EL may have a region covering the entire surface of at least the effective region AA. The control layer EL may include organic materials. The control layer EL controls the movement of charge, thus increasing the luminous efficiency and lifetime of the light-emitting element ELD. The control layer EL may include electron transport materials, electron injection materials, hole transport materials, or hole injection materials.

[0144] In this embodiment, the control layer EL is shown as being disposed on the emission pattern EMP, but this configuration is an exemplary embodiment. According to embodiments of the present invention, the control layer EL may be disposed between the emission pattern EMP and the first electrode E1, or multiple control layers may be disposed between the emission pattern EMP and the first electrode E1 and between the emission pattern EMP and the second electrode E2, but the present invention is not limited thereto.

[0145] A sixth insulating layer 60 is disposed on and encapsulates the light-emitting element ELD. In this embodiment, the sixth insulating layer 60 may be an encapsulation layer. The second electrode E2 and the sixth insulating layer 60 may also be configured to have a capping layer covering the second electrode E2 between the second electrode E2 and the sixth insulating layer 60.

[0146] The sixth insulating layer 60 may include a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63 stacked sequentially along the third direction DR3. However, it is not limited thereto, and the sixth insulating layer 60 may also include multiple inorganic layers and multiple organic layers.

[0147] The first inorganic layer 61 may cover the second electrode E2. The first inorganic layer 61 may prevent the light-emitting element (ELD) from receiving external moisture or oxygen. For example, the first inorganic layer 61 may include silicon nitride, silicon oxide, or a mixture including any combination thereof. The first inorganic layer 61 may be formed by a chemical vapor deposition process.

[0148] The first inorganic layer 61 may have a visible light transmittance lower than that of the substrate BS. For example, the first inorganic layer 61 may include silicon nitride (SiN). x The following will discuss its detailed description further.

[0149] An organic layer 62 may be disposed on and in contact with the first inorganic layer 61. The organic layer 62 may provide a flat surface for the first inorganic layer 61. The organic layer 62 covers uneven portions formed on the top surface of the first inorganic layer 61 or particles present on the top surface of the first inorganic layer 61, thus preventing the state of the top surface of the first inorganic layer 61 from affecting the components formed on the organic layer 62. Additionally, the organic layer 62 may alleviate stress between layers in contact with it. The organic layer 62 may comprise an organic material and may be formed by solution processes such as spin coating, slot coating, or inkjet coating.

[0150] A second inorganic layer 63 is disposed on and covers the organic layer 62. Compared to being formed on the first inorganic layer 61, the second inorganic layer 63 can be formed relatively more stably on a flat surface. The second inorganic layer 63 encapsulates moisture and the like released from the organic layer 62 and prevents moisture and the like from moving outward.

[0151] The second inorganic layer 63 may be optically transparent. For example, the second inorganic layer 63 may have a visible light transmittance equal to or greater than about 90%. The second inorganic layer 63 may have a visible light transmittance relatively greater than that of the first inorganic layer 61. The second inorganic layer 63 may include silicon oxide (SiO2). x ) or silicon oxynitride (SiON).

[0152] The second inorganic layer 63 can be formed by chemical vapor deposition. Each of the first inorganic layer 61, the organic layer 62, and the second inorganic layer 63 may include multiple layers, but the inventive concept is not limited thereto.

[0153] In this embodiment, an example is shown in which the sensing unit SU is disposed on the display unit DU. As discussed above, the first adjacent pattern SP1H, the second adjacent pattern SP2H, and the second connecting pattern CP2 may be some of the components included in the sensing unit SU. The sensing unit SU may be composed of the first adjacent pattern SP1H, the second adjacent pattern SP2H, the second connecting pattern CP2, and the seventh insulating layer 70.

[0154] The seventh insulating layer 70 may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73 stacked sequentially. The seventh insulating layer 70 may be configured to at least partially overlap with the effective region AA and the high-transmittance region HA.

[0155] Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may be optically transparent. For example, each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a visible light transmittance equal to or greater than about 90%. Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have an inorganic layer, an organic layer, or a stacked structure of inorganic and / or organic layers.

[0156] In this embodiment, a first adjacent pattern SP1H and a second adjacent pattern SP2H are shown disposed on the same layer, and a second connecting pattern CP2 is disposed on a different layer from the layer on which the second adjacent pattern SP2H is disposed. The second connecting pattern CP2 can be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72. The second adjacent pattern SP2H can penetrate the second sensing insulating layer 72 and can be bonded to the second connecting pattern CP2. The second connecting pattern CP2 connects the second adjacent pattern SP2H to the second main pattern (see...). Figure 3B SP2). Although Figure 4A The first connection pattern is not shown in the diagram (see [reference]). Figure 3B CP1) can be set with a first main pattern set on it (see Figure 3B It is on the same layer as SP1, so it can be directly connected to the first master pattern.

[0157] However, this is illustrated by example. The second connection pattern CP2 can be disposed on the same layer as the layer on which the second adjacent pattern SP2H is disposed, and the first connection pattern CP1 can be disposed on a different layer than the layer on which the first adjacent pattern SP1H is disposed. Optionally, the first sensing electrode (see...) Figure 3B TE1) and the second sensing electrode (see Figure 3B The TE2) can be located on different layers. The sensing unit SU according to embodiments of the present invention can be configured to have various structures, but the present invention is not limited thereto.

[0158] In an embodiment, each of the first adjacent pattern SP1H and the second adjacent pattern SP2H includes multiple grid lines, and Figure 4A A portion of the grid lines is shown. However, this is illustrated by way of example, each of the first adjacent pattern SP1H and the second adjacent pattern SP2H may include a transparent conductive oxide, and in this case, the first adjacent pattern SP1H or the second adjacent pattern SP2H may be configured to have dimensions that overlap with the emission pattern EMP when viewed in a plane.

[0159] The hole signal lines HSL1, HSL2, and HSL3 are positioned within the high-transmittance region HA. The high-transmittance region HA may include the central region HTA, the pattern region PA, and the line region LA.

[0160] The central region HTA can be a region substantially superimposed on the receiving and output portions of the electronic module EM, wherein the receiving portion receives external input and the output portion provides output. For example, when the electronic module EM is a camera module, the central region HTA can be a region at least partially superimposed on a lens of the high-transmittance region HA. The central region HTA can be the region of the high-transmittance region HA with the highest transmittance of visible light. For the sake of simplicity, Figure 4A The receiving and output portions, which are components of the electronic module EM, are shown only as examples. However, it will be understood that other arrangements may be used.

[0161] In an embodiment, in a planar view, the central region HTA can have a circular shape. The patterned region PA can have an annular shape surrounding the central region HTA. The line region LA can have an annular shape surrounding the patterned region PA. However, this is exemplarily shown, and the central region HTA can be designed to have various shapes depending on the shape of the receiving or output portion of the electronic module EM. For example, the central region HTA can be designed to have various shapes such as elliptical, polygonal, and / or any shape with at least one curved edge.

[0162] The via signal lines HSL1, HSL2, and HSL3 are positioned within the line area LA. For simplicity of description, Figure 4A The diagram shows a first hole signal line HSL1, a second hole signal line HSL2, and a third hole signal line HSL3, which correspond to some of the hole signal lines.

[0163] The first hole signal line HSL1 and the second hole signal line HSL2 constitute the display unit DU. The first hole signal line HSL1 is shown as being disposed between the second insulating layer 20 and the third insulating layer 30. The first hole signal line HSL1 can be a scan line connected to a pixel adjacent to the high transmittance region HA. The first hole signal line HSL1 can provide the same scan signal to pixels separated from each other across the high transmittance region HA via the line region LA.

[0164] The second-hole signal line HSL2 is shown disposed between the third insulating layer 30 and the fourth insulating layer 40. The second-hole signal line HSL2 can be a data line connected to a pixel adjacent to the high-transmittance region HA. The second-hole signal line HSL2 electrically connects pixels separated from each other across the high-transmittance region HA via the line region LA.

[0165] The third hole signal line HSL3 is disposed on the sixth insulating layer 60 and constitutes the sensing unit SU. In this embodiment, although the third hole signal line HSL3 is exemplarily shown as being disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, the third hole signal line HSL3 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73.

[0166] The third-hole signal line HSL3 can be a connecting line to a sensing pattern adjacent to the high-transmission region HA. For example, the third-hole signal line HSL3 connects two first adjacent patterns SP1H (or two second adjacent patterns SP2H) that are separated from each other across the high-transmission region HA via the line region LA. Therefore, even when the sensing electrodes TE1 and TE2 cross the high-transmission region HA, problems such as a decrease in sensitivity can be prevented.

[0167] The electronic panel EP may also include at least a pair of recesses GV1 and GV2, a dam DM, and a planarization pattern OCT. The recesses GV1 and GV2, the dam DM, and the planarization pattern OCT are disposed in the high-transmittance region HA.

[0168] Grooves GV1 and GV2 can be disposed in the line region LA of the high-transmittance region HA. Grooves GV1 and GV2 can be formed when at least a portion of the substrate BS is recessed. Grooves GV1 and GV2 are formed to have a depth that does not penetrate the substrate BS. Grooves GV1 and GV2 can include a first groove GV1 and a second groove GV2 that are spaced apart from each other.

[0169] The first groove GV1 can be defined relatively close to or adjacent to the effective region AA, and can be filled with the organic layer 62. The second groove GV2 can be defined relatively close to or adjacent to the central region HTA, can be separated from the organic layer 62, and is sequentially covered by the first inorganic layer 61 and the second inorganic layer 63. Each of the first groove GV1 and the second groove GV2 can have a closed line shape around the central region HTA or a discontinuous line shape around at least a portion of the edge of the central region HTA, but the inventive concept is not limited thereto.

[0170] The first insulating layer 10 may have a cut-out shape on each of the first groove GV1 and the second groove GV2. The control layer EL and the second electrode E2 may be cut on each of the first groove GV1 and the second groove GV2. Because the electronic panel EP also includes grooves GV1 and GV2, according to the present invention, grooves GV1 and GV2 can interrupt the continuity of one or more of the control layer EL and the second electrode E2 that can serve as pathways for external moisture or oxygen, which can prevent damage to components disposed in the effective area AA.

[0171] Each of the first groove GV1 and the second groove GV2 may have an inner side filled with patterns separated from the control layer EL or the second electrode E2, and may be covered by one or more of the first inorganic layer 61 and the second inorganic layer 63. Therefore, when manufacturing the electronic panel EP, it is possible to prevent certain patterns from moving into other components and affecting them. Thus, the electronic panel EP can be manufactured with increased reliability. However, this is only shown exemplarily. For the electronic panel EP according to an embodiment of the inventive concept, grooves GV1 and GV2 may be provided as a single component or may be omitted, but the inventive concept is not necessarily limited thereto.

[0172] The dam DM is positioned in the online region LA to limit the formation area of ​​the organic layer 62 and prevent further expansion of the formation area. The dam DM may be positioned between the first groove GV1 and the second groove GV2. The dam DM is shown as a stacked structure comprising multiple insulating patterns IP1 and IP2. However, this is shown exemplarily, and the dam DM may have, but is not necessarily limited to, a single-layer structure.

[0173] According to this embodiment, the line region LA can be omitted from the high-transmittance region HA. For example, the high-transmittance region HA may only include the central region HTA and the patterned region PA, and the effective region AA may be designed to directly adjoin the patterned region PA. In this case, the first groove GV1 and the second groove GV2, the dam DM, or the hole signal lines HSL1, HSL2, and HSL3 may be omitted. However, this is shown exemplarily. The high-transmittance region HA can be designed to have various shapes, as long as the high-transmittance region HA can include the central region HTA and the patterned region PA, but the inventive concept is not limited to this.

[0174] The planarization pattern OCT comprises an organic material. The planarization pattern OCT can be disposed below the sensing unit SU and within the high-transmittance region HA. The planarization pattern OCT can be at least partially superimposed on the central region HTA of the high-transmittance region HA. The planarization pattern OCT can cover the non-planar surface of the high-transmittance region HA formed by dams DM or grooves GV1 and GV2, thus providing a flat surface to the upper part of the high-transmittance region HA. Therefore, the high-transmittance region HA can stably have a flat surface disposed on the portion where the organic layer 62 is not disposed.

[0175] Planarized patterned OCTs can be optically transparent. For example, a planarized patterned OCT can have a visible light transmittance equal to or greater than about 90%.

[0176] In one embodiment, the first inorganic layer 61 can be removed from the central region HTA. The first inorganic layer 61 may have a lower visible light transmittance than the second inorganic layer 63. According to the present invention, the first inorganic layer 61 may be configured to have a shape that does not overlap with the central region HTA, thus increasing the visible light transmittance of the central region HTA.

[0177] Additionally, according to embodiments of the present invention, the electronic panel EP may also include a boundary pattern HPP. The boundary pattern HPP is disposed along the edge of the central region HTA. The boundary pattern HPP may be disposed within a patterned region PA and may have a shape surrounding the central region HTA. The boundary pattern HPP may define the boundary between the central region HTA and a region adjacent to the central region HTA (e.g., a line region LA).

[0178] For example, such as Figure 4B As shown, when viewed in a plane, the boundary pattern HPP can have a closed-line shape. The boundary pattern HPP has a ring shape that is continuously connected along the edge of the central region HTA, which has a ring shape.

[0179] For example, such as Figure 4C As shown, the boundary pattern HPP1 can have a closed polygonal shape. In this embodiment, the boundary pattern HPP1 has a ring-shaped rectangular shape. The shape of the boundary pattern HPP1 can be designed in various ways along the shape of the central region HTA1.

[0180] For example, such as Figure 4D As shown, when viewed in a plane, the boundary pattern HPP2 can have an open, curved shape. The boundary pattern HPP2 is shown as having a shape that is formed by... Figure 4B The shape shown is obtained by removing a portion of the boundary pattern HPP of the closed line shape.

[0181] For example, such as Figure 4E As shown, the boundary pattern HPP3 can have an intermittently separated shape. The boundary pattern HPP3 can include multiple patterns PT separated from each other. The patterns PT are arranged along the edge of the central region HTA and form the boundary pattern HPP3 with an intermittent shape. In some exemplary embodiments of the present invention, the boundary patterns HPP, HPP1, HPP2, and HPP3 can have various shapes, as long as the boundary patterns HPP, HPP1, HPP2, and HPP3 are arranged in the pattern region PA, and the present invention is not limited thereto.

[0182] Return to reference Figure 4AThe boundary pattern HPP can be optically opaque. Because the boundary pattern HPP is set in the pattern area PA that does not overlap with the central area HTA, it is possible to easily prevent interference between the boundary pattern HPP and the light incident on or output from the electronic module EM.

[0183] Boundary pattern HPPs can include inorganic materials. For example, boundary pattern HPPs can include metallic materials or inorganic insulating materials. Boundary pattern HPPs can be patterned by dry etching, wet etching, or laser patterning. Boundary pattern HPPs can be formed by various processes, and the formation of boundary pattern HPPs is not limited to specific embodiments.

[0184] According to the present invention, an electronic panel EP can be configured such that a central region HTA stacked with an electronic module EM is formed solely of insulating layers, each of which has high visible light transmittance. Among the insulating layers constituting the electronic panel EP, an insulating layer with high visible light transmittance is disposed in the central region HTA, and an insulating layer with low visible light transmittance is removed from the central region HTA. The insulating layer with high visible light transmittance includes a substrate BS, a first insulating layer 10, a second inorganic layer 63, a planarization pattern OCT, and a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73, while the insulating layer with low visible light transmittance includes one or more of a control layer EL and the first inorganic layer 61. In this configuration, because the central region HTA is configured to have high visible light transmittance, the electronic module EM can operate satisfactorily even without mechanical holes penetrating the central region HTA.

[0185] Figure 5A It is shown Figure 4A An enlarged view of section XX'. Figure 5B This is an enlarged cross-sectional view of an electronic panel, partially illustrating some exemplary embodiments of the concept according to the present invention. For the sake of simplicity, Figure 5B It shows the relationship with Figure 5A The section corresponding to the cross section. The following will refer to... Figure 5A and 5B Describe the concept of the invention. (Refer to...) Figures 1A to 4E The same components discussed are assigned the same reference numerals, and repeated descriptions will be omitted. It will be understood that, where certain details are not provided, they may be at least similar to those provided elsewhere in the specification for the corresponding elements.

[0186] like Figure 5AAs shown, the second groove GV2 has an undercut shape. For example, the end of the first insulating layer 10 forms a pointed portion TP protruding toward the second groove GV2. The control layer EL can be cut on the second groove GV2 by the pointed portion TP. For the sake of simplicity, the second electrode (see [reference]) is omitted. Figure 4A (E2). The second groove GV2 can be filled with a flattened pattern OCT.

[0187] According to this embodiment, the boundary pattern HPP may include multiple layers. In this embodiment, the boundary pattern HPP includes a first layer L1, a second layer L2, and a third layer L3 stacked sequentially. The first layer L1, the second layer L2, and the third layer L3 can give the boundary pattern HPP an undercut shape. For example, the third layer L3, corresponding to the uppermost one of the first layer L1, the second layer L2, and the third layer L3, may have an end TP_H that protrudes more than the second layer L2 disposed below the third layer L3.

[0188] Each of the first layer L1, the second layer L2, and the third layer L3 may comprise an inorganic material. For example, each of the first layer L1, the second layer L2, and the third layer L3 may comprise a metallic material or an inorganic insulating material. The first layer L1, the second layer L2, and the third layer L3 may all be formed of an etchable material, and the first layer L1, the second layer L2, and the third layer L3 may be formed of a material that can be patterned by laser. Optionally, each of the first layer L1, the second layer L2, and the third layer L3 may be formed of a material that can be patterned by laser.

[0189] For example, among the first layer L1, the second layer L2, and the third layer L3, at least the second layer L2 and the third layer L3 can have different etching rates relative to the same etchant. For example, the second layer L2 and the third layer L3 can be etched with different etchants. According to the concept of the present invention, because the first layer L1, the second layer L2, and the third layer L3 are controlled independently of each other in terms of the degree of patterning, it is possible to easily form a boundary pattern HPP with an undercut shape.

[0190] However, this is explained by way of example. As long as the boundary pattern HPP can have an undercut shape when viewed in cross-section, the boundary pattern HPP can be formed as a single-layer structure or can be formed from a single material, but the inventive concept is not limited thereto.

[0191] The first inorganic layer 61 covers the inner side of the second groove GV2. The end 61_E of the first inorganic layer 61 extends to the portion of the first insulating layer 10 that protrudes toward the second groove GV2, and the end 61_E does not extend to the upper part of the boundary pattern HPP or the central region HTA. The first inorganic layer 61 may not overlap with the central region HTA.

[0192] The second inorganic layer 63 is stacked with the line region LA, the pattern region PA, and the center region HTA. The second inorganic layer 63 extends through the inside of the second groove GV2 and covers the boundary pattern HPP and the center region HTA. In this embodiment, the second inorganic layer 63 may cover the undercut surface of the boundary pattern HPP.

[0193] Optionally, such as Figure 5B As shown, the second inorganic layer 63 can be cut at the region where the boundary pattern HPP is formed. When the boundary pattern HPP has a large degree of undercut, or when the end TP_H of the third layer L3 protrudes significantly relative to the second layer L2, the portion 63_P can be formed to be separated from the second inorganic layer 63. Therefore, the side surface L2_S of the second layer L2 can be exposed from the second inorganic layer 63.

[0194] A portion of the control layer EL can also be disposed on the end of the tip portion TP. When forming the electronic panel EP, the portion of the control layer EL may not be removed, but may be retained on the end of the tip portion TP. According to the present invention, the control layer EL can be disposed in various positions as long as it does not overlap with the central region HTA, but the present invention is not limited thereto.

[0195] Figures 6A to 6E This is a cross-sectional view illustrating a method for forming boundary patterns according to some exemplary embodiments of the concept of the present invention. Reference will be made below. Figures 6A to 6E Discuss the concept of this invention.

[0196] like Figure 6A As shown, a first preparatory layer L01, a second preparatory layer L02, and a third preparatory layer L03 are sequentially formed on a first insulating layer 10. Each of the first preparatory layer L01, the second preparatory layer L02, and the third preparatory layer L03 can be formed by deposition or coating. Each of the first preparatory layer L01, the second preparatory layer L02, and the third preparatory layer L03 may include a metal. In this case, the third preparatory layer L03 includes a material different from the material of the second preparatory layer L02.

[0197] After that, as Figures 6B to 6E As shown, a photoresist pattern PR is used as an etching mask to etch a first preparatory layer L01, a second preparatory layer L02, and a third preparatory layer L03. A first etching material ET1 can be used such that the third preparatory layer L03 is etched at the portion exposed from the photoresist pattern PR to form a third layer L3.

[0198] Subsequently, a second etching material ET2 can be used to etch the second preparatory layer L02 at the portion exposed from the third layer L3 to form the second layer L2. The second etching material ET2 can include various materials. For example, the second etching material ET2 can be different from the first etching material ET1. The second etching material ET2 can be a material that does not react with the third layer L3, but selectively reacts only with the second preparatory layer L02.

[0199] For example, the second etch material ET2 can be the same as the first etch material ET1. Compared to the third preparatory layer L03, the second preparatory layer L02 can be formed of a material with relatively higher reactivity than the second etch material ET2.

[0200] The second etching material ET2 can produce isotropic etching. Therefore, the second preparatory layer L02 can be etched at the portion where it overlaps with the third layer L3, thus the second layer L2 can be formed with an undercut shape starting from the third layer L3. Therefore, the side surface L3_S of the third layer L3 can protrude from the side surface L2_S of the second layer L2. The width W1 of the second layer L2 can be smaller than the width W2 of the third layer L3.

[0201] Subsequently, a third etching material ET3 can be used to etch the first preparatory layer L01 at the portions not overlapping with the photoresist pattern PR to form the first layer L1. The third etching material ET3 can be different from the second etching material ET2. Therefore, while the first preparatory layer L01 is being etched, the second layer L2 can stably maintain its shape.

[0202] The third etching material ET3 can produce anisotropic etching. Therefore, the first layer L1 can be formed with an area that at least partially overlaps with the photoresist pattern PR. According to the concept of the present invention, when the stacked first layer L1, second layer L2 and third layer L3 are controlled in terms of the degree of etching, it is possible to easily form a boundary pattern HPP with an undercut shape.

[0203] Figure 7 This is an exploded perspective view illustrating some example embodiments of an electronic device according to a concept of the present invention. Figure 8A and Figure 8B A cross-sectional view of an electronic device illustrating some example embodiments of a concept according to the present invention is shown. Figure 8A and 8B It shows the relationship with Figure 4A The section corresponding to the section below will be referred to below. Figure 7 , Figure 8A and Figure 8B Describe the concept of this invention.

[0204] like Figure 7 As shown, with Figure 1BCompared to the electronic device EA shown, electronic device EA-1 may also include an anti-reflective layer POL and an adhesive layer ADL.

[0205] An anti-reflective layer POL can be disposed between the window WM and the electronic panel EP. The anti-reflective layer POL reduces the reflectivity of external light incident from outside the window WM relative to the electronic panel EP. In this embodiment, the anti-reflective layer POL may include a polarizing film or a color filter.

[0206] An adhesive layer ADL is disposed between the antireflective layer POL and the window WM. The adhesive layer ADL combines the antireflective layer POL and the window WM. According to the present invention, when the antireflective layer POL is a color filter formed on the electronic panel EP, the adhesive layer ADL can substantially bond the electronic panel EP to the window WM. The adhesive layer ADL may include an optically transparent adhesive, an optically transparent resin, or a pressure-sensitive adhesive, and the material of the adhesive layer ADL is not limited to specific embodiments, as long as the adhesive layer ADL is optically transparent.

[0207] According to an embodiment of the present invention, the antireflective layer POL may include an aperture HA-P. The aperture HA-P may be defined at a location corresponding to the high-transmittance region HA. The aperture HA-P may be a portion having a visible light transmittance greater than that of any portion surrounding the aperture HA-P.

[0208] like Figure 8A As shown, the antireflective layer POL may include an aperture HA-P and a polarizing portion PP. The polarizing portion PP may be a portion with polarization characteristics, or a portion other than the aperture HA-P. The polarizing portion PP is superimposed on the effective region AA and the line region LA.

[0209] The aperture HA-P can be at least partially superimposed on the high-transmittance region HA. The aperture HA-P can have a size corresponding at least to the central region HTA of the high-transmittance region HA, and can be defined at the location superimposed on the central region HTA. In this embodiment, the aperture HA-P can be formed by rinsing a portion of the antireflective layer POL to remove polarization characteristics, thus the aperture HA-P can be a transparent portion of the antireflective layer POL.

[0210] Optionally, such as Figure 8B As shown, the aperture HA-P1 can penetrate the antireflective layer POL-1. Therefore, the antireflective layer POL-1 can provide relatively high visible light transmittance to the area corresponding to the central region HTA.

[0211] According to the present invention, the increased transmittance of visible light can be provided to the region corresponding to the electronic module EM, so that even when the electronic panel EP does not have a hole formed therein, the electronic module EM can stably receive light incident on the electronic panel EP, and the light emitted from the electronic module EM can be easily output through the electronic panel EP.

[0212] Figures 9A to 9L A cross-sectional view illustrating a method of manufacturing an electronic device according to some example embodiments of the concept of the present invention is shown. Reference will be made below. Figures 9A to 9L Discuss the concept of this invention. (Refer to...) Figures 1A to 8B The same components discussed are assigned the same reference numerals, and repeated descriptions will be omitted. It will be understood that, where certain details are not provided, they may be at least similar to those provided elsewhere in the specification for the corresponding elements.

[0213] like Figure 9A As shown, a boundary pattern HPP and a control electrode CE are formed on a substrate BS. In this embodiment, the boundary pattern HPP and the control electrode CE are shown to be formed from the same layer.

[0214] The boundary pattern HPP can be formed from the same material as the control electrode CE. In this case, a single mask can be used to pattern the boundary pattern HPP and the control electrode CE simultaneously, which can lead to process simplification and reduced process costs. However, this is shown exemplarily that the boundary pattern HPP can include, but is not limited to, materials different from the material of the control electrode CE.

[0215] The first insulating layer 10, the second insulating layer 20, and the semiconductor pattern SP can be formed before the boundary pattern HPP and the control electrode CE are formed. The first insulating layer 10 can be formed by depositing an inorganic material on a substrate BS or by coating an organic material on a substrate BS. The first insulating layer 10 is formed of a material with high visible light transmittance. For example, the first insulating layer 10 can be formed of silicon oxide or silicon oxynitride.

[0216] Next, a semiconductor pattern SP is formed. The semiconductor pattern SP can be formed by depositing or coating a semiconductor material on the first insulating layer 10 and then performing a patterning process. Then, a second insulating layer 20 is formed. In this embodiment, an insulating material can be deposited or coated, and then patterned to remove the portion corresponding to the high-transmittance region HA, resulting in the second insulating layer 20. However, this is shown exemplarily. According to an embodiment conceived in the present invention, the second insulating layer 20 can be formed to extend to the location corresponding to the high-transmittance region HA, and in this case, a separate process can be omitted.

[0217] After that, as Figure 9B As shown, a thin-film transistor TR, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, a dam DM, and a first electrode E1 can be formed. The third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 can be formed by depositing or coating an insulating material and then patterning the insulating material.

[0218] The dam DM can include the same material as the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. In this case, the same process can be performed to simultaneously form the dam DM and the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. For example, the same mask can be used to simultaneously pattern the first insulating pattern IP1 in the first insulating pattern IP1 and the second insulating pattern IP2 constituting the dam DM with the fourth insulating layer 40, and the same mask can be used to simultaneously pattern the second insulating pattern IP2 in the first insulating pattern IP1 and the second insulating pattern IP2 with the fifth insulating layer 50. Therefore, it is possible to simplify the process and reduce the process cost.

[0219] During the formation of the fifth insulating layer 50, an opening OP may be formed. The opening OP is formed to expose at least a portion of the first electrode E1. During the formation of the opening OP, a second insulating pattern IP2 may also be formed.

[0220] After that, as Figure 9C As shown, a mask (MSK) can be formed. The mask (MSK) can include a metal or a metal oxide. For example, the mask (MSK) can be formed from a transparent conductive oxide.

[0221] The mask MSK covers the fifth insulating layer 50 and the dam DM. Mask openings MS_OP1 and MS_OP2 can be formed in the mask MSK. Mask openings MS_OP1 and MS_OP2 can both surround the central region HTA and can be separated from each other.

[0222] After that, as Figure 9D As shown, a mask MSK can be used to pattern the first insulating layer 10 and the substrate BS. The first insulating layer 10 is removed and cut at the portion of the first insulating layer 10 that overlaps with the mask openings MS_OP1 and MS_OP2, and the substrate BS is partially removed at the portion of the substrate BS that overlaps with the mask openings MS_OP1 and MS_OP2 to form grooves GV1 and GV2 having their recessed shapes.

[0223] Grooves GV1 and GV2 can be formed to have their undercut shape relative to the first insulating layer 10. Therefore, the first insulating layer 10 can have a tip TP protruding into the grooves GV1 and GV2. Afterwards, the mask MSK is removed.

[0224] After that, as Figure 9E As shown, an emission pattern EMP, a control layer EL, and a second electrode E2 are sequentially formed to constitute a light-emitting element ELD. The opening OP can be filled using a light-emitting material (see [reference]). Figure 9B To form the emission pattern EMP.

[0225] The control layer EL and the second electrode E2 can be formed by an evaporation process. In this case, because the control layer EL and the second electrode E2 are formed with straightness, the grooves GV1 and GV2 can have neither the control layer EL nor the second electrode E2 at the portions where they are shielded by the tip TP. Therefore, the control layer EL and the second electrode E2 can be cut at the locations where they overlap with the grooves GV1 and GV2.

[0226] Alternatively, a control layer EL and a second electrode E2 can be formed in the central region HTA and the patterned region PA. The control layer EL and the second electrode E2 cover the side and top surfaces of the boundary pattern HPP.

[0227] After that, as Figure 9F and Figure 9G As shown, a first inorganic layer 61 can be formed, followed by a cleaning process. The first inorganic layer 61 can be formed by depositing an insulating material. For example, silicon nitride can be deposited to form the first inorganic layer 61. For the sake of simplicity, in Figure 9G The second electrode is omitted (see [reference]). Figure 9F E2).

[0228] The deposition process of the first inorganic layer 61 can be isotropic. Therefore, the first inorganic layer 61 can be formed while simultaneously covering the inner surfaces of grooves GV1 and GV2. In this case, the undercut shape of the boundary pattern HPP can cause the formation of certain gaps at portions of the first inorganic layer 61. Figure 9G As shown, the first inorganic layer 61 may include a portion 61-F superimposed on the central region HTA and the patterned region PA. This portion 61-F can be cut from other portions of the first inorganic layer 61 superimposed on the line region LA and can expose portions of the boundary pattern HPP.

[0229] After the first inorganic layer 61 is formed, a cleaning solution CLN can be provided. The cleaning solution CLN removes foreign matter present on the surface of the first inorganic layer 61.

[0230] like Figures 9H to 9J As shown, during the cleaning process, the cleaning solution CLN can penetrate the gaps formed at the first inorganic layer 61. Therefore, a portion 61-F of the first inorganic layer 61 can be peeled off from the central region HTA and the patterned region PA. For the sake of simplicity, in... Figure 9H and Figure 9I The second electrode is omitted (see [reference]). Figure 9F E2).

[0231] In this configuration, the second electrode E2 and the control layer EL can also be peeled off from the central region HTA and the patterned region PA together with a portion 61-F of the first inorganic layer 61. Therefore, the first inorganic layer 61, the second electrode E2, and the control layer EL can be easily removed from the central region HTA via a cleaning process. Removing the first inorganic layer 61, the second electrode E2, and the control layer EL from the central region HTA exposes the first insulating layer 10 within the central region HTA.

[0232] After that, as Figure 9K As shown, an organic layer 62 and a second inorganic layer 63 are formed sequentially. The organic layer 62 can be formed by performing a coating process to coat an organic material. The coating process may include an inkjet printing process or a screen printing process. The organic layer 62 may partially fill the grooves GV1 and GV2, and the dam DM can control the formation area of ​​the organic layer 62 to prevent the organic layer 62 from extending into the central region HTA.

[0233] The second inorganic layer 63 can be formed on the entire surface of the substrate BS. The second inorganic layer 63 can be formed by depositing an insulating material. The formation of the second inorganic layer 63 can be isotropic. Therefore, the second inorganic layer 63 can cover the inner surfaces of the grooves GV1 and GV2 having their undercut shapes. According to the present invention, because the first inorganic layer 61 is removed from the central region HTA, the second inorganic layer 63 can directly contact the first insulating layer 10 in the central region HTA.

[0234] After that, as Figure 9L As shown, a planarization pattern OCT, a seventh insulating layer 70, and conductive patterns SP1H, SP2H, CP2, and HSL3 can be formed, resulting in the fabrication of an electronic panel EP. The planarization pattern OCT can be formed in the high-transmittance region HA, providing a flat surface continuous with the effective region AA for the high-transmittance region HA.

[0235] According to the present invention, during the cleaning process, the boundary pattern HPP can cause the peeling of the first inorganic layer 61 and the control layer EL. Because the first inorganic layer 61 and the control layer EL, which have relatively low visible light transmittance, can be easily removed from the central region HTA, the central region HTA can increase the visible light transmittance. Therefore, even when no hole is formed on the electronic module EM to penetrate the electronic panel EP, the electronic module EM can easily receive light through the electronic panel EP, or output light externally through the electronic panel EP. As a result, it is possible to increase process reliability and provide an electronic device with a reduced bezel area.

[0236] According to the present invention, because the electronic module is configured to at least partially overlap with the electronic panel, the area of ​​the bezel region is reduced. Furthermore, even without forming a hole penetrating the electronic panel, the electronic panel can be provided with an area having high visible light transmittance.

[0237] Although exemplary embodiments of this disclosure have been described herein with reference to figures, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept.

Claims

1. An electronic device, the electronic device comprising: Electronic module, outputting and / or receiving light; as well as The electronic panel is divided into a first region superimposed on the electronic module, a second region surrounding at least a portion of the first region, and a third region adjacent to the second region. The electronic panel includes: Matrix substrate; Multiple pixels are disposed on the substrate and configured to display an image in the second region; An encapsulation layer, disposed on the substrate and at least partially covering the plurality of pixels; and A boundary pattern is set in the first region. The first region includes a central region and a patterned region that at least partially surrounds the central region. The encapsulation layer includes: a first inorganic layer, superimposed on the second region but not on the central region; and a second inorganic layer disposed on the first inorganic layer, the second inorganic layer extending from the second region to the first region to superimpose on both the first and second regions. The boundary pattern has an undercut shape, and The second inorganic layer is disposed on the substrate and is superimposed on the substrate in the central region.

2. The electronic device according to claim 1, wherein, The boundary pattern is separated from the central region and is set along the pattern area.

3. The electronic device of claim 2, wherein, The boundary pattern has a closed line shape that at least partially surrounds the central region.

4. The electronic device of claim 2, wherein, The encapsulation layer further includes: An organic layer is disposed between the first inorganic layer and the second inorganic layer. 5.The electronic device of claim 1, wherein, The second inorganic layer has a higher visible light transmittance than the first inorganic layer.

6. The electronic device according to claim 2, further comprising: A window is disposed on the encapsulation layer; as well as An anti-reflective layer is disposed between the window and the electronic panel, wherein, The anti-reflective layer includes holes corresponding to the central region, and The aperture has a higher transmittance of visible light than any other part of the antireflective layer.

7. The electronic device of claim 6, wherein, The aperture has a smaller degree of polarization than any other part of the antireflective layer.

8. The electronic device of claim 6, wherein, The hole penetrates the anti-reflective layer.

9. The electronic device according to claim 2, further comprising a sensing unit disposed on the encapsulation layer, the sensing unit comprising a plurality of conductive patterns and a plurality of sensing insulating layers disposed between the plurality of conductive patterns. wherein The plurality of sensing insulating layers are at least partially superimposed on the central region.

10. The electronic device of claim 9, further comprising a planarization pattern disposed below the sensing unit. wherein The flattened pattern overlaps at least partially with the central region.

11. The electronic device according to claim 1, wherein, The boundary pattern comprises a first layer, a second layer, and a third layer stacked sequentially, and The side surface of the third layer protrudes from the side surface of the second layer.

12. The electronic device of claim 11, wherein, The third layer comprises a material different from that of the second layer.

13. The electronic device of claim 1, wherein, The boundary pattern is conductive.

14. The electronic device according to claim 13, wherein, Each of the plurality of pixels includes: The light-emitting element is located in the second region; and Thin-film transistor, connected to the light-emitting element, The boundary pattern is disposed on the same layer as any one of the control electrode, input electrode, and output electrode of the thin-film transistor.

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