A SiC-based nanoscale Schottky barrier field-effect transistor

Abstract

The present invention discloses a SiC-based nanoscale Schottky barrier field-effect transistor, whose structure includes source and drain electrodes, a gate electrode, an oxide layer and an intermediate channel scattering region. Among them, the source and drain electrodes are made of two-dimensional metallic phase molybdenum disulfide (MoS2) material; the gate electrode adopts a double-gate structure, which is divided into a top gate and a back gate; an oxide layer is included between the top gate and the back gate and the substrate channel; the intermediate channel scattering region is made of two-dimensional SiC material. The present invention uses two-dimensional SiC material as the substrate and two-dimensional MoS2 material as the source and drain electrodes, forming a Schottky barrier contact with the substrate material; the double-gate structure enhances the gate's control ability over the channel, effectively solving the device performance defects caused by short-channel effect and quantum effect when the channel length is reduced to less than 10 nm. When the channel length is less than 5.1 nm, the device off-state current is less than 0.1 μA / μm, achieving normal turn-off; the on-state current is not less than 940 μA / μm, meeting the high-performance requirements of the International Technology Roadmap for Semiconductors (ITRS).

Description

Technical Field

[0001] The present invention relates to the technical field of nano-scale field effect transistors, and particularly relates to a SiC-based nano-scale Schottky barrier field effect transistor. Background Art

[0002] The development of integrated circuits has always followed Moore's law. As the device feature size continues to decrease, traditional silicon-based field effect transistors, as the core devices of integrated circuits, have reached their physical limits. The emergence of short-channel effects, quantum effects, etc. seriously affects the device performance and causes the device to malfunction. The field effect transistors using materials such as high-K gate insulators, FinFET structures, and nanotubes have high process implementation costs. Two-dimensional materials represented by graphene, transition metal sulfides, and black phosphorus have the advantages of very thin thickness, smooth and flat surface, and good bendability, and have become ideal channel materials for a new generation of electronic devices. However, when the channel length size is reduced to 5.1 nm, most of the field effect transistors based on the above two-dimensional materials cannot meet the high-performance requirements of the International Technology Roadmap for Semiconductors (ITRS). Summary of the Invention

[0003] Aiming at the above problems, the purpose of the present invention is to use a two-dimensional SiC material with a wide bandgap as the channel material of the field effect transistor to solve the performance defects of the field effect transistor when the channel length is reduced to 5.1 nm and below, and meet the high-performance requirements of ITRS.

[0004] To solve the above technical problems, the technical solution adopted by the present invention is: a SiC-based nano-scale Schottky barrier field effect transistor, characterized in that: it includes a substrate, source and drain electrodes, a gate, an oxide layer, and an intermediate channel scattering region, wherein the source and drain electrodes are made of a single-layer metal-phase MoS 2 material, the gate adopts a double-gate structure, which is divided into a top gate and a back gate. An oxide layer is included between the top gate and the back gate and the channel region. The intermediate channel scattering region is the part of the substrate covered by the oxide layer. The bias voltage between the source electrode and the drain electrode is V DS , the gate voltage is V GS , and the Z direction is the electron transport direction.

[0005] Preferably, the substrate is a two-dimensional SiC material.

[0006] Preferably, the thickness of the oxide layer is 0.41 nm.

[0007] Preferably, the bias voltage V DS between the source electrode and the drain electrode is 0.64 V.

[0008] Preferably, the source and drain electrodes are made of two-dimensional metallic phase MoS 2 material.

[0009] Preferably, the source and drain electrodes form a Schottky barrier contact with the substrate.

[0010] The SiC-based nanoscale Schottky barrier field effect transistor of the present invention has the following advantages:

[0011] 1) The wide-bandgap two-dimensional material SiC has excellent properties such as high melting point, high breakdown voltage, good thermal conductivity, and strong oxidation resistance, which can meet the new requirements for the development of modern semiconductor devices.

[0012] 2) When the gate length of the device is reduced, the on-state current is not less than 940 μA / μm, meeting the high-performance requirements of ITRS.

[0013] 3) The source and drain electrodes are made of two-dimensional metallic phase MoS 2 material, which can greatly reduce the device size and thus significantly improve the chip integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic cross-sectional structure diagram of an embodiment of the present invention.

[0015] Figure 2 is a schematic top view structure diagram of an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] As Figure 1 and Figure 2 shown, the SiC-based nanoscale Schottky barrier field effect transistor of this embodiment includes a substrate, source and drain electrodes, a gate, an oxide layer, and an intermediate channel scattering region. The source and drain electrodes are made of two-dimensional metallic phase MoS 2 material. The gate adopts a double-gate structure to enhance the gate's control ability over the channel, and is divided into a top gate and a back gate. An oxide layer is included between the top gate and the back gate and the channel region. The intermediate channel scattering region is the part of the substrate covered by the oxide layer. The substrate uses a wide-bandgap two-dimensional SiC material. The magnitude of the Bravais lattice vector of the SiC hexagonal lattice is The Si-C bond length is The bias voltage between the source and the drain is V DS , the gate voltage is V GS , and the Z direction is the electron transport direction.

[0017] In this embodiment, the substrate is a two-dimensional SiC material.

[0018] In this embodiment, the thickness of the oxide layer is 0.41 nm.

[0019] In this embodiment, the bias voltage V between the source and the drain DS is 0.64 V.

[0020] In this embodiment, two-dimensional metallic phase MoS 2 material is used as the source and drain electrodes.

[0021] In this embodiment, the source and drain electrodes form Schottky barrier contacts with the substrate.

[0022] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A SiC-based nanoscale Schottky barrier field effect transistor, Characterized in that: It includes source and drain electrodes, a gate, an oxide layer, and an intermediate scattering region with two-dimensional SiC as the channel material. Among them, the source and drain electrodes are metal-phase monolayer MoS 2 materials. The gate adopts a double-gate structure, which is divided into a top gate and a back gate. An oxide layer is included between both the top gate and the back gate and the channel region. The bias voltage between the source and drain electrodes is V DS , and the gate voltage is V GS . The Z direction is the electron transport direction.

2. The SiC-based nanoscale Schottky barrier field effect transistor according to claim 1, Characterized in that: The thickness of the oxide layer is 0.41 nm.

3. The SiC-based nanoscale Schottky barrier field effect transistor according to claim 1, Characterized in that: The bias voltage V between the source and the drain DS is 0.64 V.

4. The SiC-based nanoscale Schottky barrier field effect transistor according to claim 1, Characterized in that: The source and drain electrodes are made of two-dimensional metallic phase MoS 2 material.

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