Semiconductor device with reduced trap defects and method of forming the same

Abstract

Embodiments of the present invention relate to semiconductor devices with reduced trap defects and methods for forming the same. A method for manufacturing a semiconductor device includes: providing a substrate including a surface; depositing a first dielectric layer and a second dielectric layer on the substrate; forming a dummy gate electrode on the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly doped source / drain LDD regions on both sides of the gate spacer in the substrate; forming source / drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an interlayer dielectric ILD layer on the replacement gate and the source / drain regions; and performing a treatment by introducing a trap repair element into at least one of the gate spacer, the second dielectric layer, the surface, and the LDD region before forming the source / drain region or after forming the ILD layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device with reduced trap defects and a method for forming the same. Background Art

[0002] As technology evolves, the design and manufacture of semiconductor devices become more complex as their size becomes smaller and more circuits provide more powerful functions. Therefore, there is a need to continuously improve the methods of manufacturing semiconductor devices to enhance device robustness and reduce costs and processing time. As device size continues to shrink, the voltage or current level at which the device operates becomes lower. Therefore, it is more critical to control threshold voltage stability and mitigate leakage current to maintain device performance.

[0003] Although technologies for improving threshold voltage stability or leakage current performance have been extensively studied, the technologies still fall short in many aspects. Therefore, further solutions to the above problems are needed. Summary of the invention

[0004] One embodiment of the present invention relates to a method of manufacturing a semiconductor device, comprising: providing a substrate including a surface; depositing a first dielectric layer and a second dielectric layer on the substrate; forming a dummy gate electrode on the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly doped source / drain (LDD) regions on both sides of the gate spacer in the substrate; forming source / drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an interlayer dielectric (ILD) layer on the replacement gate and the source / drain regions; and performing a treatment by introducing a trap repair element into at least one of the gate spacer, the second dielectric layer, the surface, and the LDD region before forming the source / drain region or at a time after forming the ILD layer.

[0005] One embodiment of the present invention relates to a method for manufacturing a semiconductor device, which includes: providing a substrate including a surface; depositing a high-k dielectric layer on the substrate; forming a virtual gate electrode on the high-k dielectric layer; forming a gate spacer surrounding the virtual gate electrode; forming a lightly doped source / drain (LDD) region on both sides of the gate spacer in the substrate; forming a source / drain region in the respective LDD regions; forming a replacement gate and removing the virtual gate electrode; forming a contact plug electrically coupled to the replacement gate and the source / drain region; and performing a trap repair operation on at least one of the high-k dielectric layer, the gate spacer, the surface, and the LDD region before forming the virtual gate electrode or after forming the LDD region.

[0006] One embodiment of the present invention relates to a method for manufacturing a semiconductor device, comprising: providing a semiconductor fin including a channel region; depositing a first dielectric layer and a high-k dielectric layer on the semiconductor fin; passivating the high-k dielectric layer using a nitrogen-containing plasma; forming a patterned dummy gate on the semiconductor fin after passivating the high-k dielectric layer; forming a second dielectric layer on the dummy gate and the channel region; etching a portion of the second dielectric layer contacting the channel region; forming a lightly doped source / drain (LDD) region on both sides of the patterned dummy gate; and forming a semiconductor fin having ... The invention relates to a method for manufacturing a semiconductor device for manufacturing a semiconductor device of a semiconductor material, wherein the semiconductor device comprises a semiconductor layer and a semiconductor element. The method comprises the steps of: performing ion implantation on the LDD region using an element having a negative charge greater than that of silicon and oxygen; forming a source / drain region in the respective LDD region; performing ion implantation on the source / drain region; performing a first annealing operation on the ion-implanted source / drain region at a first temperature; forming a replacement gate by etching the patterned dummy gate; forming an interlayer dielectric layer on the source / drain region and the replacement gate; and performing a second annealing operation in a hydrogen atmosphere at a second temperature lower than the first temperature after the first annealing operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a perspective view of a semiconductor device according to some embodiments.

[0009] Figures 2 to 5 is a cross-sectional view of an intermediate stage in a method of fabricating a semiconductor device according to some embodiments.

[0010] FIG. 6A to FIG. 33B is a cross-sectional view of an intermediate stage in a method of fabricating a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the provided theme. The specific examples of components and arrangements will be described below to simplify this disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, "making a first component be formed above or on a second component" may include an embodiment in which the first component and the second component that are in direct contact are formed, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, this disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplification and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another element or components as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 70 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0013] Although the numerical ranges and parameters describing the broad scope of the present disclosure are approximate, the numerical values ​​described in the specific examples should be reported as accurately as possible. However, any numerical value inherently contains certain errors that are necessarily caused by the deviations commonly seen in the respective test measurements. In addition, as used herein, the terms "about", "approximately" and "substantially" generally mean within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, the terms "about", "approximately" and "substantially" mean within the acceptable standard error of the average value considered by ordinary technicians. Except in the operating / working examples, or unless otherwise expressly specified, all numerical ranges, quantities, values ​​and percentages disclosed herein (such as numerical ranges, quantities, values ​​and percentages of material quantities, durations, temperatures, operating conditions, quantitative ratios and the like) should be understood as being modified by the terms "about", "approximately" or "substantially" in all examples. Therefore, unless otherwise indicated, the numerical parameters described in the present disclosure and the appended claims are approximate values ​​that may be varied as needed. Finally, each numerical parameter should be interpreted at least in view of the reported significant figures and by applying general rounding techniques. Herein, ranges may be expressed as from one endpoint to another endpoint or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints.

[0014] A metal oxide semiconductor (MOS) transistor is formed of a semiconductor substrate, a gate electrode, and an oxide layer, wherein source / drain regions are formed in the semiconductor substrate on both sides of the gate electrode. A channel region is established close to the surface of the semiconductor substrate below the oxide layer and between the source / drain regions to conduct current under operating conditions. Charge carriers (electrons or holes) are attracted and accumulated on both sides of the oxide layer, wherein the carriers in the channel region form a current between the source / drain regions when driven by an electric field. The carriers are discharged after the device is turned off. The characteristics of the carrier movement (i.e., charging and discharging around the oxide and channel region) determine the performance of the MOS transistor, such as speed and turn-on voltage.

[0015] A factor that affects carrier mobility is the presence of trap defects in the constituent materials of the transistor. Trap defects are generally found in the crystal lattice (of oxides or other semiconductors), which create "deep" energy wells in which charge carriers can be "trapped" temporarily or permanently. Trap defects are usually created when depositing, removing or further processing the layers of the MOS transistor because the lattice properties of the layer or the interface between the layer and the adjacent layer are impaired. The first type of trap defect is a body trap present in the bulk material; this type of defect can occur during the recrystallization process that produces polar bonds (such as Hf-O bonds in hafnium-containing oxide materials). The second type of trap defect can occur on the processed surface of silicon. The formation of trap defects, in turn, causes carriers to be randomly trapped and released to degrade the stability of the electrical properties of the MOS transistor.

[0016] Embodiments of the present invention discuss passivation schemes for mitigating trap defects in dielectric or silicon materials of MOS transistors. The passivation schemes can be applied globally or locally to transistors. The passivation schemes can be performed by introducing trap repair elements suitable for terminating defects, such as nitrogen, fluorine, hydrogen, and the like. The trap defects in dielectric or silicon materials can be effectively reduced and the charge / discharge characteristics of carriers can be better controlled. Threshold voltage instability problems, slow slope problems of drain current, and device noise can be mitigated.

[0017] Embodiments will be described with respect to a specific context, namely, semiconductor devices and methods of forming the same. Various embodiments presented herein are discussed in the context of fin field effect transistors (FinFETs) formed using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, the present disclosure encompasses aspects for use in other types of semiconductor devices, such as planar transistor devices, multi-gate transistor devices, 2D transistor devices, wrap-around gate transistor devices, nanowire transistor devices, and the like.

[0018] Figure 1 is a perspective view of a semiconductor device 100 according to some embodiments. Figure 1A FinFET device 100 is shown, however, other types of semiconductor devices are also within the scope of the present disclosure. The semiconductor device 100 includes a substrate 102, an isolation region 114, two fins 105 on the substrate 102, a gate dielectric layer 108, and a gate electrode 112. The fins 105 protrude above the substrate 102 and extend in parallel. The isolation region 114 is formed on the substrate 102 between adjacent fins 105. The gate dielectric layer 108 is disposed on the sidewalls and top surface of each of the fins 105, and the gate electrode 112 is located on the gate dielectric layer 108. The gate electrode 112 and the gate dielectric layer 108 extend in a direction perpendicular to the fins 105. Source / drain regions SD1 and SD2 are formed on opposite sides of each fin 105 relative to the gate dielectric layer 108 and the gate electrode 112. A channel region (not shown) is established in the fin 105 between the source / drain regions SD1 and SD2 and is surrounded by the gate dielectric layer 108 and the gate electrode 112 .

[0019] Figure 1 The FinFET device 100 shown in FIG. 1 is for illustration only and is not intended to limit the scope of the present disclosure. Thus, other configurations (eg, different numbers of fins, different numbers of gate electrodes, and multiple layers of fins) are within the contemplation of the present disclosure. Figure 1 The cross-sectional lines referenced in the subsequent figures are further illustrated. Section AA is taken along the channel region, gate dielectric layer 108, and gate electrode 112 of FinFET device 100. Section BB is taken along the longitudinal axis of fin 105 perpendicular to section AA. In some embodiments, section BB is taken in the direction of current flow in the channel region.

[0020] Figures 2 to 5 According to some embodiments of the invention Figure 1 FIG. 1 is a cross-sectional view of an intermediate stage of a method of manufacturing a semiconductor device 100 . Figures 2 to 5 is along Figure 1 The cross section AA is obtained.

[0021] refer to Figure 2, providing or forming a substrate 102. The substrate 102 may be a semiconductor substrate that may be doped (e.g., doped with a p-type or n-type dopant) or undoped, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. An SOI substrate generally includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 102 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof.

[0022] In some embodiments, substrate 102 includes an integrated circuit device (not shown) formed thereon. The integrated circuit device may include active devices (such as transistors) and passive devices (such as diodes, capacitors, resistors, inductors, or combinations thereof). The integrated circuit device may be formed using any suitable method known in the art.

[0023] In some embodiments, a well region (not shown) may also be formed in the substrate 102. The substrate 102 may include a p-type well (p-well), an n-type well (n-well), or both. In some embodiments, a p-type dopant is implanted into the substrate 102 to form a p-well. The p-type dopant may be boron, BF2, or the like. In some embodiments, an n-type dopant is implanted into the substrate 102 to form an n-well. The n-type dopant may be phosphorus, arsenic, or the like. In some embodiments, an annealing operation may be performed on the substrate 102 to activate the implanted p-type and n-type dopants to improve well performance.

[0024] Figure 2 Further illustrated is a mask 104 formed on the substrate 102. In some embodiments, the mask 104 acts as an etch stop layer when patterning the substrate 102. Figure 2, in some embodiments, the mask 104 includes a first mask layer 104A and a second mask layer 104B on the first mask layer 104A. The first mask layer 104A may be a hard mask including one or more layers of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, or the like, and may be formed using any suitable process, such as thermal oxidation, thermal nitridation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), combinations thereof, or the like. The second mask layer 104B may include a photoresist for patterning the first mask layer 104A. The second mask layer 104B may be formed using a spin coating or deposition process and may be patterned using a suitable photolithography technique. In some embodiments, the mask 104 may include three or more mask layers.

[0025] Figure 3 The formation of semiconductor strips 103 from substrate 102 is shown. First, mask layers 104A and 104B may be patterned using suitable photolithography and etching operations, wherein openings are formed in mask 104 and expose portions of substrate 102. Next, an etching process is performed to etch substrate 102 using patterned mask 104 as a mask. Thus, the pattern of mask 104 is transferred to substrate 102 to form semiconductor strips 103. The etching operation may include any suitable etching process, such as wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like. In some embodiments, the etching process is anisotropic etching. In some embodiments, after semiconductor strips 103 are formed, remaining portions of mask 104 may be removed by any suitable process. In other embodiments, portions of mask 104 (e.g., first mask layer 104A) may remain on semiconductor strips 103.

[0026] refer to Figure 4 , so that the isolation region 114 is formed in the trench between adjacent semiconductor strips 103. The isolation region 114 may include an insulating material, such as a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or the like. The isolation region 114 may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), ALD, PVD, a combination thereof, or the like. Other insulating materials formed by any suitable process may also be used. In some embodiments, an annealing process may be performed after depositing the insulating material of the isolation region 114.

[0027] In some embodiments, the isolation region 114 may include a liner (not shown) formed on the sidewalls and upper surfaces of the substrate 102 and the semiconductor strips 103 prior to forming the isolation region 114. In some embodiments, the liner may include silicon nitride, silicon oxide, silicon oxynitride, a polymer, a combination thereof, or the like. The formation of the liner may include any suitable method, such as ALD, CVD, HDP-CVD, a combination thereof, or the like. In these embodiments, the liner may prevent (or at least reduce) diffusion from the semiconductor strips 103 into the isolation region 114 during annealing of the isolation region 114.

[0028] In some embodiments, a planarization operation, such as mechanical grinding or chemical mechanical polishing (CMP), may be performed to remove excess portions of isolation regions 114 so that top surfaces of isolation regions 114 and top surfaces of semiconductor strips 103 are coplanar. In some embodiments where portions of mask 104 remain on semiconductor strips 103 after forming semiconductor strips 103, the planarization process may also include removing remaining portions of mask 104.

[0029] refer to Figure 5 , so that the isolation region 114 is recessed below the semiconductor strip 103. In some embodiments, the recessed isolation region 114 is referred to as a shallow trench isolation (STI) region. The isolation region 114 is recessed so that the upper portion of the semiconductor strip 103 (referred to herein as the fin 105) protrudes from between adjacent isolation regions 114. In some embodiments, the top surface of the isolation region 114 may include a flat surface, a convex surface, or a concave surface. The isolation region 114 may be recessed using wet etching, dry etching, or a combination thereof.

[0030] FIG. 6A to FIG. 33B is a cross-sectional view of an intermediate stage of a method of manufacturing a semiconductor device 100 according to some embodiments. Figure 5 Provided after the steps shown in FIG. 6A to FIG. 33B The intermediate stage of the method shown in Figure 1 The reference section AA in the figure is shown with a figure number ending with "A"; Figure 1 The reference cross-section BB shown in FIG. 1 is shown with a figure number ending in "B". It should be understood that FIG. 6A to FIG. 33B Before the process shown in FIG. 6A to FIG. 33B The process period and FIG. 6A to FIG. 33B Additional operations are provided after the process shown in, and additional embodiments of the method may replace or eliminate some operations described below. The order of operations and processes may be interchangeable. In addition, the same or similar configuration, structure, material, operation or process of one embodiment may be used in other embodiments, and its detailed explanation may be omitted.

[0031] refer to Fig. 6A and Figure 6B, a first dielectric layer 122 is formed on the sidewalls and upper surface 105S of each of the fins 105. In some embodiments, the first dielectric layer 122 may also be formed on the isolation region 114. The first dielectric layer 122 may include an oxide, such as silicon oxide or the like. Other dielectric materials are also possible, such as nitrides, carbides, oxynitrides, and the like. In some embodiments, the first dielectric layer 122 includes a low dielectric constant (low-k) material, such as a material having a dielectric constant of less than about 4.0. The first dielectric layer 122 may be formed using ALD, CVD, or PVD, may be thermally grown, or may be formed using other suitable processes.

[0032] Subsequently, a second dielectric layer 124 is formed on the first dielectric layer 122. In some embodiments, the second dielectric layer 124 may also be formed on the isolation region 114. The second dielectric layer 124 may be different from the first dielectric layer 122 and may include a high dielectric constant (high-k) material having a dielectric constant greater than about 4.0. The dielectric material of the second dielectric layer 124 may include a metal oxide, a metal nitride, a metal silicate, a transition metal oxide, a transition metal nitride, a transition metal silicate, a metal oxynitride, a metal aluminate, a zirconium silicate, a zirconium aluminate, or the like. In some embodiments, the second dielectric layer 124 may be formed of: Al2O3, HfO2, ZrO2, HfO x N y 、ZrO x N y 、HfSi x O y 、ZrSi x O y 、HfSi x O y N z 、ZrSi x O y N z , TiO2, Ta2O5, La2O3, CeO2, Bi4Si2O 12 、WO3、Y2O3、LaAlO3、Ba 1-x Sr x TiO3, PbTiO3, BaTiO3 (BTO), SrTiO3 (STO), BaSrTiO3 (BST), PbZrO3, lead strontium titanate (PST), lead zinc niobate (PZN), lead zirconium titanate (PZT), lead magnesium niobium (PMN), yttria stabilized zirconia (YSZ), ZnO / Ag / ZnO (ZAZ), combinations thereof, or the like. The second dielectric layer 124 may be formed using ALD, CVD, PVD, molecular beam deposition (MBD), or other suitable processes.

[0033] Subsequently, a first treatment TRMT-1 is performed on the second dielectric layer 124, such as Fig. 7A and Figure 7B . The first treatment TRMT-1 is configured to mitigate or at least reduce trap defects occurring during the formation of the first dielectric layer 122 and the second dielectric layer 124. The first treatment TRMT-1 may introduce nitrogen as a trap repair element into the trap defects in the high-k dielectric material of the second dielectric layer 124 through, for example, a nitridation process. In some embodiments, the nitridation process is performed using a nitrogen-containing species such as N2 or NH3. In some embodiments, the nitridation process may increase the density of the second dielectric layer 124 to prevent it from being damaged in subsequent processes.

[0034] In some embodiments, the nitridation process provides N2 plasma by a decoupled plasma nitridation (DPN) process. For example, the second dielectric layer 124 is nitrided by thermal nitridation using nitrogen plasma at a temperature between about 100° C. and about 500° C., a pressure of 1 mtorr to 100 mtorr, and a power of about 100 watts to about 1000 watts for a period of time between about 10 seconds and about 300 seconds. In some embodiments, the nitridation uses a nitrogen-containing gas, such as pure ammonia or N2, with a flow rate between about 10 sccm and about 300 sccm. In some embodiments, the nitridation causes a nitrogen concentration in the second dielectric layer 124 between about 1% and about 10% or between about 5% and about 6%. A nitrogen-containing second dielectric layer 124 containing a nitrogen concentration of less than about 1% may not exhibit the desired passivation properties, while a nitrogen concentration greater than about 10% may increase the likelihood of adverse effects, such as negative bias temperature instability (NBTI) effects. In some embodiments, a controlled nitrogen concentration is achieved by limiting the nitrogen-containing gas to between about 10 sccm and about 300 sccm. In some embodiments, no RF bias is introduced during the DPN process.

[0035] Another nitridation process may also be incorporated into the first process TRMT-1. For example, alternatively or in addition, a post-nitridation annealing (PNA) process is performed relative to the DPN process. In some embodiments, the PNA process is performed at a temperature higher than the temperature used in the DPN (e.g., between about 400°C and about 850°C). In some embodiments, the PNA process is performed using a nitrogen-containing gas as an annealing gas over a period of about 1 second to about 180 seconds. In some embodiments, the PNA process uses a nitrogen-containing gas, such as pure N2, having a flow rate between about 10sccm and about 200sccm. In some embodiments, the PNA process causes a nitrogen concentration of about 1% to about 10% or about 5% to about 6% in the second dielectric layer 124. The PNA process may cause the second dielectric layer 124 to react with nitrogen to reach a stable state, and may drive the nitrogen to a deeper depth to produce a more uniform second dielectric layer 124.

[0036] Then, if Fig. 8A and Figure 8B , a gate electrode layer 125 and a mask layer 127 are sequentially formed on the second dielectric layer 124. In some embodiments, the material of the gate electrode layer 125 is deposited on the second dielectric layer 124 and then planarized using, for example, a CMP process. The gate electrode layer 125 may include polysilicon, but other conductive materials, such as metals, may also be used. The mask layer 127 may include, for example, one or more layers of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, or the like and may be formed using any suitable process, such as thermal oxidation, thermal nitridation, ALD, PVD, CVD, combinations thereof, or the like.

[0037] refer to Fig.9A and Fig. 9B The mask layer 127 is patterned using suitable photolithography and etching techniques to form a patterned mask layer 128. The pattern of the patterned mask layer 128 is transferred to the gate electrode layer 125, the second dielectric layer 124 and the first dielectric layer 122 by suitable etching techniques to form the gate electrode 112 across the fin 105 (eg, Figure 1 ). The gate electrode 112 may also have a longitudinal direction substantially perpendicular to the longitudinal direction of the fin 105. Therefore, the gate electrode layer 125 is patterned into a gate electrode 126 (also referred to as a virtual gate electrode 126). A channel region 112C is formed in each fin 105. The pattern of the gate electrode 112 covers the respective channel regions 112C of the fin 105 while exposing the source / drain regions SD1 and SD2 of the fin 105 (as shown in FIG. Figure 1 ). In some embodiments, the gate electrode 112 in the input / output region may have a size and pitch that is greater than the size and pitch of the gate electrode 112 in the logic region. As will be described below, the gate electrode 112 acts as a dummy gate electrode or sacrificial gate electrode and is subsequently replaced by a replacement gate. In other embodiments, portions of the dummy gate electrode 112 (e.g., dielectric layers 122 and 124) are not replaced during formation of the replacement gate, but remain in the final structure of the semiconductor device 100.

[0038] Fig. 10A and Fig. 10BA dielectric layer 132D is shown formed on the gate electrode 112, the isolation region 114, and the fin 105. The dielectric layer 132D may be conformally deposited along the sidewalls and upper surface of the gate electrode 112. In some embodiments, the dielectric layer 132D may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), combinations thereof, or the like and may be formed using PVD, CVD, ALD, combinations thereof, or the like. In some embodiments, the dielectric layer 132D has a thickness between about 2 nm and about 5 nm.

[0039] refer to Fig.11A and Fig. 11B , the dielectric layer 132D is etched to form a gate spacer 132 along the sidewalls of the gate electrode 112. The gate electrode 112, the isolation region 114, and the horizontal portion of the dielectric layer 132D on the surface 105S of the fin 105 are removed by etching. The etching may be anisotropic, such as a dry etching or RIE process using directional ion bombardment to selectively etch the horizontal portion of the dielectric layer 132D while leaving the vertical portion substantially intact. However, this bombardment may further damage the surface 105S of the fin 105 that serves as part of the channel region or source / drain region of the semiconductor device 100. Dangling bonds may remain in the lattice structure (e.g., around the surface 105S of the fin 105) due to the bombardment and may need to be passivated.

[0040] Fig. 12A and Fig. 12B Another dielectric layer 134 is shown formed on the gate electrode 112, the gate spacer 132 and the fin 105. The dielectric layer 134 may be conformally deposited along the sidewalls and upper surface of the gate electrode 112 and laterally surround the gate spacer 132. In some embodiments, the gate spacer 132 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), combinations thereof, or the like and may be formed using CVD, ALD, combinations thereof, or the like. In the depicted embodiment, the dielectric layers 132D and 134 are formed of different materials, such as silicon nitride and silicon oxide, respectively. In some embodiments, the dielectric layer 134 has a thickness between about 2 nm and about 4 nm.

[0041] During the formation of the dielectric layer 134, the properties of the surface 105S of the fin 105 are modified by depositing the material of the dielectric layer 134. Due to the different material compositions of the fin 105 and the dielectric layer 134, the surface 105S may be altered, i.e., more dangling bonds occur around the surface 105S. Fig. 7A and Figure 7B In addition to the first passivation scheme for treating TRMT-1 shown in Fig.11A and Fig. 12A and Fig. 11B and Fig. 12B The method of operating the formed dangling bond and improving the performance of the semiconductor device 100 is shown.

[0042] refer to Fig.13A and Fig. 13B , an ion implantation process IMP- 1 is performed to form lightly doped source / drain (LDD) regions of the semiconductor device 100 . Fig.13A The substrate 102 is shown to include a p-type region 110P having a p-type transistor and an n-type region 110N having an n-type transistor. In some embodiments, a photoresist 140P is deposited to mask the n-type region 110N during implantation of the p-type region 110P. Fig. 11B A cross section of the fin 105 along the p-type region 110P is depicted. P-type dopants (e.g., boron or BF2) are implanted into the fin 105 during the ion implantation process IMP-1 to form a p-type LDD region 142P between adjacent gate electrodes 112. During the implantation process IMP-1, the gate electrode 112 may act as a mask to prevent (or at least reduce) dopants from being implanted into the channel region of the fin 105.

[0043] In some embodiments, at a power greater than 0.5 KeV (e.g., between 0.5 KeV and about 2 KeV) and about 1E14 atoms / cm 2 to about 2E15 atoms / cm 2 The implantation process IMP-1 is performed at a dose between 0° and 20°. In some embodiments, the implantation process IMP-1 is performed at a tilt angle α between 0° and 20°, for example, to drive the dopant to extend under the gate corner of the dummy gate electrode 112. After the implantation process, an annealing process may be performed to activate the implanted dopant. The annealing process may be performed by rapid thermal annealing (RTA) at a temperature between about 800° C. and about 1000° C., for example, 950° C.

[0044] Fig.14A and Fig. 14BThe second treatment TRMT-2 is shown. The second treatment TRMT-2 may include an ion implantation process that introduces a trap repair element into the surface 105S of the fin 105 or a damaged dielectric layer (e.g., the gate spacer 132 and the dielectric layer 134). In some embodiments, the second treatment TRMT-2 is performed simultaneously with the ion implantation process IMP-1. The passivation element supplied to the p-type LDD region 142P by the second treatment TRMT-2 can provide a strong fixed negative charge and can effectively terminate the dangling bonds around the surface of the fin 105. Therefore, the carrier mobility performance in the channel region can be improved. In some embodiments, the second treatment TRMT-2 selectively passivates the area around the edge of the gate electrode 112, such as the portion of the dielectric layers 122 and 124 and the gate spacer 132 near the LDD region 142P. This selective passivation causes the bulk and interface trap defects to be mitigated or reduced, so that the chance of irregular charge recombination due to traps is reduced.

[0045] The second treatment TRMT-2 may implant a dopant having a dopant type opposite to that of the ion implantation process IMP-1 (e.g., an n-type dopant). In one embodiment, the second treatment TRMT-2 uses a dopant having a negative charge greater than that of silicon or oxygen to obtain better passivation performance. For example, the second treatment TRMT-2 uses a fluorine-containing gas, such as NF3, HF, SF6, CF4, and C3F8. The gas flow of the fluorine gas is in the range between about 10 sccm and about 100 sccm. In some embodiments, the second treatment TRMT-2 is performed at an RF power between, for example, about 0.5 KeV and about 2.0 KeV. In some embodiments, the RF power used by the second treatment TRMT-2 is less than the power used by the ion implantation process IMP-1 so as not to interfere with the properties of the p-type LDD region 142P. Similarly, in some embodiments, the second treatment TRMT-2 is performed at a dose substantially equal to or less than the dose used in the ion implantation process IMP-1 to cause the trap repair dopant to reach a relatively shallow depth around the surface 105S and maintain the properties of the LDD region 142P. The trap repair dopant is implanted to reach a desired shallow depth around the surface 105S by appropriately controlling the implantation parameters, such as the implantation dose and the implantation tilt angle in the second process TRMT-2. For example, in some embodiments, the second process TRMT-2 utilizes approximately 5E14 atoms / cm 2 to about 1.5E15 atoms / cm 2 In some embodiments, the ion implantation of the second process TRMT-2 is performed at a tilt angle β between about 10° and about 30°. Using an implantation dose in excess of about 5E14 atoms / cm 2Implantation with a dose ranging between about 1.5E15 atoms / cm2 or a tilt angle β greater than about 30° or less than 10° does not ensure that the dopant is implanted at the desired location and depth. In some embodiments, the ion implantation of the second process TRMT-2 is performed for a duration that is less than the duration used in ion implantation IMP-1 and may be, for example, between about 0.5 seconds and about 300 seconds.

[0046] refer to Fig.15A and Fig. 15B , a dielectric layer 136 is blanket formed on the p-type region 110P, for example, formed on the dielectric layer 134, the gate electrode 112, and the fin 105. In some embodiments, the dielectric layer 136 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), combinations thereof, or the like and may be formed using CVD, ALD, combinations thereof, or the like. In some embodiments, the dielectric layers 134 and 136 include different materials. In some embodiments, the dielectric layer 136 includes the same material as the gate spacer 132. The dielectric layer 136 may also refer to another gate spacer and its thickness may be used to control the width of the epitaxial source / drain regions subsequently formed in the fin 105. In some embodiments, the dielectric layer 136 has a thickness between about 5 nm and about 10 nm.

[0047] Forming dielectric layer 136 on dielectric layer 134 introduces bulk traps and interface traps around dielectric layer 136. The present disclosure provides a solution to mitigate trap defects and improve device performance.

[0048] FIG. 16A to FIG. 18B The epitaxial source / drain regions (eg Figure 1 The regions SD1 and SD2 in FIG. 1 are formed in the p-type region 110P. Fig.16A and Fig. 16B A patterned mask (not shown) is first formed on the gate electrode 112 and exposes the source / drain regions in the LDD region 142P. In some embodiments, the patterned mask layer may include a photoresist or the like, and may be formed using a spin coating process or the like.

[0049] Once the patterned mask is formed, a patterning process is performed on the dielectric layers 136 and 134 and the fin 105 to form a recess 144P in the LDD region 142P. In some embodiments, the patterning process may include one or more suitable etching processes using the patterned mask as an etching mask. The etching process may be anisotropic and may include reactive ion etching (RIE), neutral particle beam etching (NBE), a combination thereof, or the like. In some embodiments, the sidewall portion of the dielectric layer 136 is not completely removed during the patterning of the recess 144P, and the width of the recess 144P is defined by the dielectric layer 136. In some embodiments, a multi-step etching operation is performed to shape the recess 144P to have a desired bottom shape, such as a U-shape or a V-shape. After the recess 144P is formed, the patterned mask is stripped by an ashing or wet cleaning step.

[0050] Then, if Fig.17A and Fig. 17B , a cleaning step CLN is performed on the recess 144P. Exemplary cleaning steps include using hydrofluoric acid (HF), triborate ethylenediaminetetraacetic acid (TBE), buffered oxide etching (BOE), the like, or a combination thereof. In some embodiments, some material loss of the fin 105 or further recessing effect on the recess 144P may occur due to the etching effect of the cleaning operation CLN. This in turn causes surface defects and / or body traps to occur in the fin 105 and dielectric layers 134 and 136.

[0051] refer to Fig.18A and Fig.18B , corresponding to Figure 1 The epitaxial source / drain regions 146P of the source / drain regions SD1 and SD2 in the p-type transistor are formed in the recess 144P. In some embodiments, the epitaxial source / drain regions 146P are epitaxially grown in the recess 144P using metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), combinations thereof, or the like. In some embodiments, the epitaxial source / drain regions 146P of the p-type transistor may include SiGe, SiGeB, Ge, GeSn, or the like. Fig.18B , the surface of the epitaxial source / drain region 146P may be raised from the surface 105S and may include facets. In some embodiments, the bottom of the epitaxial source / drain region 146P extends into the semiconductor strip 103 through the LDD region 142P. In the illustrated embodiment, each of the epitaxial source / drain regions 146P is physically separated from each other, however, in other embodiments, adjacent epitaxial source / drain regions 146P on the same side of the gate electrode 112 (e.g., Figure 1Two adjacent source / drain regions SD1 in the gate electrode 112 may merge along the sidewalls of the gate electrode 112. In some embodiments, the material of the epitaxial source / drain regions 146P may be doped in a doping process similar to the process used to form the LDD regions 142P.

[0052] After forming the epitaxial source / drain regions 146P, the remaining portion of the dielectric layer 136 is removed, as shown in FIG. Fig.19A and Fig.19B In some embodiments, the dielectric layer 136 may be removed using a suitable etching process that is selective to the material of the dielectric layer 136. Once the p-type epitaxial source / drain regions 146P are formed, the photoresist 140P may be stripped using an ashing or wet etching process.

[0053] FIG. 20A to FIG. 21B Epitaxial source / drain regions 146N are shown formed in the n-type region 110N of the semiconductor device 100 . Fig. 20B and Fig.21B is taken along the cross section BB in the fin 105 of the n-type region 110N. Unless otherwise specified, Fig. 20A , Fig. 20B , Fig.21A and Fig.21B The configurations, materials, and methods for forming epitaxial source / drain regions 146N in n-type region 110N are similar to their counterparts in p-type region 110P. Fig. 20A and Fig. 20B , the photoresist 140N is used to mask the p-type region 110P while exposing the n-type region 110N. An ion implantation step (IMP-2, not shown) and a third process TRMT-3 are subsequently or simultaneously performed to form an n-type LDD region 142N in the fin 105. These steps are similar to the steps of FIG. 1 except that the n-type LDD region 142N is an n-type dopant (such as arsenic, phosphorus, or the like). FIG. 13A to FIG. 14B The steps shown in .

[0054] The third treatment TRMT-3 may include an implantation process of trap repair elements that passivate the surface 105S of the fin 105, the gate spacer 132, the LDD region 142N, or the dielectric layer 134. The passivation ions supplied by the third treatment TRMT-3 toward the LDD region 142N may provide a strong fixed negative charge and may effectively terminate dangling bonds around the surface 105S. In some embodiments, the third treatment TRMT-3 selectively passivates the area around the edge of the gate electrode 112 (e.g., portions of the gate spacer 132 and the dielectric layer 134 near the LDD region 142N), wherein body and interface trap defects are mitigated or reduced, so that the chance of irregular charge recombination due to trap defects is reduced.

[0055] The third treatment TRMT-3 may implant a dopant of a dopant type (e.g., an n-type dopant) similar to that of the dopant of the ion implantation process of the n-type LDD region 142N. In one embodiment, the third treatment TRMT-3 uses a dopant having a negative charge greater than that of silicon or oxygen to obtain better passivation performance. For example, the third treatment TRMT-3 uses a fluorine-containing gas, such as NF3, HF, SF6, CF4, and C3F8. The gas flow of fluorine gas is in the range of about 10 sccm to about 100 sccm. In some embodiments, the third treatment TRMT-3 is performed with an RF power between, for example, about 0.5 KeV to about 2.0 KeV. In some embodiments, the RF power used by the third treatment TRMT-3 is less than the power used in the ion implantation process IMP-2 so as not to interfere with the properties of the LDD region 142N. Similarly, in some embodiments, the ion implantation of the third treatment TRMT-3 utilizes about 5E14 atoms / cm 2 to about 1.5E15 atoms / cm 2 105S and maintain the properties of LDD region 142N. In some embodiments, the third process TRMT-3 is performed using a tilted implant having a tilt angle between about 10° and about 30°. In some embodiments, the third process TRMT-3 is performed for a duration between about 0.5 seconds and about 300 seconds.

[0056] Fig.21A and Fig.21B The result of forming dielectric layer 136, etching recess 144N in fin 105, cleaning recess 144N, epitaxially growing source / drain region 146N in recess 144N, and removing dielectric layer 136 is shown. The above steps are similar to those of FIG. 1 except that the dopant of n-type LDD region 142N is an n-type dopant (e.g., arsenic, phosphorus, or the like). FIG. 15A to FIG. 19B After removing the dielectric layer 136, Fig.21A and Fig.21B The formed semiconductor device 100 in the n-type region 110N shown in FIG. Fig.19A and Fig.19B Once the n-type epitaxial source / drain regions 146N are formed, the photoresist 140N may be stripped using an ashing or wet etching process.

[0057] Fig.22A and Fig. 22B Removal of the dielectric layer 134 in both the p-type region 110P and the n-type region 110N after forming the epitaxial source / drain regions 146P and 146N is demonstrated. Fig. 22BA cross-sectional view of p-type region 110P is depicted as an example. In some embodiments, dielectric layer 134 may be removed using a suitable etching process that is selective to the material of dielectric layer 134 .

[0058] refer to Fig.23A and Fig. 23B , a p-type implantation operation is performed on the p-type source / drain region 146P to form a P+ doped region 148P. A photoresist 150P is deposited to shield the n-type region 110N and expose the p-type region 110P. The photoresist 150P may be patterned to expose only the source / drain region 146P. The implantation operation may produce a P+ doped region 148P having a doping concentration greater than the doping concentration of the underlying source / drain region 146P to improve the electrical properties of the source / drain region 146P. The doped region 148P may cover the entire upper surface of the respective source / drain region 146P. In some embodiments, the P+ doped region 148P has approximately 1E20 atoms / cm 3 to about 3E21 atoms / cm 3 The photoresist 150P may be stripped after forming the P+ doping region 148P.

[0059] Similarly, refer to Fig.24A and Fig. 24B , an n-type implantation operation is performed on the n-type source / drain region 146N to form an N+ doped region 148N. A photoresist 150N is deposited to shield the p-type region 110P and expose the source / drain region 146N in the n-type region 110N. The implantation operation may produce a doped region 148N having a doping concentration greater than the doping concentration of the underlying source / drain region 146N to improve the electrical properties of the source / drain region 146N. The doped region 148N may cover the entire upper surface of the respective source / drain region 146N. In some embodiments, the doped region 148N has approximately 1E20 atoms / cm 3 to about 3E21 atoms / cm 3 The photoresist 150N may be stripped after forming the N+ doped region 148N.

[0060] Fig.25A and Fig.25BAn annealing operation ANL is shown performed on the entire semiconductor device 100. The annealing operation ANL may help activate dopants in the doped regions 148P and 148N. The annealing operation ANL may include an RTA or furnace anneal. In some embodiments, the annealing operation ANL includes a furnace anneal of less than about 5 hours and may be an RTA anneal of less than about 10 minutes. In one embodiment, the annealing operation ANL is performed until the implant damage is reduced to a predetermined amount in the doped regions 148P and 148N. The annealing operation ANL may be performed at a temperature greater than about 900° C., such as 1050° C. The annealing operation ANL may be performed in an inert gas such as argon or nitrogen.

[0061] refer to Fig.26A and Fig.26B , an interlayer dielectric (ILD) layer is formed on the gate electrode 112 , the epitaxial source / drain regions 146P and 146N, and the fin 105 . Fig.26B A cross-sectional view showing a p-type region as an example (which is also applicable to Fig.27B , Fig.28B , Fig.29B , Fig. 30B , Fig.31B , Fig.32B and Fig.33B ). An ILD layer 151 may be deposited to fill the space between the gate electrode 112 and the fin 105. In some embodiments, the ILD layer 151 is formed of a dielectric material such as silicon oxide, SiOC, ZrO2, HfO2, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low-k dielectric material, ultra-low-k dielectric material, high-k dielectric material, combinations thereof, or the like and may be deposited by any suitable method such as CVD, PECVD, spin-on coating, combinations thereof, or the like.

[0062] In some embodiments, one or more additional dielectric layers (not shown) are deposited on the gate electrode 112, the epitaxial source / drain regions 146P and 146N, and the fin 105 before forming the ILD layer 151. These dielectric layers may be used as etch stop layers or capping layers when patterning the ILD layer 151 to etch openings for subsequently formed contact plugs. In some embodiments, some of these dielectric layers may be formed in a conformal manner using materials and methods similar to those used in forming the dielectric layers 132D or 134.

[0063] refer to Fig.27A and Fig.27BA planarization process (eg, CMP or mechanical grinding) may be performed to make the top surface of the ILD layer 151 flush with the top surface of the gate electrode 112. In some embodiments, the planarization process also removes portions of the patterned mask layer 128 or the gate spacers 132 extending over the top surface of the planarized gate electrode 112.

[0064] Fig.28A and Fig.28B and Fig.29A and Fig.29B The gate replacement process for forming the replacement gate 172 is shown. First, Fig.28A and Fig.28B , one or more suitable etching processes are used to remove the patterned mask layer 128 and the patterned gate electrode 126 of the dummy gate electrode 112 to form an opening 160. Each of the openings 160 exposes a respective underlying dielectric layer 124. In the illustrated embodiment, the dielectric layers 124 and 122 of the replacement gates 172A and 172B (acting as a high-k dielectric layer and a gate dielectric layer (interface layer) respectively) remain on the channel region of the fin 105 during the etching operation. In other embodiments, the dielectric layers 122 and 124 may also be removed during the formation of the openings 160 and may be deposited in place in subsequent steps. In embodiments where the dielectric layers 122 and 124 are also removed, these layers may be conformally deposited into the openings 160, and the materials and methods of forming these layers are similar to those of reference 105. Fig. 6A and Figure 6B Materials and methods depicted.

[0065] The capping layer 152P or 152N is formed on the gate dielectric layer 124 in the p-type region 110P or the n-type region 110N, respectively. In some embodiments, the capping layer 152P or 152N is formed along the sidewalls and bottom of the opening 160 to any suitable thickness by any suitable process. For example, the capping layer 152P or 152N is formed by an ALD or PVD process to, for example, about 100 Å. to about The capping layer 152P or 152N may include titanium, titanium nitride, tantalum, tantalum nitride, other suitable materials, or combinations thereof.

[0066] Work function layers 154P and 154N are formed on capping layers 152P and 152N, respectively. In an embodiment of an n-type transistor in n-type region 110N, work function layer 154N includes Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, or the like and may be formed along the sidewalls and bottom of opening 160 using ALD, CVD, PVD, combinations thereof, or the like. In an embodiment of a p-type transistor in p-type region 110P, work function layer 154P includes TiN, WN, TaN, Ru, Co, combinations thereof, or the like and may be formed along the sidewalls and bottom of opening 160 using ALD, CVD, PVD, combinations thereof, or the like. After forming work function layers 154P and 154N, opening 160 is filled with conductive layer 156P or 156N. In some embodiments, the conductive layer 156P or 156N includes Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, or the like and can be formed using ALD, CVD, PVD, electroplating, combinations thereof, or the like.

[0067] After the opening 160 is filled with the capping layers 152P and 152N, the work function layers 154P and 154N, and the conductive layers 156P and 156N, a planarization process (e.g., a CMP process) may be performed to remove excess portions of these layers on the top surface of the ILD layer 151. The dielectric layers 122 and 124, the capping layers 152P or 152N, the work function layers 154P or 154N, and the conductive layers 156P or 156N together form respective replacement gates 172.

[0068] refer to Fig. 30A and Fig. 30B , another ILD layer 161 is formed on the replacement gate 172 and the ILD layer 151. In some embodiments, a similar method to that used to form the reference Fig.26A and Fig.26B The materials and methods of the described ILD layer 151 are used to form the ILD layer 161. In some embodiments, the ILD layers 151 and 161 are formed of the same material. In other embodiments, the ILD layers 151 and 161 are formed of different materials. A planarization process (e.g., a CMP process) may be performed to remove excess portions of the ILD material to form a top surface of the ILD layer 161.

[0069] Then, if Fig.31A and Fig.31B, the ILD layers 151 and 161 are patterned to form openings 162G and 162SD. In some embodiments, suitable photolithography and etching techniques may be used to pattern the ILD layers 151 and 161. The opening 162G exposes the respective replacement gates 172 in the p-type region 110P or the n-type region 110N. The opening 162SD exposes the epitaxial source / drain regions 146P and 146N in the respective p-type region 110P and the n-type region 110N.

[0070] In some embodiments, a salicide layer (not shown) is formed in the openings 162G and 162SD. The silicide layer may be formed by depositing a metal material in the openings 162G or 162SD and then performing an annealing operation. The metal material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, combinations thereof, or the like and may be formed using PVD, sputtering, or the like. The metal silicide layer is formed by reacting silicon in the source / drain region with the metal material during the annealing operation.

[0071] refer to Fig.32A and Fig.32B , conductive material is deposited into openings 162G and 162SD to form contact plugs 164G and 164SD, respectively. Contact plugs 164G and 164SD are electrically coupled to replacement gate 172 and source / drain regions 146P / 146N, respectively, through the silicide layer. In some embodiments, contact plugs 164G and 164SD may include a liner and a filling layer on the liner. The liner may serve as a diffusion barrier or an adhesion layer between the ILD layer 151 / 161 and the filling layer. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or the like and may be formed using CVD, PVD, ALD, a combination thereof, or the like. The filling layer may be copper, copper alloy, silver, gold, tungsten, aluminum, nickel, a combination thereof, or the like and may be formed using CVD, PVD, ALD, an electrochemical plating process, an electroless plating process, a combination thereof, or the like.

[0072] A planarization process (eg, a CMP process) may be performed to remove excess portions of the liner and the filling layer from the top surface of the ILD layer 161. The remaining portions of the liner and the filling layer form contact plugs 164G and 164SD.

[0073] refer to Fig.33A and Fig.33B, a fourth process TRMT-4 is performed in which a trap repair element is used to repair a trap defect that has been caused by a previous operation of the formed semiconductor device 100. In some embodiments, a trap defect may occur in any layer or on a layer surface of the semiconductor device 100 after the processes of the previous processes TRMT-1, TRMT-2, and TRMT-3, and thus the fourth process TRMT-4 is used to passivate the remaining or new defects. In some embodiments, the trap repair element of the fourth process TRMT-4 has a negative electronegativity less than the negative electronegativity of the trap repair element of the second or third process (TRMT-2 or TRMT-3), while having a better penetration ability to pass through various layers to the vicinity of the channel region where the trap resides to terminate the dangling bond. In some embodiments, the trap repair element of the fourth process TRMT-4 has an atomic weight less than the atomic weight of the trap repair element in the previous trap repair processes TRMT-1 to TRMT-3 to obtain a better penetration ability. In some embodiments, the fourth process TRMT-4 adopts annealing with a H2 atmosphere. In one embodiment, annealing using a hydrogen-containing gas at a high pressure level, for example, between about 10 atm and about 20 atm, is performed in the fourth process TRMT-4. In some embodiments, the fourth process TRMT-4 is performed at a temperature (for example, 700° C. or less) less than the temperature used in the second process TRMT-2 or the third process TRMT-3 so as not to interrupt the newly formed trap repair elements to terminate the dangling bonds. In some embodiments, the fourth process TRMT-4 is performed at a temperature (for example, 500° C. or less). In some embodiments, the fourth process TRMT-4 is performed at a temperature (for example, 400° C. or less).

[0074] In embodiments where an annealing operation (e.g., an annealing step for forming a silicide layer at a high temperature greater than the temperature used in the fourth process TRMT-4) is not employed during the formation of the contact plugs 164G and 164SD, or a high-temperature anneal (e.g., greater than approximately 400° C., approximately 500° C., or approximately 700° C.) is not performed when forming the contact plugs 164G and 164SD, the fourth process TRMT-4 may be performed in real time after forming / planarizing the ILD layer 161 and before forming the silicide layer or the contact plugs 164G and 164SD.

[0075] According to one embodiment, a method of manufacturing a semiconductor device includes: providing a substrate including a surface; depositing a first dielectric layer and a second dielectric layer on the substrate; forming a dummy gate electrode on the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly doped source / drain (LDD) regions on both sides of the gate spacer in the substrate; forming source / drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; forming an interlayer dielectric (ILD) layer on the replacement gate and the source / drain regions; and performing a treatment by introducing a trap repair element into at least one of the gate spacer, the second dielectric layer, the surface, and the LDD region before forming the source / drain region or at a time after forming the ILD layer.

[0076] According to one embodiment, a method for manufacturing a semiconductor device includes: providing a substrate including a surface; depositing a high-k dielectric layer on the substrate; forming a virtual gate electrode on the high-k dielectric layer; forming a gate spacer surrounding the virtual gate electrode; forming lightly doped source / drain (LDD) regions on both sides of the gate spacer in the substrate; forming source / drain regions in the respective LDD regions; forming a replacement gate and removing the dummy gate electrode; forming a contact plug electrically coupled to the replacement gate and the source / drain region; and performing a trap repair operation on at least one of the high-k dielectric layer, the gate spacer, the surface, and the LDD region before forming the dummy gate electrode or after forming the LDD region.

[0077] According to one embodiment, a method of manufacturing a semiconductor device includes: providing a substrate including a surface; depositing a first dielectric layer and a high-k dielectric layer on the substrate; passivating the high-k dielectric layer using a nitrogen-containing plasma; forming a patterned dummy gate on the substrate after passivating the high-k dielectric layer; forming a second dielectric layer on the dummy gate and a channel region; etching a portion of the second dielectric layer contacting the channel region; forming a lightly doped source / drain (LDD) region on both sides of the patterned dummy gate in the substrate; using a dielectric having a large The invention relates to a method for forming a first gate electrode and a second gate electrode in a first annealing process. The method comprises the steps of: performing ion implantation on the LDD region with an element having a negative charge than silicon and oxygen; forming a source / drain region in the respective LDD region; performing ion implantation on the source / drain region; performing a first annealing operation on the ion-implanted source / drain region at a first temperature; forming a replacement gate by etching the patterned dummy gate; forming an interlayer dielectric layer on the source / drain region and the replacement gate; and performing a second annealing operation in a hydrogen atmosphere at a second temperature lower than the first temperature after the first annealing operation.

[0078] The features of several embodiments have been summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions should not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

[0079] [Explanation of Symbols]

[0080] 100 Semiconductor devices / FinFET devices

[0081] 102 Substrate

[0082] 103 Semiconductor Strip

[0083] 104 Mask

[0084] 104A first mask layer

[0085] 104B second mask layer

[0086] 105 Fins

[0087] 105S upper surface

[0088] 108 gate dielectric layer

[0089] 110N n-type region

[0090] 110P p-type region

[0091] 112 Gate electrode

[0092] 112C Channel area

[0093] 114 Isolation Area

[0094] 122 first dielectric layer

[0095] 124 second dielectric layer

[0096] 125 gate electrode layer

[0097] 126 Virtual gate electrode

[0098] 127 Mask layer

[0099] 128 patterned mask layer

[0100] 132 Gate spacer

[0101] 132D Dielectric layer

[0102] 134 Dielectric layer

[0103] 136 Dielectric layer

[0104] 140N Photoresist

[0105] 140P Photoresist

[0106] 142N n-type lightly doped source / drain (LDD) regions

[0107] 142P p-type LDD region

[0108] 144N Groove

[0109] 144P Groove

[0110] 146N epitaxial source / drain regions

[0111] 146P Epitaxial source / drain regions

[0112] 148N N+ doped region

[0113] 148P P+ doped region

[0114] 150N Photoresist

[0115] 150P Photoresist

[0116] 151 Interlayer Dielectric (ILD) Layer

[0117] 152N Cover

[0118] 152P Cover

[0119] 154N work function layer

[0120] 154P work function layer

[0121] 156N Conductive layer

[0122] 156P Conductive layer

[0123] 160 Opening

[0124] 161 ILD layer

[0125] 162G Open

[0126] 162SD Opening

[0127] 164G Contact Plug

[0128] 164SD Contact Plug

[0129] 172 Replacement gate

[0130] 172A Replacement Gate

[0131] 172B Replacement Gate

[0132] AA Section

[0133] BB Section

[0134] ANL Annealing Operation

[0135] CLN Cleaning Procedure

[0136] IMP-1 Ion Implantation Process

[0137] IMP-2 Ion Implantation Process

[0138] SD1 Source / Drain Region

[0139] SD2 Source / Drain Region

[0140] TRMT-1 First Treatment

[0141] TRMT-2 Second Treatment

[0142] TRMT-3 Third Treatment

[0143] TRMT-4 Fourth Treatment

[0144] α Tilt angle

[0145] β Tilt angle

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate including a surface; depositing a first dielectric layer and a second dielectric layer on the substrate; forming a virtual gate electrode on the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly doped source / drain (LDD) regions on both sides of the gate spacer in the substrate; forming source / drain regions in the respective LDD regions; removing the dummy gate electrode to form a replacement gate; Forming an interlayer dielectric ILD layer on the replacement gate and the source / drain region; performing treatment by introducing a trap repair element into at least one of the gate spacer, the second dielectric layer, the surface, and the LDD region after forming the ILD layer; and After the trap repair element is introduced into the LDD region, a dielectric layer is deposited on the dummy gate and the LDD region.

2. The method according to claim 1, wherein forming a dummy gate electrode comprises: depositing a gate electrode layer on the second dielectric layer; and The gate electrode layer and the second dielectric layer are patterned into the dummy gate electrode after the processing. 3 . The method of claim 2 , wherein the treating further comprises using a nitrogen plasma to introduce nitrogen into the second dielectric layer.

4. The method of claim 3, wherein introducing nitrogen using the nitrogen plasma comprises introducing a nitrogen-containing gas at a flow rate between 10 sccm and 300 sccm. 5 . The method of claim 2 , wherein the first dielectric layer comprises silicon oxide and the second dielectric layer comprises a high-k dielectric material. 6 . The method of claim 1 , wherein performing the processing further comprises introducing the trap repair element into the LDD region, wherein the trap repair element comprises an electronegativity greater than an electronegativity of silicon or oxygen. 7 . The method of claim 6 , further comprising performing a thermal operation on the LDD region at a temperature greater than 900° C. after performing the treating. 8 . The method of claim 6 , wherein the trap repair element comprises a dopant type opposite to a dopant type of the LDD region.

9. The method of claim 6, wherein forming a lightly doped source / drain (LDD) region comprises performing a first ion implantation at a first power, and wherein introducing the trap repair element into the LDD region comprises performing an ion implantation at a second power less than the first power.

10. The method of claim 9, wherein the second power is between 0.5 KeV and 2 KeV.

11. The method of claim 6, wherein the processing comprises ion implantation with a tilt angle between 10° and 30°.

12. The method of claim 6, wherein the treatment comprises 5E14 atoms / cm 2 To 1.5E15 atoms / cm 2 The ion implantation dose is between .

13. The method of claim 1, further comprising performing a first annealing operation at a first temperature after forming the source / drain regions, wherein the treating is performed at a second temperature less than the first temperature after the first annealing operation.

14. The method of claim 13, wherein the treatment further comprises a second annealing operation performed in hydrogen at a pressure between 10 atm and 20 atm.

15. A method for manufacturing a semiconductor device, comprising: providing a substrate including a surface; depositing a high-k dielectric layer on the substrate; forming a virtual gate electrode on the high-k dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly doped source / drain (LDD) regions on both sides of the gate spacer in the substrate; forming source / drain regions in the respective LDD regions; forming a replacement gate and removing the dummy gate electrode; forming contact plugs to electrically couple to the replacement gate and the source / drain regions; performing a trap repair operation on the LDD region after forming the LDD region, wherein performing the trap repair operation after forming the LDD region comprises introducing a trap repair element into the LDD region; and After the trap repair element is introduced into the LDD region, a dielectric layer is deposited on the dummy gate and the LDD region. 16 . The method of claim 15 , wherein the trap repair element comprises a dopant type that is the same as a dopant type of the LDD region. The method of claim 16 , wherein the RF power of the trap repair operation is between 0.5 KeV and 2 KeV.

18. The method of claim 16, wherein the trap repair element comprises fluorine.

19. The method of claim 15, further comprising performing the trap repair operation at a temperature below 400°C and performing the trap repair operation after forming the replacement gate and before forming an interlayer dielectric (ILD) layer on the replacement gate, wherein the contact plug is formed within the ILD layer.

20. A method for manufacturing a semiconductor device, comprising: providing a semiconductor fin including a channel region; Depositing a first dielectric layer and a high-k dielectric layer on the semiconductor fin; passivating the high-k dielectric layer using a nitrogen-containing plasma; forming a patterned dummy gate on the semiconductor fin after passivating the high-k dielectric layer; Forming a second dielectric layer on the dummy gate and the channel region; etching a portion of the second dielectric layer contacting the channel region; Forming lightly doped source / drain (LDD) regions on both sides of the patterned dummy gate in the semiconductor fin; ion implanting the LDD region using an element having a higher electronegativity than silicon and oxygen; After introducing the element having a negative charge greater than that of silicon and oxygen into the LDD region, depositing a dielectric layer on the dummy gate and the LDD region; forming source / drain regions in the respective LDD regions; performing ion implantation on the source / drain region; performing a first annealing operation on the ion-implanted source / drain regions at a first temperature; forming a replacement gate by etching the patterned dummy gate; forming an interlayer dielectric layer on the source / drain region and the replacement gate; and After the first annealing operation, a second annealing operation is performed in a hydrogen atmosphere at a second temperature lower than the first temperature.

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