Display device

Abstract

A display device includes a substrate including a display area and an opening area in the display area; a data conductive layer on the substrate and including a source electrode in the display area and a voltage wiring in the opening area; a protective layer on the data conductive layer and covering the source electrode and the voltage wiring; a pixel electrode layer including a pixel electrode connected to the source electrode through a first contact hole and an electrode pattern connected to the voltage wiring through a second contact hole; a pixel defining layer including an opening exposing the pixel electrode and a hole exposing the electrode pattern; an emission layer on the pixel defining layer; and a common electrode on the emission layer, wherein the hole does not overlap the first contact hole and the second contact hole.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0085931, filed with the Korean Intellectual Property Office on July 16, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device that provides uniformity of the driving voltage to be applied to each of the pixels of the display device. Background Technology

[0003] Electronic devices that provide images to users (such as televisions, smartphones, tablet PCs, digital cameras, laptops, and navigation devices) include display devices used to display images.

[0004] Display devices may include display panels such as organic light-emitting display panels or liquid crystal display panels as devices for displaying images. Among these display panels, light-emitting display panels may include light-emitting elements such as light-emitting diodes (LEDs). Examples of LEDs may include organic LEDs that use organic materials as fluorescent materials and inorganic LEDs that use inorganic materials as fluorescent materials.

[0005] Such a display device may include a display panel, a gate driving circuit, a data driving circuit, and a timing controller. The display panel may include data lines, gate lines, and pixels formed at the intersections of the data lines and the gate lines. By using thin-film transistors as switching elements, each pixel can receive a data voltage from the data lines when a gate signal can be supplied to the gate lines. Each pixel can then emit light at a predetermined brightness level based on the data voltage.

[0006] Display devices capable of displaying ultra-high definition (UHD) images continue to be developed. Because high-resolution display devices can include multiple pixels, the driving voltage applied to each pixel may be uneven. As a result, low voltage may be applied to some pixels. Summary of the Invention

[0007] This disclosure provides a display device that may include an electrode pattern having the same potential as the power supply voltage and being in contact with a common electrode.

[0008] However, the aspects of this disclosure may not be limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the following detailed description.

[0009] According to embodiments of the present disclosure, a display device may include: a substrate including a display area and an opening area located in the display area; a data conductive layer disposed on the substrate and including a source electrode disposed in the display area and a voltage wiring disposed in the opening area; a protective layer disposed on the data conductive layer and covering the source electrode and the voltage wiring; a planarization layer disposed on the protective layer; a pixel electrode layer disposed on the planarization layer and including a pixel electrode connected to the source electrode through a first contact hole penetrating the planarization layer and the protective layer, and an electrode pattern connected to the voltage wiring through a second contact hole penetrating the planarization layer and the protective layer; a pixel defining layer disposed on the planarization layer and the pixel electrode layer, and including an opening exposing a portion of the pixel electrode and a hole at least partially exposing the electrode pattern; a light-emitting layer disposed on the pixel defining layer; and a common electrode disposed on the light-emitting layer, wherein the hole does not overlap with the first contact hole and the second contact hole in the thickness direction of the display device.

[0010] The electrode pattern may include: a first extension having a first width and a protrusion extending from one side of the first extension having a width less than the first width.

[0011] The first width of the first extended portion of the electrode pattern can be greater than the second width of the hole.

[0012] The second width of the hole can be greater than the third width of the second contact hole.

[0013] The third width of the second contact hole may be different from the fourth width of the first contact hole.

[0014] The hole can overlap with the first extended portion of the electrode pattern in the thickness direction of the display device.

[0015] The second contact hole can overlap with the protruding part of the electrode pattern in the thickness direction of the display device.

[0016] The electrode pattern can be made to not overlap with the first contact hole in the thickness direction of the display device.

[0017] The voltage wiring may include: a second extension portion that overlaps with the first extension portion in the thickness direction of the display device and a first extension portion extending from one side of the second extension portion, and the second contact hole may overlap with the first extension portion of the voltage wiring in the thickness direction of the display device.

[0018] The electrode pattern may include: a first electrode pattern, at least a portion of which is exposed by a hole; and a second electrode pattern not exposed by a hole, wherein a common electrode may contact the first electrode pattern but not the second electrode pattern.

[0019] The light-emitting layer can be arranged between the common electrode and the pixel electrode exposed by the opening, and can be arranged outside the first electrode pattern exposed by the hole.

[0020] The voltage wiring may include: a first voltage wiring connected to a first electrode pattern and a second voltage wiring connected to a second electrode pattern.

[0021] The data conductive layer may include: a first data conductive layer and a second data conductive layer disposed on the first data conductive layer, and the protective layer may include: a first protective layer disposed between the first data conductive layer and the second data conductive layer and a second protective layer disposed between the second data conductive layer and the planarization layer.

[0022] The second data conductive layer can be connected to the first data conductive layer through a third contact hole that penetrates the first protective layer.

[0023] The third contact hole can be designed not to overlap with the second contact hole in the thickness direction of the display device.

[0024] The pixel electrode can contact the source electrode of the second data conductive layer through the first contact hole, and the electrode pattern can contact the voltage wiring of the second data conductive layer through the second contact hole.

[0025] The display device may include: a first electrode pad disposed on a second protective layer and a second data conductive layer and in contact with a source electrode of the second data conductive layer; and a second electrode pad disposed on the second protective layer and the second data conductive layer and in contact with a voltage wiring of the second data conductive layer, wherein a pixel electrode may contact the first electrode pad and an electrode pattern may contact the second electrode pad.

[0026] According to another embodiment of this disclosure, a display device may include: a plurality of pixels, each of the plurality of pixels defining an opening region; voltage wiring disposed in the opening region of the plurality of pixels and including: a first extension portion and a first extension portion extending from one side of the first extension portion; an electrode pattern disposed in the opening region of the plurality of pixels and including a second extension portion overlapping the first extension portion in the thickness direction of the display device and a protrusion portion protruding from one side of the second extension portion; a pixel defining layer disposed on the second extension portion of the electrode pattern and including a hole exposing at least a portion of the second extension portion; and a common electrode disposed on the pixel defining layer and in contact with the exposed second extension portion of the electrode pattern, wherein the voltage wiring and the electrode pattern may be connected to each other through contact holes, and the contact holes and the holes do not overlap each other in the thickness direction of the display device.

[0027] The width of the hole can be smaller than the width of the second extension of the electrode pattern and larger than the width of the contact hole.

[0028] The contact hole may overlap with the protruding portion of the electrode pattern and the first extension of the voltage wiring, and the protruding portion of the electrode pattern may be connected to the first extension of the voltage wiring. Attached Figure Description

[0029] The above and other features and advantages of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0030] Figure 1 A plan view of a display device according to an embodiment is shown;

[0031] Figure 2 A schematic cross-sectional view of a display device according to an embodiment is shown;

[0032] Figure 3 A schematic layout diagram of the circuit layer of a first display substrate of a display device according to an embodiment is shown;

[0033] Figure 4 A schematic diagram of the equivalent circuit of a pixel of a display device according to an embodiment is shown;

[0034] Figure 5 A layout diagram of a pixel of a display device according to an embodiment is shown;

[0035] Figure 6 Showing includes Figure 5 The layout diagram of the semiconductor layer and some conductive layers in the pixel;

[0036] Figure 7 Showing includes Figure 5 A layout diagram of some conductive layers in the pixels;

[0037] Figure 8 Show along Figure 5 A schematic cross-sectional view of line IX-IX';

[0038] Figure 9 Show Figure 5 A magnified view of the opening area;

[0039] Figure 10 Show along Figure 9 A schematic cross-sectional view of the line X-X'.

[0040] Figure 11 Showing includes Figure 5 A schematic planar view of the light-emitting layer in a pixel;

[0041] Figure 12A schematic plan view showing a light-emitting layer arranged in a pixel according to an embodiment;

[0042] Figure 13 Show Figure 12 A schematic cross-sectional view of the opening region of a single pixel;

[0043] Figures 14 to 21 A schematic cross-sectional view showing a method for manufacturing a display device according to an embodiment; and

[0044] Figure 22 A schematic cross-sectional view of a first display substrate of a display device according to an embodiment is shown. Detailed Implementation

[0045] Embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, embodiments may be embodied in different forms and should not be construed as limited to the description of the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on that other layer or substrate, or there may be an intermediate layer. Throughout the disclosure, the same reference numerals denote the same components. The terms "on" or "above" mean located on or below the object portion and do not necessarily mean located on the upper side of the object portion based on the direction of gravity.

[0047] It will be understood that although the terms “first,” “second,” etc., may be used in this text to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this text, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0048] Furthermore, since the dimensions and thicknesses of the constituent components shown in the accompanying drawings can be arbitrarily given for better understanding and ease of description, the embodiments are not limited to the dimensions and thicknesses illustrated. In the drawings, the thicknesses of layers, films, panels, regions, etc., may be exaggerated for clarity. In the drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0049] Unless explicitly stated otherwise, the word “including” and variations such as “comprising” or “containing” shall be understood to imply the inclusion of the stated element, rather than the exclusion of any other element. As used herein, the term “and / or” can include any and all combinations of one or more associated listed items. When following a list of elements, expressions such as “at least one of” modify the entire list of elements without modifying any individual element in the list.

[0050] Where an embodiment can be implemented differently, a particular process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0051] Taking into account the measurements discussed and the errors associated with the measured values ​​of a particular quantity (i.e., limitations of the measurement system), as used herein, "about" or "approximately" includes the value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within, for example, ±30%, 20%, or 5% of the value.

[0052] As used in this article, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0053] In the embodiments described below, it will be understood that when an element, region, or layer is referred to as being connected to another element, region, or layer, it can be directly or indirectly connected to that other element, region, or layer. For example, it will be understood that, in this specification, when an element, region, or layer is referred to as being in contact with or electrically connected to another element, region, or layer, it can be directly or indirectly in contact with or electrically connected to that other element, region, or layer.

[0054] Furthermore, the phrase "in a plan view" means when viewing a portion of an object from above, while the phrase "in a cross-sectional view" means a section taken by vertically cutting the element portion when viewed from the side. Additionally, the terms "overlapping" or "overlapping" mean that the first object can be above, below, or to the side of the second object, and vice versa. Furthermore, the term "overlapping" can include layering, stacking, facing or oriented, extending over, covering or partially covering, or any other suitable terminology known and understood by one of ordinary skill in the art. The terms "facing" and "oriented" mean that the first element can be directly or indirectly opposite the second element. In the case of a third element inserted between the first and second elements, although still facing each other, the first and second elements can be understood as indirectly opposite each other. When an element is described as "not overlapping" or "not to overlap" another element, this can include the elements being spaced apart from each other, offset from each other, or separated from each other, or any other suitable terminology known and understood by one of ordinary skill in the art. When a layer, region, substrate, or area is referred to as being "on" another layer, region, substrate, or area, it can be directly on that other layer, region, substrate, or area, or there may be an intermediate layer, region, substrate, or area therein. Conversely, when a layer, region, substrate, or area is referred to as being "directly" on another layer, region, substrate, or area, there may be no intermediate layer, region, substrate, or area therein. Furthermore, when a layer, region, substrate, or area is referred to as being "below" another layer, region, substrate, or area, it can be directly below that other layer, region, substrate, or area, or there may be an intermediate layer, region, substrate, or area therein. Conversely, when a layer, region, substrate, or area is referred to as being "directly" below another layer, region, substrate, or area, there may be no intermediate layer, region, substrate, or area therein. Furthermore, "on" or "above" can include being located on or below an object, and does not necessarily imply a direction based on gravity.

[0055] For ease of description, the spatial relative terms “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or component and another, as illustrated in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, in the case where the device illustrated in the drawings is flipped, the device located “below” or “under” another device may be placed “above” the other device. Therefore, the illustrative term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore, the spatial relative terms may be interpreted differently depending on the orientation.

[0056] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0057] Figure 1 A plan view of a display device according to an embodiment is shown.

[0058] Display device 1 may include any electronic device that provides a display screen. Display device 1 may include televisions, laptops, monitors, billboards, mobile phones, smartphones, tablet PCs, electronic watches, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, game consoles, digital cameras, and devices used in the Internet of Things, all of which may provide a display screen.

[0059] The display device 1 illustrated in the accompanying drawings may be a television. The display device 1 may have a high resolution or ultra-high resolution, such as, but not limited to, high definition (HD), ultra-high definition (UHD), 4K, or 8K.

[0060] Display device 1 can be classified differently depending on its display method. For example, display device 1 can be classified as an organic light-emitting display device, an inorganic electroluminescent (EL) display device, a quantum dot light-emitting display device (QED), a light-emitting diode (LED) display device, a plasma display panel (PDP), a field emission display device (FED), a cathode ray tube (CRT) display device, a liquid crystal display (LCD), or an electrophoretic display device (EPD). Organic light-emitting display devices can employ the display devices described herein. However, embodiments are not limited to organic light-emitting display devices. Rather, within the spirit of the art, various types of display devices mentioned above or known in the art can be employed, including or implemented with the display devices described herein.

[0061] Display device 1 can be rectangular in a plan view. In the case of display device 1, such as a television, its long side can typically be positioned horizontally. However, embodiments are not limited to this, and the long side can also be positioned vertically. In other embodiments, display device 1 can be rotatably mounted so that its long side can be variably positioned in either the horizontal or vertical direction.

[0062] Display device 1 may include a display area DPA and a non-display area NDA. The display area DPA may be an active area capable of displaying images. The display area DPA may have a rectangular planar shape similar to the overall shape of display device 1.

[0063] The display area DPA may include pixels PX. Pixels PX may be arranged in a matrix orientation or matrix form. Each of the pixels PX may be rectangular or square in a planar view. However, the shape of each pixel PX is not limited to a rectangular or square shape, and may also be a rhombus shape with each side inclined towards one side of the display device 1. Pixels PX may include pixels PX of various colors. For example, pixels PX may include red first-color pixels PX, green second-color pixels PX, and blue third-color pixels PX. Color pixels PX may be arranged in a stripe type or a honeycomb type.

[0064] The non-display area NDA can be arranged around the display area DPA. The non-display area NDA can completely or partially surround the display area DPA. The display area DPA can be rectangular, and the non-display area NDA can be arranged adjacent to the four sides of the display area DPA. The non-display area NDA can form the bezel of the display device 1.

[0065] The driving circuitry or components for driving the display area DPA can be arranged in the non-display area NDA. Pad portions can be provided on the display substrate of the display device 1 and arranged to be adjacent to the first long side of the display device 1 (e.g., ...). Figure 1 The first non-display area NDA1, which is adjacent to the lower edge of the display device 1, and the second long edge (e.g., the lower edge of the display device 1) are arranged to be adjacent to the lower edge of the display device 1. Figure 1 In the second non-display area NDA2 adjacent to the upper side of the display device 1, the external device EXD can be mounted on the pad electrode of the pad portion. The external device EXD may include a connection film, a printed circuit board, a driver chip DIC, a connector, and a wiring connection film. The scan driver SDR formed directly or indirectly on the display substrate of the display device 1 can be arranged in a position that is arranged adjacent to the first short side of the display device 1 (e.g., the upper side of the display substrate). Figure 1 In the third non-display area NDA3 adjacent to the left of the image.

[0066] Figure 2 A schematic cross-sectional view of a display device 1 according to an embodiment is shown.

[0067] exist Figure 2 In this embodiment, the display device 1 includes a top-emitting display device in which light L is emitted in the opposite direction (i.e., towards the second substrate 21) instead of towards the first substrate 1010 having the light-emitting layer EML. However, the display device 1 may not be limited to a top-emitting display device.

[0068] refer to Figure 2 The display device 1 may include an emissive layer (EML), an encapsulation layer (ENC) covering the EML, and color control structures (WCL, TPL, and CFL) disposed on the ENC. The display device 1 may include a first display substrate 10 and a second display substrate 20 facing the first display substrate 10. The EML, ENC, and color control structures (WCL, TPL, and CFL) may be included in either the first display substrate 10 or the second display substrate 20.

[0069] The first display substrate 10 may include a first substrate 1010, a light-emitting layer (EML) disposed on the surface of the first substrate 1010, and an encapsulation layer (ENC) disposed on the light-emitting layer (EML). The second display substrate 20 may include a second substrate 21 and color control structures (WCL, TPL, and CFL) disposed on the surface of the second substrate 21 facing the first substrate 1010. The color control structures WCL, TPL, and CFL may include a color filter layer (CFL) and a wavelength conversion layer (WCL). In some pixels, the color control structures WCL, TPL, and CFL may include a light-transmitting layer (TPL) disposed at the same level as the wavelength conversion layer (WCL).

[0070] The filler layer 30 can be disposed between the encapsulation layer ENC and the color control structures WCL, TPL, and CFL. The filler layer 30 can fill the space between the first display substrate 10 and the second display substrate 20 and bond the first display substrate 10 and the second display substrate 20 together.

[0071] The first substrate 1010 of the first display substrate 10 may be an insulating substrate. The first substrate 1010 may include a transparent material. For example, the first substrate 1010 may include a transparent insulating material such as glass or quartz. The first substrate 1010 may be a rigid substrate. However, the first substrate 1010 is not limited to the above. The first substrate 1010 may also include a plastic such as polyimide and may have flexible properties so that it can be bent, folded, rolled, or bent.

[0072] Pixel electrodes PXE can be disposed on the surface of the first substrate 1010. Pixel electrodes PXE can be disposed individually in pixels PX. Pixel electrodes PXE of adjacent pixels PX can be separated from each other. A circuit layer CCL for driving the pixels PX can be disposed on the first substrate 1010. The circuit layer CCL can be disposed between the first substrate 1010 and the pixel electrodes PXE. Pixel electrodes PXE can be first electrodes, such as the anode of an LED. Each of the pixel electrodes PXE can have a stacked structure in which a material layer with a high work function and a reflective material layer are stacked. The material layer with a high work function includes, but is not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and the reflective material layer includes, but is not limited to, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or mixtures thereof. A material layer with a high work function can be arranged on the reflective material layer so as to be close to the emissive layer EML. The pixel electrode PXE can have, but is not limited to, a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO.

[0073] A pixel defining layer (PDL) may be formed along the boundary of each pixel (PX) on the surface of the first substrate 1010. The PDL may be disposed on the pixel electrode (PXE) and include openings exposing the pixel electrode (PXE). The PDL and the openings may define an emitting region (EMA) and a non-emitting region (NEM). The PDL may include an organic insulating material, such as, but not limited to, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The PDL may also include inorganic materials.

[0074] The light-emitting layer (EML) can be disposed on the pixel electrode (PXE) exposed by the pixel defining layer (PDL). In embodiments where the display device 1 is an organic light-emitting display device, the EML may include an organic layer comprising organic materials. The organic layer may include an organic light-emitting layer, and in some cases, may include a hole injection / transport layer and / or an electron injection / transport layer as auxiliary layers to assist in light emission. In cases where the display device 1 is an LED display device, the EML may include inorganic materials such as inorganic semiconductors.

[0075] The emissive layer (EML) can have a tandem structure comprising organic light-emitting layers that overlap or face each other in the thickness direction and a charge-generating layer disposed between the organic light-emitting layers. The organic light-emitting layers can emit light of the same wavelength, but can also emit light of different wavelengths. At least some of the emissive layers of a pixel can be separated from their corresponding portions (or emissive layers) of adjacent pixels.

[0076] For each color pixel PX, the wavelength of light emitted from each emissive layer EML can be the same. For example, the emissive layer EML of each color pixel PX can emit blue light or ultraviolet light, and the color control structures WCL, TPL, and CFL can include a wavelength conversion layer WCL to display the color of each pixel PX.

[0077] For each color pixel PX, the wavelength of light emitted from each emissive layer EML can be different. For example, the emissive layer EML of the first color pixel PX can emit light of the first color, the emissive layer EML of the second color pixel PX can emit light of the second color, and the emissive layer EML of the third color pixel PX can emit light of the third color. The emissive layer EML can be disposed on the entire surface of the pixel electrode PXE and the pixel defining layer PDL. However, the embodiments are not limited to this, and the emissive layer EML can also be disposed corresponding to the opening of the pixel defining layer PDL, and can be disposed in areas other than the aforementioned openings.

[0078] The common electrode CME can be disposed on the emissive layer EML. The common electrode CME can contact not only the emissive layer EML, but also the upper surface of the pixel defining layer PDL.

[0079] The common electrode CME can be formed as a single electrode extending continuously over each of the pixels PX. The common electrode CME can also be an entire surface electrode disposed over the pixels PX. The common electrode CME can be a second electrode, for example, the cathode of each LED.

[0080] The common electrode CME may include a material layer having a small work function, including but not limited to Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., mixtures of Ag and Mg). The common electrode CME may include a transparent metal oxide layer disposed on the material layer having a small work function.

[0081] Each light-emitting element (e.g., each organic light-emitting element) can be composed of a pixel electrode (PXE), an emissive layer (EML), and a common electrode (CME). Light emitted from the emissive layer (EML) can be output upwards through the common electrode (CME).

[0082] The encapsulation layer ENC can be disposed on the common electrode CME. The encapsulation layer ENC can include one or more encapsulation layers. For example, the encapsulation layer can include a first inorganic layer ENC1, an organic layer ENC2, and a second inorganic layer ENC3. Each of the first inorganic layer ENC1 and the second inorganic layer ENC3 can include, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof. The organic layer ENC2 can include an organic insulating material, such as, but not limited to, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB), or combinations thereof.

[0083] The second display substrate 20 can be disposed above the encapsulation layer ENC to face the encapsulation layer ENC. The second substrate 21 of the second display substrate 20 may include a transparent material. The second substrate 21 may include a transparent insulating material such as glass or quartz. The second substrate 21 may be a rigid substrate. However, the second substrate 21 is not limited to this. The second substrate 21 may also include a plastic such as polyimide and may have flexible properties so that it can be bent, folded, rolled, or bent.

[0084] The second substrate 21 can be the same as the first substrate 1010, but it can differ from the first substrate 1010 in terms of material, thickness, transmittance, etc. For example, the second substrate 21 can have a higher transmittance than the first substrate 1010. The second substrate 21 can be thicker or thinner than the first substrate 1010.

[0085] The light-shielding member BM can be disposed along the boundary of each pixel PX on the surface of the second substrate 21 facing the first substrate 1010. The light-shielding member BM can overlap with or face the pixel defining layer PDL of the first display substrate 10, and can be located in the non-emitting region NEM. The light-shielding member BM may include openings exposing the surfaces of the second substrate 21 that overlap with or face the emitting region EMA. The light-shielding member BM can be formed in a grid shape in a plan view.

[0086] The light-shielding component BM can include organic materials. The light-shielding component BM can reduce color distortion caused by the reflection of external light by absorbing it. The light-shielding component BM can prevent light emitted from the emissive layer EML of each pixel PX from entering adjacent pixels PX.

[0087] The light-shielding component BM can absorb all visible light wavelengths. The light-shielding component BM may include light-absorbing materials. For example, the light-shielding component BM may be made of the material used as the black matrix in the display device 1.

[0088] A color filter layer CFL can be disposed on the surface of the second substrate 21 that may include a light-shielding member BM. The color filter layer CFL can be disposed on the surface of the second substrate 21 that is to be exposed through the opening in the light-shielding member BM. The color filter layer CFL can be disposed on a portion of an adjacent light-shielding member BM.

[0089] The color filter layer CFL may include a first color filter layer CFL1 disposed in a first color pixel PX, a second color filter layer CFL2 disposed in a second color pixel PX, and a third color filter layer CFL3 disposed in a third color pixel PX. Each color filter layer CFL1, CFL2, or CFL3 may include a colorant (such as a dye or pigment) that absorbs wavelengths different from the corresponding color wavelength. The first color filter layer CFL1 may be a red color filter layer, the second color filter layer CFL2 may be a green color filter layer, and the third color filter layer CFL3 may be a blue color filter layer. Adjacent color filter layers disposed on the light-shielding member BM may be spaced apart from each other, or may overlap each other or at least partially overlap each other.

[0090] A first capping layer 22 can be disposed on the color filter layer CFL. The first capping layer 22 can prevent impurities such as moisture or air from entering from the outside and damaging or contaminating the color filter layer CFL. The first capping layer 22 can prevent the colorant of the color filter layer CFL from diffusing to other components.

[0091] The first capping layer 22 can be directly or indirectly attached to the surface of the color filter layer CFL (e.g., Figure 2 The first capping layer 22 is in contact with the lower surface of the substrate. The first capping layer 22 may be made of an inorganic material. For example, the first capping layer 22 may include, but is not limited to, silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, silicon oxynitride, or combinations thereof.

[0092] The barrier layer PTL can be disposed on the first capping layer 22. The barrier layer PTL can be located in the non-emissive region NEM. The barrier layer PTL can overlap with or face the light-shielding member BM. The barrier layer PTL may include openings that expose the color filter layer CFL. The barrier layer PTL may include a photosensitive organic material. However, embodiments are not limited to this, and the barrier layer PTL may include a light-shielding material.

[0093] The wavelength conversion layer (WCL) and / or the light-transmitting layer (TPL) can be arranged in the space exposed by the opening of the barrier layer (PTL). The wavelength conversion layer (WCL) and the light-transmitting layer (TPL) can be formed by an inkjet process using the barrier layer (PTL) as a dam, but the embodiments are not limited thereto.

[0094] In an embodiment where the emissive layer EML of each pixel PX emits light of a third color, the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 disposed in the first-color pixel PX and a second wavelength conversion pattern WCL2 disposed in the second-color pixel PX. The transmissive layer TPL may be disposed in the third-color pixel PX.

[0095] The first wavelength conversion pattern WCL1 may include a first substrate resin BRS1 and a first wavelength conversion material WCP1 disposed within the first substrate resin BRS1. The second wavelength conversion pattern WCL2 may include a second substrate resin BRS2 and a second wavelength conversion material WCP2 disposed within the second substrate resin BRS2. The light-transmitting layer TPL may include a third substrate resin BRS3 and a scatterer SCP disposed within the third substrate resin BRS3.

[0096] The first substrate resin BRS1 to the third substrate resin BRS3 may comprise a light-transmitting organic material. For example, the first substrate resin BRS1 to the third substrate resin BRS3 may include, but are not limited to, epoxy resin, acrylic resin, calorie resin, imide resin, or combinations thereof. The first substrate resin BRS1 to the third substrate resin BRS3 may be made of the same material, but the embodiments are not limited to this.

[0097] The scattering component (SCP) can be a metal oxide particle or an organic particle. The metal oxide can be, for example, titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2). The organic particle can be made of acrylic resin or urethane resin.

[0098] The first wavelength conversion material WCP1 can be a material that converts a third color to a first color, and the second wavelength conversion material WCP2 can be a material that converts a third color to a second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 can be quantum dots, quantum rods, or phosphors. Examples of quantum dots may include, but are not limited to, group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, and / or combinations thereof. Each of the first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may include a scatterer SCP to increase wavelength conversion efficiency.

[0099] The light-transmitting layer (TPL) arranged within the third-color pixel (PX) transmits third-color light that can be incident from the emissive layer (EML) while maintaining the light's wavelength. The scattering component (SCP) of the TPL can modulate the emission path of the light emitted through it. The TPL may not include wavelength conversion materials.

[0100] The second capping layer 23 can be disposed on the wavelength conversion layer WCL and the light-transmitting layer TPL. The second capping layer 23 can be made of an inorganic material. The second capping layer 23 may include a material selected from those listed as example materials of the first capping layer 22. The second capping layer 23 and the first capping layer 22 may be made of the same material, but the embodiments are not limited to this.

[0101] A filler layer 30 can be disposed between the first display substrate 10 and the second display substrate 20. The filler layer 30 fills the space between the first display substrate 10 and the second display substrate 20, and bonds the first display substrate 10 and the second display substrate 20 together. The filler layer 30 can be disposed between the thin-film encapsulation layer ENC of the first display substrate 10 and the second capping layer 23 of the second display substrate 20. The filler layer 30 can be made of, but is not limited to, silicon-based organic materials or epoxy-based organic materials.

[0102] The circuit layer CCL of display device 1 will be discussed below.

[0103] Figure 3 A schematic layout diagram of the circuit layer CCL of the first display substrate 10 of the display device 1 according to an embodiment is shown.

[0104] refer to Figure 3 Wiring can be arranged on the first substrate 1010. Wiring may include scan lines SCL, sense lines SSL, data lines DTL, reference voltage lines RVL, and first power lines ELVDL. Although not shown, wiring may include second power lines.

[0105] Scan line SCL and sensing line SSL can extend in the first direction DR1. Scan line SCL and sensing line SSL can be connected to scan driver SDR. Scan driver SDR can include driving circuitry made of circuit layer CCL. Scan driver SDR can be disposed on the first substrate 1010 in a third non-display area NDA3. However, embodiments are not limited to this, and scan driver SDR can also be disposed in a fourth non-display area positioned opposite to the third non-display area NDA3, or can be disposed in both the third non-display area NDA3 and the fourth non-display area. Scan driver SDR can be connected to signal connection wiring CWL, and at least one end of signal connection wiring CWL can form a pad WPD_CW in the first non-display area NDA1 and / or the second non-display area NDA2, and thus can be connected to an external device EXD (see...). Figure 1 ).

[0106] The data line DTL and the reference voltage line RVL may extend in a second direction DR2, intersecting the first direction DR1. The first power line ELVDL may include a portion extending in the second direction DR2. The first power line ELVDL may include a portion extending in the first direction DR1. The first power line ELVDL may have a mesh structure. Although not shown, like the first power line ELVDL, the second power line may include a portion extending in the second direction DR2 and a portion extending in the first direction DR1.

[0107] Routing pads (WPDs) can be placed at at least one end of each of the data line (DTL), the reference voltage line (RVL), and the first power line (ELVDL). Each routing pad (WPD) can be placed in a non-display area (NDA). The routing pad (WPD_DT) of the data line (DTL) (hereinafter referred to as the "data pad") can be placed in the first non-display area (NDA1), and the routing pad (WPD_RV) of the reference voltage line (RVL) (hereinafter referred to as the "reference voltage pad") and the routing pad (WPD_ELVD) of the first power line (ELVDL) (hereinafter referred to as the "first power pad") can be placed in the second non-display area (NDA2). In another example, the data pad (WPD_DT), the reference voltage pad (WPD_RV), and the first power pad (WPD_ELVD) can all be placed in the same area, for example, in the first non-display area (NDA1). External device (EXD) (see...) Figure 1 External devices (EXDs) can be mounted on the wiring pads (WPD). External devices (EXDs) can be mounted on the wiring pads (WPD) via anisotropic conductive films, ultrasonic bonding, etc.

[0108] Each pixel PX on the first substrate 1010 may include a pixel driving circuit. The aforementioned wiring may pass through or around each pixel PX to transmit driving signals to each pixel driving circuit. The pixel driving circuit may include transistors and capacitors. The number of transistors and capacitors included in each pixel driving circuit may vary. The pixel driving circuit described herein may be a 3TIC type, in which the pixel driving circuit includes three transistors and one capacitor. However, embodiments are not limited to this, and various other pixel structures such as 2TIC, 7TIC, and 6TIC structures may also be applicable.

[0109] Figure 4 A schematic diagram of the equivalent circuit of pixel PX of display device 1 according to an embodiment is shown.

[0110] refer to Figure 4 In addition to the light-emitting element EMD, each pixel PX of the display device 1 according to the embodiment may include three transistors DRT, SCT and SST and a storage capacitor CST.

[0111] An EMD (Emitting Device) can emit light based on the current supplied through a driving transistor DRT. EMDs can be implemented as organic LEDs, micro LEDs, or nano LEDs.

[0112] The first electrode (e.g., anode) of the light-emitting element EMD can be connected to the source electrode of the driving transistor DRT, and the second electrode (e.g., cathode) of the light-emitting element EMD can be connected to the second power line. A low potential voltage (e.g., the second power supply voltage ELVS) lower than the high potential voltage (e.g., the first power supply voltage ELVD) of the first power supply line ELVDL can be supplied to the second power line.

[0113] The driving transistor DRT can regulate the current flowing from the first power line ELVDL (the first power supply voltage ELVD can be supplied to the first power line ELVDL) to the light-emitting element EMD based on the voltage difference between the gate electrode and the source electrode. The driving transistor DRT may include a gate electrode connected to the first source / drain electrode of the first switching transistor SCT, a source electrode connected to the first electrode of the light-emitting element EMD, and a drain electrode connected to the first power line ELVDL, the first power supply voltage ELVD being applied to the first power line ELVDL.

[0114] The first switching transistor SCT can be turned on by the scan signal of the scan line SCL, and the data line DTL can be connected to the gate electrode of the driving transistor DRT. The first switching transistor SCT may include a gate electrode connected to the scan line SCL, a first source / drain electrode connected to the gate electrode of the driving transistor DRT, and a second source / drain electrode connected to the data line DTL.

[0115] The second switching transistor SST can be turned on by the sensing signal of the sensing line SSL, and can connect the reference voltage line RVL to the source electrode of the driving transistor DRT. The second switching transistor SST may have a gate electrode connected to the sensing line SSL, a first source / drain electrode connected to the reference voltage line RVL, and a second source / drain electrode connected to the source electrode of the driving transistor DRT.

[0116] The first source / drain electrode of each of the first switching transistor SCT and the second switching transistor SST can be the source electrode, and the second source / drain electrode can be the drain electrode, or vice versa.

[0117] A storage capacitor CST can be formed between the gate and source electrodes of the driving transistor DRT. The storage capacitor CST can store the difference between the gate voltage and the source voltage of the driving transistor DRT.

[0118] The driving transistor DRT, the first switching transistor SCT, and the second switching transistor SST can be formed as thin-film transistors. The driving transistor DRT, the first switching transistor SCT, and the second switching transistor SST can be formed as N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but the embodiments are not limited to this. In other embodiments, the driving transistor DRT, the first switching transistor SCT, and the second switching transistor SST can be formed as P-type MOSFETs. Similarly, in other embodiments, some of the driving transistor DRT, the first switching transistor SCT, and the second switching transistor SST can be formed as N-type MOSFETs, while others can be formed as P-type MOSFETs.

[0119] The pixel configuration of the display device 1 according to the embodiment will be discussed below.

[0120] Figure 5 A layout diagram of the pixels PX of the display device 1 according to an embodiment is shown. Figure 6 Showing includes Figure 5 The layout diagram of the semiconductor layer 1100 and some conductive layers in the pixel PX. Figure 7 Showing includes Figure 5 The layout diagram of some conductive layers in the pixel PX.

[0121] refer to Figures 5 to 7 The display device 1 according to the embodiment may include a semiconductor layer 1100 and conductive layers 1200, 1300 and 1400. The display device 1 may include insulating layers 1020, 1030, 1050, 1060, 1070 and 1080 (see [link to example]) disposed between the semiconductor layer 1100 and the conductive layers 1200, 1300 and 1400. Figure 8 Conductive layers 1200, 1300, and 1400 may include a gate conductive layer 1200, a first data conductive layer 1300, and a second data conductive layer 1400. Insulating layers 1020, 1030, 1050, 1060, 1070, and 1080 may include a buffer layer 1020, a gate insulating layer 1030, a first interlayer insulating layer 1050, a first protective layer 1060, a second protective layer 1070, and a planarization layer 1080.

[0122] Figure 5 A layout diagram of a semiconductor layer 1100 and a conductive layer stacked in a pixel PX of a display device 1 according to an embodiment is shown. Figure 6 The layout diagram shows the stacked semiconductor layer 1100, gate conductive layer 1200 and first data conductive layer 1300. Figure 7 The diagram shows a layout of the stacked first data conductive layer 1300, second data conductive layer 1400, pixel electrode PXE, and pixel limiting layer PDL.

[0123] Each pixel PX of display device 1 may include sub-pixels. Figures 5 to 7 The region of pixel PX illustrated in the diagram can form a first sub-pixel, another region can form a second sub-pixel, and yet another region can form a third sub-pixel. Each sub-pixel may include a transistor, a storage capacitor, and wiring, as shown in the reference above. Figure 4 The equivalent circuit described is shown. Figures 5 to 7 Three sub-pixels are shown, each of which may include a driving transistor DRT, a first switching transistor SCT, a second switching transistor SST, and a storage capacitor CST. These sub-pixels may be connected to different data wirings, but may be electrically connected to the same power wirings. Regarding the layers arranged in the sub-pixels, the layers arranged in each pixel PX or sub-pixel of display device 1 are discussed below. Reference Figure 5 and Figure 6 The semiconductor layer 1100 can be disposed on the first substrate 1010. Buffer layer 1020 (see...) Figure 8 The semiconductor layer 1100 can be disposed on the first substrate 1010, and the semiconductor layer 1100 can be disposed on the buffer layer 1020. The semiconductor layer 1100 may include a first semiconductor layer 1110, a second semiconductor layer 1120, and a third semiconductor layer 1130. The first semiconductor layer 1110 may be an active layer of a driving transistor DRT included in a pixel PX, the second semiconductor layer 1120 may be an active layer of a first switching transistor SCT, and the third semiconductor layer 1130 may be an active layer of a second switching transistor SST.

[0124] The first semiconductor layer 1110, the second semiconductor layer 1120, and the third semiconductor layer 1130 may extend in a first direction DR1 (that is, in the horizontal direction), and the two ends of each of the first semiconductor layer 1110, the second semiconductor layer 1120, and the third semiconductor layer 1130 may be extended to have an increased width relative to the rest of their portions. A portion of each of the first semiconductor layer 1110, the second semiconductor layer 1120, and the third semiconductor layer 1130 extending in the first direction DR1 may overlap with the gate conductive layer 1200 to form the gate electrode of each transistor, and the two extended ends of each of the layers may contact the first data conductive layer 1300 to form the source electrode and drain electrode of each transistor. The two ends of the semiconductor layer 1100 may be partially conductive to form conductive regions (see...). Figure 8 Furthermore, it can form channel regions between conductive regions (see...). Figure 8 ).

[0125] The first semiconductor layer 1110 may include an eleventh semiconductor layer 1110a located above the center of pixel PX, and a twelfth semiconductor layer 1110b and a thirteenth semiconductor layer 1110c positioned adjacent to the center of pixel PX. The eleventh semiconductor layer 1110a may be the active layer of the driving transistor DRT of the first sub-pixel, the twelfth semiconductor layer 1110b may be the active layer of the driving transistor DRT of the second sub-pixel, and the thirteenth semiconductor layer 1110c may be the active layer of the driving transistor DRT of the third sub-pixel.

[0126] The first semiconductor layer 1110 can be patterned to extend in the same direction. For example, a first side of each of the first semiconductor layers 1110 can contact a portion of the first conductive pattern 1380 of the first data conductive layer 1300, a second side of each of the first semiconductor layers 1110 can contact a portion of the first voltage wiring 1350 of the first data conductive layer 1300, and a portion between the first and second sides can overlap with a portion of the gate conductive pattern 1250 of the gate conductive layer 1200. The first data conductive layer 1300 contacting the first side of each of the first semiconductor layers 1110 can be the source electrode of a driving transistor DRT, and the first data conductive layer 1300 contacting the second side of each of the first semiconductor layers 1110 can be the drain electrode of a driving transistor DRT. The gate conductive layer 1200 overlapping with or facing the portion between the first and second sides of each of the first semiconductor layers 1110 can be the gate electrode of a driving transistor DRT.

[0127] The second semiconductor layer 1120 can be disposed to the right of the center of pixel PX. The second semiconductor layer 1120 may include a twenty-first semiconductor layer 1120a, a twenty-second semiconductor layer 1120b, and a twenty-third semiconductor layer 1120c. The twenty-first semiconductor layer 1120a may be the active layer of the first switching transistor SCT of the first sub-pixel, the twenty-second semiconductor layer 1120b may be the active layer of the first switching transistor SCT of the second sub-pixel, and the twenty-third semiconductor layer 1120c may be the active layer of the first switching transistor SCT of the third sub-pixel.

[0128] The second semiconductor layer 1120 can be patterned to extend in the same direction. A first side of each of the second semiconductor layers 1120 can contact a portion of the second conductive pattern 1390 of the first data conductive layer 1300, and a second side of each of the second semiconductor layers 1120 can contact one of the first data signal lines 1310, 1320, and 1330 of the first data conductive layer 1300. A portion between the first and second sides of each of the second semiconductor layers 1120 can overlap with or face a portion of the scan signal line 1210 of the gate conductive layer 1200. The first data conductive layer 1300 contacting the first side of each of the second semiconductor layers 1120 can be the source electrode of the first switching transistor SCT, and the first data conductive layer 1300 contacting the second side can be the drain electrode of the first switching transistor SCT. The gate conductive layer 1200 that overlaps with or faces the portion between the first and second sides of each of the second semiconductor layers 1120 may be the gate electrode of the first switching transistor SCT.

[0129] The second side of the second semiconductor layer 1120 can contact different first data signal lines 1310, 1320, and 1330. The twenty-first semiconductor layer 1120a can contact the eleventh data signal line 1310, the twenty-second semiconductor layer 1120b can contact the twelfth data signal line 1320, and the twenty-third semiconductor layer 1120c can contact the thirteenth data signal line 1330. Because the second semiconductor layer 1120 can contact different first data signal lines 1310, 1320, and 1330, different data signals can be transmitted to different sub-pixels.

[0130] The third semiconductor layer 1130 can be positioned adjacent to the left side of the center of pixel PX. The third semiconductor layer 1130 may include a thirty-first semiconductor layer 1130a, a thirty-second semiconductor layer 1130b, and a thirty-third semiconductor layer 1130c. The thirty-first semiconductor layer 1130a may be the active layer of the second switching transistor SST of the first sub-pixel, the thirty-second semiconductor layer 1130b may be the active layer of the second switching transistor SST of the second sub-pixel, and the thirty-third semiconductor layer 1130c may be the active layer of the second switching transistor SST of the third sub-pixel.

[0131] The third semiconductor layer 1130 can be patterned to extend in the same direction. A first side of each of the third semiconductor layers 1130 can contact a first conductive pattern 1380 of the first data conductive layer 1300, and a second side of each of the third semiconductor layers 1130 can contact a first reference voltage wiring 1360 of the first data conductive layer 1300. A portion between the first and second sides of each of the third semiconductor layers 1130 can overlap with or face a portion of the sensing signal line 1220 of the gate conductive layer 1200. The first data conductive layer 1300 contacting the first side of each of the third semiconductor layers 1130 can be the source electrode of the second switching transistor SST, and the first data conductive layer 1300 contacting the second side can be the drain electrode of the second switching transistor SST. The gate conductive layer 1200 overlapping with or facing the portion between the first and second sides of each of the third semiconductor layers 1130 can be the gate electrode of the second switching transistor SST.

[0132] Semiconductor layer 1100 may include oxide semiconductor. For example, the oxide semiconductor of semiconductor layer 1100 may be indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0133] Gate insulation layer 1030 (see Figure 8 This can be arranged on semiconductor layer 1100. See below for reference. Figure 8 Let's discuss it.

[0134] The gate conductive layer 1200 can be disposed on the gate insulating layer 1030 or the buffer layer 1020. The gate conductive layer 1200 may include a scan signal line 1210, a sensing signal line 1220, a gate conductive pattern 1250, and a gate pattern portion 1260. The scan signal line 1210 can transmit a scan signal to a first switching transistor SCT for each pixel PX or sub-pixel, and the sensing signal line 1220 can transmit a sensing signal to a second switching transistor SCT for each pixel PX or sub-pixel. For example, the scan signal line 1210 may be... Figure 4 The scan line SCL, and the sensing signal line 1220 can be Figure 4 The sensing line SSL. The gate conductive pattern 1250 may overlap with or face the first semiconductor layer 1110 to form the gate electrode of the driving transistor DRT. The gate pattern portion 1260 may overlap with or face the second voltage wiring 1370 of the first data conductive layer 1300.

[0135] The scan signal line 1210 may extend in a first direction DR1 and includes a first extension portion 1215 branching from the scan signal line 1210 and extending in a second direction DR2. The scan signal line 1210 may extend in the first direction DR1 above the pixel PX. The scan signal line 1210 may extend in the first direction DR1 to another pixel PX adjacent to the pixel PX. The first extension portion 1215 may be located in a portion of the scan signal line 1210 (e.g., to the right of the center of the pixel PX) and may extend in the second direction DR2 within the pixel PX.

[0136] The first extension 1215 of the scan signal line 1210 may overlap with or face a portion of each of the second semiconductor layers 1120. The first extension 1215 may form the gate electrode of the first switching transistor SCT in each pixel PX or sub-pixel. The first switching transistor SCT may receive scan signals from the scan signal line 1210 through the first extension 1215.

[0137] The sensing signal line 1220 may extend in a first direction DR1 and includes a second extension portion 1225 branching from the sensing signal line 1220 and extending in a second direction DR2. The sensing signal line 1220 may extend in the first direction DR1 below the pixel PX. The sensing signal line 1220 may extend in the first direction DR1 to another pixel PX adjacent to the pixel PX. The second extension portion 1225 may be located in a portion of the sensing signal line 1220 (e.g., to the left of the center of the pixel PX) and may extend in the second direction DR2 within the pixel PX.

[0138] The second extension 1225 of the sensing signal line 1220 may overlap with or face a portion of each of the third semiconductor layers 1130. The second extension 1225 may form the gate electrode of the second switching transistor SST in each pixel PX or sub-pixel. The second switching transistor SST can receive sensing signals from the sensing signal line 1220 through the second extension 1225.

[0139] A gate conductive pattern 1250 may be disposed between a first extension 1215 of a scan signal line 1210 and a second extension 1225 of a sensing signal line 1220. The gate conductive pattern 1250 may include a first gate conductive pattern 1250a, a second gate conductive pattern 1250b, and a third gate conductive pattern 1250c. The first gate conductive pattern 1250a, the second gate conductive pattern 1250b, and the third gate conductive pattern 1250c may each partially overlap with or partially face the first semiconductor layer 1110. The first gate conductive pattern 1250a may overlap with or face a portion of the eleventh semiconductor layer 1110a to form the gate electrode of the driving transistor DRT of the first sub-pixel. The first gate conductive pattern 1250a may at least overlap with or at least face the channel region of the eleventh semiconductor layer 1110a. Similarly, the second gate conductive pattern 1250b may overlap with or face a portion of the twelfth semiconductor layer 1110b to form the gate electrode of the driving transistor DRT of the second sub-pixel, and the third gate conductive pattern 1250c may overlap with or face a portion of the thirteenth semiconductor layer 1110c to form the gate electrode of the driving transistor DRT of the third sub-pixel.

[0140] The gate conductive pattern 1250 may overlap or contact the first conductive pattern 1380 and the second conductive pattern 1390 of the first data conductive layer 1300. Each of the gate conductive patterns 1250 may overlap or contact the first conductive pattern 1380 to form the first electrode of the storage capacitor CST for each pixel PX or sub-pixel. The gate conductive pattern 1250 may contact the first conductive pattern 1380 and is therefore electrically connected to the second switching transistor SST, and may contact the second conductive pattern 1390 and is therefore electrically connected to the first switching transistor SCT.

[0141] For example, the first gate conductive pattern 1250a may overlap or contact the eleventh conductive pattern 1380a to form the second electrode of the storage capacitor CST of the first sub-pixel. The first gate conductive pattern 1250a may contact the eleventh conductive pattern 1380a and is therefore electrically connected to the source electrode of the second switching transistor SST of the first sub-pixel, and may contact the twenty-first conductive pattern 1390a and is therefore electrically connected to the source electrode of the first switching transistor SCT of the first sub-pixel. Similarly, the second gate conductive pattern 1250b may partially overlap or contact the twelfth conductive pattern 1380b and the twenty-second conductive pattern 1390b, and the third gate conductive pattern 1250c may partially contact the thirteenth conductive pattern 1380c and the twenty-third conductive pattern 1390c.

[0142] The gate pattern portion 1260 may include an extension portion extending in the second direction DR2 and an expansion portion having an increased width relative to the remainder. The gate pattern portion 1260 may be arranged on the left side (e.g., see...). Figure 5 It can be arranged between the scan signal line 1210 and the sensing signal line 1220 extending in the first direction DR1. The gate pattern portion 1260 can be electrically connected to the second voltage wiring 1370 and can reduce the wiring resistance of the second voltage wiring 1370.

[0143] The gate conductive layer 1200 may include one or more metals selected from, but not limited to, molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and / or combinations thereof. The gate conductive layer 1200 may include a single layer or multiple layers.

[0144] First interlayer insulation layer 1050 (see...) Figure 8 It can be arranged on the gate conductive layer 1200. See below for reference. Figure 8 Let's discuss it.

[0145] The first data conductive layer 1300 may be disposed on the first interlayer insulating layer 1050. The first data conductive layer 1300 may include first data signal lines 1310, 1320 and 1330, a first voltage wiring 1350, a first reference voltage wiring 1360, a second voltage wiring 1370, a first conductive pattern 1380 and a second conductive pattern 1390.

[0146] Each of the first data signal lines 1310, 1320, and 1330 can transmit a data signal to each pixel PX or sub-pixel. For example, each of the first data signal lines 1310, 1320, and 1330 can be Figure 4 The data lines DTL. First data signal lines 1310, 1320, and 1330 may be arranged on one side (e.g., the right side) of the center of pixel PX in a first direction DR1, and may extend in a second direction DR2. First data signal lines 1310, 1320, and 1330 may extend in the second direction DR2 to another pixel PX adjacent to pixel PX.

[0147] The first data signal lines 1310, 1320, and 1330 may include an eleventh data signal line 1310, a twelfth data signal line 1320, and a thirteenth data signal line 1330. The eleventh data signal line 1310 may contact the second side of the twenty-first semiconductor layer 1120a to transmit a data signal to the first switching transistor SCT of the first sub-pixel. The twelfth data signal line 1320 may contact the second side of the twenty-second semiconductor layer 1120b to transmit a data signal to the first switching transistor SCT of the second sub-pixel. The thirteenth data signal line 1330 may contact the second side of the twenty-third semiconductor layer 1120c to transmit a data signal to the first switching transistor SCT of the third sub-pixel.

[0148] See below for reference. Figure 8 As described, the first interlayer insulating layer 1050 on which the first data conductive layer 1300 may be disposed may include a contact hole. The contact hole may penetrate the first interlayer insulating layer 1050 and / or the gate insulating layer 1030 and the buffer layer 1020 to expose the semiconductor layer 1100.

[0149] The first interlayer insulating layer 1050 may include a thirty-seventh contact hole CNT37, which can penetrate the first interlayer insulating layer 1050 and the gate insulating layer 1030 to expose a portion of the second semiconductor layer 1120. First data signal lines 1310, 1320, and 1330 can contact the second side of the second semiconductor layer 1120 through the thirty-seventh contact hole CNT37, respectively. For example, the eleventh data signal line 1310 can contact the second side of the twenty-first semiconductor layer 1120a through the (37-1) contact hole CNT37a. Similarly, the twelfth data signal line 1320 and the thirteenth data signal line 1330 can contact the second sides of the twenty-second and twenty-third semiconductor layers 1120b and 1120c, respectively, through the (37-2) contact hole CNT37b and the (37-3) contact hole CNT37c, respectively.

[0150] The first voltage wiring 1350 can transmit the first power supply voltage ELVD to each pixel PX or sub-pixel. For example, the first voltage wiring 1350 can be Figure 4 The first power supply line ELVDL. The first voltage wiring 1350 may be arranged on one side (e.g., the left side) of the center of pixel PX in a first direction DR1, and may extend in a second direction DR2. The first voltage wiring 1350 may extend in the second direction DR2 to another pixel PX adjacent to pixel PX. The first voltage wiring 1350 may contact a second side of the first semiconductor layer 1110 to apply the first power supply voltage ELVD to the driving transistor DRT of each sub-pixel.

[0151] The first interlayer insulating layer 1050 may include a thirty-fifth contact hole CNT35, which may expose a portion of the first semiconductor layer 1110. A first voltage wiring 1350 may contact the second side of the first semiconductor layer 1110 through the thirty-fifth contact hole CNT35. For example, the first voltage wiring 1350 may contact the second side of the eleventh semiconductor layer 1110a through the (35-1) contact hole CNT35a. Similarly, the first voltage wiring 1350 may contact the second sides of the twelfth semiconductor layer 1110b and the thirteenth semiconductor layer 1110c through the (35-2) contact holes CNT35b and the (35-3) contact holes CNT35c, respectively.

[0152] The first reference voltage wiring 1360 can apply a reference voltage RV to each pixel PX or sub-pixel. For example, the first reference voltage wiring 1360 can be... Figure 4 The reference voltage line RVL. A first reference voltage wiring 1360 may be arranged on one side (e.g., the left side) of the first voltage wiring 1350 in a first direction DR1, and may extend in a second direction DR2. The first reference voltage wiring 1360 may extend in the second direction DR2 to another pixel PX adjacent to pixel PX. The first reference voltage wiring 1360 may contact a second side of the third semiconductor layer 1130 to apply the reference voltage RV to the second switching transistor SST of each sub-pixel.

[0153] The first interlayer insulating layer 1050 may include a thirty-sixth contact hole CNT36, which can expose a portion of the third semiconductor layer 1130. A first reference voltage wiring 1360 may contact the second side of the third semiconductor layer 1130 through the thirty-sixth contact hole CNT36. For example, the first reference voltage wiring 1360 may contact the second side of the thirty-first semiconductor layer 1130a through the (36-1) contact hole CNT36a. Similarly, the first reference voltage wiring 1360 may contact the second sides of the thirty-second and thirty-third semiconductor layers 1130b and 1130c through the (36-2) and (36-3) contact holes CNT36b and CNT36c, respectively.

[0154] The second voltage wiring 1370 can apply the second power supply voltage ELVS to each pixel PX or sub-pixel. For example, the second voltage wiring 1370 can be... Figure 4 The second power line is ELVSL. The second voltage wiring 1370 can be arranged on one side (e.g., the left side) of the reference voltage wiring 1360 in the first direction DR1, and can extend in the second direction DR2. The second voltage wiring 1370 can extend in the second direction DR2 to another pixel PX adjacent to pixel PX.

[0155] Although not shown, a second power supply voltage ELVS can be applied to an electrode of the light-emitting element EMD (e.g., a common electrode CME), which can be the cathode of the light-emitting element EMD. The common electrode CME can be connected to the second power supply line ELVSL via power wiring located in the non-display area NDA, and can receive the second power supply voltage ELVS due to the connection.

[0156] In the case where the display device 1 may have a high resolution due to including a large number of pixels PX, the second power supply voltage ELVS applied to the common electrode CME, which is only in contact with the power supply wiring in the non-display area NDA, may decrease depending on the position of the pixel PX in the display area DPA. Since the second power supply voltage ELVS, which may have a lower potential than the second power supply voltage ELVS that can be applied to the pixel PX spaced apart from the non-display area NDA, can be applied to pixels PX that are adjacent to the non-display area NDA, the intensity of light emitted from the light-emitting element EMD of each pixel PX may be non-uniform. However, in the display device 1 according to the embodiment, the second voltage wiring 1370 and the fourth voltage wiring 1470 located in at least a portion of the pixel PX can be electrically connected to the common electrode CME. Therefore, the second power supply voltage ELVS can be applied to each pixel PX at a uniform potential. The common electrode CME can be connected to the opening area LDA of each pixel PX (see...). Figure 5 Some conductive layers in the circuit are electrically connected to the second voltage wiring 1370 and the fourth voltage wiring 1470. According to an embodiment, the second voltage wiring 1370 may include a first extension SP1 extending in the second direction DR2 and a first extension EP1 located in the opening region LDA and having a wider width than the first extension SP1 (see [link to embodiment]). Figure 9 The hole HLD of the pixel-defining layer PDL arranged on the first data conductive layer 1300 (see...) Figure 10 The common electrode CME can be located in the first extension portion EP1, and can contact another conductive layer through the hole HLD. The conductive layer contacting the common electrode CME can contact the second voltage wiring 1370 and the fourth voltage wiring 1470 through the contact hole located in the planarization layer 1080, and thus the common electrode CME can be electrically connected to the second voltage wiring 1370 and the fourth voltage wiring 1470.

[0157] Since the conductive layer and the insulating layer can be arranged between the common electrode CME and the second voltage wiring 1370, if the common electrode CME and the second voltage wiring 1370 are connected to each other at their overlapping locations, the size of the contact hole or hole HLD used to expose the conductive layer arranged under the common electrode CME may need to be increased. However, the width of the contact hole in each pixel PX of the high-resolution display device 1 may be limited. Therefore, it may be difficult to ensure within the pixel PX that the contact hole can be arranged to allow the common electrode CME and the second voltage wiring 1370 to connect. In the display device 1 according to the embodiment, the hole HLD through which the common electrode CME and the conductive layer contact each other can be spaced apart from the contact hole through which the conductive layer and the second voltage wiring 1370 or the fourth voltage wiring 1470 contact each other. Therefore, the width of the hole HLD and the contact hole can be minimized because the hole HLD and the contact hole may not overlap or face each other in the thickness direction.

[0158] The second voltage wiring 1370 can contact the gate pattern portion 1260 through the 55th contact hole CNT55 and the 57th contact hole CNT57, which can penetrate the first interlayer insulation layer 1050 to expose a portion of the gate pattern portion 1260.

[0159] The first conductive pattern 1380 and the second conductive pattern 1390 can be arranged between the first data signal lines 1310, 1320, and 1330 and the first voltage wiring 1350. The first conductive pattern 1380 and the second conductive pattern 1390 can overlap with or face the first sides of the first semiconductor layer 1110, the second semiconductor layer 1120, and the third semiconductor layer 1130. The first conductive pattern 1380 can overlap with or face the gate conductive pattern 1250. The first conductive pattern 1380 can contact the first sides of the first semiconductor layer 1110 and the third semiconductor layer 1130 through the thirty-first contact hole CNT31 and the thirty-third contact hole CNT33 formed in the first interlayer insulating layer 1050. The second conductive pattern 1390 can contact the first side of the second semiconductor layer 1120 through the thirty-second contact hole CNT32 formed in the first interlayer insulating layer 1050.

[0160] The first conductive pattern 1380 and the second conductive pattern 1390 can form the source electrode of the driving transistor DRT and the second switching transistor SST of each sub-pixel, and each of the second conductive patterns 1390 can form the source electrode of the first switching transistor SCT of each sub-pixel. Each of the first conductive patterns 1380 can overlap with or face the gate conductive pattern 1250 to form the second electrode of the storage capacitor CST of each sub-pixel.

[0161] The first conductive pattern 1380 may include an eleventh conductive pattern 1380a, a twelfth conductive pattern 1380b, and a thirteenth conductive pattern 1380c, and the second conductive pattern 1390 may include a twenty-first conductive pattern 1390a, a twenty-second conductive pattern 1390b, and a twenty-third conductive pattern 1390c.

[0162] The eleventh conductive pattern 1380a can contact the first side of the eleventh semiconductor layer 1110a through the (31-1) contact hole CNT31a. The (31-1) contact hole CNT31a can penetrate the first interlayer insulating layer 1050 and the gate insulating layer 1030 to expose the first side of the eleventh semiconductor layer 1110a. The eleventh conductive pattern 1380a can form the source electrode of the driving transistor DRT of the first sub-pixel. The eleventh conductive pattern 1380a can contact the first side of the thirty-first semiconductor layer 1130a through the (33-1) contact hole CNT33a. The (33-1) contact hole CNT33a can penetrate the first interlayer insulating layer 1050 and the gate insulating layer 1030 to expose the first side of the thirty-first semiconductor layer 1130a. The eleventh conductive pattern 1380a can be electrically connected to the second switching transistor SST of the first sub-pixel.

[0163] The 21st conductive pattern 1390a can contact the first side of the 21st semiconductor layer 1120a through the (32-1) contact hole CNT32a. The (32-1) contact hole CNT32a can penetrate the first interlayer insulating layer 1050 and the gate insulating layer 1030 to expose the first side of the 21st semiconductor layer 1120a. The 21st conductive pattern 1390a can form the source electrode of the first switching transistor SCT of the first sub-pixel.

[0164] The first conductive pattern 1380 can contact the conductive layer disposed on the first substrate 1010 through a contact hole. The contact hole can penetrate the first interlayer insulating layer 1050, the gate insulating layer 1030, and the buffer layer 1020 to expose the conductive layer. The eleventh conductive pattern 1380a can contact the conductive layer through the forty-first contact hole CNT41, the twelfth conductive pattern 1380b can contact the conductive layer through the forty-second contact hole CNT42, and the thirteenth conductive pattern 1380c can contact the conductive layer through the forty-third contact hole CNT43.

[0165] Display device 1 may include a light-shielding layer BML disposed between the first substrate 1010 and the buffer layer 1020 (see...). Figure 8 The first conductive pattern 1380 can contact the light-shielding layer BML through the forty-first contact hole CNT41, the forty-second contact hole CNT42, and the forty-third contact hole CNT43.

[0166] The second conductive pattern 1390 can contact the conductive layer through a contact hole, which can penetrate the first interlayer insulating layer 1050 to expose a portion of the gate conductive pattern 1250. The twenty-first conductive pattern 1390a can contact the gate conductive pattern 1250 through the fifty-first contact hole CNT51. The twenty-second conductive pattern 1390b ​​can contact the gate conductive pattern 1250 through the fifty-second contact hole CNT52. The twenty-third conductive pattern 1390c can contact the gate conductive pattern 1250 through the fifty-third contact hole CNT53. The second conductive pattern 1390 can form the source electrode of the first switching transistor SCT and connect the source electrode of the first switching transistor SCT to the gate electrode of the driving transistor DRT and the first electrode of the storage capacitor CST.

[0167] The above description of the eleventh conductive pattern 1380a and the twenty-first conductive pattern 1390a can also be applied to the description of the twelfth conductive pattern 1380b, the thirteenth conductive pattern 1380c, the twenty-second conductive pattern 1390b, and the twenty-third conductive pattern 1390c arranged in other sub-pixels.

[0168] The first data conductive layer 1300 may include one or more metals selected from, but not limited to, molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), and / or combinations thereof. The first data conductive layer 1300 may include a single layer or multiple layers. For example, the first data conductive layer 1300 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, or combinations thereof.

[0169] First protective layer 1060 (see...) Figure 8 The data conductive layer 1300 can be arranged on the first data conductive layer 1300. In addition to the first data conductive layer 1300, the display device 1 may also include a second data conductive layer 1400. The second data conductive layer 1400 may overlap with or face the first data conductive layer 1300, and may have substantially the same shape as the first data conductive layer 1300. The first data conductive layer 1300 and the second data conductive layer 1400 may be electrically connected to each other. Wiring for transmitting power or data signals can be divided into different layers, including, for example, the first data conductive layer 1300 and the second data conductive layer 1400. Therefore, the space for wiring pads (WPD) and the non-display area (NDA) where wiring can be arranged can be minimized.

[0170] The second data conductive layer 1400 may include second data signal lines 1410, 1420, and 1430, a third voltage wiring 1450, a second reference voltage wiring 1460, a fourth voltage wiring 1470, and a third conductive pattern 1480, to correspond to the first data conductive layer 1300. The second data signal lines 1410, 1420, and 1430 may overlap with or face the first data signal lines 1310, 1320, and 1330, respectively. The third voltage wiring 1450 may overlap with or face the first voltage wiring 1350. The second reference voltage wiring 1460 may overlap with or face the first reference voltage wiring 1360. The fourth voltage wiring 1470 may overlap with or face the second voltage wiring 1370. Therefore, the fourth voltage wiring 1470 may include a second extension portion SP2 extending in one direction and a second extension portion EP2 having a wider width. The positional relationship and shape of the above components may be substantially the same as the positional relationship and shape of the components of the first data conductive layer 1300.

[0171] The second data signal lines 1410, 1420, and 1430 can contact the first data signal lines 1310, 1320, and 1330 through contact holes, which can penetrate the first protective layer 1060 to expose portions of the first data signal lines 1310, 1320, and 1330. The twenty-first data signal line 1410 can contact the eleventh data signal line 1310 through the twenty-first contact hole CNT21. The twenty-second data signal line 1420 can contact the twelfth data signal line 1320 through the twenty-second contact hole CNT22, and the twenty-third data signal line 1430 can contact the thirteenth data signal line 1330 through the twenty-third contact hole CNT23.

[0172] The third voltage wiring 1450 can contact the first voltage wiring 1350 through the twenty-fifth contact hole CNT25, which exposes a portion of the first voltage wiring 1350. The second reference voltage wiring 1460 can contact the first reference voltage wiring 1360 through the twenty-sixth contact hole CNT26, and the fourth voltage wiring 1470 can contact the second voltage wiring 1370 through the twenty-seventh contact hole CNT27.

[0173] The third conductive pattern 1480 can contact the first conductive pattern 1380 through the twenty-eighth contact hole CNT28, which can penetrate the first protective layer 1060 to expose a portion of the first conductive pattern 1380. The thirty-first conductive pattern 1480a can contact the eleventh conductive pattern 1380a through the (28-1) contact hole CNT28a. The thirty-second conductive pattern 1480b can contact the twelfth conductive pattern 1380b through the (28-2) contact hole CNT28b, and the thirty-third conductive pattern 1480c can contact the thirteenth conductive pattern 1380c through the (28-3) contact hole CNT28c.

[0174] The second data conductive layer 1400 may include a material substantially the same as that of the first data conductive layer 1300.

[0175] Second protective layer 1070 and planarization layer 1080 (see...) Figure 8 It can be arranged on the second data conductive layer 1400.

[0176] The pixel electrode layer can be disposed on the planarization layer 1080. The pixel electrode layer may include a pixel electrode PXE, which may be the anode of the light-emitting element EMD of each sub-pixel, and an electrode pattern PXP, which may be located in the opening region LDA.

[0177] A pixel electrode (PXE) may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). The first pixel electrode (PXE1) may be the anode of the light-emitting element (EMD) of the first sub-pixel. The second pixel electrode (PXE2) may be the anode of the light-emitting element (EMD) of the second sub-pixel. The third pixel electrode (PXE3) may be the anode of the light-emitting element (EMD) of the third sub-pixel.

[0178] The first pixel electrode PXE1 can be arranged adjacent to the right side of the center of pixel PX. The first pixel electrode PXE1 can be located overlapping with or facing the data signal lines 1310, 1320, 1330, 1410, 1420, and 1430 of the first and second data conductive layers 1300 and 1400. The first pixel electrode PXE1 can contact the thirty-first conductive pattern 1480a through the eleventh contact hole CNT11, which can penetrate the planarization layer 1080 to expose the thirty-first conductive pattern 1480a. The first pixel electrode PXE1 can be electrically connected to the source electrode of the driving transistor DRT of the first sub-pixel through the thirty-first conductive pattern 1480a.

[0179] The second pixel electrode PXE2 can be arranged adjacent to the center of pixel PX. The second pixel electrode PXE2 can be located at a position overlapping with or facing the conductive patterns 1380 and 1480 of the first and second data conductive layers 1300 and 1400, respectively. The second pixel electrode PXE2 can contact the thirteenth conductive pattern 1480b through the twelfth contact hole CNT12. The second pixel electrode PXE2 can be electrically connected to the source electrode of the driving transistor DRT of the second sub-pixel through the thirteenth conductive pattern 1480b.

[0180] The third pixel electrode PXE3 can be disposed to the left of the center of pixel PX. The third pixel electrode PXE3 can be disposed at a position overlapping with or facing the first voltage wiring 1350, the third voltage wiring 1450, the reference voltage wiring 1360 of the first data conductive layer 1300, and the reference voltage wiring 1460 of the second data conductive layer 1400. The third pixel electrode PXE3 can contact the thirty-third conductive pattern 1480c through the thirteenth contact hole CNT13. The third pixel electrode PXE3 can be electrically connected to the source electrode of the driving transistor DRT of the third sub-pixel through the thirty-third conductive pattern 1480c.

[0181] Display device 1 may include an electrode pattern PXP disposed in a pixel electrode layer. The electrode pattern PXP may be disposed on the same layer as the pixel electrode PXE, and may overlap with or face the second voltage wiring 1370 and the fourth voltage wiring 1470, to which a second power supply voltage ELVS may be applied. For example, the electrode pattern PXP may be disposed in the opening region LDA of each pixel PX, and at least a portion of the electrode pattern PXP may overlap with or face the first extension portion EP1 of the second voltage wiring 1370 and the second extension portion EP2 of the fourth voltage wiring 1470 in the thickness direction. The electrode pattern PXP may include a third extension portion EP3 and a protrusion portion PP. As described below, the third extension portion EP3 can contact the common electrode CME, and the protruding portion PP can contact the first data conductive layer 1300 and the second data conductive layer 1400 located beneath the protruding portion PP. A pixel defining layer PDL can be disposed on the pixel electrode layer and the planarization layer 1080. The pixel defining layer PDL may include an aperture OPH. The pixel defining layer PDL of some pixels PX may include an aperture HLD. For example, in Figure 7 The middle figure shows the locations of the opening OPH and the hole HLD. The opening OPH can partially expose the pixel electrode PXE. The opening OPH can include a first opening OPH1, a second opening OPH2, and a third opening OPH3. The first opening OPH1 can be located on the first pixel electrode PXE1 to expose a portion of the first pixel electrode PXE1. The second opening OPH2 can be located on the second pixel electrode PXE2 to expose a portion of the second pixel electrode PXE2. The third opening OPH3 can be located on the third pixel electrode PXE3 to expose a portion of the third pixel electrode PXE3. As described above, the light-emitting layer EML and the common electrode CME can be arranged on the pixel defining layer PDL and the pixel electrode PXE of the entire pixel PX. The light-emitting layer EML can contact the pixel electrode PXE exposed by the opening OPH and can emit light by receiving electrical signals from the pixel electrode PXE and the common electrode CME arranged on the pixel electrode PXE.

[0182] The light-emitting layer EML may not be disposed within the aperture HLD of the opening region LDA. The aperture HLD may be disposed at a location overlapping or facing the electrode pattern PXP, and may penetrate the pixel defining layer PDL to expose a portion of the electrode pattern PXP. During the manufacture of the display device 1, the aperture HLD may be formed after the light-emitting layer EML is placed over the entire pixel PX. Therefore, the light-emitting layer EML may not be disposed on the electrode pattern PXP that can be exposed by the aperture HLD. Therefore, the common electrode CME on the light-emitting layer EML disposed over the entire pixel PX can contact the electrode pattern PXP through the aperture HLD.

[0183] The common electrode CME of the display device 1 can be electrically connected to the second voltage wiring 1370 and / or the fourth voltage wiring 1470 of some pixels PX in order to suppress the drop of the second power supply voltage ELVS. The common electrode CME can contact the electrode pattern PXP through the hole HLD in the opening region LDA of each pixel PX. The electrode pattern PXP can contact the first data conductive layer 1300 and the second data conductive layer 1400, which can be exposed through the contact hole in the opening region LDA (e.g., the fifteenth contact hole CNT15 that can penetrate the planarization layer 1080). The common electrode CME can be spaced apart from the electrode pattern PXP by the hole HLD that contacts the electrode pattern PXP through the fifteenth contact hole CNT15 that contacts the first data conductive layer 1300 and the second data conductive layer 1400. Therefore, in the display device 1 with high resolution by including a large number of pixels PX, the area of ​​a pixel PX can be minimized due to the spacing between the hole HLD and, for example, the fifteenth contact hole CNT15.

[0184] The hole HLD (which can be the area where the common electrode CME can contact the electrode pattern PXP) can be in the thickness direction without overlapping with or facing the fifteenth contact hole CNT15 (which can be the area where the electrode pattern PXP can contact the first data conductive layer 1300 and the second data conductive layer 1400). Therefore, the width of the fifteenth contact hole CNT15 located under the hole HLD can be minimized.

[0185] Electrode pads 1500 can be disposed in contact holes through which the pixel electrode layer can contact the second data conductive layer 1400. Embodiments include a fifteenth contact hole CNT15 through which the electrode pattern PXP can contact the fourth voltage wiring 1470, and eleventh to thirteenth contact holes CNT11 to CNT13 through which the pixel electrode PXE contacts the third conductive pattern 1480, respectively. Electrode pads 1500 can be disposed in the region where the pixel electrode layer contacts the second data conductive layer 1400 to reduce the contact resistance between the pixel electrode layer and the second data conductive layer 1400. However, embodiments are not limited to this, wherein electrode pads 1500 may be omitted.

[0186] Figure 8 Show along Figure 5 A schematic cross-sectional view of the line IX-IX'.

[0187] Figure 8 The diagram shows a cross-section of the driving transistor DRT, storage capacitor CST, and first pixel electrode PXE1 of a pixel PX in the display device 1. Figure 8 The stacked structure of the pixel confinement layer (PDL), the emissive layer (EML), the common electrode (CME), and the circuit layer (CCL) is shown below. (See below for reference.) Figure 8 The description can be applied to other sub-pixels.

[0188] Figure 8 The driving transistor DRT shown may include a first active layer 350, a first gate electrode 310, a first source electrode 330, a first drain electrode 340, and a light-shielding layer BML. The first active layer 350, first gate electrode 310, first source electrode 330, and first drain electrode 340 of the driving transistor DRT may be portions of a first semiconductor layer 1110, a gate conductive pattern 1250, a first conductive pattern 1380, and a first voltage wiring 1350, respectively. For example, it can be understood that in Figure 8 In this process, a portion of the conductive layer and the semiconductor layer form a driving transistor (DRT). The first substrate 1010 may be an insulating substrate and includes a transparent material.

[0189] A buffer layer 1020 may be disposed on the first substrate 1010. The buffer layer 1020 protects the driving transistor DRT of the pixel PX, as well as the first switching transistor SCT and the second switching transistor SST, from moisture introduced through the first substrate 1010. The buffer layer 1020 may consist of alternately stacked inorganic layers. For example, the buffer layer 1020 may be multilayered, wherein layers selected from silicon oxide (SiO2) may be alternately stacked. x ) layer, silicon nitride (SiN) x One or more inorganic layers, including silicon oxynitride (SiON) layers.

[0190] A light-shielding layer BML can be disposed between the first substrate 1010 and the buffer layer 1020 of the display device 1. The light-shielding layer BML can overlap with or face the first active layer 350 of the driving transistor DRT. The light-shielding layer BML can block light from the first substrate 1010 from entering the first active layer 350 of the driving transistor DRT, thereby preventing leakage current from flowing through the first active layer 350. The width of the light-shielding layer BML can be greater than the width of the first active layer 350 of the driving transistor DRT. The light-shielding layer BML can cover the channel region of the first active layer 350, but the embodiment is not limited to this. Figure 8 A cross-section of only a portion of a pixel PX is shown, so the light-shielding layer BML can be shown as not contacting the first source electrode 330. The light-shielding layer BML can contact the first source electrode 330 through a forty-first contact hole CNT41 that exposes a portion of the light-shielding layer BML. Therefore, the light-shielding layer BML can suppress voltage variations in the driving transistor DRT. The light-shielding layer BML can be a Ti / Cu bilayer in which titanium and copper layers can be stacked.

[0191] The first active layer 350 or the first semiconductor layer 1110 can be disposed on the buffer layer 1020. Although Figure 8 Only the first active layer 350 of the driving transistor DRT is shown, but the active layers of other transistors (i.e., the first switching transistor SCT and the second switching transistor SST) may also be arranged on the buffer layer 1020. The first active layer 350 may include a first conductive region 350a, a second conductive region 350b, and a channel region 350c. The first conductive region 350a may contact the first source electrode 330, and the second conductive region 350b may contact the first drain electrode 340.

[0192] The first active layer 350 may include an oxide semiconductor as described above, but embodiments may not be limited thereto. Some of the semiconductor layers disposed on the buffer layer 1020 may include polysilicon.

[0193] The gate insulating layer 1030 can be disposed on the first active layer 350. The gate insulating layer 1030 can be made of materials such as silicon oxide (SiO2). x ) or silicon nitride (SiN) x It is made of inorganic materials, or can form SiO in them. x and SiN x In a stacked structure, although the gate insulating layer 1030 can be disposed on the entire surface of the buffer layer 1020 and the first active layer 350, the embodiment is not limited to this. For example, the gate insulating layer 1030 may be formed only on the first active layer 350.

[0194] The first gate electrode 310 and the first electrode of the storage capacitor CST can be disposed on the gate insulating layer 1030. Figures 5 to 7 The described gate conductive pattern is 1250.

[0195] The first gate electrode 310 may overlap with or face the first active layer 350, and the gate insulating layer 1030 is inserted between the first gate electrode 310 and the first active layer 350. The first gate electrode 310 may overlap with or face the channel region 350c of the first active layer 350.

[0196] An interlayer insulating layer 1050 can be disposed on the first gate electrode 310 and the first electrode of the storage capacitor CST. The interlayer insulating layer 1050 can be made of materials such as silicon oxide (SiO2). x ) or silicon nitride (SiN) x It is made of inorganic materials, or can be made of SiO2. x and SiN x The stacking forms.

[0197] The 31st contact hole CNT31 and the 35th contact hole CNT35 may be formed in the interlayer insulating layer 1050. The 31st contact hole CNT31 may expose the first conductive region 350a of the first active layer 350, and the 35th contact hole CNT35 may expose the second conductive region 350b of the first active layer 350. Contact holes (e.g., the 41st contact hole CNT41 that exposes a portion of the light-shielding layer BML) may also be formed in the interlayer insulating layer 1050. As described above, additional contact holes may be formed in the interlayer insulating layer 1050.

[0198] The first data conductive layer 1300 can be disposed on the interlayer insulating layer 1050. The first conductive pattern 1380 of the first data conductive layer 1300 can contact the first conductive region 350a of the first active layer 350 through the thirty-first contact hole CNT31. The first conductive pattern 1380 can form the first source electrode 330 of the driving transistor DRT. The first conductive pattern 1380 can overlap with or face the gate conductive pattern 1250 and form the second electrode of the storage capacitor CST. The first voltage wiring 1350 of the first data conductive layer 1300 can contact the second conductive region 350b of the first active layer 350 through the thirty-fifth contact hole CNT35. The first voltage wiring 1350 can form the first drain electrode 340 of the driving transistor DRT.

[0199] In one embodiment, the first protective layer 1060 may be disposed on the first data conductive layer 1300. In other embodiments, the first protective layer 1060 may be disposed on the first data conductive layer 1300 or on the first source electrode 330 and the first drain electrode 340 of the driving transistor DRT. The first protective layer 1060 may include materials such as silicon oxide (SiO2). x ) or silicon nitride (SiN) x Inorganic materials, or those that can be formed as SiO x and SiN x The stacking. The twenty-fifth contact hole CNT25 may be formed in the first protective layer 1060 to penetrate the first protective layer 1060 and expose a portion of the first voltage wiring 1350. Although not shown, the twenty-eighth contact hole CNT28 may be formed in the first protective layer 1060 to expose a portion of the first conductive pattern 1380.

[0200] The second data conductive layer 1400 can be disposed on the first protective layer 1060. The third voltage wiring 1450 of the second data conductive layer 1400 can contact the first voltage wiring 1350 through the twenty-fifth contact hole CNT25. Although not shown, the third conductive pattern 1480 can contact the first conductive pattern 1380 through the twenty-eighth contact hole CNT28.

[0201] The second protective layer 1070 can be disposed on the second data conductive layer 1400. The second protective layer 1070 can be made of materials such as silicon oxide (SiO2). x ) or silicon nitride (SiN) x It is made of inorganic materials, or can be formed as SiO. x and SiN x The stacking.

[0202] The planarization layer 1080 can be disposed on the second protective layer 1070. The planarization layer 1080 can flatten the steps formed by thin-film transistors such as driving transistors DRT and first switching transistors SCT.

[0203] The pixel electrode layer, including the pixel electrode PXE and the electrode pattern PXP, can be arranged on the planarization layer 1080. Figure 8 A portion of the first pixel electrode PXE1 and a portion of the third pixel electrode PXE3 are shown. The first pixel electrode PXE1 can contact the third conductive pattern 1480 through the eleventh contact hole CNT11.

[0204] Display device 1 may include electrode pads 1500, and electrode contact holes (CNTIs) exposing portions of the second data conductive layer 1400 may be formed in the second protective layer 1070. Each of the electrode contact holes (CNTIs) may be formed in the region where the pixel electrode (PXE) contacts the second data conductive layer 1400, and the electrode pads 1500 may be disposed on the second protective layer 1070 and the second data conductive layer 1400 exposed through the electrode contact holes (CNTIs). Figure 8 As shown, a first electrode contact hole CNTI1 can be formed in the second protective layer 1070 to expose a portion of the third conductive pattern 1480, and a first electrode pad 1510 can be disposed on the second protective layer 1070 and the third conductive pattern 1480. The first pixel electrode PXE1 can contact the third conductive pattern 1480 through the first electrode pad 1510. Therefore, the contact resistance between the first pixel electrode PXE1 and the third conductive pattern 1480 can be reduced.

[0205] The pixel-limited layer (PDL) can be placed on the planarization layer 1080. Figure 8 A portion of the third opening OPH3 formed in the pixel-defining layer PDL is shown. The light-emitting layer EML disposed on the pixel-defining layer PDL can contact the third pixel electrode PXE3 exposed through the third opening OPH3. The common electrode CME can be disposed on the light-emitting layer EML. Figure 9 Show Figure 5 A magnified plan view of the LDA opening region. Figure 10 Show along Figure 9 A schematic cross-sectional view of the line X-X'. Figure 11 Showing includes Figure 5 A planar view of the emissive layer EML in pixel PX.

[0206] Figure 9 and Figure 10 Show Figure 5 Plan view and cross-sectional view of the opening region LDA of a pixel PX. Figure 10 Show along Figure 9 The cross section intercepted by the line X-X' passing through the electrode pattern PXP. Figure 11 Showing the arrangement in Figure 5 A planar view of the emissive layer EML in a pixel PX.

[0207] refer to Figures 9 to 11Electrode patterns PXP can be disposed in the aperture region LDA of pixel PX. Electrode patterns PXP can contact the gate conductive layer 1200, the first data conductive layer 1300, and the second data conductive layer 1400 disposed beneath electrode patterns PXP. Gate pattern portion 1260, second voltage wiring 1370, and fourth voltage wiring 1470 can be disposed in the aperture region LDA. Second electrode pattern 1550 can be disposed in the region where the fourth voltage wiring 1470 and electrode patterns PXP overlap or face each other. However, the second electrode pattern 1550 can be omitted. Although not shown, pixel defining layer PDL can be disposed on electrode patterns PXP in a region other than aperture HLD, and common electrode CME can be disposed on pixel defining layer PDL. At least some pixels PX of display device 1 can have aperture HLD in the aperture region LDA, and common electrode CME can contact electrode patterns PXP in each of pixels PX through aperture HLD.

[0208] Each of the second voltage wiring 1370, the fourth voltage wiring 1470, and the electrode pattern PXP may include an extension portion EP. The second voltage wiring 1370 may include a first extension portion SP1 and a first extension portion EP having a width wider than the first extension portion SP1. The fourth voltage wiring 1470 may include a second extension portion SP2 and a second extension portion EP2. The first extension portion EP1 and the second extension portion EP2 may overlap or face each other in the thickness direction. The first extension portion SP1 and the second extension portion SP2 may contact each other through a twenty-seventh contact hole CNT27. The gate pattern portion 1260 may include extension portions and extension portions, and the second voltage wiring 1370 may contact the gate pattern portion 1260 through a fifty-seventh contact hole CNT57. Since the gate pattern portion 1260, the second voltage wiring 1370, and the fourth voltage wiring 1470 can be electrically connected to each other, they may have the same potential when a second power supply voltage ELVS is applied to the second voltage wiring 1370 and the fourth voltage wiring 1470.

[0209] The electrode pattern PXP may include a third extension portion EP3 and a protrusion portion PP projecting from the side surface of the third extension portion EP3. The third extension portion EP3 may overlap with or face the first extension portion EP1 and the second extension portion EP2, and the protrusion portion PP may be disposed on the first extension portion SP1 and the second extension portion SP2. A hole HLD formed in the pixel defining layer PDL may be formed on the third extension portion EP3 of the electrode pattern PXP.

[0210] The first width Wp of the third extension portion EP3 of the electrode pattern PXP can be greater than the second width WL of the via HLD. A portion of the electrode pattern PXP can be disposed under the pixel definition layer PDL and exposed through the via HLD. The common electrode CME can only contact the portion of the electrode pattern PXP exposed through the via HLD.

[0211] The width of the protruding portion PP of the electrode pattern PXP can be substantially the same as the width of the extension portion SP1 or SP2 of the second voltage wiring 1370 and / or the fourth voltage wiring 1470. The protruding portion PP of the electrode pattern PXP can overlap with or face the fifteenth contact hole CNT15 formed in the planarization layer 1080. Therefore, the electrode pattern PXP can contact the second voltage wiring 1370 and / or the fourth voltage wiring 1470 disposed under the electrode pattern PXP.

[0212] Hole HLD and the fifteenth contact hole CNT15 may not overlap or face each other in the thickness direction. Hole HLD may be formed to overlap with or face the third extension portion EP3 of electrode pattern PXP, and the fifteenth contact hole CNT15 may be formed to overlap with or face the protruding portion PP of electrode pattern PXP. Therefore, hole HLD and the fifteenth contact hole CNT15 may be spaced apart from each other. Common electrode CME may contact electrode pattern PXP, which may have the same potential as the second voltage wiring 1370 and the fourth voltage wiring 1470 (the second power supply voltage ELVS may be applied to the second voltage wiring 1370 and the fourth voltage wiring 1470), thereby preventing voltage drop within the display area DPA. Since hole HLD and the fifteenth contact hole CNT15 may be spaced apart from each other, they may be configured to have a narrow width, and space within the pixel PX may be ensured even when a large number of pixels PX can be provided to obtain the high-resolution display device 1.

[0213] The fifteenth contact hole CNT15 may not overlap with or face the twenty-seventh contact hole CNT27 in the thickness direction. Similar to the case where the hole HLD and the fifteenth contact hole CNT15 do not overlap or face each other in the thickness direction, the fifteenth contact hole CNT15 between the electrode pattern PXP and the fourth voltage wiring 1470 may not overlap with or face the twenty-seventh contact hole CNT27 between the fourth voltage wiring 1470 and the second voltage wiring 1370 in the thickness direction.

[0214] Display device 1 may include contact holes, and some of these contact holes may have different widths. The second width WL of the hole HLD may be greater than the third width Wc of the fifteenth contact hole CNT15. ​​During the manufacture of display device 1, once the light-emitting layer EML can be formed, the hole HLD can be formed on the electrode pattern PXP in the opening region LDA by a laser irradiation process. The contact hole (e.g., the fifteenth contact hole CNT15 formed in another insulating layer including the planarization layer 1080) can be formed by a mask process. Therefore, the second width WL of the hole HLD may be greater than the third width Wc of the fifteenth contact hole CNT15. ​​Therefore, the common electrode CME can contact the electrode pattern PXP over the wide region so that the drop in the second power supply voltage ELVS applied to the common electrode CME can be effectively suppressed.

[0215] The pixel electrode PXE, through its contact holes CNT11, CNT12, and CNT13 that contact the third conductive pattern 1380, can be formed in the planarization layer 1080 together with the fifteenth contact hole CNT15. ​​Some of the contact holes formed in the planarization layer 1080 can have different widths. (See again...) Figure 8 The third width Wc of the fifteenth contact hole CNT15 can be greater than the fourth width Wd of each of the eleventh to thirteenth contact holes CNT13. Since the eleventh to thirteenth contact holes CNT11 to CNT13 can be formed to enable the pixel electrode PXE to contact the third conductive pattern 1480, they can have a width narrower than that of the fifteenth contact hole CNT15, which can be formed to suppress voltage drop.

[0216] Hole HLDs may be formed only in some pixels PX, and may not be formed in other adjacent pixels PX. Electrode patterns PXP may be arranged in the opening region LDA of each pixel PX, but only some pixels PX may include hole HLDs so that the common electrode CME can contact the electrode pattern PXP, and other pixels PX may not include hole HLDs.

[0217] Figure 12 A schematic plan view of an emissive layer (EML) arranged in a pixel according to an embodiment is shown. Figure 13 Show Figure 12 A schematic cross-sectional view of the opening region LDA of a pixel PX.

[0218] refer to Figure 12 and Figure 13 as well as Figure 11 The display device 1 may include a first pixel PX1 with a hole HLD and pixels PX without a hole HLD (e.g., second pixels PX2 to fourth pixels PX4). Figure 12Only the light-emitting layer EML arranged in the pixel is shown, and therefore although the first pixel PX1 includes an aperture HLD in which the light-emitting layer EML may not be arranged, the second pixel PX2 to the fourth pixel PX4 may not include the aperture HLD. Figure 10 It can be the cross-section of the opening region LDA of the first pixel PX1.

[0219] Figure 13 The diagram shows a cross-section of the opening region LDA of each of the second pixels PX2 to the fourth pixels PX4. In each of the second pixels PX2 to the fourth pixels PX4, the aperture HLD may not be formed therein, and the common electrode CME may not be in contact with the electrode pattern PXP. Since the common electrode CME of the first pixel PX1 is in contact with the electrode pattern PXP (which may have the same potential as the second power supply voltage ELVS), voltage drops in the common electrode CMEs arranged in pixels adjacent to the first pixel PX1 can also be suppressed. Therefore, the laser process for forming the aperture HLD can be performed on all or some of the pixels PX. Although the aperture HLD can be shown as being formed in only one of the four pixels PX (e.g., the first pixel PX1), the embodiment is not limited to this. The pixel PX with the aperture HLD (e.g., the first pixel PX1) can be the only pixel PX among three or more pixels PX that includes the aperture. For example, the aperture HLD can be formed in only one of every four or more pixels PX.

[0220] A hole HLD can be formed in at least some pixels PX so that a portion of the common electrode CME can contact the electrode pattern PXP having the same potential as the second power supply voltage ELVS. Therefore, in a high-resolution display device 1 comprising a large number of pixels PX, voltage drop of the common electrode CME can be suppressed.

[0221] The fifteenth contact hole CNT15, which exposes the second voltage wiring 1370 and / or the fourth voltage wiring 1470, can be spaced apart from the hole HLD of the exposed electrode pattern PXP. Therefore, the hole HLD and the fifteenth contact hole CNT15 can be formed with relatively narrow widths, and the space in each pixel PX where the hole HLD and the fifteenth contact hole CNT15 can be formed can be minimized.

[0222] Figures 14 to 21 A schematic cross-sectional view illustrating a method for manufacturing a display device according to an embodiment is shown.

[0223] Figures 14 to 21 This illustrates that the driving transistor DRT can be arranged in the display area DPA and the aperture area LDA. Therefore, Figures 14 to 21 It can represent Figure 8 and Figure 10 The configuration shown.

[0224] refer to Figure 14 A light-shielding layer (BML) can be formed on the first substrate 1010. The patterned light-shielding layer (BML) can be formed using a masking process. For example, once a material layer used to form the lower metal layer can be deposited across the entire surface of the first substrate 1010, this material layer can be patterned using a photolithography process to form the light-shielding layer (BML), such as... Figure 14 As shown in the diagram.

[0225] The buffer layer 1020 and the semiconductor layer 1100 can be formed on the first substrate 1010 on which the light-shielding layer BML can be formed. Figure 14 The first active layer 350 of the driving transistor DRT of the semiconductor layer 1100 is shown. The semiconductor layer 1100 can be formed by a mask process. For example, an oxide semiconductor can be deposited on the entire surface of the buffer layer 1020 and then patterned by a photolithography process to form the semiconductor layer 1100, as shown below. Figure 14 As shown in the diagram.

[0226] refer to Figure 15 The gate insulating layer 1030 can be formed on the semiconductor layer 1100. The gate conductive layer 1200 can be formed on the gate insulating layer 1030. Figure 15 The diagram shows a gate conductive pattern 1250 including a first gate electrode 310 of a gate conductive layer 1200 and a gate pattern portion 1260. The gate conductive pattern 1250 can be formed by a process for forming a buffer layer 1020 or a process for forming a light-shielding layer BML.

[0227] refer to Figure 16 An interlayer insulating layer 1050 may be formed on a gate insulating layer 1030 on which a gate conductive layer 1200 may be formed, and a 57th contact hole CNT57 and 31st and 35th contact holes CNT31 and CNT35 that expose portions of the first active layer 350 may be formed. The contact hole forming process may be a mask process.

[0228] refer to Figure 17 and Figure 18 A first data conductive layer 1300 and a first protective layer 1060 may be formed on an interlayer insulating layer 1050, and a second data conductive layer 1400 may be formed on the first protective layer 1060. In these respects, a first voltage wiring 1350, a first conductive pattern 1380, and a second voltage wiring 1370 of the first data conductive layer 1300 may be provided. A third voltage wiring 1450, a third conductive pattern 1480, and a fourth voltage wiring 1470 of the second data conductive layer 1400 may also be provided. (See reference...) Figure 19The second protective layer 1070 and the planarization layer 1080 can be formed on the second data conductive layer 1400, and contact holes can be formed in the second protective layer 1070 and the planarization layer 1080. An eleventh contact hole CNT11 overlapping with or facing the pixel electrode PXE and a fifteenth contact hole CNT15 overlapping with or facing the electrode pattern PXP can be formed. Electrode pads 1500 can be arranged between the second protective layer 1070 and the planarization layer 1080. The process of forming the electrode contact holes CNT11 in the second protective layer 1070 can be performed before forming the planarization layer 1080.

[0229] refer to Figure 20 The pixel electrode layer and pixel limiting layer (PDL) can be formed on the planarization layer 1080, and the light-emitting layer (EML) can be formed on the pixel electrode layer and pixel limiting layer (PDL). The pixel electrode layer may include pixel electrodes (PXE) and electrode patterns (PXP). Once the process of forming the aperture (OPH) in the pixel limiting layer (PDL) is completed, the light-emitting layer (EML) can be disposed. The light-emitting layer (EML) can be disposed in the aperture region (LDA) and the entire display region (DPA).

[0230] Finally, refer to Figure 21 The aperture HLD can be formed in the pixel-defining layer PDL of the aperture region LDA, and the common electrode CME can be placed in the aperture HLD. The aperture HLD can be formed by the laser irradiation process described above. Since the aperture HLD can be formed once the process of forming the emissive layer EML is completed, the emissive layer EML can be removed from the aperture HLD. The common electrode CME can overlap with or face the pixel electrode PXE exposed through the aperture OPH (the emissive layer EML is inserted between the common electrode CME and the pixel electrode PXE), and can contact the electrode pattern PXP exposed through the aperture HLD. Figure 22A schematic cross-sectional view of a first display substrate 10 of a display device 1 according to an embodiment is shown, wherein a display area DPA and an opening area LDA of the first display substrate 10 of the display device 1 can be provided. The electrode pads 1500 disposed between the pixel electrode layer and the second data conductive layer 1400 can be omitted. An eleventh contact hole CNT11 can penetrate the planarization layer 1080 and the second protective layer 1070 to directly expose a portion of the third conductive pattern 1380 of the second data conductive layer 1400. Pixel electrodes PXE (e.g., first pixel electrode PXE1) can directly contact the third conductive pattern 1380 through the eleventh contact hole CNT11. A fifteenth contact hole CNT15 can penetrate the planarization layer 1080 and the second protective layer 1070 to directly expose the fourth voltage wiring 1470 of the second data conductive layer 1400. Electrode patterns PXP can directly contact the fourth voltage wiring 1470 through the fifteenth contact hole CNT15.

[0231] according to Figure 22 The display device 1 of the embodiment and Figure 8 and Figure 10 The difference in the embodiment is that the electrode pads 1500 can be omitted. In areas where the contact resistance can be minimized in the contact area between the pixel electrode PXE and the electrode pattern PXP and the second data conductive layer 1400, the electrode pads 1500 can be omitted to reduce the number of steps required to manufacture the display device 1.

[0232] The display device according to an embodiment may include an electrode pattern having the same potential as the voltage wiring, and a common electrode of some pixels may be connected to the electrode pattern to suppress voltage drop. The electrode pattern and voltage wiring may be connected through contact holes that do not overlap with or face the common electrode and electrode pattern's connection holes. Therefore, even in a high-resolution display device that can provide a large number of pixels, space can be ensured in each pixel for wiring.

[0233] In concluding this detailed description, those skilled in the art will understand that, as described herein, many variations and modifications can be made to the disclosed embodiments without departing substantially from the principles of the embodiments. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and an opening area located in the display area; A data conductive layer disposed on the substrate, the data conductive layer including a source electrode disposed in the display area and a voltage wiring disposed in the opening area; A protective layer disposed on the data conductive layer, the protective layer covering the source electrode and the voltage wiring; A planarization layer disposed on the protective layer; A pixel electrode layer disposed on the planarization layer, the pixel electrode layer comprising: Pixel electrode, the pixel electrode being connected to the source electrode through a first contact hole penetrating the planarization layer and the protective layer; and An electrode pattern, wherein the electrode pattern is connected to the voltage wiring through a second contact hole penetrating the planarization layer and the protective layer; A pixel defining layer disposed on the planarization layer and the pixel electrode layer, the pixel defining layer comprising: An opening that exposes a portion of the pixel electrode; and The holes in the electrode pattern are at least partially exposed; The light-emitting layer disposed on the pixel defining layer; and The common electrode arranged on the light-emitting layer, Wherein, the hole does not overlap with the first contact hole and the second contact hole in the thickness direction of the display device, and The electrode pattern includes: A first extension portion having a first width; and A protruding portion that protrudes from one side of the first extension and has a width smaller than the first width.

2. The display device of claim 1, wherein, The first width of the first extended portion of the electrode pattern is greater than the second width of the hole.

3. The display device of claim 2, wherein, The second width of the hole is greater than the third width of the second contact hole.

4. The display device of claim 3, wherein, The third width of the second contact hole is different from the fourth width of the first contact hole.

5. The display device of claim 1, wherein, The hole overlaps with the first extended portion of the electrode pattern in the thickness direction of the display device.

6. The display device of claim 5, wherein, The second contact hole overlaps with the protruding portion of the electrode pattern in the thickness direction of the display device.

7. The display device of claim 6, wherein, The electrode pattern does not overlap with the first contact hole in the thickness direction of the display device.

8. The display device of claim 1, wherein, The voltage wiring includes: A second extension portion that overlaps with the first extension portion in the thickness direction of the display device; and The first extension portion extends from one side of the second extension portion. The second contact hole overlaps with the first extension portion of the voltage wiring in the thickness direction of the display device.

9. The display device of claim 1, wherein, The electrode pattern includes: A first electrode pattern, at least a portion of which is exposed by the aperture; and The second electrode pattern not exposed by the hole The common electrode is in contact with the first electrode pattern but not with the second electrode pattern.

10. The display device of claim 9, wherein, The light-emitting layer is disposed between the common electrode and the pixel electrode exposed by the opening, and is not disposed on the first electrode pattern exposed by the hole.

11. The display device according to claim 9, wherein, The voltage wiring includes: First voltage wiring; and A second voltage wiring is connected to the first voltage wiring and the second electrode pattern.

12. A display device, comprising: A substrate, the substrate including a display area and an opening area located in the display area; A data conductive layer disposed on the substrate, the data conductive layer including a source electrode disposed in the display area and a voltage wiring disposed in the opening area; A protective layer disposed on the data conductive layer, the protective layer covering the source electrode and the voltage wiring; A planarization layer disposed on the protective layer; A pixel electrode layer disposed on the planarization layer, the pixel electrode layer comprising: Pixel electrode, the pixel electrode being connected to the source electrode through a first contact hole penetrating the planarization layer and the protective layer; and An electrode pattern, wherein the electrode pattern is connected to the voltage wiring through a second contact hole penetrating the planarization layer and the protective layer; A pixel defining layer disposed on the planarization layer and the pixel electrode layer, the pixel defining layer comprising: An opening that exposes a portion of the pixel electrode; and The holes in the electrode pattern are at least partially exposed; The light-emitting layer disposed on the pixel defining layer; and The common electrode arranged on the light-emitting layer, Wherein, the hole does not overlap with the first contact hole and the second contact hole in the thickness direction of the display device. The data conductive layer includes: First data conductive layer; and A second data conductive layer is disposed on the first data conductive layer, and The protective layer includes: A first protective layer disposed between the first data conductive layer and the second data conductive layer; and A second protective layer is disposed between the second data conductive layer and the planarization layer.

13. The display device according to claim 12, wherein, The second data conductive layer is connected to the first data conductive layer through a third contact hole that penetrates the first protective layer.

14. The display device according to claim 13, wherein, The third contact hole does not overlap with the second contact hole in the thickness direction of the display device.

15. The display device according to claim 13, wherein, The pixel electrode contacts the source electrode of the second data conductive layer through the first contact hole, and The electrode pattern makes contact with the voltage wiring of the second data conductive layer through the second contact hole.

16. The display device according to claim 15, further comprising: A first electrode pad is disposed on the second protective layer and the second data conductive layer, and the first electrode pad is in contact with the source electrode of the second data conductive layer; as well as A second electrode pad is disposed on the second protective layer and the second data conductive layer, and the second electrode pad is in contact with the voltage wiring of the second data conductive layer. The pixel electrode is in contact with the first electrode pad, and the electrode pattern is in contact with the second electrode pad.

17. A display device, comprising: Multiple pixels, each of which includes an opening region; Voltage wiring arranged in the opening regions of the plurality of pixels, the voltage wiring comprising: First extension section; and The first extension portion extends from one side of the first extension portion; An electrode pattern disposed in the opening region of the plurality of pixels, the electrode pattern comprising: A second extension portion that overlaps with the first extension portion in the thickness direction of the display device; and A protruding portion that extends from one side of the second extension portion; A pixel defining layer disposed on the second extended portion of the electrode pattern, the pixel defining layer including an aperture exposing at least a portion of the second extended portion; and A common electrode is disposed on the pixel defining layer, the common electrode being in contact with the exposed second extension portion of the electrode pattern. The voltage wiring and the electrode pattern are connected to each other through contact holes, and the contact holes and the holes do not overlap each other in the thickness direction of the display device. The width of the hole is smaller than the width of the second extended portion of the electrode pattern but larger than the width of the contact hole.

18. The display device according to claim 17, wherein, The contact hole overlaps with the protruding portion of the electrode pattern and the first extension portion of the voltage wiring, and The protruding portion of the electrode pattern is connected to the first extension portion of the voltage wiring.

Images