Resistive memory device

Abstract

A resistive memory device is provided. The resistive memory device includes a resistive memory cell electrically connected to a local word line node; a local word line transistor configured to electrically connect the local word line node to a global word line node; a global word line transistor configured to electrically connect the global word line node to a sense node; and a margin compensation circuit including a margin compensation switch electrically connected to the local word line node and the global word line node.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0091660, filed on July 29, 2019, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The methods and apparatus consistent with the embodiments relate to resistive memory devices. Background Technology

[0004] Examples of non-volatile memories using resistive materials include phase-change random access memory (PRAM), resistive RAM (RRAM), and magnetic RAM (MRAM). While dynamic RAM (DRAM) or flash memory uses charge to store data, non-volatile memories using resistive materials store data using the state changes of phase change materials (such as chalcogenide alloys) (in the case of PRAM), the resistance changes of variable resistive materials (in the case of RRAM), or the resistance changes of magnetic tunnel junction (MTJ) films based on the magnetization state of ferromagnetic materials (in the case of MRAM).

[0005] Specifically, the phase change material of the PRAM changes to either a crystalline or amorphous state upon heating and cooling. The phase change material exhibits low resistance in its crystalline state and high resistance in its amorphous state. Therefore, the crystalline state can be defined as setting data or data 0, and the amorphous state can be defined as resetting data or data 1. Summary of the Invention

[0006] A resistive memory device with improved read reliability is provided.

[0007] This disclosure is not limited to the embodiments described herein.

[0008] According to one aspect of the embodiments, a resistive memory device is provided, comprising: a resistive memory cell electrically connected to a local word line node; a local word line transistor configured to electrically connect the local word line node to a global word line node; a global word line transistor configured to electrically connect the global word line node to a sensing node; and a margin compensation circuit including a margin compensation switch electrically connected to the local word line node and the global word line node.

[0009] According to one aspect of the embodiments, a resistive memory device is provided, comprising: a resistive memory cell electrically connected to a bit line and a word line, the resistive memory cell being connected to the word line at a local word line node, and the resistive memory cell including an access element having a first threshold voltage; a local word line transistor configured to electrically connect the local word line node to a global word line node from a first time point to a second time point to precharge the word line to a precharge voltage; a global word line transistor configured to electrically connect the global word line node to a sensing node; and a word line precharge circuit configured to generate the precharge voltage and provide the precharge voltage to the sensing node. The local word line transistor is further configured to remain in an off state after the second time point, while the global word line transistor electrically connects the global word line node to the sensing node.

[0010] According to one aspect of an embodiment, a resistive memory device is provided, comprising: a power supply; a resistive memory cell electrically connected to a local bit line node and a local word line node; a clamping circuit configured to provide a clamping voltage based on power received from the power supply; a global bit line transistor configured to receive the clamping voltage from the clamping circuit; a local bit line transistor configured to receive the clamping voltage from the global bit line transistor and provide the clamping voltage to the resistive memory cell; a local word line transistor inserted between the local word line node and the global word line node; a global word line transistor inserted between the global word line node and a sensing node; a margin compensation circuit electrically connected to the local word line node and the global word line node, the margin compensation circuit including a margin compensation switch; a word line precharge circuit electrically connected to the sensing node; and a sensing amplifier including a first terminal connected to the sensing node and a second terminal connected to a reference node. Attached Figure Description

[0011] The above and other aspects and features will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating a resistive memory device according to some embodiments.

[0013] Figures 2 to 4 This illustrates some embodiments. Figure 1 A diagram of a resistive memory cell array.

[0014] Figure 5 This is another block diagram illustrating a resistive memory device according to some embodiments.

[0015] Figure 6 This is a graph showing the resistance distribution of a resistive memory cell in a resistive memory device according to some embodiments.

[0016] Figure 7This is a block diagram illustrating a resistive memory device.

[0017] Figure 8 yes Figure 7 An exemplary circuit diagram of the clamping unit.

[0018] Figure 9 It is an explanation Figure 7 Timing diagram of the operation of resistive memory devices.

[0019] Figure 10 It is an explanation Figure 7 A graph showing the operation of a resistive memory device.

[0020] Figure 11 This is a block diagram illustrating a resistive memory device according to some embodiments.

[0021] Figure 12 This illustrates some embodiments. Figure 11 An exemplary circuit diagram of a margin compensation switch in a margin compensation circuit of a resistive memory device.

[0022] Figure 13 This illustrates some embodiments. Figure 11 An exemplary circuit diagram of a region of a resistive memory device.

[0023] Figure 14 This illustrates some embodiments. Figure 11 Timing diagram of the operation of resistive memory devices.

[0024] Figure 15 This is an explanation of the inclusion of some embodiments. Figure 13 A graph showing the operation of a resistive memory device with a margin compensation circuit.

[0025] Figure 16 This illustrates some embodiments. Figure 11 Another exemplary circuit diagram of the area of ​​a resistive memory device.

[0026] Figure 17 This is an explanation of the inclusion of some embodiments. Figure 16 A graph showing the operation of a resistive memory device with a margin compensation circuit. Detailed Implementation

[0027] Figure 1 This is a block diagram illustrating a resistive memory device according to some embodiments. In the following description, the resistive memory device includes sixteen memory banks. Figure 1 The example shown is provided, but this disclosure is not limited thereto.

[0028] refer to Figure 1According to some embodiments, a resistive memory device includes a resistive memory cell array, a plurality of sense amplifiers and write drivers (SA / WD) 2_1 to 2_8, and a peripheral circuit region 3.

[0029] The resistive memory cell array may include multiple memory banks 1_1 to 1_16, and each of the memory banks 1_1 to 1_16 may include multiple memory blocks BLK0 to BLK7. Each of the memory blocks BLK0 to BLK7 includes multiple resistive memory cells arranged in a matrix. In the following description, an example is shown where each of the memory banks 1_1 to 1_16 includes eight memory blocks, but this disclosure is not limited thereto.

[0030] Row selection circuits and column selection circuits can be arranged to correspond to each of memory banks 1_1 to 1_16. The row selection circuits and column selection circuits specify the row and column of the resistive memory cell to be written to and read from, respectively.

[0031] Each of the sense amplifiers and write drivers 2_1 to 2_8 is arranged to correspond to two of the memory banks 1_1 to 1_16, and read and write operations are performed on these two corresponding memory banks. In embodiments of this disclosure, the case where each of the sense amplifiers and write drivers 2_1 to 2_8 corresponds to two of the memory banks 1_1 to 1_16 is used as an example, but this disclosure is not limited thereto. That is, each of the sense amplifiers and write drivers 2_1 to 2_8 may correspond to one memory bank or four memory banks.

[0032] Furthermore, in each of the sense amplifiers and write drivers 2_1 to 2_8, the number of sense amplifiers and the number of write drivers can be different from each other. In particular, the number of sense amplifiers can be greater than the number of write drivers.

[0033] In peripheral circuit area 3, multiple logic circuit blocks and power supplies can be configured to operate the column select circuit, the row select circuit, and the sense amplifier and write drivers 2_1 to 2_8.

[0034] Figures 2 to 4 This illustrates some embodiments. Figure 1 A diagram of a resistive memory cell array.

[0035] refer to Figure 2A resistive memory cell array can have a cross-point structure. A cross-point structure refers to a structure in which a resistive memory cell MC is formed in a region where one line intersects with another line. For example, bit lines BL1_1 to BL4_1 can extend in a first direction, and word lines WL1_1 to WL3_1 can extend in a second direction to intersect with bit lines BL1_1 to BL4_1. The resistive memory cell MC can be formed in the region where each of the bit lines BL1_1 to BL4_1 intersects with each of the word lines WL1_1 to WL3_1. Each resistive memory cell MC may include a variable resistor element B and an access element A that controls the current flowing through the variable resistor element B.

[0036] refer to Figure 3 According to some embodiments, the memory cell 100 of the resistive memory cell array may include a first memory cell MC1 disposed between a word line (e.g., WL1_1) and a bit line (e.g., BL4_1), and a second memory cell MC2 disposed between another word line (e.g., WL2_1) and a bit line (e.g., BL4_1). The first memory cell MC1 and the second memory cell MC2 may operate as independent memory cells.

[0037] The first memory cell MC1 may include a first heating electrode 110, a first information storage element 120, a first switching element 130, etc. The first switching element 130 may include a first switching electrode 131, a second switching electrode 132, and a first selection layer 133 disposed therebetween. In some embodiments, the first selection layer 133 may include a bidirectional threshold switch (OTS) material. When a voltage greater than a threshold voltage is applied between the first switching electrode 131 and the second switching electrode 132, current can flow through the first selection layer 133.

[0038] In the direction in which the first heating electrode 110 and the first information storage element 120 contact each other, the cross-sectional area of ​​the first heating electrode 110 may be the same as or different from the cross-sectional area of ​​the first information storage element 120. When the cross-sectional area of ​​the first heating electrode 110 is different from the cross-sectional area of ​​the first information storage element 120 in the direction in which the first heating electrode 110 and the first information storage element 120 contact each other, the temperature applied to the first memory cell MC1 during the operation of the semiconductor device may vary, and in this case, the process may be increased or changed.

[0039] In some embodiments, the first memory unit MC1 may not include the first heating electrode 110.

[0040] The first information storage element 120 may include a phase change material. In some embodiments, the first information storage element 120 may include a chalcogenide material, but the embodiments are not limited thereto. In some other embodiments, the first information storage element 120 may include, for example, Ge-Sb-Te (GST). Based on the type and chemical composition ratio of the elements included in the first information storage element 120, the crystallization temperature, melting point, and phase change rate based on the crystallization energy of the first information storage element 120 can be determined.

[0041] The second memory cell MC2 may have a structure similar to that of the first memory cell MC1. The second memory cell MC2 may include a second heating electrode 140, a second information storage element 150, a second switching element 160, etc. The structure and characteristics of the second heating electrode 140, the second information storage element 150, and the second switching element 160 may be similar to the structure and characteristics of the first heating electrode 110, the first information storage element 120, and the first switching element 130, respectively. The second switching element 160 may include a first switching electrode 161, a second switching electrode 162, and a selection layer 163 disposed therebetween.

[0042] In some embodiments, the second memory unit MC2 may not include the second heating electrode 140.

[0043] like Figure 4 As shown, according to some embodiments, the resistive memory cell array can have a three-dimensional (3D) stacked structure. A 3D stacked structure refers to a structure in which multiple resistive memory cell layers 111_1 to 111_8 are vertically stacked. Although eight resistive memory cell layers 111_1 to 111_8 are shown stacked in the figures, this disclosure is not limited thereto. Each of the resistive memory cell layers 111_1 to 111_8 may include multiple groups of resistive memory cells and / or multiple groups of redundant memory cells. If the resistive memory cell array has a 3D stacked structure, each of the resistive memory cell layers 111_1 to 111_8 may have… Figure 2 The intersection structure. However, this disclosure is not limited thereto.

[0044] When the resistive memory cells in resistive memory cell layers 111_1 to 111_8 are PRAMs, the resistive memory cell MC may include a variable resistive element B containing a phase change material and an access element A that controls the current flowing through the variable resistive element B. Here, the access element A may be a diode or a transistor connected in series with the variable resistive element B.

[0045] Examples of phase change materials can include combinations of two elements (such as GaSb, InSb, InSe, Sb₂Te₃, or GeTe), combinations of three elements (such as GeSbTe, GaSeTe, InSbTe, SnSb₂Te₄, or InSbGe), and combinations of four elements (such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), or Te). 81 Ge 15 Sb2S2). Among them, GeSbTe, which contains germanium (Ge), antimony (Sb) and tellurium (Te), can usually be used as a phase change material.

[0046] For example, when the resistive memory cells in resistive memory cell layers 111_1 to 111_8 are RRAM, the variable resistance element B may include NiO or perovskite. Perovskite may be, for example, permanganate (Pr 0.7 Ca 0.3 MnO3, Pr 0.5 Ca 0.5 The composition includes MnO3, other PCMO, LCMO, etc., titanate (STO:Cr) or zirconate (SZO:Cr, Ca2Nb2O7:Cr, Ta2O5:Cr). The filament can be formed in the variable resistive element B.

[0047] In resistive memory cell layers 111_1 to 111_8 according to some embodiments, bit lines and / or word lines may be shared between adjacent resistive memory cell layers (e.g., 111_7 and 111_8).

[0048] Figure 5 This is a block diagram illustrating a resistive memory device according to some embodiments.

[0049] refer to Figure 5 According to some embodiments, a resistive memory device may include a peripheral logic structure PS and a cell array structure CS.

[0050] The cell array structure CS can be stacked on the peripheral logic structure PS. That is, in a plan view, the peripheral logic structure PS and the cell array structure CS can overlap each other. According to some embodiments, resistive memory devices can have a cell over periphery (COP) structure.

[0051] For example, the cell array structure CS can include Figures 2 to 4 An array of resistive memory cells. The peripheral logic structure PS may include... Figure 1 Peripheral circuit area 3.

[0052] The cell array structure CS may include multiple memory cell blocks BLK1 to BLKn arranged on the peripheral logic structure PS.

[0053] Figure 6 This is a graph showing the resistance distribution of a resistive memory cell in a resistive memory device according to some embodiments.

[0054] refer to Figure 6 A resistive memory cell can be, for example, a single bit cell. A resistive memory cell can also be a multi-bit cell. However, this disclosure is not limited thereto. In the following, it is assumed that the resistive memory cell is a single bit cell.

[0055] A resistive memory cell can store either first data ST or second data RST. Figure 6 The resistance distribution shown can be the distribution immediately following the write operation.

[0056] The first data ST and the second data RST can correspond to the first resistance level L1 and the second resistance level L2, respectively. The resistance values ​​can increase in the order of the first resistance level L1 and the second resistance level L2. For example, the first resistance level L1 is greater than RH1 and less than RL1, and the second resistance level L2 is greater than RH2 and less than RL2. Here, RL1, RL2, RH1, and RH2 can be reference values ​​used in the verification read operation to check whether the write operation was performed correctly during the write operation.

[0057] exist Figure 6 In the resistance distribution shown, in a resistive memory cell array, based on a reference voltage or read voltage Vread, the SET state (e.g., first data ST) can correspond to the case where the variable resistive element is in a crystalline state. The RESET state (e.g., second data RST) can correspond to the case where the variable resistive element is in an amorphous state.

[0058] Figure 7 This is a block diagram illustrating a resistive memory device for sensing charge.

[0059] refer to Figure 7 The resistive memory device may include a power supply 200, a clamping switch transistor CST, a clamping unit 210, a global bit line transistor GPTn, a local bit line transistor LPTn, a resistive memory cell 220, and a charging capacitor C. A Local word line transistor LNTn, parasitic capacitance C PAR The system includes a global word line transistor GNTn, a sense amplifier 230, a reference voltage transistor RVT, and a precharge unit 240.

[0060] Resistive memory cell 220 is one of a plurality of resistive memory cells in a memory cell array, and can be selectively read from the plurality of resistive memory cells. Because resistive memory cell 220 is related to the above... Figure 2 The resistive memory cell MC is the same, so its detailed description will be omitted.

[0061] Power supply 200 can supply power voltage to clamping unit 210 through power node NP. In this case, clamping switch transistor CST connected between power supply 200 and clamping unit 210 can be turned on or off by clamping activation signal CL_EN to transfer the power voltage supplied from power supply 200 to power node NP or prevent the power voltage from being transferred to power node NP.

[0062] Clamp unit 210 can receive a power supply voltage VP from power supply 200. Clamp unit 210 can clamp the power supply voltage VP received from power supply 200 to a clamping voltage VC for bit line pre-charging. Specifically, clamp unit 210 can receive a clamping control voltage VCon from an external source and transmit the clamping voltage VC to the clamping node NC. For example, clamp unit 210 may include, for example, a clamping control voltage VCon. Figure 8 The circuit structure shown is shown.

[0063] Figure 8 This is an exemplary circuit diagram of clamping unit 210. (Example circuit diagram follows.) Figure 7 As shown, clamping unit 210 can be connected between global bit-line transistor GPTn and power node NP. Specifically, clamping unit 210 includes clamping transistor CNT to which a power supply voltage VP is applied. Operational amplifier OP is connected to the gate of clamping transistor CNT. Clamping control voltage Vcon is applied to the negative input terminal (-) of operational amplifier OP. Clamping voltage can be applied to the positive input terminal (+) of operational amplifier OP.

[0064] Refer again Figure 7 The global bit-line transistor GPTn can receive the clamping voltage VC from the clamping node NC. The global bit-line transistor GPTn can also receive the global bit-line control voltage GYn to transfer the clamping voltage VC to the local bit-line transistor LPTn. Multiple local bit-line transistors LPTn can be connected to a single global bit-line transistor GPTn.

[0065] The local bitline transistor LPTn can receive the clamping voltage VC from the global bitline transistor GPTn. The local bitline transistor LPTn can also receive the local bitline control voltage LYn to transmit the clamping voltage VC to the bitline node NB.

[0066] The bit lines of resistive memory cell 220 can receive a clamping voltage VC from the local bit line transistor LPTn, causing the clamping voltage VC to be pre-charged to bit line node NB after a predetermined time point. After a specific time period, bit line node NB can be pre-charged to the clamping voltage VC. (See later...) Figure 9 and Figure 10 Describe the operation over time in detail.

[0067] The precharge unit 240 includes first precharge transistors PCT1 through PCTn. Each gate of precharge transistors PCT1 through PCTn can be configured to receive a corresponding selection signal, and one of the first precharge voltages Vpre1 ​​through VpreN can be transmitted to the sensing node NS based on which of the precharge transistors PCT1 through PCTn is selected. For example, the first precharge transistor PCT1 can be turned on by the selection signal SEL1, transmitting the first precharge voltage Vpre1 ​​to the sensing node NS.

[0068] The global word line transistor GNTn can be gated by the global word line control voltage GXn to transfer the precharge voltage received through the sensing node NS to the global word line node NG.

[0069] The local word line transistor LNTn can be selected by the local word line control voltage LXn to transfer the precharge voltage to the local word line node NW through the global word line node NG.

[0070] The word line of resistive memory cell 220 can receive a pre-charge voltage from the local word line transistor LNTn, such that the pre-charge voltage is pre-charged to the local word line node NW after a predetermined time point. After a specific time period, the local word line node NW can be pre-charged to the pre-charge voltage. (See later...) Figure 9 and Figure 10 Describe the operation over time in detail.

[0071] Subsequently, when the voltage between the bit line node NB and the local word line node NW is greater than or equal to the threshold voltage of the resistive memory cell 220, the charge in the bit line node NB can be transferred to the local word line node NW. During this process, the charge accumulated in the local word line node NW can be accumulated in the charging capacitor C. A Chinese. Will refer to later. Figure 9 and Figure 10 Describe the operation over time in detail.

[0072] The sensing amplifier 230 can receive a reference voltage Vref from the reference node NR and output a sensed output value Sout by comparing the reference voltage Vref with the voltage of the sensing node NS. At any time point after the bit line node NB is pre-charged with the pre-charge voltage, the reference voltage transistor RVT can be turned on by the switching voltage VS to make the voltage of the reference node NR equal to the voltage of the sensing node NS. The reference voltage transistor RVT can be an NMOS transistor, but is not limited to it, and can also be a PMOS transistor or a transfer transistor. The voltage of the sensing node NS or the voltage of the reference node NR (making them equal) can be compared with the voltage of the charging capacitor C. A The voltage of the local word line node NW is compared with the voltage of the accumulated charge. The voltage of the local word line node NW can be transmitted to the sensing node NS through the local word line transistor LNTn and the global word line transistor GNTn. The sensing amplifier 230 can determine whether the resistive memory cell 220 is in reference mode based on the voltage transmitted to the sensing node NS. Figure 6 The description of the SET or RESET state determines the output of the sensed value Sout, which can be simply referred to as charge sensing.

[0073] However, parasitic capacitance may form in the global word line node NG through transistors surrounding it. Therefore, when the local word line transistor LNTn is turned on to charge capacitor C... A Problems may arise when the charge moves to the sensing amplifier 230. That is, because charge sharing occurs in the charging capacitor C... A and parasitic capacitance C PAR Between, therefore the charging capacitor C A The charge in the capacitor is retained and cannot be transferred to the sensing amplifier 230. In charge sensing, when the capacitor C is charged... A According to the law of conservation of charge and parasitic capacitance C PAR When sharing charge, the sensing margin of resistive memory devices may decrease. This will refer to... Figures 9 to 10 The time-related graph is used to describe it.

[0074] Figure 9 It is an explanation Figure 7 Timing diagram of the operation of resistive memory devices. Figure 10 It is an explanation Figure 7 A graph showing the operation of a resistive memory device.

[0075] refer to Figures 7 to 10Before the first time point t1, the global bit line control voltage GYn, the local bit line control voltage LYn, and the clamp activation signal CL_EN go high, while the global bit line transistor GPTn, the local bit line transistor LPTn, and the clamp switch transistor CST remain off. Therefore, at the first time point t1, the local word line node NW, the bit line node NB, the global word line node NG, and the sensing node NS can have arbitrary initial voltage values. These arbitrary initial voltage values ​​can be, for example, 0V.

[0076] During the word line precharge period tWP from the first time point t1 to the second time point t2, the local word line node NW can be precharged by the precharge voltage (e.g., Vpre1) supplied from the precharge unit 240.

[0077] In this scenario, the global bitline control voltage GYn and the local bitline control voltage LYn can be switched low at the first time point t1 to turn on the global bitline control transistor GPTn and the local bitline control transistor LPTn. However, because the clamp activation signal CL_EN remains logic high from the first time point t1 to the second time point t2, the power supply voltage VP supplied from power supply 200 may not be transmitted to the bitline node NB. Therefore, the bitline node NB maintains an arbitrary initial voltage value until the second time point t2.

[0078] Because the global word line control voltage GXn remains logic high from the first time point t1 to the fourth time point t4, the global word line transistor GNTn can remain on. To precharge the local word line node NW, the local word line transistor LNTn can be turned on by keeping the local word line control voltage LXn logic high during the word line precharge period tWP from the first time point t1 to the second time point t2.

[0079] The precharge voltage (e.g., Vpre1) delivered from the precharge unit 240 can be delivered to the local word line node NW via the global word line transistor GNTn and the local word line transistor LNTn. The local word line node NW can be precharged from any initial voltage value to the precharge voltage (e.g., Vpre1) during the word line precharge period tWP.

[0080] After the local word line node NW is precharged to the precharge voltage (e.g., Vpre1), the bit line node NB is precharged during the bit line precharge period tBP from a second time point t2 to a third time point t3. In resistive memory devices according to some embodiments, the local word line node NW may be floated for at least a portion of the bit line precharge period tBP.

[0081] Specifically, by keeping the global bit line control voltage GYn and the local bit line control voltage LYn low during the bit line precharge period tBP, the global bit line transistor GPTn and the local bit line transistor LPTn can remain in the on state. By keeping the clamp activation signal CL_EN low during the bit line precharge period tBP, the clamp switch transistor CST can remain in the on state.

[0082] In other words, the power supply voltage VP supplied from power source 200 can be transmitted to power node NP via clamping switching transistor CST. Subsequently, clamping unit 210 can generate clamping voltage VC for pre-charging bit line node NB. Clamping unit 210 can transmit the generated clamping voltage VC to bit line node NB via global bit line transistor GPTn and local bit line transistor LPTn for pre-charging bit line node NB. During the bit line pre-charging period tBP after the second time point t2, bit line node NB can be pre-charged from any initial voltage value to the clamping voltage VC.

[0083] At this time, at time t0 after the second time point t2 when the reference voltage transistor is turned on, in the sense amplifier 230, the reference voltage transistor RVT connected between the reference node NR and the sense node NS to which the reference voltage Vref is applied can be turned on by the switching voltage VS, so that the voltage between the sense node NS and the reference node NR is equal. Thereafter, the sense amplifier 230 compares the voltage between the sense node NS and the reference node NR (making them equal) with the voltage of the local word line node NW, thereby sensing whether the resistive memory cell 220 is in a SET state or a RESET state.

[0084] After the reference voltage transistor turns on at time point t0, the voltage difference between the pre-charged local word line node NW and the pre-charged bit line node NB can be the threshold voltage Vth at which the resistive memory cell 220 turns on. After the threshold voltage time point tr, where the voltage difference between the pre-charged local word line node NW and the pre-charged bit line node NB becomes the threshold voltage Vth, the voltage level of the local word line node NW can vary depending on whether the resistive memory cell 220 is in a SET state or a RESET state.

[0085] Specifically, when the resistive memory cell 220 is in the SET state, the local word line node NW, precharged to a precharge voltage (e.g., Vpre1), can be charged by charge from the precharged bit line node NB, and this voltage can be varied along the NWSET curve. When the local word line node NW receives charge from the bit line node NB through the resistive memory cell 220, this charge can be stored in the charging capacitor C. A middle.

[0086] If the resistive memory cell 220 is in the RESET state, the local word line node NW, which is precharged to a precharge voltage (e.g., Vpre1), may not be charged by the charge from the precharged bit line node NB, and this voltage may be maintained at the precharge voltage (e.g., Vpre1) along the NWRST curve. That is, because the resistive memory cell 220 is not turned on, the local word line node NW is maintained at the precharge voltage (e.g., Vpre1), as shown in the NWRST curve.

[0087] The voltage between the NWSET curve and the NWRST curve can be maintained at the difference between the threshold voltage Vth and the sustaining voltage Vh generated by the resistive memory cell 220 due to the snapback phenomenon, wherein the resistive memory cell 220 is turned on at the threshold voltage Vth.

[0088] After the bit line node NB is precharged to the clamping voltage VC through the bit line precharge period tBP, during the sensing period tSA from the third time point t3 to the fourth time point t4, the charging capacitor C A The charge in the charging state can be compared with the charge at the sensing node NS to sense whether the resistive memory cell 220 is in a SET state or a RESET state.

[0089] Specifically, after the third time point t3, by making the global bitline control voltage GYn and the local bitline control voltage LYn logic high, the global bitline transistor GPTn and the local bitline transistor LPTn can be turned off. That is, the clamping voltage VC can be prevented from being transmitted to the bitline node NB. Additionally, the clamping activation signal CL_EN can also become logic high, and the power supply voltage VP generated from power supply 200 can be prevented from being transmitted to clamping unit 210. In other words, the pre-charging of the bitline node NB is stopped.

[0090] By maintaining the global word line control voltage GXn at logic high until the fourth time point t4, the global word line transistor GNTn can remain on. The local word line control voltage LXn can go high at the third time point t3 and remain high until the fourth time point t4. That is, during the sensing period tSA, both the local word line transistor LNTn and the global word line transistor GNTn can be turned on to move the charge charged in the local word line node NW to the sensing node NS.

[0091] However, according to Equation 1, when the local word line transistor LNTn is turned on, the charging capacitor C A The total charge during charging should be equal to the charge of the parallel-connected charging capacitor C. A and parasitic capacitance C PARThe amount of charge stored in them is the same.

[0092] C A *(Vth-Vs) = (C A +C PAR )*(ΔV SMQ Equation 1

[0093] When the local word line transistor LNTn is turned on, the charging capacitor C... A and the parasitic capacitance C formed at the global word line node NG. PAR Charge sharing may occur between them.

[0094] In other words, after the third time point t3, the local word line transistor LNTn can be turned on to charge the capacitor C. A and parasitic capacitance C PAR A parallel connection is formed between them. Due to charge sharing, based on the charge sharing at the charge sharing time point tq after the third time point t3 after the start of sensing, the NWSET curve of the local word line node NW can have the SET charge sharing voltage V. SMQ Similarly, due to charge sharing, based on the charge sharing at the charge sharing time point tq after the third time point t3 at the start of sensing, the NWRST curve of the local word line node NW can have the RESET charge sharing voltage V. SMQ RST.

[0095] If due to parasitic capacitance C PAR If charge sharing does not occur, then even during the sensing period tSA, the voltage of the local word line node NW in the SET state can maintain the SET ideal voltage V. SMI SET. That is, the SET sensing margin between the voltage of the sensing node NS and the voltage of the local word line node NW (through which the sensing amplifier 230 can determine whether the resistive memory cell 220 is in a SET state) can be maintained at a high value, such as the SET ideal margin ΔV. SMI SET.

[0096] However, when due to parasitic capacitance C PAR When charge sharing occurs, after the charge sharing time point tq, the voltage of the local word line node NW can be lower than the ideal voltage V of SET. SMI SET charge-sharing voltage V SMQ SET. That is, the SET sensing margin between the voltage of sensing node NS and the voltage of local word line node NW (through which sensing amplifier 230 can determine whether resistive memory cell 220 is in a SET state) has a lower than the ideal SET voltage V. SMISET charge sharing margin ΔV SMQ Therefore, the reliability of the result obtained by the sensing amplifier 230 in determining whether the resistive memory cell 220 is in a SET state may be reduced.

[0097] Similarly, if due to parasitic capacitance C PAR Since charge sharing does not occur, the voltage of the local word line node NW in the RESET state can maintain the ideal RESET voltage V even during the sensing period tSA. SMI RST. In other words, the RESET sensing margin between the voltage of the sensing node NS and the voltage of the local word line node NW (through which the sensing amplifier 230 can determine whether the resistive memory cell 220 is in a RESET state) can be maintained at a high value, such as the RESET ideal margin ΔV. SMI RST.

[0098] However, when due to parasitic capacitance C PAR When charge sharing occurs, after the charge sharing time point tq, the voltage of the local word line node NW can be lower than the ideal RESET voltage V. SMI RST's RESET charge-sharing voltage V SMQ RST. In other words, the RESET sensing margin between the voltage of sensing node NS and the voltage of local word line node NW (through which sensing amplifier 230 can determine whether resistive memory cell 220 is in a RESET state) has a lower than the ideal RESET margin ΔV. SMI RST's RESET charge sharing margin ΔV SMQ RST. Therefore, the reliability of the result obtained by the sensing amplifier 230 in determining whether the resistive memory cell 220 is in a RESET state may be reduced.

[0099] In other words, due to the parasitic capacitance C PAR and charging capacitor C A Charge sharing between them is used by the sensing amplifier 230 to determine whether the resistive memory cell 220 is in a SET or RESET state, with a sensing margin from the ideal margin ΔV. SMI Reduced to charge sharing margin ΔV SMQ Furthermore, the reliability of resistive memory devices may be reduced.

[0100] In the following, a resistive memory device according to some embodiments for preventing a reduction in sensing margin due to charge sharing will be described.

[0101] Figure 11 This is a block diagram illustrating a resistive memory device according to some embodiments. Figure 12 This illustrates some embodiments. Figure 11 An exemplary circuit diagram of a margin compensation switch in a margin compensation circuit of a resistive memory device. In the following description, redundant descriptions will be omitted, and the differences will be described primarily.

[0102] refer to Figure 11 ,and Figure 7 Depending on the specific circumstances, the margin compensation circuit 250 can be connected to the local word line node NW and the global word line node NG. The margin compensation circuit 250 may include a margin compensation switch. For example... Figure 12 As shown, the margin compensation switch can be a margin compensation NMOS transistor MCNT. The margin compensation switch can also be a PMOS transistor or a transfer transistor, but is not limited to these.

[0103] In addition, with Figure 7 The situation differs depending on the specific implementation. Figure 11 In the resistive memory device, the circuitry for switching between the reference node NR and the sensing node NS of the sensing amplifier 230 can be omitted. That is, the sensing amplifier 230 can sense the difference between the reference voltage Vref and the voltage of the sensing node NS, and output the result of determining whether the resistive memory cell 220 is in a SET state or a RESET state as a sensing output value Sout.

[0104] refer to Figure 12 In the margin compensation circuit 250, the margin compensation NMOS transistor MCNT can be selected by the local word line node NW to transfer the margin compensation voltage VMC connected to the drain to the global word line node NG. When the margin compensation switch is a PMOS transistor, the margin compensation voltage VMC connected to the source can be transferred to the global word line node NG. The operation of the margin compensation switch is not limited to this, and other switching operations are possible depending on the switch configuration, as long as the switch operation is selected by the local word line node NW to transfer the margin compensation voltage VMC to the global word line node NG. Furthermore, according to some embodiments, the margin compensation voltage VMC may correspond to ground voltage. However, this disclosure is not limited thereto.

[0105] Figure 13 This illustrates some embodiments. Figure 11 An exemplary circuit diagram of region R of a resistive memory device. Based on the discussion below and... Figure 13 In some embodiments shown, the margin compensation circuit 250 can be connected to a resistive memory device. Hereinafter, the description will be given assuming that the margin compensation switch in the margin compensation circuit 250 is a margin compensation NMOS transistor MCNT.

[0106] refer to Figures 11 to 13In region R, a resistive memory cell layer can be connected between a global bit line transistor GPTn that receives a clamping voltage VC from clamping cell 210 and a global word line transistor GNTn that receives a pre-charge voltage from sensing node NS.

[0107] Specifically, multiple local bit line transistors LPT1n to LPTnn can be connected to a global bit line transistor GPTn. The multiple local bit line transistors LPT1n to LPTnn can transmit the clamping voltage VC received from the global bit line transistor GPTn to multiple bit lines BL1_1 to BLn_1 connected to it, respectively.

[0108] Additionally, multiple local word line transistors LNT1 to LNTn can be connected to a global word line transistor GNTn. The multiple local word line transistors LNT1 to LNTn can transmit the pre-charge voltage (e.g., Vpre1) received from the global word line transistor GNTn to multiple word lines WL1_1 to WLn_1 connected thereto.

[0109] As per the above reference Figure 2 As described, a resistive memory cell 220 can be formed at the intersection of each bit line and each word line. Because it is related to the reference... Figure 2 Since the descriptions are the same, a detailed description of them will be omitted.

[0110] According to some embodiments, the margin compensation circuit 250 of a resistive memory device may include a plurality of margin compensation switches, each selected by a plurality of local word line nodes NW1 to NWn. In the figures, the plurality of margin compensation switches are shown as a plurality of margin compensation NMOS transistors MCNT1 to MCNTn.

[0111] The source of each of the margin-compensated NMOS transistors MCNT1 to MCNTn can be connected to the global word line node NG. That is, each margin-compensated NMOS transistor MCNT1 to MCNTn can be selected by multiple local word line nodes NW to transmit the margin-compensated voltage VMC to the global word line node NG.

[0112] By connecting a margin compensation circuit 250 between the local word line node NW and the global word line node NG, the above reference can be prevented. Figure 7 The margin of the description is reduced. (Refer to...) Figure 14 and Figure 15 Provide a detailed description.

[0113] Figure 14 This illustrates some embodiments. Figure 11 Timing diagram of the operation of resistive memory devices. Figure 15 This is an explanation of the inclusion of some embodiments. Figure 13A graph showing the operation of a resistive memory device with a margin compensation circuit. For simplicity, references are omitted. Figures 7 to 10 The description is a repetitive description.

[0114] In the following text, it is assumed that the local bit line node NB, the local bit line transistor LPTn, the local word line node NW, and the local word line transistor LNTn are respectively the nth local bit line node NB among a plurality of local bit line nodes, the nth local bit line transistor LPTn among a plurality of local bit line transistors LPT1n to LPTnn, the nth local word line node NWn among a plurality of local word line nodes NW1 to NWn, and the nth local word line transistor LNTn among a plurality of local word line transistors LNT1 to LNTn.

[0115] refer to Figures 11 to 14 For the global bit line control voltage GYn, the local bit line control voltage LYn, the global word line control voltage GXn, the local word line control voltage LXn, and the clamp activation signal CL_EN, the logic value changes and references in the word line precharge period tWP and the bit line precharge period tBP are as follows. Figure 9 The description is the same. For the global bit line control voltage GYn, the local bit line control voltage LYn, the global word line control voltage GXn, and the clamp activation signal CL_EN, the logic value changes during the sensing period tSA are also the same as the reference. Figure 9 The descriptions are the same.

[0116] However, during the sensing period tSA, with Figure 9 In some embodiments of the resistive memory device, the local word line control voltage LXn remains logic low and the local word line transistor LNTn is turned off.

[0117] In other words, Figure 9 In the process, when the local word line control voltage LXn becomes logic high during the sensing period tSA and the local word line transistor LNTn is turned on, the local word line node NW and the global word line node NG share charge, resulting in a reduction in sensing margin.

[0118] However, according to some embodiments Figure 14 In the timing of resistive memory devices, the local word line transistor LNTn can be turned off by maintaining the local word line control voltage LXn at logic low during the sensing period tSA. Therefore, charge sharing between the local word line node NW and the global word line node NG will not occur during the sensing period tSA, thus preventing a reduction in sensing margin. This will refer to... Figure 15 A more detailed description is needed. (Omissions and references will be omitted.) Figures 7 to 10 The description is a repetitive description.

[0119] refer to Figures 11 to 15By turning off the local word line transistor LNTn during the sensing period tSA, the sensing margin can maintain the ideal margin ΔV. SMI .

[0120] In other words, because no charge sharing occurs between the local word line node NW and the global word line node NG, the NWSET curve can maintain the ideal SET voltage V even after the sensing period tSA. SMI SET. Furthermore, because no charge sharing occurs between the local word line node NW and the global word line node NG, the NWRST curve can maintain the ideal RESET voltage V even after the sensing period tSA. SMI RST.

[0121] When the pre-charge voltage (e.g., Vpre1) is less than the first margin compensation voltage VMC(a), the sensing operation of the sensing amplifier 230 can be performed along the sensing node curve NS(a), or when the pre-charge voltage (e.g., Vpre1) is greater than the second margin compensation voltage VMC(b), the sensing operation of the sensing amplifier 230 can be performed along the sensing node curve NS(b). Furthermore, the pre-charge voltage according to some embodiments of this disclosure may be less than 0. However, this disclosure is not limited thereto.

[0122] First, in the graph NS(a), starting from a first time point t1, the sensing node NS can have a pre-charge voltage (e.g., Vpre1) provided by the pre-charge unit 240. Subsequently, at the threshold voltage time point tr, the margin compensation NMOS switch can be turned on by the local word line node NW to transmit the first margin compensation voltage VMC(a) to the global word line node NG. That is, the sensing node NS can have a graph such as VSSET(a). If the margin compensation NMOS switch is not turned on by the local word line node NW at the threshold voltage time point tr, the sensing node NS maintains the pre-charge voltage (e.g., Vpre1) and can have a graph such as VSRST(a).

[0123] One could consider using a first margin compensation voltage VMC(a) to set the first reference voltage Vref, so that the first SET ideal margin ΔV SMI SET(a) and the first RESET ideal margin ΔV SMIRST(a) has a sufficiently large value. That is, according to some embodiments, the resistive memory device can perform the operation of sensing whether the resistive memory cell 220 is in a SET state or a RESET state independently, without turning on the local word line transistor LNTn. Therefore, the first reference voltage Vref and the first margin compensation voltage VMC(a) are specified to have the sensing margin required by the user, while not losing charge at the local word line node NW, thereby improving the reliability of the resistive memory device according to some embodiments.

[0124] Next, in the graph NS(b), starting from the first time point t1, the sensing node NS can have a pre-charge voltage (e.g., Vpre1) provided by the pre-charge unit 240. Thereafter, at the threshold voltage time point tr, the margin compensation NMOS switch can be turned on by the local word line node NW to transmit the second margin compensation voltage VMC(b) to the global word line node NG. That is, the sensing node NS can have a graph such as VSSET(b). If the margin compensation NMOS switch is not turned on by the local word line node NW at the threshold voltage time point tr, the sensing node NS maintains the pre-charge voltage (e.g., Vpre1) and can have a graph such as VSRST(b).

[0125] A second margin compensation voltage VMC(b) can be considered to set the second reference voltage Vref, so that the second SET ideal margin ΔV SMI SET(b) and the ideal margin ΔV of the second RESET SMI RST(b) has a sufficiently large value. That is, according to some embodiments, the resistive memory device can perform the operation of sensing whether the resistive memory cell 220 is in a SET state or a RESET state independently, without turning on the local word line transistor LNTn. Therefore, the second reference voltage Vref and the second margin compensation voltage VMC(b) are specified to have the sensing margin required by the user, while not losing charge at the local word line node NW, thereby improving the reliability of the resistive memory device according to some embodiments.

[0126] Figure 16 This illustrates some embodiments. Figure 11 Another exemplary circuit diagram of region R of a resistive memory device. For reference, except that the margin compensation transistor is a PMOS transistor and includes multiple margin compensation transistors MCPT1 to MCPTn, it has the same... Figure 13 Same configuration.

[0127] In region R, a resistive memory cell layer can be connected between a global bit line transistor GPTn that receives a clamping voltage VC from clamping cell 210 and a global word line transistor GNTn that receives a pre-charge voltage from sensing node NS.

[0128] Specifically, multiple local bit line transistors LPT1n to LPTnn can be connected to a global bit line transistor GPTn. The multiple local bit line transistors LPT1n to LPTnn can transmit the clamping voltage VC received from the global bit line transistor GPTn to multiple bit lines BL1_1 to BLn_1 connected to it, respectively.

[0129] Additionally, multiple local word line transistors LNT1 to LNTn can be connected to a global word line transistor GNTn. The multiple local word line transistors LNT1 to LNTn can transmit the pre-charge voltage (e.g., Vpre1) received from the global word line transistor GNTn to multiple word lines WL1_1 to WLn_1 connected thereto.

[0130] As per the above reference Figure 2 As described, a resistive memory cell 220 can be formed at the intersection of each bit line and each word line. Its detailed description will be omitted because it is consistent with the reference. Figure 2 The descriptions are the same.

[0131] According to some embodiments, the margin compensation circuit 250 of a resistive memory device may include a plurality of margin compensation switches, each selected by a plurality of local word line nodes NW1 to NWn. In the figures, the plurality of margin compensation switches are shown as a plurality of margin compensation PMOS transistors MCPT1 to MCPTn.

[0132] The drain of each of the margin-compensated PMOS transistors MCPT1 to MCPTn can be connected to the global word line node NG. That is, the corresponding margin-compensated PMOS transistors MCPT1 to MCPTn can be selected by multiple local word line nodes NW to transmit the margin-compensated voltage VMC to the global word line node NG.

[0133] By connecting the margin compensation circuit 250 between the local word line node NW and the global word line node NG, the above reference can be prevented. Figure 7 The margin of the description is reduced. (Refer to...) Figure 11 , Figure 12 , Figure 14 and Figure 16 Provide a detailed description.

[0134] Figure 17 This is an explanation of the inclusion of some embodiments. Figure 16 A graph showing the operation of a resistive memory device with a margin compensation circuit.

[0135] refer to Figure 11 , Figure 12 , Figure 14 , Figure 16 and Figure 17 For the global bit line control voltage GYn, the local bit line control voltage LYn, the global word line control voltage GXn, the local word line control voltage LXn, and the clamp activation signal CL_EN, the logic value changes and references in the word line precharge period tWP and the bit line precharge period tBP are as follows. Figure 9 The description is the same. For the global bit line control voltage GYn, the local bit line control voltage LYn, the global word line control voltage GXn, and the clamp activation signal CL_EN, the logic value changes during the sensing period tSA are also the same as the reference. Figure 9 The descriptions are the same.

[0136] However, during the sensing period tSA, with Figure 9 In some embodiments of the resistive memory device, the local word line control voltage LXn remains logic low and the local word line transistor LNTn remains off.

[0137] In other words, Figure 9 In the process, when the local word line control voltage LXn becomes logic high during the sensing period tSA and the local word line transistor LNTn is turned on, the local word line node NW and the global word line node NG share charge, resulting in a reduction in sensing margin.

[0138] However, according to some embodiments Figure 14 In resistive memory devices, the local word line transistor LNTn can be turned off by maintaining the local word line control voltage LXn at logic low during the sensing period tSA. Therefore, charge sharing between the local word line node NW and the global word line node NG does not occur during the sensing period tSA, thus preventing a reduction in sensing margin. This will refer to... Figure 17 A more detailed description is needed. (Omissions and references will be omitted.) Figures 7 to 10 The description is a repetitive description.

[0139] refer to Figure 11 , Figure 12 , Figure 14 , Figure 16 and Figure 17 By turning off the local word line transistor LNTn during the sensing period tSA, the sensing margin can maintain the ideal margin ΔV. SMI In other words, because no charge sharing occurs between the local word line node NW and the global word line node NG, the NWSET curve can maintain the ideal SET voltage V even after the sensing period tSA. SMISET. In addition, since charge sharing does not occur between the local word line node NW and the global word line node NG, the NWRST graph can maintain the RESET ideal voltage V even after the sensing period tSA SMI RST.

[0140] When the precharge voltage (e.g., Vpre1) is greater than the first margin compensation voltage VMC(a), the sensing operation of the sense amplifier 230 can be performed along the sensing node graph NS(a), or when the precharge voltage (e.g., Vpre1) is less than the second margin compensation voltage VMC(b), the sensing operation of the sense amplifier 230 can be performed along the sensing node graph NS(b).

[0141] First, in the graph NS(a), starting from the first time point t1, the sensing node NS may have the first margin compensation voltage VMC(a) connected to the source of the margin compensation PMOS transistor MCPTn. Compared with Figure 15 the case where, the margin compensation switch of the margin compensation circuit 250 is a PMOS transistor. Therefore, when the resistive memory cell 220 has a voltage lower than the threshold voltage, charge may not be transferred from the bit line node NB to the local word line node NW. In this case, a logic low is applied to the margin compensation PMOS transistor MCPTn, and the margin compensation PMOS transistor can be turned on. That is, from the first time point t1 to the threshold voltage time point tr at which a voltage greater than or equal to the threshold voltage Vth is applied to the resistive memory cell 220, the first margin compensation voltage VMC(a) can be transmitted to the sensing node NS through the margin compensation PMOS transistor MCPTn. Thereafter, at the threshold voltage time point tr, the margin compensation PMOS switch can be turned off by the local word line node NW, so that the precharge voltage (e.g., Vpre1) supplied by the precharge unit 240 is applied to the sensing node NS.

[0142] That is, when the resistive memory cell 220 is in the SET state, the sensing node NS may have a graph such as VSSET(a). If at the threshold voltage time point tr, the margin compensation PMOS switch MCPTn is not turned off by the local word line node NW, the sensing node NS maintains the first margin compensation voltage VMC(a), and may have a graph such as VSRST(a).

[0143] The first reference voltage Vref can be set in consideration of the first margin compensation voltage VMC(a), such that the first ideal SET margin ΔV SMI SET(a) and the first ideal RESET margin ΔV SMIRST(a) has a sufficiently large value. That is, according to some embodiments, the resistive memory device can perform the operation of sensing whether the resistive memory cell 220 is in a SET state or a RESET state independently, without turning on the local word line transistor LNTn. Therefore, the first reference voltage Vref and the first margin compensation voltage VMC(a) are specified to have the sensing margin required by the user, while not losing charge at the local word line node NW, thereby improving the reliability of the resistive memory device according to some embodiments.

[0144] Next, in the graph NS(b), starting from the first time point t1, the sensing node NS can have a second margin compensation voltage VMC(b) connected to the source of the margin compensation PMOS transistor MCPTn. Figure 15 Unlike other cases, the margin compensation switch of the margin compensation circuit 250 is a PMOS transistor. Therefore, when the resistive memory cell 220 has a voltage below the threshold voltage, charge may not transfer from the bit line node NB to the local word line node NW. In this case, a logic low is applied to the margin compensation PMOS transistor MCPTn, and the margin compensation PMOS transistor can be turned on. That is, from the first time point t1 to the threshold voltage time point tr at which a voltage greater than or equal to the threshold voltage Vth is applied to the resistive memory cell 220, the first margin compensation voltage VMC(a) can be transferred to the sensing node NS through the margin compensation PMOS transistor MCPTn. Thereafter, at the threshold voltage time point tr, the margin compensation PMOS switch can be turned off by the local word line node NW to apply the pre-charge voltage (e.g., Vpre1) supplied from the pre-charge cell 240 to the sensing node NS.

[0145] In other words, when the resistive memory cell 220 is in the SET state, the sensing node NS can have a graph such as VSSET(b). If the margin-compensated PMOS switch MCPTn is not turned off by the local word line node NW at the threshold voltage time point tr, the sensing node NS maintains the second margin-compensated voltage VMC(b) and can have a graph such as VSRST(b).

[0146] A second margin compensation voltage VMC(b) can be considered to set the second reference voltage Vref, so that the second SET ideal margin ΔV SMI SET(b) and the ideal margin ΔV of the second RESET SMIRST(b) has a sufficiently large value. That is, according to some embodiments, the resistive memory device can perform the operation of sensing whether the resistive memory cell 220 is in a SET state or a RESET state independently, without turning on the local word line transistor LNTn. Therefore, the second reference voltage Vref and the second margin compensation voltage VMC(b) are specified to have the sensing margin required by the user, while not losing charge at the local word line node NW, thereby improving the reliability of the resistive memory device according to some embodiments.

[0147] Although embodiments have been described, those skilled in the art will understand that many changes and modifications can be made without departing from the principles of this disclosure.

Claims

1. A resistive memory device, comprising: Resistive memory cells are electrically connected to local word line nodes; Local word line transistors are configured to electrically connect the local word line node to the global word line node; A global word line transistor is configured to electrically connect the global word line node to a sensing node; as well as A margin compensation circuit includes a margin compensation switch electrically connected to the local word line node and the global word line node, wherein the margin compensation switch is configured to provide a margin compensation voltage to the global word line node based on the voltage applied to the local word line node.

2. The resistive memory device of claim 1, further comprising a word line precharge circuit configured to provide a precharge voltage to the sensing node.

3. The resistive memory device according to claim 2, in, The margin compensation voltage is greater than the pre-charge voltage.

4. The resistive memory device according to claim 2, in, The margin compensation voltage is less than the pre-charge voltage.

5. The resistive memory device according to claim 4, wherein, The margin compensation voltage corresponds to the grounding voltage.

6. The resistive memory device according to claim 1, wherein, The margin compensation switch is configured to provide the margin compensation voltage to the global word line node based on the fact that the voltage applied to the local word line node is a ground voltage.

7. A resistive memory device, comprising: A resistive memory cell electrically connected to a bit line and a word line, the resistive memory cell being connected to the word line at a local word line node, and the resistive memory cell including an access element having a first threshold voltage; A local word line transistor is configured to electrically connect the local word line node to a global word line node from a first time point to a second time point in order to precharge the word line to a precharge voltage. A global word line transistor is configured to electrically connect the global word line node to a sensing node; A word line precharge circuit is configured to generate the precharge voltage and provide the precharge voltage to the sensing node; as well as A margin compensation switch, electrically connected to the global word line node and the local word line node, is configured to provide a margin compensation voltage to the global word line node based on the voltage applied to the local word line node. The local word line transistor is further configured to remain off after the second time point, while the global word line transistor electrically connects the global word line node to the sensing node.

8. The resistive memory device according to claim 7, wherein, The margin compensation switch is also configured to provide the margin compensation voltage to the global word line node at a third time point.

9. The resistive memory device according to claim 7, wherein, The margin compensation voltage is greater than the pre-charge voltage.

10. The resistive memory device according to claim 7, wherein, The margin compensation voltage is less than the pre-charge voltage.

11. The resistive memory device according to claim 7, wherein, The margin compensation switch is also configured to provide the margin compensation voltage to the global word line node from the first time point to the third time point, and The pre-charge voltage is provided to the global word line node after the third time point.

12. The resistive memory device according to claim 7, wherein, After the word line is precharged to the precharge voltage, and after a third time point when the voltage difference between the bit line and the word line becomes the first threshold voltage, the voltage of the global word line node becomes the margin compensation voltage.

13. The resistive memory device according to claim 12, wherein, The pre-charge voltage is less than 0.

14. The resistive memory device according to claim 12, wherein, The margin compensation voltage corresponds to the grounding voltage.

15. The resistive memory device according to claim 7, wherein, After the second time point, during at least a portion of the bit line pre-charging period during which the bit line is pre-charged to the clamping voltage, the word line is floated.

16. A resistive memory device, comprising: power supply; Resistive memory cells are electrically connected to local bit line nodes and local word line nodes; A clamping circuit is configured to provide a clamping voltage based on power received from the power source; A global bit-line transistor is configured to receive the clamping voltage from the clamping circuit; A local bitline transistor is configured to receive the clamping voltage from the global bitline transistor and provide the clamping voltage to the resistive memory cell; Local word line transistors are inserted between local word line nodes and global word line nodes; A global word line transistor is inserted between the global word line node and the sensing node; A margin compensation circuit, electrically connected to the local word line node and the global word line node, the margin compensation circuit including a margin compensation switch configured to provide a margin compensation voltage to the global word line node based on the voltage applied to the local word line node; The word line pre-charge circuit is electrically connected to the sensing node; as well as The sensing amplifier includes a first terminal connected to the sensing node and a second terminal connected to the reference node.

17. The resistive memory device according to claim 16, wherein, The word line precharge circuit is configured to provide a precharge voltage to the sensing node.

18. The resistive memory device according to claim 17, wherein, The margin compensation voltage is greater than the pre-charge voltage.

19. The resistive memory device according to claim 17, wherein, The margin compensation voltage is less than the pre-charge voltage.

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