Semiconductor package structure and method of manufacturing the same

Abstract

A semiconductor package structure and a method of manufacturing the same are disclosed. The semiconductor package structure includes a first semiconductor device, a redistribution structure, a second semiconductor device, and a plurality of conductive components. The first semiconductor device has an active surface. The redistribution structure is electrically connected with the first semiconductor device. The second semiconductor device is bonded to the active surface of the first semiconductor device and disposed between the first semiconductor device and the redistribution structure. The conductive components are located on the active surface of the first semiconductor device and outside of the second semiconductor device, wherein the first semiconductor device electrically connects the redistribution structure through the conductive components.

Description

[0001] Cross-referencing related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 878,593, filed July 25, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to semiconductor packaging, and more specifically, to a semiconductor packaging structure and a method of manufacturing said semiconductor packaging structure. Background Technology

[0004] As device electrical performance continues to drive the development of more efficient packaging solutions, methods to address speed / performance challenges will be needed. For example, semiconductor chips are being integrated with an increasing number of electronic components to achieve improved electrical performance and additional functionality. Therefore, to enable electrical connections and signal transmission between these chips and components, more intermediate substrates, redistributed structures, input / output (I / O) pads, and solder balls are required. All these various signal "interfaces" can generate electrical losses. Therefore, packaging structures that can reduce these losses are needed. Summary of the Invention

[0005] Embodiments of this disclosure provide a semiconductor package structure. The semiconductor package structure includes: a first semiconductor device having an active surface; a redistribution structure electrically connected to the first semiconductor device; a second semiconductor device coupled to the active surface of the first semiconductor device and disposed between the first semiconductor device and the redistribution structure; and a plurality of conductive components located on the active surface of the first semiconductor device and outside the second semiconductor device, wherein the first semiconductor device is electrically connected to the redistribution structure through the conductive components.

[0006] Embodiments of this disclosure provide a method for manufacturing a semiconductor package structure. The method includes: providing a first semiconductor device having an active surface; forming a plurality of conductive components on the active surface of the first semiconductor device; bonding a second semiconductor device to the active surface of the first semiconductor device, wherein the conductive components are located outside the second semiconductor device; and forming a redistribution structure electrically connected to the first semiconductor device via the conductive components, wherein the second semiconductor device is disposed between the first semiconductor device and the redistribution structure. Attached Figure Description

[0007] Various aspects of some embodiments of this disclosure will be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 This is a cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure.

[0009] Figure 1A This is a cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure.

[0010] Figure 2A It is displayed as Figure 1 The diagram illustrates the relatively short power supply paths for the first and second semiconductor devices in the semiconductor package structure described herein.

[0011] Figure 2B This is a schematic diagram showing a relatively long path for powering the first and second semiconductor devices in different semiconductor package structures.

[0012] Figure 3A This is a cross-sectional view of a semiconductor package structure according to another embodiment of the present disclosure.

[0013] Figure 3B This is a cross-sectional view of a semiconductor package structure according to yet another embodiment of the present disclosure.

[0014] Figure 3C This is a cross-sectional view of a semiconductor package structure according to yet another embodiment of the present disclosure.

[0015] Figure 3D This is a cross-sectional view of a semiconductor package structure according to yet another embodiment of the present disclosure.

[0016] Figure 4A and 4B It is based on the embodiments of this disclosure. Figure 3A A schematic top view of the substrate in the semiconductor package structure illustrated herein.

[0017] Figure 5A This is a cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure.

[0018] Figure 5B This is a cross-sectional view of a semiconductor package structure according to another embodiment of the present disclosure.

[0019] Figure 6 This is a cross-sectional view of a semiconductor package structure according to another embodiment of the present disclosure.

[0020] Figures 7A to 7F Each describes the manufacturing process according to an embodiment of this disclosure as follows: Figure 1Cross-sectional views of one or more stages of a method for describing and illustrating a semiconductor packaging structure.

[0021] Figures 8A to 8H These are cross-sectional views of one or more stages of an exemplary method for forming a bonding joint between a first semiconductor device and a second semiconductor device in a semiconductor package structure.

[0022] Figure 9A This is a cross-sectional view illustrating a method for forming a bonding joint between a first semiconductor device and a second semiconductor device in a semiconductor package structure according to another embodiment of the present disclosure.

[0023] Figure 9B This is a cross-sectional view illustrating a method for forming a bonding joint between a first semiconductor device and a second semiconductor device in a semiconductor package structure according to yet another embodiment of the present disclosure.

[0024] Figure 9C This is a cross-sectional view illustrating a method for forming a bonding joint between a first semiconductor device and a second semiconductor device in a semiconductor package structure according to another embodiment of the present disclosure.

[0025] Figures 10A to 10E Each is a cross-sectional view illustrating one or more stages of a method for forming a bonding joint between a first semiconductor device and a second semiconductor device in a semiconductor package structure according to another embodiment of the present disclosure.

[0026] Figures 11A to 11E Each of these are cross-sectional views illustrating one or more stages of a method for manufacturing a semiconductor package structure according to yet another embodiment of this disclosure.

[0027] Figures 12A to 12C Each is a cross-sectional view illustrating one or more stages of a method for manufacturing a semiconductor package structure according to another embodiment of the present disclosure.

[0028] Figures 13A to 13D Each of these are cross-sectional views illustrating one or more stages of a method for manufacturing a semiconductor package structure according to yet another embodiment of this disclosure.

[0029] Figures 14A to 14J Each of these are cross-sectional views illustrating one or more stages of a method for manufacturing a semiconductor package structure according to embodiments of the present disclosure.

[0030] Figures 15A to 15H Each of these are cross-sectional views illustrating one or more stages of a method for manufacturing a semiconductor package structure according to embodiments of the present disclosure. Detailed Implementation

[0031] Common reference numerals are used throughout the drawings and detailed description to indicate the same or similar elements. Embodiments of this disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0032] Spatial descriptions, such as "above," "below," "upward," "left," "right," "downward," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc., are specified relative to a particular component or group of components or a plane thereof, for the orientation of components as shown in the associated diagrams. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantages of the embodiments of this disclosure are not affected by such arrangement.

[0033] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, embodiments in which a first feature is formed on or over a second feature may include instances where the first and second features are formed or disposed in direct contact, and embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0034] In the semiconductor package structure according to this disclosure, a second semiconductor device, such as a decoupling capacitor or inductor, is directly coupled to a first semiconductor device, such as a digital processor. This coupling configuration reduces or minimizes electrical losses and impedance through the semiconductor package structure. In contrast, in some existing methods, intermediate or interconnect layers, which may include solder and redistribution structures, exist between the digital processor and the decoupling capacitor. This can result in relatively high losses and impedance associated with the transmission paths through these layers. In some embodiments according to this disclosure, performance is enhanced by placing discrete components, such as decoupling capacitors and interconnect structures, closer to the digital processor, shortening the transmission path and reducing or minimizing the resistivity of the materials. Therefore, by coupling and closely arranging the components to be decoupled, power supply and grounding of the first and second semiconductor devices can be achieved in a relatively short path, resulting in less electrical loss.

[0035] Figure 1 This is a cross-sectional view of a semiconductor package structure 100 according to an embodiment of the present disclosure.

[0036] refer to Figure 1The semiconductor package structure 100 includes a first semiconductor device 11 and a second semiconductor device 12 encapsulated in an encapsulation layer 31. The first semiconductor device 11 has a first surface 11a (“active surface”) and a second surface 11b (“back surface”) opposite the first surface 11a, and includes a plurality of conductive pads 119, a plurality of conductive pillars 112 (“conductive elements”), and a plurality of conductive studs 115 at the first surface 11a. The conductive pillars 112 and conductive studs 115 for electrical connection are disposed on the conductive pads 119. The conductive pillars 112 (“conductive elements”) are located on the first surface 11a (“active surface”) of the first semiconductor device 11 and outside the second semiconductor device 12. Therefore, the first semiconductor device 11 is electrically connected to the redistribution structure 40 through the conductive pillars 112 (“conductive elements”). The second semiconductor device 12 includes conductive posts 125 bonded to conductive posts 115 of the first semiconductor device 11, thereby forming bonded joints 135 between the first semiconductor device 11 and the second semiconductor device 12. The semiconductor package structure 100 also includes a redistribution structure 40, which further includes a dielectric layer 42 and a conductive layer 45. Additionally, electrical contacts 81 are mounted on a surface 42a of the redistribution structure 40. As shown in FIG. 1, the electrical contacts 81 are located on the conductive layer 45 of the redistribution structure 40. The redistribution structure 40 and the electrical contacts 81 provide electrical connection between the first semiconductor device 11 and an external structure, which may include other semiconductor devices or components. For example, the semiconductor package structure 100 can be attached to a substrate, an interposer, or a printed circuit board (PCB) via the electrical contacts 81.

[0037] In one embodiment, the first semiconductor device 11 includes a digital processing device, while the second semiconductor device 12 includes a decoupling capacitor. Furthermore, the digital processing device may include one or more general-purpose processing devices, such as an application processor, microprocessor, central processing unit, or controller. Alternatively, the digital processing device may include one or more special-purpose processing devices, such as a digital signal processor (DSP), graphics processing unit, application-specific integrated circuit (ASIC), or field-programmable gate array (FGA). Additionally, the digital processing device may include a network processor, which further includes a core unit and multiple microengines. Furthermore, the digital processing device may include any combination of general-purpose and special-purpose processing devices.

[0038] Furthermore, decoupling capacitors are used to reduce noise. A decoupling capacitor is a capacitor used to decouple one part of an electrical network or circuit from another. Noise caused by other circuit elements is shunt through the capacitor, thereby reducing its impact on the remaining circuitry. In embodiments according to this disclosure, the Q value of the decoupling capacitor is related to the material used and its thickness (volume). As the thickness decreases with decreasing dimensions, impedance is reduced, for example, by reducing the path between the digital processor (first semiconductor device 11) and the decoupling capacitor (second semiconductor device 12) and the portion of the circuit to be decoupled via the decoupling capacitor.

[0039] Electrical contact 81 may include solder balls that can be arranged in a ball grid array (BGA). Alternatively, electrical contact 81 may include metal pads arranged in a land grid array (LGA). Additionally, electrical contact 81 may include leads arranged in a pin grid array (PGA). Furthermore, electrical contact 81 may include controlled collapse chip connection (C4) bumps, which include lead-based or lead-free bumps or balls.

[0040] When the semiconductor package structure 100 is attached to an external structure, such as a PCB, the first semiconductor device 11 is oriented "face-down" with its active surface 11a facing the PCB. In this configuration, a large portion of the encapsulation layer 31 surrounding the second semiconductor device 12 is disposed between the first semiconductor device 11 and the PCB, providing the required mechanical reliability. Furthermore, by combining the first semiconductor device 11 and the second semiconductor device 12, the transmission path is shortened, while the material resistivity caused by intermediate layers present in some existing methods is reduced or minimized. Additionally, reference will be made below. Figure 2A and 2B As discussed, the direct connection between the first semiconductor device 11 and the second semiconductor device 12 via the connector 135 helps to reduce parasitic effects and thus reduce electrical losses.

[0041] Figure 1A This is a cross-sectional view of a semiconductor package structure 100a according to an embodiment of the present disclosure.

[0042] refer to Figure 1A The semiconductor packaging structure 100a is similar to Figure 1 The semiconductor package structure 100 described and illustrated differs in that, for example, the second semiconductor device 12a further includes a plurality of conductive vias 126. The conductive vias 126 are disposed within the second semiconductor device 12a and electrically connect the conductive pillars 125 and the conductive layer 45. In some embodiments, the conductive vias 126 may be through silicon vias (TSVs).

[0043] Figure 2A It is displayed as Figure 1 A schematic diagram of the relatively short power supply paths for the first semiconductor device 11 and the second semiconductor device 12 in the semiconductor package structure 100 described herein.

[0044] refer to Figure 2AWhen the semiconductor package structure 100 is attached to an external structure, such as a PCB, a power supply path (shown in solid lines) is formed by supplying a voltage V, used as an operating voltage, from the PCB to the first semiconductor device 11 via one of the electrical contacts 81 (labeled "81P"), the wiring path in the RDL structure 40 (not shown), the first conductive pillar 112, the first coupling connector "135P" between the first semiconductor device 11 and the second semiconductor device 12, and subsequently the second coupling connector 135P. The first coupling connector 135P is formed by conductive pillar 125 and a corresponding conductive pillar 115, and is therefore shared by the first semiconductor device 11 and the second semiconductor device 12. The power supply path for supplying power to the first semiconductor device 11 and the second semiconductor device 12 in the semiconductor package structure 100 on the PCB is relatively short.

[0045] Figure 2B This is a schematic diagram showing a relatively long path for powering the first and second semiconductor devices in different semiconductor package structures 150. In the semiconductor package structure 100 according to this disclosure, the first semiconductor device 11 and the second semiconductor device 12 are disposed on the same side of the redistribution structure 40. Specifically, the second semiconductor device 12 is disposed between the first semiconductor device 11 and the redistribution structure 40. (See reference...) Figure 2B The semiconductor package structure 150 includes semiconductor devices and components similar to those in the semiconductor package structure 100. However, in the semiconductor package structure 150, the first semiconductor device 211 and the second semiconductor device 212 are disposed on different sides of the redistribution structure 240. Specifically, the redistribution structure 240 is disposed between the first semiconductor device 211 and the second semiconductor device 212.

[0046] Regarding the power supply path, a voltage V is supplied from the PCB toward the first semiconductor device 211 via the first electrical contact 81P, the first wiring path (not shown) on the RDL structure 240, the first conductor 125P, the second semiconductor device 212, and subsequently the second conductor 125P, the second wiring path (not shown) in the RDL structure 240, and the first conductive post 115P, thereby forming the power supply path. Compared to Figure 2A The power supply path described and illustrated herein is relatively long for supplying power to the first semiconductor device 211 in the semiconductor package structure 150 on the PCB.

[0047] refer to Figure 2BThe described and illustrated semiconductor package structure 150 can employ an advanced solution: using a wafer redistribution (RDL) line fabrication process to create the application processor substrate, which may have lower losses due to smaller via sizes, lower dielectric materials, and thinner layers. The challenge is that the bottom decoupling capacitor may still have solder balls, and I / O must still travel through the RDL layer to reach the application processor die positioned on top of the bottom decoupling capacitor. Significant losses occur along this path, degrading performance. Additionally, connectivity between the bottom / top additional packages may be limited due to spacing.

[0048] From a circuit perspective, decoupling capacitors are placed in front of the power input node of a load, such as that of a processor, to bypass noise and reduce current spikes or insufficiencies in the associated power supply rail. Placing decoupling capacitors further away from the associated power or ground pins can result in undesirable inductance and resistance, thus leading to power losses. Conversely, placing decoupling capacitors closer to the associated power or ground pins bypasses more inductance, thus resulting in lower power losses. In the semiconductor package structure 100 according to this disclosure, the second semiconductor device 12 (acting as a decoupling capacitor) is directly coupled to the first semiconductor device 11 (processor) without the need for wiring to interconnect via additional intermediate semiconductor structures or components required in some existing methods (including semiconductor package structure 150). Those skilled in the art will readily understand that... Figure 2A Compared to the relatively short path in the semiconductor package structure 100 described herein, Figure 2B The relatively long paths in the semiconductor package structure 150 described herein can induce more parasitic effects. Therefore, electrical losses can be significantly reduced in the semiconductor package structure 100.

[0049] Figure 3A This is a cross-sectional view of a semiconductor package structure 200 according to another embodiment of the present disclosure.

[0050] refer to Figure 3AThe semiconductor package structure 200 includes a first semiconductor device 11, a second semiconductor device 12, and a substrate 50 (“intermediate”) all sealed within an encapsulation layer 31. The encapsulation layer 31 has a first surface 31a and a second surface 31b opposite to the first surface 31a. The substrate 50 substantially surrounds the first semiconductor device 11 and the second semiconductor device 12 and supports signal transmission within the semiconductor package structure 200. In an embodiment, the substrate 50 comprises a coreless substrate 51. Alternatively, the substrate 50 may comprise a wafer-based redistribution structure instead of a coreless substrate to accommodate different design rules, and a direct redistribution layer (RDL) plating technique for copper vias may be used. In the case of a coreless substrate as in this embodiment, the coreless substrate 51 includes a wiring layer and microvias electrically connected to the wiring layer. Furthermore, the first conductive pad 55 (upper pad) and the second conductive pad 58 (lower pad) of the coreless substrate 51 serve as input / output (I / O) pads for electrically connecting the wiring layer to other semiconductor devices, components, or structures. Figure 1 As shown, the first conductive pad 55 is adjacent to the first surface 31a of the encapsulation layer 31 and electrically connected to the redistribution structure 40. Communication throughout the wiring layer is achieved via microvias rather than via plated through holes. Signal transmission can pass directly through the coreless substrate 51 in a substantially vertical direction. Furthermore, the coreless substrate 51 can facilitate additional wiring for signal transmission through different wiring layers in a substantially lateral direction. Additionally, passive devices can be embedded in the wiring layers of the coreless substrate 51, allowing the coreless substrate 51 to be used efficiently in the desired area.

[0051] In some embodiments, the coreless substrate 51 takes the form of a continuous ring or a continuous rectangle. Figure 4A This is a schematic top view of an exemplary coreless substrate 51 having a continuous rectangular shape. The continuous rectangle can be formed by fabricating the entire rectangular coreless substrate in a separate manufacturing process and then removing its central portion using, for example, a laser cutting process to accommodate the first semiconductor device 11.

[0052] In other embodiments, the coreless substrate 51 includes separate portions that collectively form a ring or rectangular profile. Figure 4B This is a schematic top view of an exemplary coreless substrate 51 including discrete portions 501, 502, and 503. These portions 501, 502, and 503 can be formed in separate manufacturing processes and then individually attached to the carrier 21. Figures 7C to 7E )superior.

[0053] Return to reference Figure 3A The semiconductor package structure 200 further includes a first redistribution structure 40 (“redistribution structure”) disposed on a first surface 31a of the encapsulation layer 31, and a second redistribution structure 60 (“first additional redistribution structure”) disposed on a second surface 31b of the encapsulation layer 31. The first redistribution structure 40 may include several dielectric layers and conductive layers. For convenience, only dielectric layer 42 and conductive layer 45 are shown. Similarly, the second redistribution structure 60 includes dielectric layer 62 and conductive layer 65, although it may include several dielectric layers and conductive layers.

[0054] The semiconductor package structure 200 further includes one or more third semiconductor devices 70 attached to the first redistribution structure 40. Each of the third semiconductor devices 70 includes conductive vias 75 and I / O pads 78 for signal transmission. In this embodiment, the third semiconductor devices 70 are arranged in a stack. In this embodiment, the third semiconductor devices 70 include memory, such as a wide I / O memory, for example, high bandwidth memory (HBM). The wide I / O memory may contain more than six hundred (600) I / Os, for example, 2,000 to 5,000 I / Os. Communication between the first semiconductor device 11 and the third semiconductor 70 is achieved via an electrical path routed from the first semiconductor device 11 to the third semiconductor device 70 via conductive pillars 112, conductive layers 45 in the first redistribution structure 40, and I / O pads 78, and vice versa.

[0055] The semiconductor package structure 200 also includes electrical contacts 82 mounted on the second redistribution structure 60 for electrical connection to, for example, external devices, components or structures of a substrate, interposers, PCBs, etc. Communication between the first semiconductor device 11 and the external device is achieved via an electrical path routed from the first semiconductor device 11 toward the PCB via conductive pillars 112, conductive layers 45 in the first redistribution structure 40, upper pads 55 of a coreless substrate 51 electrically connected to the conductive layers 45, wiring layers in the coreless substrate 51, conductive layers 65 in the second redistribution structure 60, electrical contacts 82, and electrical connections to the conductive layers 65, and vice versa.

[0056] In the semiconductor package structure 200, the second semiconductor device 12 is directly coupled to the first semiconductor device 11. Similar to... Figure 1The semiconductor package structure 100 described and illustrated shortens the transmission path and minimizes material resistivity due to intermediate layers present in some existing methods by combining a first semiconductor device 11 and a second semiconductor device 12. Furthermore, by placing the components including the first redistribution structure 40 and the third semiconductor device 70 closer to the first semiconductor device 11, these components (including the first redistribution structure 40 and the third semiconductor device 70) are served (and decoupled from) by the second semiconductor device 12 (decoupling capacitor), similarly shortening the transmission path and reducing impedance. Additionally, power is supplied to both the first semiconductor device 11 and the second semiconductor device 12 in a relatively short path. Therefore, the semiconductor package structure 200 also benefits from the combined configuration and ensures lower power loss.

[0057] Furthermore, in the semiconductor package structure 200, the first semiconductor device 11 is "face-up" positioned with its first surface 11a (active surface) facing the third semiconductor device 70. This configuration facilitates routing between the first semiconductor device 11 and the third semiconductor device 70, which is positioned above the first semiconductor device 11, by means of the conductive pillars 112. The face-up first semiconductor device 11 communicates directly with the second semiconductor device 12 via a coupling connector 135 and with the third semiconductor device 70 via a first redistribution structure 40.

[0058] Figure 3B This is a cross-sectional view of a semiconductor package structure 300 according to yet another embodiment of the present disclosure.

[0059] refer to Figure 3B The semiconductor packaging structure 300 is similar to the reference. Figure 3A The semiconductor package structure 200 described and illustrated differs in that, for example, the first semiconductor device 11 is placed "face-down" with its first surface 11a (active surface) facing the electrical contact 82. When the semiconductor package structure 300 is attached to an external structure, such as a PCB, via the electrical contact 82, a significant portion of the encapsulation layer 31 surrounding the second semiconductor device 12 is disposed between the first semiconductor device 11 and the PCB, providing the necessary mechanical reliability. Furthermore, the direct connection between the first semiconductor device 11 and the second semiconductor device 12 via the connector 135 helps reduce parasitic effects and thus electrical losses.

[0060] Figure 3C This is a cross-sectional view of a semiconductor package structure 200a according to yet another embodiment of the present disclosure.

[0061] refer to Figure 3C The semiconductor package structure 200a is similar to the reference. Figure 3AThe semiconductor package structure 200 described and illustrated differs in that, for example, the coreless substrate 51 is replaced by a pre-molded carrier 51a. The pre-molded carrier 51a includes a body 52a, a plurality of vias 53a, and at least one routing layer 54a. The body 52a may be made of a molding compound. The vias 53a extend through the body 52a. The bottom portion of the vias 53a may be electrically connected to a second conductive pad 58. The routing layer 54a may be disposed on the body 52a and may electrically connect the vias 53a and the first conductive pad 55. Since the encapsulation layer 31 and the body 52a of the pre-molded carrier 51a may both be made of molding compounds, their coefficients of thermal expansion (CTE) may be the same or very close, thus reducing the warpage of the encapsulation layer 31 when the pre-molded carrier 51a is sealed within the encapsulation layer 31. In addition, the electrical characteristics of Dk / Df were improved.

[0062] Figure 3D This is a cross-sectional view of a semiconductor package structure 300a according to yet another embodiment of the present disclosure.

[0063] refer to Figure 3D The semiconductor packaging structure 300a is similar to Figure 3B The semiconductor package structure 300 described and illustrated differs in that, for example, the coreless substrate 51 is replaced by a pre-molded carrier 51a. The pre-molded carrier 51a includes a body 52a, a plurality of vias 53a, and at least one routing layer 54a. The body 52a may be made of a molding compound. The vias 53a extend through the body 52a. The bottom portion of the vias 53a may be electrically connected to a second conductive pad 58. The routing layer 54a may be disposed on the body 52a and may electrically connect the vias 53a and a first conductive pad 55. Since the encapsulation layer 31 and the body 52a of the pre-molded carrier 51a may both be made of molding compounds, their coefficients of thermal expansion (CTE) may be the same or very close, thus reducing the warpage of the encapsulation layer 31 when the pre-molded carrier 51a is sealed within the encapsulation layer 31. Additionally, the Dk / Df electrical characteristics are improved.

[0064] Figure 5A This is a cross-sectional view of a semiconductor package structure 400 according to an embodiment of the present disclosure.

[0065] refer to Figure 5AThe semiconductor package structure 400 includes a first semiconductor device 11, a second semiconductor device 12 bonded to the first semiconductor device 11, a coreless substrate 51, a first redistribution structure 40 (“second additional redistribution structure”), a second redistribution structure 60 (“first additional redistribution structure”), and a third redistribution structure 90. The first semiconductor device 11 and the coreless substrate 51 are sealed in a first encapsulating layer 31 (“additional encapsulating layer”). Furthermore, the first semiconductor device 11, the first encapsulating layer 31 (“additional encapsulating layer”), conductive pillars (including first conductive pillar 812) and the second semiconductor device 12 are sealed in a second encapsulating layer 32 (“encapsulating layer”). The first semiconductor device 11 includes conductive pads 119 at a first surface 11a. The first redistribution structure 40 includes a conductive layer 45, which further includes a first portion 451 disposed on a conductive pad 119 of the first semiconductor device 11, and a second portion 452 disposed on a second conductive pad 58 of the coreless substrate 51. The first conductive pad 55 and the second conductive pad 58 are substantially flush with the first surface 11a and the second surface 11b of the first semiconductor device 11, respectively.

[0066] In this embodiment, the first semiconductor device 11 may include densely spaced I / Os with relatively close spacing. For example, the conductive pads 119 of the first semiconductor device 11 are arranged with a smaller pitch than the conductive pillars 125 of the second semiconductor device 12, or with a smaller pitch than the conductive layer 95 in the third redistribution structure 90. A first portion 451 of the conductive layer 45 is disposed on the conductive pads 119 of the first semiconductor device 11 to facilitate fan-out of the I / Os on the conductive pads 119. Furthermore, a first conductive pillar 812 is disposed on the first portion 451 to facilitate fan-out. Additionally, the semiconductor package structure 400 includes a second conductive pillar 822 disposed on a second portion 452 to provide electrical connection between the first redistribution structure 40 and the third redistribution structure 90. The second conductive pillar 822 facilitates signal fan-out, which is desirable for the relatively closely spaced first semiconductor device 11.

[0067] The semiconductor package structure 400 further includes one or more third semiconductor devices 70 attached to the third redistribution structure 90. Communication between the first semiconductor device 11 and the third semiconductor device 70 is achieved via an electrical path routed from the first semiconductor device 11 to the third semiconductor device 70 via a first portion 451 of the conductive layer 45 in the first redistribution structure 40, a first conductive pillar 812 on the first portion 451, the conductive layer 95 in the third redistribution structure 90, and I / O pads 78, and vice versa.

[0068] A second redistribution structure 60 disposed on a second surface 11b of a first semiconductor device 11 includes a dielectric layer 62 and a conductive layer 65. Electrical contacts 82, such as solder balls, are disposed on the second redistribution structure 60 to electrically connect the first semiconductor device 11 to an external device, such as a PCB. Communication between the first semiconductor device 11 and the PCB is achieved via an electrical path routed from the first semiconductor device 11 toward the PCB via a first portion 451 of the conductive layer 45 in the first redistribution structure 40, a first conductive pillar 812 on the first portion 451, a conductive layer 95 in the third redistribution structure 90, a second conductive pillar 822 on a coreless substrate 51, a second portion 452 of the conductive layer 45 on the coreless substrate 51, a wiring layer in the coreless substrate 51, a first pad 55 on the coreless substrate 51, a conductive layer 65 in the second redistribution structure 60, and electrical contacts 82, and vice versa.

[0069] In the semiconductor package structure 400, the second semiconductor device 12 is directly coupled to the first semiconductor device 11. Similar to... Figure 1 The semiconductor package structure 100 described and illustrated shortens the transmission path and minimizes material resistivity due to intermediate layers present in some existing methods by combining the first semiconductor device 11 and the second semiconductor device 12. Furthermore, by placing the components including the first redistribution structure 40, the third semiconductor device 70, and the third redistribution structure 90 closer to the first semiconductor device 11, these components (including the first redistribution structure 40, the third semiconductor device 70, and the third redistribution structure 90) will be served (decoupled by) the second semiconductor device 12 (decoupling capacitor), similarly shortening the transmission path and reducing impedance. Additionally, power is supplied to the first semiconductor device 11 and the second semiconductor device 12 in a relatively short path. Therefore, the semiconductor package structure 400 also benefits from a direct-coupled configuration and ensures lower power loss.

[0070] Furthermore, in the semiconductor package structure 400, the first semiconductor device 11 is positioned "upward" facing the third semiconductor device 70 via its first surface 11a (active surface). This configuration facilitates routing between the first semiconductor device 11 and the third semiconductor device 70, which is positioned above the first semiconductor device 11, by means of the first conductive pillar 812 and the second conductive pillar 822. The upward-facing first semiconductor device 11 communicates directly with the second semiconductor device 12 via a coupling connector 135, and with the third semiconductor device 70 via the first redistribution structure 40 and the third redistribution structure 90.

[0071] Figure 5B This is a cross-sectional view of a semiconductor package structure 500 according to an embodiment of the present disclosure.

[0072] refer to Figure 5B The semiconductor packaging structure 500 is similar to Figure 5A The semiconductor package structure 400 described and illustrated differs in that, for example, the first semiconductor device 11 is positioned "downward" with its first surface 11a (active surface) facing the electrical contact 82. When the semiconductor package structure 500 is attached to an external structure, such as a PCB, via the electrical contact 82, a significant portion of the second encapsulation layer 32 surrounding the second semiconductor device 12 is disposed between the first semiconductor device 11 and the PCB, providing the necessary mechanical reliability. Furthermore, the direct connection between the first semiconductor device 11 and the second semiconductor device 12 via the connector 135 helps reduce parasitic effects and thus electrical losses.

[0073] Figure 6 This is a cross-sectional view of a semiconductor package structure 600 according to another embodiment of the present disclosure.

[0074] refer to Figure 6 The semiconductor package structure 600 includes a first semiconductor device 11, a second semiconductor device 12, a first redistribution structure 40, and a second redistribution structure 60. The first semiconductor device 11 is sealed within a first encapsulation layer 31. The second semiconductor device 12 and the first encapsulation layer 31 are sealed within a second encapsulation layer 32. The first semiconductor device 11 includes conductive pads 119 at a first surface 11a. The first redistribution structure 40, disposed on the first surface 11a of the first semiconductor device 11 and the first surface 31a of the first encapsulation layer 31, includes a conductive layer 45. A first portion 451 of the conductive layer 45 is disposed on the conductive pads 119 at the first surface 11a of the first semiconductor device 11. A second portion 452 of the conductive layer 45 is disposed on the first surface 31a of the first encapsulation layer 31 and is separate from the first portion 451. The second semiconductor device 12 is bonded to the first semiconductor device 11, thereby forming a bonding joint 135 therebetween.

[0075] Similar to a reference Figure 5A In the described and illustrated embodiment, the first semiconductor device 11 may include I / Os densely spaced at relatively close intervals. Specifically, the conductive pads 119 of the first semiconductor device 11 are arranged with a smaller pitch than the conductive pads of the second semiconductor device 12. A first portion 451 of the conductive layer 45 is disposed on the conductive pads 119 of the first semiconductor device 11 to facilitate fan-out of the I / Os on the conductive pads 119. Furthermore, the semiconductor package structure 600 includes a first conductive pillar 812 disposed on the first portion 451 and extending between the first redistribution structure 40 and the second redistribution structure 60, thereby providing electrical connection to the first semiconductor device 11. The semiconductor package structure 600 also includes a second conductive pillar 822 disposed on the second portion 452 and extending between the first redistribution structure 40 and the second redistribution structure 60 to facilitate fan-out.

[0076] In the semiconductor package structure 600, the second semiconductor device 12 is directly coupled to the first semiconductor device 11. Similar to... Figure 1 The described and illustrated semiconductor package structure 100 shortens the transmission path by combining a first semiconductor device 11 and a second semiconductor device 12, while minimizing material resistivity caused by intermediate layers present in some existing methods. Furthermore, power is supplied to both the first semiconductor device 11 and the second semiconductor device 12 in a relatively short path. Therefore, the semiconductor package structure 600 benefits from a direct-bonding configuration and ensures low electrical losses. Additionally, a significant portion of the second encapsulation layer 32 surrounding the second semiconductor device 12 is disposed between the first semiconductor device 11 and an external device, such as a PCB, providing the required mechanical reliability.

[0077] Figures 7A to 7F Each describes the manufacturing process according to an embodiment of this disclosure as follows: Figure 1 A cross-sectional view of one or more stages of a method for describing and illustrating a semiconductor package structure 100.

[0078] refer to Figure 7AA first semiconductor device 11 is formed on a wafer, the first semiconductor device 11 having a first surface 11a and a second surface 11b opposite to the first surface 11a. Conductive pillars 112 and conductive posts 115 for electrical connection to other devices, components, or structures are formed on conductive pads 119 at the first surface 11a (“active surface”). Thus, conductive components 112 are formed on the active surface 11a of the first semiconductor device 11. As previously described, the first semiconductor device 11 includes digital processing devices. Suitable materials for the conductive pillars 112 and conductive posts 115 may include copper (Cu), gold (Au), aluminum (Al), palladium (Pd), or solder, or alloys thereof.

[0079] refer to Figure 7B A second semiconductor device 12 is provided. The second semiconductor device 12, fabricated in another manufacturing process, includes conductive pillars 125 formed on its first surface 121. The second semiconductor device 12 is positioned downwards toward the first surface 11a of the first semiconductor device 11, so that the conductive pillars 125 correspond in position to the conductive pillars 115. Subsequently, the second semiconductor device 12 is bonded to the first semiconductor device 11 (as indicated by the arrow). As previously described, the second semiconductor device 12 includes a decoupling capacitor. Suitable materials for the conductive pillars 125 may include copper (Cu), gold (Au), aluminum (Al), palladium (Pd), or solder, or alloys thereof.

[0080] In some embodiments, conductive posts 115 and 125 are in direct contact with each other. For example, such as Figures 8A to 8H The details illustrate how conductive posts 115 and 125 are bonded together in a copper-to-copper (Cu to Cu) direct bonding process. Alternatively, as... Figures 10A to 10E In detail, conductive posts 115 and 125 can be joined together in a solder-joint bonding process.

[0081] Subsequently, in the wafer dicing process, the first semiconductor device 11, which is combined with the second semiconductor device 12, is separated from the other semiconductor devices. Now refer to Figure 7CA carrier 21 with a release film 210 is provided. A first semiconductor device 11 (currently in the form of a semiconductor die, or in the form of a chip after chip dicing) is attached to the release film 210 at its second surface 11b. The carrier 21 is used to support semiconductor components, devices, or structures subsequently formed or disposed thereon. In embodiments, the carrier 21 comprises an organic material, such as bismalleimide triazine (BT), polyimide (PI), Ajinomoto build-up film (ABF), or other suitable materials. Alternatively, the carrier 21 comprises an inorganic material, such as silicon, glass, or other suitable materials. The release film 210 is used to induce release of the carrier 21 from the semiconductor structure temporarily held by the carrier 21. In embodiments, the release film 210 comprises a non-metallic material, such as PI, ABF, epoxy resin, molding compound, solder resist ink, or other suitable materials. Additionally, the release film 210 is optional and therefore negligible.

[0082] refer to Figure 7D An encapsulation layer 310 is formed on the carrier 21, thereby covering the first semiconductor device 11 and the second semiconductor device 12. The encapsulation layer 310 may contain a molding compound.

[0083] refer to Figure 7E The height of the encapsulating layer 310 is then reduced using processes such as grinding or mechanical polishing, resulting in a reduced encapsulating layer 31. The reduced encapsulating layer 31 exposes the conductive pillars 112. The carrier 21 and release film 210 are then removed. In some embodiments, the carrier 21 comprises a glass carrier, which can be removed in a laser lift-off process.

[0084] Next, refer to Figure 7FA redistribution structure 40 is formed on a reduced encapsulation layer 31. The redistribution structure 40 provides interconnection and may include a dielectric layer 42 and a conductive layer 45. The redistribution structure 40 is electrically connected to the first semiconductor device 11 via the conductive component (conductive pillar 112). In one embodiment, the dielectric layer 42 comprises an organic material, such as a molding compound, polyamide (PA), polyimide (PI), polybenzoxazole (PBO), or an epoxy-based material. In another embodiment, the dielectric layer 42 comprises an inorganic material, such as silicon oxide (SiOx), silicon nitride (SiNx), or tantalum oxide (TaOx). Additionally, the conductive layer 45 comprises titanium (Ti), titanium-tungsten alloy (TiW), nickel (Ni), copper (Cu), titanium-copper alloy (TiCu), silver (Ag), gold (Au), or other suitable conductive materials.

[0085] Then return to the reference. Figure 1 Electrical contacts 81 are mounted on surface 42a of the redistribution structure 40 above the reduced encapsulation layer 31. Electrical contacts 81 provide electrical connection between the first semiconductor device 11 and an external structure (not shown). In one embodiment, electrical contacts 81 may include solder balls that can be arranged in a ball grid array (BGA). In another embodiment, electrical contacts 81 may include metal pads arranged in a grid array (LGA). In yet another embodiment, electrical contacts 81 may include pins arranged in a pin grid array (PGA). Furthermore, electrical contacts 81 may include controlled collapse chip connection (C4) bumps, which include lead-based or lead-free bumps or balls.

[0086] Figures 8A to 8H Each explains as follows Figure 1 Cross-sectional views of one or more stages of an exemplary method for forming a bonding connector 135 between a first semiconductor device 11 and a second semiconductor device 12 in a semiconductor package structure 100, as described and illustrated. As will be discussed below, the exemplary method includes forming conductive pillars on the input / output (I / O) pads of the first semiconductor device 11 in a copper-to-copper (Cu-to-Cu) direct bonding process, and forming conductive pillars separately on the I / O pads of the second semiconductor device 12 in a hybrid bonding process.

[0087] refer to Figure 8AFor the first semiconductor device 11, an initial dielectric layer 161 is formed on a first surface 11a of a substrate 160 of the first semiconductor device 11 by, for example, chemical vapor deposition (CVD). The first semiconductor device 11 includes I / O pads 119 at the surface 11a of the substrate 160. The dielectric layer 161 may contain an oxide, such as silicon oxide (SiOx). Next, a patterned photoresist layer 162 is formed on the dielectric layer 161, thereby exposing portions of the dielectric layer 161 through openings 168. These exposed portions are located corresponding to the I / O pads 119 of the first semiconductor device 11.

[0088] refer to Figure 8B The exposed portion of dielectric layer 161 is removed by, for example, an etching process, thereby creating a patterned dielectric layer 171. The patterned dielectric layer 171 exposes I / O pads 119 through openings 168. The patterned photoresist layer 162 is then removed.

[0089] refer to Figure 8C The first conductive layer 163 is formed, for example, in a sputtering process on the patterned dielectric layer 171 and the exposed I / O pads 119. The first conductive layer 163 is substantially conformal to the topology of the patterned dielectric layer 171 and serves as a seed layer for subsequent conductive layers formed thereon. In an embodiment, the first conductive layer 163 comprises a titanium (Ti) layer and a copper layer stacked on the titanium layer.

[0090] Next, refer to Figure 8D A second conductive layer 164, a third conductive layer 165, and a fourth conductive layer 166 are sequentially formed on a first conductive layer 163 using a process such as electroplating. Specifically, the second conductive layer 164 is conformally formed on the first conductive layer 163, the third layer 165 is conformally formed on the second conductive layer 164, and the fourth conductive layer 166 fills the opening 168 and is also formed on the third conductive layer 165. In an embodiment, the second conductive layer 164 comprises copper, the third conductive layer 165 comprises nickel (Ni), and the fourth conductive layer 166 comprises solder, such as an alloy of tin and silver (SnAg). Therefore, the second conductive layer 164, i.e., the copper layer, ensures the required conductivity. Additionally, the fourth conductive layer 166, i.e., the SnAg layer, provides the required solubility to facilitate bonding. Furthermore, the third conductive layer 165, i.e., the nickel layer, prevents electrochemical corrosion between the copper layer 164 and the SnAg layer 166, ensuring the required conductivity and a strong bond.

[0091] Now for reference Figure 8EThe first conductive layer 163, the second conductive layer 164, the third conductive layer 165, and the fourth conductive layer 166 are patterned using a polishing process such as chemical mechanical polishing (CMP) to form a composite material. Figure 1 The conductive pillar 115 is illustrated with a patterned first conductive layer 173, a second conductive layer 174, a third conductive layer 175, and a fourth conductive layer 176. The patterned dielectric layer 171 is exposed and planarized after a polishing process, which facilitates the bonding between the conductive pillar 115 and the corresponding conductive pillar 125.

[0092] Regarding the second semiconductor device 12, see reference... Figure 8F Together they constitute such Figure 1 The patterned first conductive layer 273, second conductive layer 274, third conductive layer 275 and fourth conductive layer 276 of the conductive pillar 125 described herein are as shown in the reference. Figures 8A to 8E A similar manner as described and illustrated is formed on the I / O pads 129 at the first surface 121 of the substrate 260 of the second semiconductor device 12. Thus, the patterned dielectric layer 271 on the substrate 260 is exposed and planarized.

[0093] refer to Figure 8G The second semiconductor device 12 is bonded to the first semiconductor device 11. Specifically, the conductive post 125 of the second semiconductor device 12 is bonded to its corresponding conductive post 115 of the first semiconductor device 11 in a "hybrid bonding" process. "Hybrid bonding" combines a dielectric bond with an embedded metal to form an interconnect. Initially, as... Figure 8H As explained, when in contact with each other, the dielectric bond between dielectric layers 271 and 171 is formed at room temperature by van der Waals forces, thereby creating a bonded dielectric layer 371. Next, a thermal process is performed to force the patterned second conductive layers 274 and 174 to form a bonding junction 135. Figures 8A to 8H The exemplary bonding process described and illustrated can be performed at the wafer-level stage. Subsequently, the first semiconductor device 11 is monomerized in a wafer dicing process, wherein the second semiconductor device 12 is bonded thereon.

[0094] Figure 9A This describes another embodiment of the present disclosure as follows: Figure 1 A cross-sectional view illustrating a method for forming a bonding joint between a first semiconductor device 11 and a second semiconductor device 12 in a semiconductor package structure 100. The method is similar to that described in reference [reference needed]. Figures 8A to 8H The method of description and explanation differs, for example, in the conductive post 525 of the second semiconductor device 12. Specifically, the conductive post 515 of the first semiconductor device 11 and... Figure 8GThe conductive pillars 115 are the same or similar. The conductive pillars 525 of the second semiconductor device 12 may consist only of a patterned first conductive layer 273 and a patterned second conductive layer 574. To form a bonding interface, similarly, a dielectric bond between dielectric layers 271 and 171 is formed at room temperature, and a subsequent metal bond is formed by the patterned second conductive layers 174 and 574 using a thermal process.

[0095] Figure 9B This describes yet another embodiment of the present disclosure. Figure 1 A cross-sectional view illustrating a method for forming a bonding joint between a first semiconductor device 11 and a second semiconductor device 12 in a semiconductor package structure 100. The method is similar to that described in reference [reference needed]. Figures 8A to 8H The method of description and explanation differs, for example, in the conductive post 515 of the first semiconductor device 11. Specifically, the conductive post 525 of the second semiconductor device 12 and... Figure 8G The conductive pillars 125 are the same or similar. The conductive pillars 515 of the first semiconductor device 11 may consist only of a patterned first conductive layer 173 and a patterned second conductive layer 674. To form a bonding interface, similarly, a dielectric bond between dielectric layers 271 and 171 is formed at room temperature, and a subsequent metal bond is formed by patterned second conductive layers 674 and 274 using a thermal process.

[0096] Figure 9C This describes yet another embodiment of the present disclosure. Figure 1 A cross-sectional view illustrating a method for forming a bonding joint between a first semiconductor device 11 and a second semiconductor device 12 in a semiconductor package structure 100. (See reference...) Figure 9C The conductive pillar 515 of the first semiconductor device 11 may consist only of a patterned first conductive layer 173 and a patterned second conductive layer 674. Similarly, the conductive pillar 525 of the second semiconductor device 12 may consist only of a patterned first conductive layer 273 and a patterned second conductive layer 574. To form a bonding interface, similarly, a dielectric bond between dielectric layers 271 and 171 is formed at room temperature, and a subsequent metal bond is formed by the patterned second conductive layers 574 and 674 using a thermal process.

[0097] Figures 10A to 10E Each explains as follows Figure 1 A cross-sectional view of one or more stages of another method for forming a bonding joint 135 between a first semiconductor device 11 and a second semiconductor device 12 in a semiconductor package structure 100, as described and illustrated.

[0098] refer to Figure 10AA patterned dielectric layer 181 is formed on a first surface 11a of the first semiconductor device 11 using, for example, a photolithographic process, thereby exposing I / O pads 119 from openings 188. The patterned dielectric layer 181 may comprise polyimide.

[0099] refer to Figure 10B A patterned conductive layer 115 is formed on the patterned dielectric layer 181 and conductive pads 119 using an electroplating process followed by an etching process. The patterned conductive layer 115 includes conductive pillars for bonding with the conductive pillars of the second semiconductor device 12. Subsequently, refer to Figure 10C The conductive pillar 112 is formed on the I / O pad 119 in a manner similar to that used to form the conductive pillar 115.

[0100] refer to Figure 10D A second semiconductor device 12 is provided. The second semiconductor device 12 includes a patterned conductive layer 125 formed on a patterned dielectric layer 281 and I / O pads 129. The patterned conductive layer 125 includes conductive pillars for bonding with conductive pillars 115 of the first semiconductor device 11. Then, by means of, for example, solder 681, the conductive pillars 125 of the second semiconductor device 12 are bonded to the conductive pillars 115 of the first semiconductor device 11, thereby creating a... Figure 10E The described joint 135.

[0101] Figures 11A to 11E Each describes yet another embodiment according to this disclosure. Figure 3A Cross-sectional views of one or more stages of a method for manufacturing a semiconductor package structure 200, which are described and illustrated.

[0102] refer to Figure 11A Similar to the operation described and illustrated with reference to 7C, a carrier 21 having a release film 210 is provided. Subsequently, a first semiconductor device 11, coupled to a second semiconductor device 12, is attached to the release film 210 at its second surface 11b. Furthermore, a substrate 50 is attached to the release film 210. The substrate 50 may comprise a coreless substrate 51.

[0103] refer to Figure 11B An encapsulation layer 310 is formed on the carrier 21, thereby covering the first semiconductor device 11, the second semiconductor device 12, and the coreless substrate 51. Then, referring to... Figure 11C The height of the encapsulation layer 310 is reduced by a polishing process, such as mechanical polishing, thereby creating a reduced encapsulation layer 31. The reduced encapsulation layer 31 exposes the conductive pillars 112 of the first semiconductor device 11 and the upper pads 55 of the coreless substrate 51 from its first surface 31a.

[0104] refer to Figure 11DThe carrier 21 and release film 210 are then removed, thereby exposing the second surface 11b of the first semiconductor device 11 and the lower pad 58 of the coreless substrate 51 from the second surface 31b of the reduced encapsulation layer 31. The second surface 31b is opposite to the first surface 31a of the reduced encapsulation layer 31. Subsequently, a first redistribution structure 40 is formed on the first surface 31a of the reduced encapsulation layer 31. The first redistribution structure 40 is used to provide electrical connections and may include a plurality of dielectric and conductive layers. For convenience, only the dielectric layer 42 and the conductive layer 45 are shown.

[0105] refer to Figure 11E The second redistribution structure 60 is formed on the second surface 31b of the reduced encapsulation layer 31 and the second surface 11b of the first semiconductor device 11. Similarly, the second redistribution structure 60 is used to provide electrical connections and may include several dielectric and conductive layers. For simplicity, only the dielectric layer 62 and the conductive layer 65 are shown. Figure 7F As described, the suitable materials used for the second dielectric layer 62 and the second conductive layer 65 are similar to or the same as the materials used for the dielectric layer 42 and the conductive layer 45, respectively, and therefore will not be discussed further.

[0106] Next, return to the reference. Figure 3A The third semiconductor device 70 is stacked and attached to the first redistribution structure 40. The third semiconductor device 70 includes a high-bandwidth memory (HBM). Additionally, electrical contacts 82 are mounted on the second redistribution structure 60. (See reference...) Figure 1 The suitable materials and deployment for electrical contact 82 are similar to those for electrical contact 81, and therefore will not be discussed further.

[0107] Figure 3B The semiconductor package structure 300 can be used with a reference Figures 11A to 11E The methods described and explained are similar to those used in manufacturing, the difference being, for example, in... Figure 11E In operation, the stack of the third semiconductor device 70 is attached to the second redistribution structure 60, and the electrical contact 82 is mounted on the first redistribution structure 40.

[0108] Figures 12A to 12C Each describes another embodiment according to this disclosure as follows: Figure 3A Cross-sectional views of one or more stages of a method for manufacturing a semiconductor package structure 200, which are described and illustrated.

[0109] refer to Figure 12A The first semiconductor device 11 is similar to the reference. Figure 3A The first semiconductor device 11 described and illustrated differs, for example, in that the conductive pillar 512 is higher than the conductive pillar 112. Therefore, by configuring the conductive pillar 512 as a grinding stop, in such a way... Figure 11CAfter the polishing process performed to reduce the size of the encapsulation layer 310, the conductive pillar 512 is exposed from the reduced encapsulation layer 31, while the coreless substrate 51 is still covered by the reduced encapsulation layer 31.

[0110] Next, refer to Figure 12B The reduced encapsulation layer 31 is patterned, for example, by a laser drilling process, thereby exposing the upper pads 55 of the coreless substrate 51 through openings 57.

[0111] Subsequently, reference Figure 12C The first redistribution structure 40 is formed on the first surface 31a of the patterned, reduced encapsulation layer 31. During the formation of the first redistribution structure 40, the conductive layer 45 fills the opening 57 and the upper electrical connection pads 55 and conductive pillars 512. Further operations are described in the references. Figure 11E and 3A The operations described and referenced are similar or identical, and therefore will not be discussed further.

[0112] Figures 13A to 13D Each describes yet another embodiment according to this disclosure. Figure 3A Cross-sectional views of one or more stages of a method for manufacturing a semiconductor package structure 200, which are described and illustrated.

[0113] refer to Figure 13A The structure is similar to the reference. Figure 11A The structure described and illustrated differs in that, for example, additional pillars 522 are formed on the upper pads 55 of the coreless substrate 51. The additional pillars 522 of the coreless substrate 51 are substantially flush with the conductive pillars 112 of the first semiconductor device 11.

[0114] refer to Figure 13B An encapsulation layer 310 is formed on the carrier 21, thereby covering the conductive pillar 112 of the first semiconductor device 11, the second semiconductor device 12, and the additional pillar 522 of the coreless substrate 51. Then, referring to... Figure 13C The height of the encapsulation layer 310 is reduced by a polishing process, such as mechanical polishing, thereby creating a reduced encapsulation layer 31. The reduced encapsulation layer 31 exposes the conductive pillars 112 of the first semiconductor device 11 and the additional pillars 522 of the coreless substrate 51 from its first surface 31a.

[0115] Subsequently, reference Figure 13D A first redistribution structure 40 is formed on the first surface 31a of the reduced encapsulation layer 31. During the formation of the first redistribution structure 40, a conductive layer 45 electrically connects the additional pillars 522 of the coreless substrate 51 and the conductive pillars 112 of the first semiconductor device 11. Further operations are referenced. Figure 11E and 3AThe operations described and referenced are similar or identical, and therefore will not be discussed further.

[0116] Figures 14A to 14J Each describes the manufacturing process according to an embodiment of this disclosure as follows: Figure 5A A cross-sectional view of one or more stages of a method for describing and illustrating a semiconductor package structure 400.

[0117] refer to Figure 14A A first carrier 21 having a first release film 210 is provided. Subsequently, a first semiconductor device 11 is attached to the first release film 210 at its first surface 11a. The first semiconductor device 11 includes conductive pads 119 at the first surface 11a. Additionally, a coreless substrate 51 is also attached to the first release film 210. The coreless substrate 51 includes a first pad 55 and a second pad 58. When attaching the first semiconductor device 11, the conductive pads 119 of the first semiconductor device 11 and the second pads 58 of the coreless substrate 51 are attached to the first release film 210.

[0118] refer to Figure 14B A first encapsulation layer 310 is formed on the release film 210, thereby covering the first semiconductor device 11 and the coreless substrate 51. Subsequently, the first carrier 21 and the first release film 210 are removed, thereby exposing the first surface 11a and conductive pads 119 of the first semiconductor device 11, and the second pads 58 of the coreless substrate 51.

[0119] Next reference Figure 14C A first redistribution structure 40 is formed on a first surface 11a of a first semiconductor device 11 and a first surface 31a of a first encapsulation layer 310. The first redistribution structure 40 includes a conductive layer 45, which further includes a first portion 451 disposed on a conductive pad 119 of the first semiconductor device 11, and a second portion 452 disposed on a second pad 58 of a coreless substrate 51. Subsequently, a first conductive pillar 812 is formed on the first portion 451 of the conductive layer 45, and a second conductive pillar 822 is formed on the second portion 452 of the conductive layer 45. Suitable materials for the first conductive pillar 812 and the second conductive pillar 822 are as described in the reference. Figure 3A The conductive support 112 described is made of a similar or identical material. Subsequently, refer to... Figure 14D The second semiconductor device 12 is coupled to the first semiconductor device 11, thereby forming a coupling joint 135 therebetween.

[0120] refer to Figure 14E The thickness of the first encapsulation layer 310 is reduced by a grinding process, thereby creating a reduced first encapsulation layer 31. The reduced first encapsulation layer 31 exposes the second surface 11b of the first semiconductor device 11 and the first pad 55 of the coreless substrate 51.

[0121] Subsequently, reference Figure 14F A second carrier 22 having a second release film 220 is provided. For example... Figure 14E The encapsulation structure described herein is attached to the second release film 220 at the second surface 11b. Subsequently, a second encapsulation layer 320 is formed on the second release film 220, thereby covering the encapsulation structure and the second semiconductor device 12. The encapsulation structure includes a reduced first encapsulation layer 31 that seals the first semiconductor device 11 and the coreless substrate 51. The second carrier 22 and the second release film 220 are then removed, thereby exposing the second surface 11b and the first pad 55 of the coreless substrate 51.

[0122] Now for reference Figure 14G A second redistribution structure 60 is formed on the second surface 11b of the first semiconductor device 11 and the first pad 55 of the coreless substrate 51. The second redistribution structure 60 includes a second dielectric layer 62 and a second conductive layer 65. A portion of the second conductive layer 65 is electrically connected to the first pad 55 of the coreless substrate 51.

[0123] Next reference Figure 14H The height of the second encapsulation layer 320 is reduced by a grinding process, thereby creating a reduced second encapsulation layer 32. The reduced second encapsulation layer 32 exposes the first conductive pillar 812 and the second conductive pillar 822 from its first surface 32a.

[0124] refer to Figure 14I A third redistribution structure 90 is subsequently formed on the first surface 32a of the reduced second encapsulation layer 32. The third redistribution structure 90 includes a third dielectric layer 92 and a third conductive layer 95. A portion of the conductive layer 95 forms an electrical connection with the first conductive pillar 812 and the second conductive pillar 822, and subsequently with the first portion 451 and the second portion 452 of the conductive layer 45, respectively. (See reference...) Figure 7F As described, suitable materials for the third dielectric layer 92 and the third conductive layer 95 are similar to or the same as those for the dielectric layer 42 and the conductive layer 45, respectively.

[0125] Subsequently, reference Figure 14J Electrical contacts 82 are mounted on the second redistribution structure 60 to electrically connect the first semiconductor device 11 to, for example, a PCB.

[0126] Now return to the reference Figure 5A The third semiconductor device 70 is stacked and attached to the third redistribution structure 90. The third semiconductor device 70 includes a high-bandwidth memory (HBM).

[0127] Figure 5B The semiconductor package structure 500 can be used with a reference Figures 14A to 14IThe methods of description and explanation are similar to those used in manufacturing, the difference being, for example, in Figure 14I After the operation, the stack of the third semiconductor device 70 is attached to the second redistribution structure 60, and the electrical contact 82 is mounted on the first redistribution structure 40.

[0128] Figures 15A to 15H Each describes the manufacturing process according to an embodiment of this disclosure as follows: Figure 6 A cross-sectional view of one or more stages of a method for describing and illustrating a semiconductor package structure 600.

[0129] refer to Figure 15A A first carrier 21 having a first release film 210 is provided. Subsequently, a first semiconductor device 11 is attached to the first release film 210 at its first surface 11a. The first semiconductor device 11 includes conductive pads 119 at the first surface 11a.

[0130] refer to Figure 15B A first encapsulation layer 310 is formed on the release film 210 to cover the first semiconductor device 11. The first carrier 21 and the first release film 210 are then removed to expose the first surface 11a and conductive pads 119 of the first semiconductor device 11.

[0131] Next reference Figure 15C A first redistribution structure 40 is formed on a first surface 11a of the first semiconductor device 11. The first redistribution structure 40 includes a conductive layer 45, which further includes a first portion 451 and a second portion 452 separated from the first portion 451. Subsequently, a first conductive pillar 812 and a second conductive pillar 822 are formed on the conductive layer 45 to provide electrical connections to the conductive pads 119 of the first semiconductor device 11. Then, refer to... Figure 15D The second semiconductor device 12 is integrated into the first semiconductor device 11.

[0132] refer to Figure 15E The thickness of the first encapsulation layer 310 is reduced by a grinding process, thereby creating a reduced first encapsulation layer 31. The reduced first encapsulation layer 31 exposes the second surface 11b of the first semiconductor device 11 and the first surface 31a of the reduced first encapsulation layer 31.

[0133] Next reference Figure 15F A second carrier 22 having a second release film 220 is provided. For example... Figure 15EThe encapsulation structure described herein is attached to the second release film 220 at the second surface 11b. Optionally, for example, a passive device 88 of an inductor may also be attached to the second release film 220. Thereafter, a second encapsulation layer 320 is formed on the second release film 220, thereby covering the passive device 88 (if present), the encapsulation structure, and the second semiconductor device 12, the encapsulation structure including a reduced first encapsulation layer 31 sealing the first semiconductor device 11. After the second encapsulation layer 320 is formed, the second carrier 22 and the second release film 220 are removed, thereby exposing the second surface 11b and the first surface 31a of the reduced first encapsulation layer 31.

[0134] refer to Figure 15G The height of the second encapsulation layer 320 is reduced by a grinding process, thereby creating a reduced second encapsulation layer 32. The reduced second encapsulation layer 32 exposes the first conductive pillar 812 and the second conductive pillar 822 from its first surface 32a.

[0135] Subsequently, reference Figure 15H A second redistribution structure 60 is formed on the first surface 32a of the reduced second encapsulation layer 32. The second redistribution structure 60 includes a second dielectric layer 62 and a second conductive layer 65. A portion of the second conductive layer 65 forms an electrical connection with the first conductive pillar 812 and the second conductive pillar 822.

[0136] Now return to the reference Figure 6 Electrical contacts 82 are mounted on the second redistribution structure 60. The second redistribution structure 60 and electrical contacts 82 are used to provide electrical connection between the first semiconductor device 11 and, for example, a PCB.

[0137] As used herein, the terms “approximately,” “substantially,” “roughly,” and “about” are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms may refer to examples where the event or situation occurred precisely or very approximately. Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format herein. It should be understood that this range format is used for convenience and brevity and should be interpreted flexibly, encompassing not only the numerical value explicitly specified as the limit of the range but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly specified.

[0138] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproductions in this disclosure and actual equipment. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor package structure comprising: A first semiconductor device having an active surface and including conductive pillars; A redistributed structure, which is electrically connected to the first semiconductor device; A second semiconductor device is coupled to the active surface of the first semiconductor device and disposed between the first semiconductor device and the redistribution structure, the second semiconductor device including conductive pillars that directly contact the conductive pillars of the first semiconductor device. Multiple conductive components are located on the active surface of the first semiconductor device and outside the second semiconductor device, wherein the first semiconductor device is electrically connected to the redistribution structure through the conductive components; A coreless substrate surrounds the first semiconductor device and the second semiconductor device, wherein the coreless substrate includes a first conductive pad and a second conductive pad. and An encapsulation layer that seals the first semiconductor device and the coreless substrate, a first conductive pad adjacent to a first surface of the encapsulation layer and electrically connected to the redistribution structure, and a second conductive pad adjacent to a second surface of the encapsulation layer, wherein the first conductive pad and the second conductive pad serve as input / output pads for electrically connecting the wiring layer of the coreless substrate to other components.

2. The semiconductor packaging structure according to claim 1, wherein the conductive pillar of the second semiconductor device is bonded to the conductive pillar of the first semiconductor device in a hybrid bonding process.

3. The semiconductor packaging structure according to claim 2, wherein the conductive pillar of the first semiconductor device comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer.

4. The semiconductor packaging structure according to claim 3, wherein the first conductive layer comprises a titanium layer, the second conductive layer comprises copper, the third conductive layer comprises nickel, and the fourth conductive layer comprises solder.

5. The semiconductor packaging structure according to claim 3, wherein the conductive pillar of the second semiconductor device comprises a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer.

6. The semiconductor packaging structure according to claim 5, wherein the first conductive layer comprises a titanium layer, the second conductive layer comprises copper, the third conductive layer comprises nickel, and the fourth conductive layer comprises solder.

7. The semiconductor package structure of claim 6, further comprising a first additional redistribution structure on the second surface of the encapsulation layer, the second surface being opposite to the first surface of the encapsulation layer.

8. The semiconductor package structure of claim 7, wherein the second semiconductor device further comprises a plurality of conductive vias disposed within the second semiconductor device and electrically connecting the conductive pillars of the second semiconductor device and the conductive layer of the redistribution structure.

9. The semiconductor packaging structure according to claim 7, wherein the first conductive pad and the second conductive pad are respectively flush with the first surface and the second surface of the first semiconductor device.

10. The semiconductor package structure of claim 7, wherein the first semiconductor device includes a digital processing device, and the second semiconductor device includes a decoupling capacitor, the semiconductor package structure further including a third semiconductor device disposed on the first additional redistribution structure, wherein the third semiconductor device includes a memory device.

11. The semiconductor package structure of claim 7, further comprising a second encapsulation layer, the second encapsulation layer sealing the encapsulation layer and the second semiconductor device, the second encapsulation layer having a first surface and a second surface opposite to the first surface.

12. The semiconductor packaging structure according to claim 11, further comprising: A second additional redistribution structure is disposed on the first surface of the second encapsulation layer and includes a conductive layer, the conductive layer being further comprising a first portion at the active surface of the first semiconductor device and a second portion on the coreless substrate. A first conductive pillar is disposed on the first portion of the conductive layer and is used to make an electrical connection between the redistribution structure and the second additional redistribution structure. and The second conductive pillar is disposed on the second portion of the conductive layer and is used to make an electrical connection between the coreless substrate and the second additional redistribution structure.

13. The semiconductor package structure of claim 11, wherein the second encapsulation layer contacts the second semiconductor device, the encapsulation layer does not contact the second semiconductor device, and the second encapsulation layer contacts a side of the encapsulation layer.

14. The semiconductor packaging structure of claim 1, wherein the coreless substrate comprises a wiring layer and a microvia electrically connected to the wiring layer.

15. The semiconductor package structure of claim 1, wherein the coreless substrate comprises a body, a plurality of vias and at least one routing layer, wherein the body is made of a molding compound, the plurality of vias extend through the body, wherein the bottom portions of the plurality of vias are electrically connected to the second conductive pad, wherein the routing layer is disposed on the body and electrically connects the plurality of vias and the first conductive pad.

16. A method for manufacturing a semiconductor package structure, the method comprising: Provide a first semiconductor device having an active surface; Multiple conductive components are formed on the active surface of the first semiconductor device; A second semiconductor device is attached to the active surface of the first semiconductor device, wherein the conductive component is located outside the second semiconductor device and the conductive post of the second semiconductor device is in direct contact with the conductive post of the first semiconductor device. A coreless substrate is provided surrounding the first semiconductor device and the second semiconductor device, wherein the coreless substrate includes a first conductive pad and a second conductive pad; An encapsulation layer is formed to cover the first semiconductor device and the coreless substrate; A redistribution structure is formed on the first surface of the encapsulation layer. The redistribution structure is electrically connected to the first semiconductor device via the conductive component. The second semiconductor device is disposed between the first semiconductor device and the redistribution structure. The first conductive pad is adjacent to the first surface of the encapsulation layer and electrically connected to the redistribution structure. The second conductive pad is adjacent to the second surface of the encapsulation layer. The first and second conductive pads serve as input / output pads for electrically connecting the wiring layer of the coreless substrate to other components.

17. The method of claim 16, wherein the conductive post of the second semiconductor device is bonded to the conductive post of the first semiconductor device using a hybrid bonding process.

18. The method of claim 17, further comprising: A second encapsulation layer is formed to seal the first semiconductor device, the encapsulation layer, the second semiconductor device, and the conductive component.

19. The method of claim 18, wherein the second encapsulation layer contacts a side of the encapsulation layer.

20. The method of claim 16, wherein the first semiconductor device comprises a digital processing device, and the second semiconductor device comprises a decoupling capacitor, the method further comprising providing a third semiconductor device on the redistribution structure, wherein the third semiconductor device comprises a memory device.

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