wiring structure

Abstract

A wiring structure includes an upper conductive structure, a lower conductive structure, and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and joins the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer includes a plurality of sub-layers. Each of the sub-layers is formed of a polymeric material. A boundary is formed between two adjacent sub-layers.

Description

Technical Field

[0001] This disclosure relates to a wiring structure, and more specifically, to a wiring structure comprising at least two conductive structures attached or joined together by an intermediate layer. Background Technology

[0002] With the rapid development of the electronics industry and the advancement of semiconductor processing technology, semiconductor chips integrate an increasing number of electronic components to achieve better electrical performance and more functions. Correspondingly, semiconductor chips have more input / output (I / O) connections. To manufacture semiconductor packages containing semiconductor chips with an increased number of I / O connections, the circuit layers of the semiconductor substrate supporting the semiconductor chips may need to be increased accordingly. Therefore, the thickness of the semiconductor substrate may increase, and the yield of the semiconductor substrate may decrease. Summary of the Invention

[0003] In some embodiments, a wiring structure includes an upper conductive structure, a lower conductive structure, and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper and lower conductive structures together. The upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer includes a plurality of sublayers. Each of the sublayers is formed of a polymeric material. A boundary is formed between two adjacent sublayers.

[0004] In some embodiments, a wiring structure includes an upper conductive structure, a lower conductive structure, and an intermediate layer. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper and lower conductive structures together. The upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer includes a plurality of sub-layers. The material of the sub-layers is different from the material of the dielectric layer of the lower conductive structure and the material of the dielectric layer of the upper conductive structure. At least two of the sub-layers are made of different materials.

[0005] In some embodiments, a wiring structure includes a low-density stacked structure, a high-density stacked structure, and an intermediate layer. The low-density stacked structure includes at least one dielectric layer and at least one low-density circuit layer in contact with the dielectric layer. The high-density stacked structure is disposed on the low-density stacked structure. The high-density stacked structure includes at least one dielectric layer and at least one high-density circuit layer in contact with the dielectric layer of the high-density stacked structure. The intermediate layer is disposed between the low-density stacked structure and the high-density stacked structure and bonds the low-density stacked structure and the high-density stacked structure together. The low-density stacked structure is electrically connected to the high-density stacked structure. The intermediate layer includes a plurality of sublayers. Each of the sublayers is formed of a polymeric material. A boundary is formed between two adjacent sublayers. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, various aspects of some embodiments of this disclosure can be readily understood from the following detailed description. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0008] Figure 2 illustrate Figure 1 An enlarged view of section "A" in the image.

[0009] Figure 3 illustrate Figure 1 A partially enlarged top view of the upper conductive structure.

[0010] Figure 4 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0011] Figure 5 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0012] Figure 5A A top view illustrating an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0013] Figure 5B A top view illustrating an example of a reference mark for a lower conductive structure according to some embodiments of the present disclosure.

[0014] Figure 5C illustrate Figure 5A The reference mark of the upper conductive structure and Figure 5B A top view of a composite image of the reference marks on the lower conductive structure.

[0015] Figure 5DA top view illustrating an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0016] Figure 5E A top view illustrating an example of a reference mark for a lower conductive structure according to some embodiments of the present disclosure.

[0017] Figure 5F illustrate Figure 5D The reference mark of the upper conductive structure and Figure 5E A top view of a composite image of the reference marks on the lower conductive structure.

[0018] Figure 5G A top view illustrating an example of a reference mark of an upper conductive structure according to some embodiments of the present disclosure.

[0019] Figure 5H A top view illustrating an example of a reference mark for a lower conductive structure according to some embodiments of the present disclosure.

[0020] Figure 5I illustrate Figure 5G The reference mark of the upper conductive structure and Figure 5H A top view of a composite image of the reference marks on the lower conductive structure.

[0021] Figure 6 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0022] Figure 7 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0023] Figure 8 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0024] Figure 9 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0025] Figure 10 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0026] Figure 11 A cross-sectional view illustrating the bonding between the package structure and the substrate.

[0027] Figure 12 A cross-sectional view illustrating the bonding between the package structure and the substrate.

[0028] Figure 13 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0029] Figure 14A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0030] Figure 15 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0031] Figure 16 A cross-sectional view illustrating a wiring structure according to some embodiments of the present disclosure.

[0032] Figure 17 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0033] Figure 18 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0034] Figure 19 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0035] Figure 20 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0036] Figure 21 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0037] Figure 22 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0038] Figure 23 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0039] Figure 24 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0040] Figure 25 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0041] Figure 26 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0042] Figure 27 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0043] Figure 28 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0044] Figure 29 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0045] Figure 30 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0046] Figure 31 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0047] Figure 32 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0048] Figure 33 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0049] Figure 34 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0050] Figure 35 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0051] Figure 36 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0052] Figure 37 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0053] Figure 38 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0054] Figure 39 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0055] Figure 40 This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure.

[0056] Figure 41This describes one or more stages of an example of a method for manufacturing a wiring structure according to some embodiments of the present disclosure. Detailed Implementation

[0057] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of this disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0058] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed or disposed in direct contact, and may also include embodiments where additional features may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0059] To meet the increased I / O count requirements, the number of dielectric layers on the substrate must be increased. In some embodiments, the manufacturing process of the core substrate may include the following steps: First, a core with two copper foils disposed on both sides of the core is provided. Subsequently, multiple dielectric layers and multiple circuit layers are formed or stacked on the two copper foils. One circuit layer may be embedded in one dielectric layer. Therefore, the core substrate may contain multiple stacked dielectric layers and multiple circuit layers embedded in the dielectric layers on both sides of the core. Because the line width / line space (L / S) of the circuit layers of such a core substrate can be greater than or equal to 10 micrometers (μm) / 10 μm, the number of dielectric layers of such a core substrate must be relatively large. Although the manufacturing cost of such a core substrate is lower, the manufacturing yield of the circuit layers and dielectric layers of such a core substrate is also lower, thus the yield of such a core substrate is low. In addition, the dielectric layers are relatively thick, therefore, such a core substrate is relatively thick. In a comparative embodiment, if the package has 10,000 I / O counts, then such a core substrate may require twelve circuit layers and dielectric layers. The manufacturing yield of one layer (containing a circuit layer and a dielectric layer) of such a core substrate can be 90%. Therefore, the yield of such a core substrate can be (0.9). 12 =28.24%. Furthermore, the warpage of the twelve circuit and dielectric layers can accumulate, potentially resulting in severe warpage in the top few layers. Consequently, the manufacturing yield of such core substrates may be even lower.

[0060] At least some embodiments of this disclosure provide wiring structures with an acceptable trade-off between yield and manufacturing cost. In some embodiments, the wiring structure includes an upper conductive structure and a lower conductive structure bonded to the upper conductive structure via an intermediate layer. At least some embodiments of this disclosure further provide techniques for manufacturing the wiring structures.

[0061] Figure 1 The diagram illustrates a cross-sectional view of a wiring structure 1 according to some embodiments of the present disclosure. The wiring structure 1 includes an upper conductive structure 2, a lower conductive structure 3, an intermediate layer 12, and at least one upper through via 14.

[0062] The upper conductive structure 2 includes at least one dielectric layer (including, for example, two first dielectric layers 20 and one second dielectric layer 26) and at least one circuit layer (including, for example, three first circuit layers 24 and one second circuit layer 28 formed of metal, metal alloy or other conductive material) in contact with the dielectric layer (e.g., the first dielectric layer 20 and the second dielectric layer 26). The dielectric layer (including, for example, two first dielectric layers 20 and one second dielectric layer 26) may be referred to as the upper dielectric layer, and the circuit layer (including, for example, three first circuit layers 24 and one second circuit layer 28) may be referred to as the upper circuit layer. In some embodiments, the upper conductive structure 2 may resemble a coreless substrate and may be of wafer type, panel type or strip type. The upper conductive structure 2 may also be referred to as a "stacked structure" or a "high-density conductive structure" or a "high-density stacked structure". The circuit layer of the upper conductive structure 2 (including, for example, three circuit layers 24) may also be referred to as a "high-density circuit layer". In some embodiments, the density of the circuit lines (including, for example, traces or pads) of the high-density circuit layer is greater than the density of the circuit lines of the low-density circuit layer. In other words, the number of circuit lines (including, for example, traces or pads) per unit area of ​​a high-density circuit layer is greater than the number of circuit lines per unit area of ​​a low-density circuit layer, for example, about 1.2 times or more, about 1.5 times or more, about 2 times or more, or about 5 times or more. Alternatively or in combination, the linewidth / spacing (L / S) of the high-density circuit layer is smaller than the L / S of the low-density circuit layer, for example, about 90% or less, about 50% or less, or about 20% or less. Furthermore, a conductive structure containing a high-density circuit layer may be designated as a "high-density conductive structure," and a conductive structure containing a low-density circuit layer may be designated as a "low-density conductive structure."

[0063] The upper conductive structure 2 has a top surface 21 and a bottom surface 22 opposite to the top surface 21. The upper conductive structure 2 includes multiple dielectric layers (e.g., two first dielectric layers 20 and one second dielectric layer 26), multiple circuit layers (e.g., three first circuit layers 24 and one second circuit layer 28), and at least one inner via 25. The dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) are stacked on top of each other. For example, the second dielectric layer 26 is disposed on the first dielectric layer 20, and therefore, the second dielectric layer 26 is the topmost dielectric layer. In one embodiment, the material of the dielectric layers (e.g., the first dielectric layer 20 and the second dielectric layer 26) is transparent and can be seen through by the human eye or a machine. In some embodiments, the transparent material of the dielectric layers has a transmittance of at least about 60%, at least about 70%, or at least about 80% for wavelengths in the visible range (or other relevant wavelengths used for detecting markers).

[0064] Furthermore, each first dielectric layer 20 has a top surface 201 and a bottom surface 202 opposite to the top surface 201. The second dielectric layer 26 has a top surface 261 and a bottom surface 262 opposite to the top surface 261. The bottom surface 262 of the second dielectric layer 26 is disposed on and in contact with the top surface 201 of the adjacent first dielectric layer 20. Therefore, the top surface 21 of the upper conductive structure 2 is the top surface 261 of the second dielectric layer 26, and the bottom surface 22 of the upper conductive structure 2 is the bottom surface 202 of the bottommost first dielectric layer 20.

[0065] The first circuit layer 24 may be a fan-out circuit layer or a redistribution layer (RDL), and the L / S ratio of the first circuit layer 24 may be less than or equal to 2μm / 2μm, or less than or equal to 1.8μm / 1.8μm. In some embodiments, the first circuit layer 24 is embedded in a corresponding first dielectric layer 20, and the top surface of the first circuit layer 24 may be substantially coplanar with the top surface 201 of the first dielectric layer 20. In some embodiments, the first circuit layer 24 may include a seed layer 243 and a conductive metal material 244 disposed on the seed layer 243. Figure 1 As shown, the bottommost first circuit layer 24 is disposed on the bottom surface 22 of the upper conductive structure 2 (i.e., the bottom surface 202 of the bottommost first dielectric layer 20) and protrudes from the bottom surface 22. Additionally, the second circuit layer 28 is disposed on the top surface 21 of the upper conductive structure 2 (i.e., the top surface 261 of the second dielectric layer 26) and protrudes from the top surface 21, and may include at least one pad 281 and at least one trace 282 electrically connected to the pad 281. The L / S ratio of the second circuit layer 28 may be greater than or equal to the L / S ratio of the first circuit layer 24. Figure 1 As shown in the embodiment, there are no horizontally connected or extended circuit layers in the second dielectric layer 26.

[0066] The upper conductive structure 2 includes a plurality of internal vias 25. Some internal vias 25 are disposed between two first circuit layers 24 to electrically connect the two first circuit layers 24. Some internal vias 25 are disposed between the first circuit layer 24 and the second circuit layer 28 to electrically connect the first circuit layer 24 and the second circuit layer 28. In some embodiments, the internal vias 25 may include a seed layer 251 and a conductive metal material 252 disposed on the seed layer 251. In some embodiments, the internal vias 25 and the corresponding first circuit layers 24 may be integrally formed as a single piece or a single component structure. Each internal via 25 gradually narrows upward along the direction from the bottom surface 22 of the upper conductive structure 2 toward the top surface 21.

[0067] The lower conductive structure 3 includes at least one dielectric layer (including, for example, a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) and at least one circuit layer (including, for example, a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a, and two second lower circuit layers 38a, 38a', formed of metal, metal alloy, or other conductive material) contacting the dielectric layer (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower circuit layer 36a). In some embodiments, the lower conductive structure 3 may resemble a core substrate, further including a core portion 37, and may be wafer-type, panel-type, or strip-type. The lower conductive structure 3 may also be referred to as a "stacked structure," a "low-density conductive structure," or a "low-density stacked structure." The circuit layer of the lower conductive structure 3 (including, for example, a first upper circuit layer 34; two second upper circuit layers 38, 38'; a first lower circuit layer 34a; and two second lower circuit layers 38a, 38a') can also be referred to as a "low-density circuit layer". For example... Figure 1 As shown, the lower conductive structure 3 has a top surface 31 and a bottom surface 32 opposite to the top surface 31. The lower conductive structure 3 includes multiple dielectric layers (e.g., a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a and a second lower dielectric layer 36a), multiple circuit layers (e.g., a first upper circuit layer 34, two second upper circuit layers 38, 38', a first lower circuit layer 34a and two second lower circuit layers 38a, 38a'), and at least one internal via (including, for example, multiple upper interconnect vias 35 and multiple lower interconnect vias 35a).

[0068] The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371, and defines a plurality of through holes 373 extending through the core portion 37. Interconnection vias 39 are disposed or formed in each through hole 373 for vertical connection. In some embodiments, each interconnection via 39 includes a base metal layer 391 and an insulating material 392. The base metal layer 391 is disposed or formed on the sidewall of the through hole 373 and defines a central through hole. The insulating material 392 fills the central through hole defined by the base metal layer 391. In some embodiments, the insulating material may be omitted from the interconnection via 39, and it may include a bulk metal material filling the through hole 373.

[0069] A first upper dielectric layer 30 is disposed on the top surface 371 of the core portion 37, and has a top surface 301 and a bottom surface 302 opposite to the top surface 301. A second upper dielectric layer 36 is stacked or disposed on the first upper dielectric layer 30, and has a top surface 361 and a bottom surface 362 opposite to the top surface 361. Therefore, the second upper dielectric layer 36 is the topmost dielectric layer. Additionally, a first lower dielectric layer 30a is disposed on the bottom surface 372 of the core portion 37, and has a top surface 301a and a bottom surface 302a opposite to the top surface 301a. A second lower dielectric layer 36a is stacked or disposed on the first lower dielectric layer 30a, and has a top surface 361a and a bottom surface 362a opposite to the top surface 361a. Figure 1 As shown, the top surface 31 of the lower conductive structure 3 is the top surface 361 of the second upper dielectric layer 36, and the bottom surface 32 of the lower conductive structure 3 is the bottom surface 362a of the second lower dielectric layer 36a.

[0070] The thickness of each dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) is less than or equal to about 40%, less than or equal to about 35%, and less than or equal to about 30% of the thickness of each dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a). For example, the thickness of each dielectric layer of the upper conductive structure 2 (e.g., the first dielectric layer 20 and the second dielectric layer 26) may be less than or equal to about 7 μm, and the thickness of each dielectric layer of the lower conductive structure 3 (e.g., the first upper dielectric layer 30, the second upper dielectric layer 36, the first lower dielectric layer 30a, and the second lower dielectric layer 36a) may be about 40 μm.

[0071] The L / S ratio of the first upper circuit layer 34 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the first upper circuit layer 34 can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. In some embodiments, the first upper circuit layer 34 is formed or disposed on the top surface 371 of the core portion 37 and is covered by the first upper dielectric layer 30. In some embodiments, the first upper circuit layer 34 may include a first metal layer 343, a second metal layer 344, and a third metal layer 345. The first metal layer 343 is disposed on the top surface 371 of the core portion 37 and may be formed of copper foil (e.g., may constitute part of copper foil). The second metal layer 344 is disposed on the first metal layer 343 and may be a copper-plated layer. The third metal layer 345 is disposed on the second metal layer 344 and may be another copper-plated layer. In some embodiments, the third metal layer 345 may be omitted.

[0072] The L / S ratio of the second upper circuit layer 38 can be greater than or equal to about 10 μm / about 10 μm. Therefore, the L / S ratio of the second upper circuit layer 38 can be approximately equal to the L / S ratio of the first upper circuit layer 34, and can be greater than or equal to about five times the L / S ratio of the first circuit layer 24 of the upper conductive structure 2. In some embodiments, the second upper circuit layer 38 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 and is covered by the second upper dielectric layer 36. The bottom surface 382 of the second upper circuit layer 38 contacts the top surface 301 of the first upper dielectric layer 30. In some embodiments, the second upper circuit layer 38 is electrically connected to the first upper circuit layer 34 through an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layer 38 and the first upper circuit layer 34 for electrically connecting the second upper circuit layer 38 and the first upper circuit layer 34. In some embodiments, the second upper circuit layer 38 and the upper interconnect via 35 are integrally formed as a single block or single piece structure.

[0073] Additionally, in some embodiments, the second upper circuit layer 38' is disposed on and protrudes from the top surface 361 of the second upper dielectric layer 36. In some embodiments, the second upper circuit layer 38 is electrically connected to the second upper circuit layer 38' via an upper interconnect via 35. That is, the upper interconnect via 35 is disposed between the second upper circuit layers 38 and 38' to electrically connect the second upper circuit layers 38 and 38'. In some embodiments, the second upper circuit layer 38' and the upper interconnect via 35 are integrally formed as a single piece or monolithic structure.

[0074] The structures and materials of the first lower circuit layer 34a, the second lower circuit layer 38a, the lower interconnect via 35a, and the second lower circuit layer 38a' are substantially similar to or the same as the structures and materials of the first upper circuit layer 34, the second upper circuit layer 38, the upper interconnect via 35a, and the second upper circuit layer 38'. For example, the first lower circuit layer 34a may include a first metal layer 343a, a second metal layer 344a, and a third metal layer 345a. The first metal layer 343a is disposed on the bottom surface 372 of the core portion 37, the second metal layer 344a is disposed on the first metal layer 343a, and the third metal layer 345a is disposed on the second metal layer 344a. In some embodiments, the third metal layer 345a may be omitted. In addition, the lower interconnect via 35a is disposed between the second lower circuit layers 38a and 38a' for electrical connection of the second lower circuit layers 38a and 38a'. In some embodiments, the second lower circuit layer 38a' and the lower interconnect via 35 are integrally formed as a single block or single piece structure.

[0075] In some embodiments, each interconnect via 39 is electrically connected to the first upper circuit layer 34 and the first lower circuit layer 34a. The base metal layer 391 of the interconnect via 39, the second metal layer 344 of the first upper circuit layer 34, and the second metal layer 344a of the first lower circuit layer 34a can be integrally and simultaneously formed as a single block or a single piece structure.

[0076] An intermediate layer 12 is inserted or disposed between the upper conductive structure 2 and the lower conductive structure 3 to bond the upper conductive structure 2 and the lower conductive structure 3 together. That is, the intermediate layer 12 adheres to the bottom surface 22 of the upper conductive structure 2 and the top surface 31 of the lower conductive structure 3. The intermediate layer 12 may include multiple sub-layers (e.g., including, for example, a first sub-layer 125 and a second sub-layer 126), and each of the sub-layers 125 and 126 is formed of a polymeric material. In some embodiments, the sub-layers of the intermediate layer 12 (e.g., the first sub-layer 125 and the second sub-layer 126) may be adhesive layers cured from an adhesive material (e.g., comprising a cured adhesive material, such as an adhesive polymer). That is, the material of each of the polymeric materials is different from the material of the dielectric layers 20 and 26 of the upper conductive structure 2 and the dielectric layers 30, 36, 30a, and 36a of the lower conductive structure 3. The sublayers of the intermediate layer 12 (e.g., the first sublayer 125 and the second sublayer 126) may not be part of either the upper conductive structure 2 or the lower conductive structure 3. Furthermore, each of the polymeric materials has a viscosity, and the viscosities of the polymeric materials in two adjacent sublayers (e.g., the first sublayer 125 and the second sublayer 126) are different from each other. Figure 1As shown, at least two of the sublayers (e.g., first sublayer 125 and second sublayer 126) are made of different materials, and a boundary 127 is formed between two adjacent sublayers (e.g., first sublayer 125 and second sublayer 126). The intermediate layer 12 does not contain any horizontally extending circuit layers on the boundary 127. There are no horizontally extending circuit layers disposed adjacent to the boundary 127.

[0077] The intermediate layer 12 has a top surface 121 and a bottom surface 122 opposite to the top surface 121. The top surface 121 of the intermediate layer 12 contacts the bottom surface 22 of the upper conductive structure 2, and the bottom surface 122 of the intermediate layer 12 contacts the top surface 31 of the lower conductive structure 3. Therefore, the bottommost first circuit layer 24 (e.g., first circuit layer 24) of the upper conductive structure 2 and the topmost circuit layer 38' (e.g., second upper circuit layer 38') of the lower conductive structure 3 are embedded in the intermediate layer 12.

[0078] like Figure 1 As shown, the intermediate layer 12 comprises a first sublayer 125 formed of a first polymeric material and a second sublayer 126 formed of a second polymeric material. The viscosity of the first polymeric material is greater than that of the second polymeric material. For example, the viscosity of the first polymeric material is about three, five, or ten times greater than that of the second polymeric material. Therefore, the first polymeric material of the first sublayer 125 is used to provide adhesion, and the second sublayer 126 is used to provide a smooth, flat surface. In some embodiments, the material of the first polymeric material may comprise polyimide (PI), and the material of the second polymeric material may comprise an Ajinomoto build-up film (ABF). In some embodiments, the materials of the intermediate layer 12 (e.g., the first sublayer 125 and the second sublayer 126) are transparent and can be seen through by the human eye or a machine.

[0079] like Figure 1As shown, the first sublayer 125 contacts the lower conductive structure 3 and covers the topmost circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). Due to the relatively high viscosity of the first polymeric material and the small thickness of the first sublayer 125 (or the first polymeric material), the top surface of the first sublayer 125 (or the first polymeric material) is substantially conformal to the second upper circuit layer 38' and the top surface 31. Therefore, the top surface of the first sublayer 125 (or the first polymeric material) is not a smooth, flat surface, which can reduce the bonding quality between the upper conductive structure 2 and the lower conductive structure 3. To solve this problem, a second polymeric material with a relatively low viscosity is applied onto the first polymeric material. The top surface of the second polymeric material (or the second sublayer 126) is a substantially smooth, flat surface. Therefore, when the upper conductive structure 2 is attached to the second polymeric material (or the second sublayer 126), the bonding quality between the upper conductive structure 2 and the lower conductive structure 3 is improved. At the same time, the second polymeric material (or the second sublayer 126) contacts the upper conductive structure 2. In addition, the thickness of the intermediate layer 12 (i.e., the sum of the thickness of the first sublayer 125 and the thickness of the second sublayer 126) can be reduced.

[0080] In some embodiments, the bonding force between two adjacent dielectric layers of the upper conductive structure 2 (e.g., two adjacent first dielectric layers 20) is greater than the bonding force between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12. For example, in terms of root mean squared surface roughness, the surface roughness of the boundary between the two adjacent dielectric layers of the upper conductive structure 2 (e.g., two adjacent first dielectric layers 20) is approximately 1.1 times or greater, approximately 1.3 times or greater, or approximately 1.5 times or greater than the surface roughness of the boundary between the dielectric layer of the upper conductive structure 2 (e.g., the bottom first dielectric layer 20) and the intermediate layer 12. In some embodiments, the bonding force between the first sublayer 125 and the lower conductive structure 3 may be greater than the bonding force between the second sublayer 126 and the upper conductive structure 2.

[0081] Wiring structure 1 may define vias 23 extending through at least a portion of the upper conductive structure 2 and the intermediate layer 12, and exposing a portion of the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'). Upper vias 14 are formed or disposed in corresponding vias 23 and are formed of metal, metal alloy, or other conductive materials. Therefore, upper vias 14 extend through at least a portion of the upper conductive structure 2 and the intermediate layer 12, and are electrically connected to the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'). Figure 1As shown, the upper via 14 extends through and contacts the bottommost first circuit layer 24 of the upper conductive structure 2, and terminates at or on a portion of the topmost circuit layer of the lower conductive structure 3 (e.g., the top surface of the second upper circuit layer 38'), and contacts said portion. Therefore, the upper conductive structure 2 is electrically connected to the lower conductive structure 3 through the upper via 14.

[0082] In some embodiments, the low-density circuit layer (e.g., the second upper circuit layer 38') of the low-density conductive structure (e.g., the lower conductive structure 3) is electrically connected to the high-density circuit layer (e.g., the bottom first circuit layer 24) of the high-density conductive structure (e.g., the upper conductive structure 2) only through the upper via 14. The length (along the longitudinal axis) of the upper via 14 is greater than the thickness of the high-density conductive structure (e.g., the upper conductive structure 2). Furthermore, the upper via 14 gradually narrows downwards; that is, the size of the top portion of the upper via 14 is greater than the size of the bottom portion of the upper via 14. Therefore, the narrowing direction of the internal via 25 of the upper conductive structure 2 is different from the narrowing direction of the upper via 14. In some embodiments, the upper via 14 is a monolithic structure or a single-piece structure with a homogeneous material composition. The upper via 14 and the pad 281 of the second circuit layer 28 can be integrally formed as a monolithic or single-piece structure.

[0083] like Figure 1 As shown, the upper conductive structure 2 includes a high-density region 41 and a low-density region 47. In some embodiments, the density of circuit lines (including, for example, traces or pads) in the high-density region 41 is greater than the density of circuit lines in the low-density region 47. Alternatively or in combination, the L / S ratio of the circuit layers in the high-density region 41 is less than the L / S ratio of the circuit layers in the low-density region 47. Furthermore, the upper via 14 is disposed in the low-density region 47 of the high-density conductive structure (e.g., the upper conductive structure 2). In some embodiments, the high-density region 41 may be a chip bonding region.

[0084] like Figure 1As illustrated in the embodiments described herein, wiring structure 1 is a combination of upper conductive structure 2 and lower conductive structure 3, wherein the circuit layer 24 of the upper conductive structure 2 has fine pitch, high yield, and low thickness; and the circuit layers 34, 38, 38', 34a, 38a, and 38a' of the lower conductive structure 3 have low manufacturing cost. Therefore, wiring structure 1 offers a favorable trade-off between yield and manufacturing cost, and has a relatively low thickness. In some embodiments, if the package has 10,000 I / Os, then wiring structure 1 comprises three first circuit layers 24 of the upper conductive structure 2 and six circuit layers 34, 38, 38', 34a, 38a, and 38a' of the lower conductive structure 3. The manufacturing yield of one layer of the first circuit layer 24 of the upper conductive structure 2 can be 99%, and the manufacturing yield of one layer of the circuit layer of the lower conductive structure 3 (e.g., the first upper circuit layer 34, the second upper circuit layers 38, 38', the first lower circuit layer 34a, and the second lower circuit layers 38a, 38a') can be 90%. Therefore, the yield of the wiring structure 1 can be improved. Furthermore, the warpage of the upper conductive structure 2 and the warpage of the lower conductive structure 3 are separate and do not affect each other. That is, the warpage of the lower conductive structure 3 does not accumulate on the warpage of the upper conductive structure 2. Therefore, the yield of the wiring structure 1 can be further improved.

[0085] Furthermore, during the manufacturing process, the lower conductive structure 3 and the upper conductive structure 2 can be tested separately before being joined together. Therefore, known good lower conductive structures 3 and known good upper conductive structures 2 can be selectively joined together. Defective (or unqualified) lower conductive structures 3 and defective (or unqualified) upper conductive structures 2 can be discarded. Therefore, the yield of the wiring structure 1 can be further improved.

[0086] Figure 2 illustrate Figure 1 An enlarged view of section "A" in the image. Figure 3 illustrate Figure 1 A partially enlarged top view of the upper conductive structure 2. (See attached image.) Figure 2As shown, the first sub-layer 125 has a top surface (i.e., boundary 127). The top surface (i.e., boundary 127) of the first sub-layer 125 has a highest point H and a lowest point L, and the height difference D between the highest point H and the lowest point L is greater than 3 μm, greater than 5 μm, or greater than 7 μm. For example, the height difference D between the highest point H and the lowest point L is greater than one-third or one-half of the thickness T of the topmost circuit layer (i.e., the second upper circuit layer 38') of the lower conductive structure 3. Additionally, the via 23 includes a top portion 231 with a first width W1 and a bottom portion 232 with a second width W2. Since the via 23 can be formed by laser drilling, the second width W2 can be smaller than the first width W1. For example, the second width W2 can be 70% or 75% of the first width W1. That is, the ratio of the second width W2 to the first width W1 can be fixed. Therefore, if the value of the second width W2 is fixed, then the value of the first width W1 is proportional to the total thickness of the upper conductive structure 2 and the intermediate layer 12 through which the via 23 extends. In other words, a larger total thickness of the upper conductive structure 2 and the intermediate layer 12 will result in a larger first width W1. Furthermore, the value of the third width W3 of the pad 281 of the second circuit layer 28 can be proportional to the value of the first width W1 of the top portion 231 of the via 23. Therefore, the third width W3 of the pad 281 can be proportional to the total thickness of the upper conductive structure 2 and the intermediate layer 12 through which the via 23 extends.

[0087] like Figure 3 As shown, pads 281 are arranged in multiple rows (including, for example, a first row 18a, a second row 18b, and a third row 18c). In the illustrated embodiment, the third width W3 (e.g., diameter) of pads 281 may be proportional to the total thickness of the upper conductive structure 2 and the intermediate layer 12, and as stated above, the thickness of the intermediate layer 12 (i.e., the sum of the thicknesses of the first sublayer 125 and the second sublayer 126) may be reduced. Therefore, the third width W3 (e.g., diameter) of pads 281 may be reduced to a minimum. If the distance d between the first row 18a and the second row 18b is fixed, then the third row 18c and six tracks 282 may be positioned between the first row 18a and the second row 18b. In a comparative embodiment, the third width W3 (e.g., diameter) of pads 281 is relatively large due to the large thickness of the intermediate layer 12. Therefore, when the distance d between the first row 18a and the second row 18b is fixed, the third row 18c may not be able to be placed between the first row 18a and the second row 18b, or the number of trajectories 282 may be reduced.

[0088] Figure 4 This illustration shows a cross-sectional view of a wiring structure 1a according to some embodiments of the present disclosure. The wiring structure 1a is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the intermediate layer 12a. For example... Figure 4As shown, the first sublayer 125 contacts the upper conductive structure 2, and the second sublayer 126 contacts the lower conductive structure 3 and covers the topmost circuit layer of the lower conductive structure 3 (i.e., the second upper circuit layer 38'). The boundary 127 can be a flat surface. That is, the highest and lowest points of the boundary 127 can be close to zero, for example, less than 1 μm, less than 0.1 μm, or less than 0.05 μm. In addition, the bonding force between the first sublayer 125 and the upper conductive structure 2 is greater than the bonding force between the second sublayer 126 and the lower conductive structure 3.

[0089] Figure 5 This illustration shows a cross-sectional view of a wiring structure 1b according to some embodiments of the present disclosure. The wiring structure 1b is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2b and the lower conductive structure 3b. For example... Figure 5 As shown, both the upper conductive structure 2b and the lower conductive structure 3b are strip structures. Therefore, the wiring structure 1b is a strip structure. In some embodiments, the lower conductive structure 3b may be a panel structure carrying multiple strip upper conductive structures 2b. Therefore, the wiring structure 1b is a panel structure. Furthermore, the lateral peripheral surface 27 of the upper conductive structure 2b is not coplanar with the lateral peripheral surface 33 of the lower conductive structure 3b (e.g., it is recessed inward or otherwise offset from it).

[0090] like Figure 5 As shown, the upper conductive structure 2b includes at least one reference mark 43 at its corner, and the lower conductive structure 3b has at least one reference mark 45 at its corner. During the manufacturing process, the reference mark 43 of the upper conductive structure 2b is aligned with the reference mark 45 of the lower conductive structure 3b to ensure the relative positions of the upper conductive structure 2b and the lower conductive structure 3b. In one embodiment, the reference mark 43 of the upper conductive structure 2b is disposed on and protrudes from the bottom surface 22 of the upper conductive structure 2b (e.g., the bottom surface 202 of the bottommost first dielectric layer 20). The reference mark 43 and the bottommost first circuit layer 24 may be co-layered or partially co-layered and may be formed simultaneously. Additionally, the reference mark 45 of the lower conductive structure 3b is disposed on and protrudes from the top surface 31 of the lower conductive structure 3b (e.g., the top surface 361 of the second upper dielectric layer 36). The reference mark 45 and the second upper circuit layer 38' may be co-layered or partially co-layered and may be formed simultaneously.

[0091] Figure 5A This is a top view illustrating an example of a reference mark 43a of the upper conductive structure 2b according to some embodiments of the present disclosure. The reference mark 43a of the upper conductive structure 2b has a continuous cross shape.

[0092] Figure 5B This is a top view illustrating an example of a reference mark 45a of the lower conductive structure 3b according to some embodiments of the present disclosure. The reference mark 45a of the lower conductive structure 3b comprises four square segments at the four corners.

[0093] Figure 5C illustrate Figure 5A The reference mark 43a and the upper conductive structure 2b Figure 5B The combined image is a top view of the reference mark 45a of the lower conductive structure 3b. When the upper conductive structure 2b is precisely aligned with the lower conductive structure 3b, the combined image shows the complete reference mark 43a and the complete reference mark 45a, as shown. Figure 5C As shown. That is to say, from the top view, datum mark 43a does not cover or overlap datum mark 45a.

[0094] Figure 5D This is a top view illustrating an example of a reference mark 43b of the upper conductive structure 2b according to some embodiments of the present disclosure. The reference mark 43b of the upper conductive structure 2b is a continuously inverted "L" shape.

[0095] Figure 5E This is a top view illustrating an example of a reference mark 45b of the lower conductive structure 3b according to some embodiments of the present disclosure. The reference mark 45b of the lower conductive structure 3b has a continuously inverted "L" shape that is substantially the same as the reference mark 43b of the upper conductive structure 2b.

[0096] Figure 5F illustrate Figure 5D The reference mark 43b of the upper conductive structure 2b and Figure 5E The combined image is a top view of the reference mark 45b of the lower conductive structure 3b. When the upper conductive structure 2b is precisely aligned with the lower conductive structure 3b, the combined image only shows the reference mark 43b of the upper conductive structure 2b, as shown. Figure 5F As shown. That is to say, from the top view, datum mark 43b completely covers or overlaps datum mark 45b.

[0097] Figure 5G This is a top view illustrating an example of a reference mark 43c of the upper conductive structure 2b according to some embodiments of the present disclosure. The reference mark 43c of the upper conductive structure 2b has a continuous circular shape.

[0098] Figure 5H This is a top view illustrating an example of a reference mark 45c of the lower conductive structure 3b according to some embodiments of the present disclosure. The reference mark 45c of the lower conductive structure 3b has a continuous circular shape that is larger than that of the reference mark 43c of the upper conductive structure 2b.

[0099] Figure 5I illustrate Figure 5G The reference mark 43c of the upper conductive structure 2b and Figure 5H A top view of the combined image of the reference mark 45c of the lower conductive structure 3b. When the upper conductive structure 2b and the lower conductive structure 3b are precisely aligned, the combined image shows two concentric circles, as shown. Figure 5I As shown. That is, the reference mark 43c is set at the center of the reference mark 45c.

[0100] Figure 6 This illustration shows a cross-sectional view of a wiring structure 1c according to some embodiments of the present disclosure. The wiring structure 1c is similar to... Figure 1 The wiring structure 1 shown differs from the one described above in the structure of the upper conductive structure 2c and the lower conductive structure 3c. Additionally, [details omitted]. Figure 1 The upper guide hole 14, and in Figure 6 The wiring structure 1c further includes at least one lower via 15. For example... Figure 6 As shown, wiring structure 1c defines a via 40 extending through the lower conductive structure 3c and the intermediate layer 12. The via 40 gradually narrows upwards. Furthermore, the thickness of the bottommost first circuit layer 24a of the upper conductive structure 2c is greater than the thickness of the other first circuit layers 24, for example, approximately 1.1 times or more, approximately 1.3 times or more, or approximately 1.5 times or more. For example, the thickness of the bottommost first circuit layer 24a may be approximately 4 μm, and the thickness of the other first circuit layers 24 may be approximately 3 μm. This is because the bottommost first circuit layer 24a can be used to block laser beams during the manufacturing process. The bottommost circuit layer 24a (e.g., the bottommost first circuit layer 24a) is disposed on and protrudes from the bottom surface 22 of the upper conductive structure 2c (e.g., the bottom surface 202 of the bottommost first dielectric layer 20).

[0101] A lower via 15 is formed or disposed in the via 40. Therefore, the lower via 15 extends through at least a portion of the lower conductive structure 3c and the intermediate layer 12, and is electrically connected to the circuit layer of the upper conductive structure 2c (e.g., the bottommost first circuit layer 24a). Figure 6As shown, the lower via 15 extends through and contacts the topmost circuit layer (e.g., the second upper circuit layer 38') of the upper conductive structure 3c, and terminates at or above a portion of the bottommost circuit layer (e.g., the bottommost first circuit layer 24a) of the upper conductive structure 2c, contacting said portion. The length of the lower via 15 is greater than the thickness of the low-density conductive structure (e.g., the upper conductive structure 3c). Furthermore, the lower via 15 gradually narrows upwards. Therefore, the narrowing direction of the internal via 25 of the upper conductive structure 2c is the same as the narrowing direction of the lower via 15. In some embodiments, the lower via 15 and the second lower circuit layer 38a' may be integrally formed as a single piece or monolithic structure.

[0102] Figure 7 This illustration shows a cross-sectional view of a wiring structure 1d according to some embodiments of the present disclosure. The wiring structure 1d is similar to... Figure 6 The wiring structure 1c shown differs from that of the intermediate layer 12a. For example... Figure 7 As shown, the first sub-layer 125 is in contact with the upper conductive structure 2c, and the second sub-layer 126 is in contact with the upper conductive structure 3c and covers the topmost circuit layer of the upper conductive structure 3c (i.e., the second upper circuit layer 38').

[0103] Figure 8 This illustration shows a cross-sectional view of a wiring structure 1e according to some embodiments of the present disclosure. The wiring structure 1e is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2c and the lower conductive structure 3c. Additionally, in Figure 8 The wiring structure 1e also includes at least one lower via 15. Figure 8 The structure of the lower through hole 15 is similar to Figure 6 The lower through hole 15. The size of the top portion of the lower through hole 15 may be approximately equal to the size of the bottom portion of the upper through hole 14, and the gradually narrowing direction of the lower through hole 15 may be different from the gradually narrowing direction of the upper through hole 14.

[0104] Figure 9 This illustration shows a cross-sectional view of a wiring structure 1f according to some embodiments of the present disclosure. The wiring structure 1f is similar to... Figure 8 The wiring structure 1e shown differs from that of the intermediate layer 12a. For example... Figure 9 As shown, the first sub-layer 125 is in contact with the upper conductive structure 2c, and the second sub-layer 126 is in contact with the upper conductive structure 3c and covers the topmost circuit layer of the upper conductive structure 3c (i.e., the second upper circuit layer 38').

[0105] Figure 10This illustration shows a cross-sectional view of a wiring structure 1g according to some embodiments of the present disclosure. The wiring structure 1g is similar to... Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2g and the lower conductive structure 3g. Additionally, the upper via 14 is replaced with at least one penetrating via 16. Figure 10 As shown, wiring structure 1g defines at least one via 17 extending through the upper conductive structure 2g, the intermediate layer 12, and the lower conductive structure 3g. The maximum width of the via 17 can be from about 100 μm to about 1000 μm. In some embodiments, the via 17 can be formed by mechanical drilling. Therefore, the via 17 may not taper gradually. A through-hole 16 is formed or disposed in the corresponding via 17 and is formed of metal, metal alloy, or other conductive material. Therefore, the through-hole 16 extends through the upper conductive structure 2g, the intermediate layer 12, and the lower conductive structure 3g. Figure 10 As shown, the through-hole 16 extends through and contacts the bottom first circuit layer 24 of the upper conductive structure 2g, the top circuit layer (e.g., the second upper circuit layer 38') of the lower conductive structure 3g, and the bottom circuit layer (e.g., the second lower circuit layer 38a') of the lower conductive structure 3g. In some embodiments, the through-hole 16 is a monolithic structure or a single-piece structure with isomorphic material composition. In some embodiments, the through-hole 16 and the second circuit layer 28 may be integrally formed.

[0106] Figure 11 This illustration shows a cross-sectional view illustrating the bonding of the package structure 4 with the substrate 46 according to some embodiments. The package structure 4 includes a wiring structure 1h, a semiconductor chip 42, a plurality of first connecting elements 44, and a plurality of second connecting elements 48. Figure 11 The wiring structure 1h is similar to Figure 1 The wiring structure 1 shown differs in the structure of the upper conductive structure 2h and the lower conductive structure 3h. Both the upper conductive structure 2h and the lower conductive structure 3h are bare dies and can be singulated simultaneously. Therefore, wiring structure 1h is a unit structure. That is, the lateral peripheral surface 27h of the upper conductive structure 2h, the lateral peripheral surface 33h of the lower conductive structure 3h, and the lateral peripheral surface of the intermediate layer 12 are substantially coplanar with each other. The semiconductor chip 42 is electrically connected and bonded to the second circuit layer 28 of the upper conductive structure 2h via a first connecting element 44 (e.g., solder bumps or other conductive bumps). The second lower circuit layer 38a' of the lower conductive structure 3h is electrically connected and bonded to the substrate 46 (e.g., a motherboard, such as a printed circuit board (PCB)) via a second connecting element 48 (e.g., solder bumps or other conductive bumps).

[0107] Figure 12This image illustrates a cross-sectional view showing the bonding between the package structure 4a and the substrate 46 according to some embodiments. The package structure 4a is similar to... Figure 11 The packaging structure 4 shown differs in that the intermediate layer 12a has a different structure. For example... Figure 12 As shown in the wiring structure 1j, the first sub-layer 125 is in contact with the upper conductive structure 2h, and the second sub-layer 126 is in contact with the lower conductive structure 3h and covers the topmost circuit layer of the lower conductive structure 3h (i.e., the second upper circuit layer 38').

[0108] Figure 13 This illustration shows a cross-sectional view of a wiring structure 1k according to some embodiments of the present disclosure. The wiring structure 1k is similar to... Figure 1 The wiring structure 1 shown is different in that the middle layer 12k has a different structure. For example... Figure 13 As shown, a third sublayer 125a formed of a third polymeric material is inserted or located between the upper conductive structure 2 and the second sublayer 126. That is, the intermediate layer 12k includes a first sublayer 125, a second sublayer 126, and a third sublayer 125a. The second sublayer 126 is inserted or located between the first sublayer 125 and the third sublayer 125a. The viscosity of the first polymeric material is greater than the viscosity of the second polymeric material, and the viscosity of the third polymeric material is greater than the viscosity of the second polymeric material. In some embodiments, the material of the first sublayer 125 is substantially the same as the material of the third sublayer 125a, and different from the material of the second sublayer 126. The viscosity of the first polymeric material is substantially equal to the viscosity of the third polymeric material. Figure 13 As shown, the first sublayer 125 contacts the lower conductive structure 3 and covers the topmost circuit layer of the lower conductive structure 3 (i.e., the second upper circuit layer 38'), and the third sublayer 125b contacts the upper conductive structure 2.

[0109] Figure 14 This illustration shows a cross-sectional view of a wiring structure 1m according to some embodiments of the present disclosure. The wiring structure 1m is similar to... Figure 4 The wiring structure 1a shown is different in that the middle layer 12m has a different structure. For example... Figure 14 As shown, a fourth sublayer 126a formed of a fourth polymeric material is inserted or located between the upper conductive structure 2 and the first sublayer 125. That is, the intermediate layer 12m includes the first sublayer 125, the second sublayer 126, and the fourth sublayer 126a. The first sublayer 125 is inserted or located between the second sublayer 126 and the fourth sublayer 126a. The viscosity of the second polymeric material is less than the viscosity of the first polymeric material, and the viscosity of the fourth polymeric material is less than the viscosity of the first polymeric material. In some embodiments, the material of the second sublayer 126 is substantially the same as the material of the fourth sublayer 126a, and different from the material of the first sublayer 125. The viscosity of the second polymeric material is substantially equal to the viscosity of the fourth polymeric material. Figure 14As shown, the second sub-layer 126 contacts the lower conductive structure 3 and covers the topmost circuit layer of the lower conductive structure 3 (i.e., the second upper circuit layer 38'), and the fourth sub-layer 126a contacts the upper conductive structure 2.

[0110] Figure 15 This illustration shows a cross-sectional view of a wiring structure 1n according to some embodiments of the present disclosure. The wiring structure 1n is similar to... Figure 1 The wiring structure 1 shown differs from the structure of the upper conductive structure 2n. For example... Figure 15 As shown, the upper conductive structure 2n further includes a bottom first dielectric layer 20a covering the bottom first circuit layer 24. Therefore, the entire bottom surface 22 of the upper conductive structure 2n (e.g., the bottom surface 202 of the bottom first dielectric layer 20a) is substantially flat. The second sub-layer 126 of the intermediate layer 12 is adhered to the bottom surface 22 of the upper conductive structure 2n (e.g., the bottom surface 202 of the bottom first dielectric layer 20a). Therefore, the entire top surface 121 of the intermediate layer 12 is substantially flat. The second sub-layer 126 of the intermediate layer 12 does not contain or contact horizontally extending or connected circuit layers. That is, there are no horizontally extending or connected circuit layers disposed or embedded in the second sub-layer 126 of the intermediate layer 12.

[0111] Figure 16 This illustration shows a cross-sectional view of a wiring structure 1p according to some embodiments of the present disclosure. The wiring structure 1p is similar to... Figure 15 The wiring structure 1n shown is different in that the intermediate layer 12a has a different structure. For example... Figure 16 As shown, the first sublayer 125 is in contact with the bottom surface 22 of the upper conductive structure 2n (e.g., the bottom surface 202 of the bottommost first dielectric layer 20a). The second sublayer 126 is in contact with the lower conductive structure 3 and covers the topmost circuit layer of the lower conductive structure 3 (i.e., the second upper circuit layer 38').

[0112] Figures 17 to 41 This invention describes a method for manufacturing a wiring structure according to some embodiments of the present disclosure. In some embodiments, the method is used to manufacture... Figure 1 The wiring structure 1 and / or shown Figure 11 The packaging structure shown is 4.

[0113] refer to Figures 17 to 26 A lower conductive structure 3 is provided. The lower conductive structure 3 is manufactured as follows. (See reference) Figure 17 A core portion 37 is provided, having a top copper foil 50 and a bottom copper foil 52. The core portion 37 can be of wafer type, panel type, or strip type. The core portion 37 has a top surface 371 and a bottom surface 372 opposite to the top surface 371. The top copper foil 50 is disposed on the top surface 371 of the core portion 37, and the bottom copper foil 52 is disposed on the bottom surface 372 of the core portion 37.

[0114] refer to Figure 18 Multiple through holes 373 are formed by drilling techniques (such as laser drilling or mechanical drilling) or other suitable techniques to extend through the core portion 37, the top copper foil 50 and the bottom copper foil 52.

[0115] Next, a second metal layer 54 is formed or disposed on the sidewalls of the top copper foil 50, the bottom copper foil 52, and the through-hole 373 using plating technology or other suitable techniques. A portion of the second metal layer 54 on the sidewall of each through-hole 373 defines a central through-hole.

[0116] Next, insulating material 392 is placed to fill the central through-hole defined by the second metal layer 54.

[0117] refer to Figure 19 A top third metal layer 56 and a bottom third metal layer 56a are formed or disposed on the second metal layer 54 by means of plating technology or other suitable technology. The third metal layers 56 and 56a are covered with insulating material 392.

[0118] refer to Figure 20 A top photoresist layer 57 is formed or disposed on the top third metal layer 56, and a bottom photoresist layer 57a is formed or disposed on the bottom third metal layer 56a. Then, the photoresist layers 57 and 57a are patterned by exposure and development.

[0119] refer to Figure 21 The portions of the top copper foil 50, the second metal layer 54, and the top third metal layer 56 that are not covered by the top photoresist layer 57 are removed using etching or other suitable techniques. The portions of the top copper foil 50, the second metal layer 54, and the top third metal layer 56 covered by the top photoresist layer 57 are retained to form the first upper circuit layer 34. Simultaneously, the portions of the bottom copper foil 52, the second metal layer 54, and the bottom third metal layer 56a that are not covered by the bottom photoresist layer 57a are removed using etching or other suitable techniques. The portions of the bottom copper foil 52, the second metal layer 54, and the bottom third metal layer 56a covered by the bottom photoresist layer 57a are retained to form the first lower circuit layer 34a. Meanwhile, the portions of the second metal layer 54 and the insulating material 392 disposed in the via 373 form interconnect vias 39.

[0120] refer to Figure 22 The top photoresist layer 57 and the bottom photoresist layer 57a are removed by stripping techniques or other suitable techniques.

[0121] refer to Figure 23A first upper dielectric layer 30 is formed or disposed on the top surface 371 of the core portion 37 using lamination technology or other suitable techniques to cover the top surface 371 and the first upper circuit layer 34 of the core portion 37. Simultaneously, a first lower dielectric layer 30a is formed or disposed on the bottom surface 372 of the core portion 37 using lamination technology or other suitable techniques to cover the bottom surface 372 and the first lower circuit layer 34a of the core portion 37. Next, at least one via 303 is formed extending through the first upper dielectric layer 30 using drilling technology or other suitable techniques, thereby exposing a portion of the first upper circuit layer 34. Simultaneously, at least one via 303a is formed extending through the first lower dielectric layer 30a using drilling technology or other suitable techniques, thereby exposing a portion of the first lower circuit layer 34a.

[0122] refer to Figure 24 The second upper circuit layer 38 is formed on the first upper dielectric layer 30, and the upper interconnect via 35 is formed in the via 303. At the same time, the second lower circuit layer 38a is formed on the first lower dielectric layer 30a, and the lower interconnect via 35a is formed in the via 303a.

[0123] refer to Figure 25 A second upper dielectric layer 36 is formed or disposed on the top surface 301 of the first upper dielectric layer 30 using lamination technology or other suitable techniques to cover the top surface 301 of the first upper dielectric layer 30 and the second upper circuit layer 38. Simultaneously, a second lower dielectric layer 36a is formed or disposed on the bottom surface 302a of the first lower dielectric layer 30a using lamination technology or other suitable techniques to cover the bottom surface 302a of the first lower dielectric layer 30a and the second lower circuit layer 38a. Next, at least one via 363 is formed extending through the second upper dielectric layer 36 using drilling technology or other suitable techniques, thereby exposing a portion of the second upper circuit layer 38. Simultaneously, at least one via 363a is formed extending through the second lower dielectric layer 36a using drilling technology or other suitable techniques, thereby exposing a portion of the second lower circuit layer 38a.

[0124] refer to Figure 26 The second upper circuit layer 38' is formed on the second upper dielectric layer 36, and the upper interconnect via 35 is formed in the via 363. At the same time, the second lower circuit layer 38a' is formed on the second lower dielectric layer 36a, and the lower interconnect via 35a is formed in the via 363a.

[0125] Simultaneously, a lower conductive structure 3 is formed, and dielectric layers (including a first upper dielectric layer 30, a second upper dielectric layer 36, a first lower dielectric layer 30a, and a second lower dielectric layer 36a) are cured. The lower conductive structure 3 can be a wafer structure, a strip structure, or a panel structure. Next, the electrical properties of the lower conductive structure 3 are tested (e.g., open circuit / short circuit).

[0126] refer to Figures 27 to 33 An upper conductive structure 2 is provided. The upper conductive structure 2 is manufactured as follows. (See reference...) Figure 27 A carrier 65 is provided. The carrier 65 can be a glass carrier and can be of wafer type, panel type, or strip type. Next, a release layer 66 is coated on the bottom surface of the carrier 65. Then, a conductive layer 67 (e.g., a seed layer) is formed or disposed on the release layer 66 by physical vapor deposition (PVD) or other suitable techniques.

[0127] refer to Figure 28 A second dielectric layer 26 is formed on the conductive layer 67 using a coating technique or other suitable technique. Then, at least one via 264 is formed to extend through the second dielectric layer 26 using an exposure and development technique or other suitable technique, thereby exposing a portion of the conductive layer 67.

[0128] refer to Figure 29 A seed layer 68 is formed on the bottom surface 262 of the second dielectric layer 26 and in the via 264 using PVD technology or other suitable techniques. Next, a photoresist layer 69 is formed on the seed layer 68. Then, the photoresist layer 69 is patterned to expose portions of the seed layer 68 using exposure and development techniques or other suitable techniques. The photoresist layer 69 defines a plurality of openings 691. At least one opening 691 of the photoresist layer 69 corresponds to and is aligned with the via 264 of the second dielectric layer 26.

[0129] refer to Figure 30 Conductive material 70 (e.g., metallic material) is placed in the opening 691 of the photoresist layer 69 and on the seed layer 68 by means of plating technology or other suitable technology.

[0130] refer to Figure 31 The photoresist layer 69 is removed by stripping techniques or other suitable techniques.

[0131] refer to Figure 32 The portion of the seed layer 68 not covered by the conductive material 70 is removed by etching or other suitable techniques. Simultaneously, a circuit layer 24 and at least one internal via 25 are formed.

[0132] refer to Figure 33 By repeating Figures 28 to 32In the next stage, multiple first dielectric layers 20 and multiple first circuit layers 24 are formed. Simultaneously, an upper conductive structure 2 is formed, and dielectric layers (including first dielectric layer 20 and second dielectric layer 26) are cured. Next, the electrical properties of the upper conductive structure 2 are tested (e.g., open circuit / short circuit).

[0133] refer to Figure 34 A first polymeric material 125' is formed or applied to the top surface 31 of the lower conductive structure 3 and covers the topmost circuit layer of the lower conductive structure 3 (e.g., the second upper circuit layer 38'). Due to the relatively high viscosity and small thickness of the first polymeric material 125', the top surface of the first polymeric material 125' is substantially conformal to the top surface 31 of the lower conductive structure 3 and the second upper circuit layer 38'. Therefore, the top surface of the first polymeric material 125' is not a smooth, flat surface.

[0134] refer to Figure 35 The second polymeric material 126' is formed or applied to the top surface of the first polymeric material 125'. Due to the relatively low viscosity of the second polymeric material 126', the top surface of the second polymeric material 126' is a generally smooth and flat surface.

[0135] refer to Figure 36 The upper conductive structure 2 is attached to the lower conductive structure 3 via a first polymeric material 125' and a second polymeric material 126'. Then, the first polymeric material 125' and the second polymeric material 126' are cured to form a first sublayer 125 and a second sublayer 126, respectively. Simultaneously, an intermediate layer 12 is formed. In some embodiments, the upper conductive structure 2 can be pressed onto the lower conductive structure 3. Therefore, the thickness of the intermediate layer 12 is determined by the gap between the upper conductive structure 2 and the lower conductive structure 3. Since the top surface of the second polymeric material 126' is a generally smooth, flat surface, the bonding quality between the upper conductive structure 2 and the lower conductive structure 3 is improved. Furthermore, the thickness of the intermediate layer 12 (i.e., the sum of the thicknesses of the first sublayer 125 and the second sublayer 126) can be reduced.

[0136] refer to Figure 37 Remove the carrier 65, release layer 66 and conductive layer 67 to expose a portion of the internal via 25.

[0137] refer to Figure 38 At least one via 23 is formed by drilling (e.g., laser drilling) to extend through at least a portion of the upper conductive structure 2 and the intermediate layer 12 to expose the circuit layer of the lower conductive structure 3 (e.g., a second upper circuit layer 38'). The via 23 gradually narrows downwards.

[0138] refer to Figure 39A metal layer 72 is formed on the surface 21 of the upper conductive structure 2 and in the through hole 23 by means of plating technology or other suitable technology, so as to form at least one upper through hole 14 in the through hole 23.

[0139] refer to Figure 40 A top photoresist layer 73 is formed or disposed on the metal layer 72, and a bottom photoresist layer 73a is formed or disposed on the bottom surface 32 of the lower conductive structure 3. Next, the top photoresist layer 73 is patterned using exposure and development techniques or other suitable techniques.

[0140] refer to Figure 41 The portion of metal layer 72 not covered by the top photoresist layer 73 is removed using etching or other suitable techniques. The portion of metal layer 72 covered by the top photoresist layer 73 is retained to form the second circuit layer 28. Next, the top photoresist layer 73 and the bottom photoresist layer 73a are removed using stripping or other suitable techniques to obtain... Figure 1 Wiring structure 1.

[0141] In some embodiments, semiconductor chip 42 ( Figure 11 The upper conductive structure 2 is electrically connected and bonded to the outer circuit layer 28 of the upper conductive structure 2 via multiple first connecting elements 44 (e.g., solder bumps or other conductive bumps). Then, the upper conductive structure 2, the intermediate layer 12, and the lower conductive structure 3 are simultaneously separated to form... Figure 11 The package structure 4 is shown. The package structure 4 includes a wiring structure 1h and a semiconductor chip 42. Then, the second lower circuit layer 38a' of the lower conductive structure 3h is electrically connected and bonded to the substrate 46 (e.g., motherboard, such as PCB) through a plurality of second connecting elements 48 (e.g., solder bumps or other conductive bumps).

[0142] Unless otherwise stated, spatial descriptions such as “above,” “below,” “up,” “left,” “right,” “lower,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “above,” “below,” “upper,” “above,” “below,” etc., indicate relative to the orientation shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, the limitation being that the advantage of the embodiments of this disclosure is not affected by such arrangement.

[0143] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples in which the event or situation clearly occurred and examples in which the event or situation is very close to occurring. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the first value is within a range of less than or equal to ±10% of the second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value can be considered "substantially" the same as or equal to the second value.

[0144] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, then the surface can be considered substantially flat.

[0145] As used herein, unless the context clearly indicates otherwise, the singular terms “a” and “the” may include multiple indicators.

[0146] As used herein, the terms "conductive" and "electrically conductive" refer to the ability to conduct electric current. Conductive materials are generally those that exhibit very little or no resistance to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials have a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of the material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.

[0147] Additionally, quantities, ratios, and other values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only values ​​explicitly specified as range limits, but also all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0148] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions for equivalents may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, the process reproduction in this disclosure may differ from actual equipment. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A wiring structure comprising: An upper conductive structure includes multiple dielectric layers, multiple circuit layers in contact with the multiple dielectric layers, multiple internal vias, and at least one reference mark, wherein the multiple internal vias gradually narrow upwards, and wherein the multiple dielectric layers of the upper conductive structure are transparent. The lower conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the plurality of dielectric layers, and at least one reference mark, wherein the reference mark of the upper conductive structure is aligned with the reference mark of the lower conductive structure; and An intermediate layer is disposed between the upper conductive structure and the lower conductive structure, and bonds the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure, wherein the intermediate layer is made of a transparent material, wherein the intermediate layer comprises a first sublayer formed of a first polymeric material and a second sublayer formed of a second polymeric material, the viscosity of the first polymeric material being greater than the viscosity of the second polymeric material, the first sublayer contacting the lower conductive structure and covering the topmost circuit layer of the lower conductive structure, the top surface of the first sublayer being substantially conformal to the topmost circuit layer of the lower conductive structure and the top surface of the lower conductive structure; and The upper via extends through the upper conductive structure and the middle layer, and is electrically connected to the topmost circuit layer of the lower conductive structure.

2. The wiring structure according to claim 1, wherein the line spacing of the circuit layer of the lower conductive structure is greater than the line spacing of the circuit layer of the upper conductive structure.

3. The wiring structure according to claim 1, wherein the lower conductive structure further includes a core portion, and the plurality of dielectric layers and the plurality of circuit layers of the lower conductive structure are adjacent to the surface of the core portion.

4. The wiring structure according to claim 1, wherein the upper conductive structure comprises a low-density region and a high-density region located between the low-density regions, wherein within the vertical projection range of the high-density region, there is no vertical conductive path between the upper conductive structure and the lower conductive structure.

5. The wiring structure according to claim 4, wherein the upper through-hole is disposed in the low-density area.

6. The wiring structure according to claim 5, wherein the high-density region is a chip bonding region.

7. The wiring structure according to claim 1, wherein the reference mark of the upper conductive structure and the bottommost circuit layer of the plurality of circuit layers of the upper conductive structure are on the same layer and are formed simultaneously.

8. The wiring structure according to claim 7, wherein the reference mark of the lower conductive structure and the topmost circuit layer of the lower conductive structure are on the same layer and are formed simultaneously.

9. The wiring structure according to claim 8, wherein the top surface of the first sub-layer has a highest point and a lowest point, and the height difference between the highest point and the lowest point is greater than 3 μm.

10. The wiring structure according to claim 8, wherein the top surface of the first sub-layer has a highest point and a lowest point, and the height difference between the highest point and the lowest point is greater than one-third of the thickness of the topmost circuit layer of the lower conductive structure.

11. The wiring structure according to claim 8, wherein the bottommost circuit layer of the upper conductive structure and the topmost circuit layer of the lower conductive structure are embedded in the intermediate layer.

12. The wiring structure according to claim 1, wherein the upper via terminates at the topmost circuit layer.

13. The wiring structure according to claim 12, wherein the upper through hole gradually narrows downwards.

14. The wiring structure of claim 13, wherein some of the plurality of internal vias of the upper conductive structure are disposed between two adjacent circuit layers in the upper circuit layer to electrically connect the two adjacent circuit layers, and other of the plurality of internal vias are exposed from the top surface of the upper conductive structure.

15. The wiring structure of claim 14, wherein the second circuit layer of the upper conductive structure is disposed on the top surface of the upper conductive structure and protrudes from the top surface, and includes a pad and traces electrically connected to the pad, wherein the upper via and the pad of the second circuit layer are integrally formed as a single piece.

16. The wiring structure of claim 15, wherein the traces of the second circuit layer of the upper conductive structure contact the exposed internal vias.

17. The wiring structure according to claim 16, wherein the upper conductive structure is a coreless substrate and the lower conductive structure is a core substrate.

18. The wiring structure according to claim 1, further comprising a lower via extending through the lower conductive structure and the intermediate layer, and electrically connected to the bottommost circuit layer of the upper conductive structure.

19. The wiring structure of claim 18, wherein the lower via terminates at the bottommost circuit layer of the upper conductive structure.

20. The wiring structure according to claim 19, wherein the lower through-hole gradually narrows upwards.

21. The wiring structure according to claim 20, wherein the top end of the lower through-hole and the bottom end of the upper through-hole horizontally overlap in the intermediate layer.

22. The wiring structure according to claim 1, wherein the lateral peripheral surface of the upper conductive structure is not coplanar with the lateral peripheral surface of the lower conductive structure.

23. A wiring structure comprising: The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer; An intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together, wherein the upper conductive structure is electrically connected to the lower conductive structure. The intermediate layer comprises a plurality of sublayers, the materials of which are different from the materials of the dielectric layers of the lower conductive structure and the dielectric layers of the upper conductive structure, and at least two of the sublayers are made of different materials from each other. and A through-hole extends through the upper conductive structure, the intermediate layer, and the lower conductive structure, wherein the through-hole has a uniform width.

24. The wiring structure of claim 23, wherein a boundary is formed between two adjacent sublayers, and the intermediate layer does not include horizontally extending circuit layers on the boundary.

25. The wiring structure of claim 23, wherein the intermediate layer comprises a first sublayer in contact with the lower conductive structure and a second sublayer in contact with the upper conductive structure, the bonding force between the first sublayer and the lower conductive structure being greater than the bonding force between the second sublayer and the upper conductive structure.

26. The wiring structure of claim 23, wherein the intermediate layer comprises a first sublayer in contact with the upper conductive structure and a second sublayer in contact with the lower conductive structure, the bonding force between the first sublayer and the upper conductive structure being greater than the bonding force between the second sublayer and the lower conductive structure.

27. The wiring structure of claim 23, wherein the intermediate layer comprises a first sub-layer in contact with the lower conductive structure, a third sub-layer in contact with the upper conductive structure, and a second sub-layer located between the first sub-layer and the third sub-layer, wherein the material of the first sub-layer is the same as the material of the third sub-layer and is different from the material of the second sub-layer.

28. The wiring structure of claim 23, wherein the through-hole is disposed in the low-density region of the upper conductive structure, wherein the through-hole extends through and contacts the bottommost circuit layer of the upper conductive structure, the topmost circuit layer of the lower conductive structure, and the bottommost circuit layer of the lower conductive structure.

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