Semiconductor device package and method of manufacturing the same

Abstract

A semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer, and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed on the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced apart from and electrically connected to the second conductive pillar.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device package and a method for manufacturing the same. More specifically, this disclosure relates to a semiconductor device package including conductive pillars and a method for manufacturing the same. Background Technology

[0002] Conductive pillars (e.g., copper pillars) are widely used for electrical connections in semiconductor device packages, and high conductivity pillars (e.g., height greater than 200 micrometers) are required in many applications. However, forming high conductivity pillars can present several challenges. For example, to protect the conductive pillars, molding compound can be formed to completely cover them, and a polishing process can be performed to remove a portion of the molding compound to expose the conductive pillars. However, the conductive pillars can be damaged during the manufacturing process.

[0003] Furthermore, in existing processes for manufacturing semiconductor device packages, a redistribution layer (RDL) is formed, conductive pillars and a die (or chip) are formed on the RDL, and then a molding compound is formed on the RDL to cover the conductive pillars and die. Therefore, if any step in the manufacturing process fails, the entire semiconductor device package will be considered a failure, even if the die itself is functional. This increases manufacturing costs and reduces yield. Summary of the Invention

[0004] In one or more embodiments, a semiconductor device package includes a conductive layer, a first conductive pillar, a circuit layer, and a second conductive pillar. The conductive layer has a first surface. The first conductive pillar is disposed on the first surface of the conductive layer. The circuit layer is disposed on the conductive layer. The circuit layer has a first surface facing the conductive layer. The second conductive pillar is disposed on the first surface of the circuit layer. The first conductive pillar is physically spaced from and electrically connected to the second conductive pillar.

[0005] In one or more embodiments, a semiconductor device package includes a circuit layer, an electronic component, a conductive element, and a package body. The circuit layer has a first surface and a second surface opposite to the first surface. The electronic component is disposed on the first surface of the circuit layer. The conductive element is disposed on the first surface of the circuit layer. The package body is disposed on the first surface of the circuit layer and covers the conductive element. The package body has a cavity for receiving the electronic component.

[0006] In one or more embodiments, a method of manufacturing a semiconductor device package includes: (a) providing a first structure having a conductive layer and a first conductive post disposed on the conductive layer; (b) providing a second structure having a circuit layer and a second conductive post disposed on the circuit layer; and (c) connecting the first conductive post and the second conductive post by conductive adhesive. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the features may not be drawn to scale, and the dimensions of the features may be increased or decreased arbitrarily for clarity of discussion.

[0008] Figure 1 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown;

[0009] Figure 2 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown;

[0010] Figure 3 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown;

[0011] Figure 4 A cross-sectional view of a semiconductor device package according to some embodiments of the present disclosure is shown;

[0012] Figure 5A , Figure 5B and Figure 5C The various stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are illustrated.

[0013] Figure 6A , Figure 6B , Figure 6C and Figure 6D The various stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are illustrated.

[0014] Figure 7A and Figure 7B The various stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are illustrated.

[0015] Figure 8A , Figure 8B , Figure 8C and Figure 8D This illustrates various stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure; and

[0016] Figure 9A , Figure 9B , Figure 9C and Figure 9D The various stages of a method for manufacturing a semiconductor device package according to some embodiments of the present disclosure are illustrated.

[0017] Common reference numerals are used throughout the accompanying drawings and detailed description to indicate the same or similar elements. This disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Detailed Implementation

[0018] The structure, manufacture, and use of embodiments of this disclosure are discussed in detail below. However, it should be understood that the embodiments illustrate multiple applicable concepts that can be embodied in various specific contexts. It should be understood that the following disclosure provides many different embodiments or instances of various features implementing the various embodiments. Specific examples of components and arrangements are described below for illustrative purposes. Of course, these are merely examples and are not intended to be limiting.

[0019] The embodiments or examples shown in the figures below are disclosed using specific languages. However, it will be understood that the embodiments or examples described are not intended to be limiting. As will be understood by those skilled in the art, any changes and modifications to the disclosed embodiments and any further application of the principles disclosed in this document are within the scope of this disclosure.

[0020] Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0021] Figure 1 A cross-sectional view of a semiconductor device package 1 according to some embodiments of the present disclosure is shown. The semiconductor device package 1 includes a carrier 10, electronic components 11, conductive pillars 12 and 13, connecting elements 14, a package body 15, a circuit layer 16, and electrical contacts 17.

[0022] The carrier 10 has a passivation layer 10p and a conductive layer 10r disposed on its surface 101. In some embodiments, the passivation layer 10p includes silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide, or hafnium oxide. The conductive layer is or contains a conductive material, such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or alloys thereof. A portion of the conductive layer 10r is covered by the passivation layer 10p, while another portion of the conductive layer 10r is exposed from the passivation layer 10p for electrical connection.

[0023] Electronic component 11 is disposed on surface 10p1 of passivation layer 10p. Electronic component 11 has an active surface away from carrier 10 and a back surface facing carrier 10. The back surface of electronic component 11 is attached to passivation layer 10p by adhesive layer 11d (e.g., die attach film (DAF), Ajinomoto deposited film (ABF), epoxy resin, sintering, etc.). One or more electrical contacts 11p (e.g., microbumps) are disposed on the active surface of electronic component 11. Electronic component 11 may be a chip or die, in which a semiconductor substrate, one or more integrated circuit devices, and one or more overlay interconnect structures are contained. Integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof.

[0024] Conductive pillar 12 is disposed on the surface 10p1 of passivation layer 10p. Conductive pillar 12 is electrically connected to conductive layer 10r exposed from passivation layer 10p. In some embodiments, conductive pillar 12 may contain Cu. However, other conductive materials, such as nickel (Ni) and / or Al, or combinations of various metals or other conductive materials, may also be used in conductive pillar 12. In some embodiments, the height of conductive pillar 12 is less than 200 micrometers.

[0025] In some embodiments, the conductive posts 12 have the same diameter. Alternatively, the conductive posts 12 may have different diameters. For example, the diameter of the conductive posts 12 farther from the electronic component 11 is larger than the diameter of the conductive posts 12 adjacent to the electronic component 11. For example, the diameter of the conductive posts 12 farther from the electronic component 11 is smaller than the diameter of the conductive posts 12 adjacent to the electronic component 11. In some embodiments, the surface 121 of each of the conductive posts 12 and the surface 11p1 of each of the electrical contacts 11p are substantially coplanar (or at the same level). For example, the distance between the surface 121 of each of the conductive posts 12 and the surface 10p1 of the passivation layer 10p is substantially the same as the distance between the surface 11p1 of each of the electrical contacts 11p and the surface 10p1 of the passivation layer 10p. In some embodiments, the spacing of the conductive posts 12 adjacent to the electronic component 11 is greater than the spacing of the conductive posts 12 farther from the electronic component 11.

[0026] Conductive posts 13 are disposed on the surface 121 of conductive posts 12. Conductive posts 13 are spaced apart from conductive posts 12. Conductive posts 13 are aligned with conductive posts 12 and electrically connected to conductive posts 12 via connecting elements 14. For example, each of the conductive posts 13 has a surface 131 facing the surface 121 of the corresponding conductive post 12, and the surface 131 of each of the conductive posts 13 is connected to the surface 121 of the corresponding conductive post 12 via the connecting element 14. In some embodiments, the connecting element 14 is or comprises a conductive material, such as solder, conductive paste, etc. In some embodiments, the surfaces 131 of the conductive posts 13 are substantially coplanar (or at the same level).

[0027] In some embodiments, the conductive posts 13 have the same diameter. Alternatively, the conductive posts 13 may have different diameters. In some embodiments, the diameter of the conductive post 13 is the same as the diameter of the corresponding conductive post 12 connected to the conductive post 13 (e.g., the two connected conductive posts have the same diameter). Alternatively, the conductive post 13 and the corresponding conductive post 12 connected to the conductive post 13 have different diameters. For example, the diameter of the conductive post 13 connected to the conductive post 12 with a relatively larger diameter is smaller than the diameter of the conductive post 13 connected to the conductive post 12 with a relatively smaller diameter. In some embodiments, the spacing of the conductive posts 13 adjacent to the center of the circuit layer 16 is greater than the spacing of the conductive posts 13 adjacent to the edge of the circuit layer 16.

[0028] An underfill 11u is disposed on the surface 10p1 of the passivation layer 10p. The underfill 11u covers or encapsulates the electronic component 11 and the conductive pillar 12. In some embodiments, a portion of the conductive pillar 12 is exposed from the underfill 10u for electrical connection. For example, the surface 121 of the conductive pillar 12 is exposed from the underfill 10u. For example, the surface 11u1 of the underfill 11u is substantially coplanar with the surface 121 of the conductive pillar 12. In some embodiments, the underfill 11u comprises epoxy resin, molding compound (e.g., epoxy molding compound or other molding compound), polyimide, phenolic compound or material, material containing silicone dispersed therein, or combinations thereof. In some embodiments, the underfill 11u does not contain a filler.

[0029] The encapsulation body 15 is disposed on the surface 10p1 of the passivation layer 10p. The encapsulation body 15 covers or encapsulates the underfill 11u and the conductive pillars 13. In some embodiments, the underfill 11u may be omitted, and the encapsulation body 15 directly covers or encapsulates the electronic component 11, the conductive pillars 12 and 13. In some embodiments, the encapsulation body 15 comprises epoxy resin, molding compound (e.g., epoxy molding compound or other molding compound), polyimide, phenolic compound or material, material having silicone dispersed therein, or a combination thereof, having a filler.

[0030] The circuit layer 16 (which may also be a carrier or substrate) includes an interconnect layer (e.g., a redistribution layer, RDL) 16r and a dielectric layer 16d. A portion of the interconnect layer 16r is covered or encapsulated by the dielectric layer 16d, while another portion of the interconnect layer 16r is exposed from the dielectric layer 16d to provide electrical connectivity. In some embodiments, the dielectric layer 16d may comprise molding compound, prepreg composite fiber (e.g., prepreg), borosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), and any combination thereof. Examples of molding compounds may include, but are not limited to, epoxy resin containing fillers dispersed therein. Examples of prepregs may include, but are not limited to, multilayer structures formed by stacking or laminating multiple prepreg materials / sheets. In some embodiments, any number of interconnect layers 16r may be present depending on design specifications. The circuit layer 16 includes a surface 161 on which the package body 15 is disposed and a surface 162 opposite to surface 161.

[0031] Electrical contacts 17 are disposed on surface 162 of circuit layer 16 and electrically connected to interconnect layer 16r to provide electrical connection between semiconductor device package 1 and other circuits or circuit boards. In some embodiments, electrical contacts 17 may be or include controlled collapse chip connection (C4) bumps, microbumps, solder balls or copper pillars.

[0032] Figure 2 A cross-sectional view of a semiconductor device package 2 according to some embodiments of the present disclosure is shown. The semiconductor device package 2 is similar to... Figure 1 Semiconductor device package 1 differs from semiconductor device package 2 in that it also includes RDL 11r. RDL 11r is disposed on the active surface of electronic component 11 to provide fan-out functionality for electronic component 11. In some embodiments, electronic component 11 may include thousands of pins (or terminals), so RDL 11r facilitates the connection between electronic component 11 and electrical contact 11p.

[0033] Figure 3 A cross-sectional view of a semiconductor device package 3 according to some embodiments of the present disclosure is shown. The semiconductor device package 3 is similar to... Figure 1 The semiconductor device packages 1 in the text are described below, and the differences between them are described below.

[0034] Electronic component 11 is disposed on surface 161 of circuit layer 16. The active surface of electronic component 11 faces circuit layer 16 and is electrically connected to circuit layer 16 (e.g., to interconnect layer 16r) via flip chip or other suitable technology. In some embodiments, such as Figure 2 The RDL 11r shown is Figure 3 (Not shown) can be placed between the active surface of electronic component 11 and electrical contact 11p.

[0035] The underfill 11u is disposed on the surface 161 of the circuit layer 16 and covers at least a portion of the electronic component 11 (e.g., an active surface) and the conductive pillars 13. The package body 15 covers the underfill 11u, a portion of the electronic component 11, and the conductive pillars 13 exposed from the underfill 11u and the conductive pillars 12. In some embodiments, the underfill 11u may be omitted, and the package body 15 directly covers the conductive pillars 12, 13 and the electronic component 11.

[0036] Figure 4 A cross-sectional view of a semiconductor device package 4 according to some embodiments of the present disclosure is shown. The semiconductor device package 4 is similar to... Figure 3 The semiconductor device packages in section 3 are described below, and the differences between them are described below.

[0037] The conductive post 13 and connecting element 14 are omitted, and the conductive post 12 is directly connected between the circuit layer 16 and the conductive layer 10r. For example, as... Figure 3 The connection between the circuit layer 16 and the conductive layer 10r shown can be achieved by two separate conductive posts (e.g., conductive posts 12 and 13) connected by connecting element 14, while... Figure 4In this embodiment, the connection between circuit layer 16 and conductive layer 10r is achieved through a single conductive post (e.g., conductive post 12). In other embodiments, conductive post 12 may be replaced by other connection structures, such as solder balls, Cu core balls, solder bumps, or other suitable connection structures.

[0038] The package body 15 includes a cavity 15c for accommodating the electronic component 11. In some embodiments, the cavity 15c may be filled with another package body. In some embodiments, the package body 15 and the package body filling the cavity 15c may contain the same or different materials, depending on different design requirements.

[0039] Figure 5A , Figure 5B and Figure 5C These are cross-sectional views of semiconductor structures manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure. In some embodiments, Figure 5A , Figure 5B and Figure 5C The operations shown can be used to manufacture Figure 1 It is part of the semiconductor device package. Alternatively, Figure 5A , Figure 5B and Figure 5C The operations shown can be used to manufacture other semiconductor device packages.

[0040] refer to Figure 5A A carrier 10 is provided. A passivation layer 10p is formed on the carrier 10. In some embodiments, the passivation layer 10p is patterned to form one or more openings 10o to expose the carrier 10.

[0041] refer to Figure 5B Conductive material is disposed or formed within the opening 10° to form a conductive pillar 12. In some embodiments, the conductive material may be formed by, for example, electroplating or any other suitable process. In some embodiments, the height of the conductive pillar 12 is less than 200 micrometers.

[0042] refer to Figure 5C Electronic component 11 is disposed on passivation layer 10p. In some embodiments, the back surface of electronic component 11 is attached to passivation layer 10p by, for example, an adhesive layer (e.g., DAF, ABF, epoxy resin, sintering, etc.).

[0043] Figure 6A , Figure 6B , Figure 6C and Figure 6D These are cross-sectional views of semiconductor structures manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure. In some embodiments, Figure 6A , Figure 6B , Figure 6C and Figure 6D The operations shown can be used to manufacture Figure 1 Semiconductor device package 1 in the middle. Alternatively, Figure 6A , Figure 6B , Figure 6C and Figure 6D The operations shown can be used to manufacture other semiconductor device packages.

[0044] refer to Figure 6A A carrier 59 is provided. A circuit layer 16 (including an interconnect layer and a dielectric layer covering a portion of the interconnect layer) is formed on the carrier 59. A conductive material is disposed or formed on the interconnect layer of the circuit layer 16 exposed from the dielectric layer to form conductive pillars 13. In some embodiments, the conductive material may be formed by, for example, electroplating or any other suitable process.

[0045] refer to Figure 6B Through, for example, flip-chip bonding or any other suitable technique, Figure 6A The structure shown is connected to Figure 5C The structure is shown in the diagram. For example, conductive post 13 is aligned with conductive post 12 and connected to conductive post 12 via connecting element 14. Then, a reflow process can be performed.

[0046] refer to Figure 6C A bottom filler 11u is formed to cover a portion of the electronic component 11 and the conductive pillar 12. Then, a package body 15 covering the bottom filler 11u and the conductive pillar 13 is formed by, for example, compression molding or other suitable molding techniques. In some embodiments, the formation of the bottom filler 11u may be omitted, and the package body 15 covering the electronic component 11, conductive pillars 12 and 13 may be formed directly between the passivation layer 10p and the circuit layer 16.

[0047] refer to Figure 6D The carrier 59 is removed from the circuit layer 16 to expose the circuit layer 16. Then, electrical contacts 17 are formed on the interconnect layer of the circuit layer 16 exposed from the dielectric layer to form, as shown in the diagram. Figure 1 The semiconductor device package 1 shown. In some embodiments, the electrical contacts 17 may be formed by a bumping process or any other suitable process.

[0048] according to Figures 5A-5CAs shown in embodiments 6A-6D, conductive pillars 12 and 13 are formed separately on different sides (e.g., conductive pillar 12 is formed on passivation layer 10p, and conductive pillar 13 is formed on circuit layer 16), and then connected by connection element 14 to define a high pillar. Therefore, it is not necessary to form a single high pillar in one process. Furthermore, since the package body 15 covering the electronic component 11 and the conductive pillars 12, 13 and / or the underfill 11u are formed after the conductive pillars 12 and 13 have been connected, it is not necessary to form a molding compound that completely covers the conductive pillars and then expose the conductive pillars by grinding away a portion of the molding compound. This eliminates or reduces the risk of damaging the conductive pillars during manufacturing and reduces the cost, time, and complexity of manufacturing the semiconductor device package 1.

[0049] In addition, because they are located in Figures 5A-5C and Figures 6A-6D The process shown separates the formation of the structure containing the electronic component 11 and the structure containing the circuit layer 16, which ensures that the structure containing the circuit layer 16 functions well before the two structures are connected. This improves the yield rate of manufacturing the semiconductor device package 1. In some embodiments, by employing Figures 5A-5C The operation shown in 6A-6D is used to manufacture semiconductor device package 1 with a yield of 99% or greater.

[0050] Figure 7A and Figure 7B These are cross-sectional views of semiconductor structures manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure. In some embodiments, Figure 7A and Figure 7B The operations shown can be used to manufacture Figure 3 It is part of the semiconductor device package. Alternatively, Figure 7A and Figure 7B The operations shown can be used to manufacture other semiconductor device packages.

[0051] Figure 7A and Figure 7B The operation shown is similar to Figure 6B The operation shown is different in that... Figure 7B In this process, an electronic component 11 is further disposed on the circuit layer 16. The active surface of the electronic component 11 faces the circuit layer 16 and is electrically connected to the circuit layer 16 by, for example, flip chip bonding or any other suitable process.

[0052] Figure 8A , Figure 8B , Figure 8C and Figure 8D These are cross-sectional views of semiconductor structures manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure. In some embodiments, Figure 8A , Figure 8B , Figure 8C and Figure 8D The operations shown can be used to manufacture Figure 3 Semiconductor device package 3 in the middle. Alternatively, Figure 8A , Figure 8B , Figure 8C and Figure 8D The operations shown can be used to manufacture other semiconductor device packages.

[0053] Figures 8A-8D The operation shown is similar to Figures 6A-6D The operations shown, and one of the main differences includes: in Figures 6A-6D middle, Figure 6A The structure shown is connected to Figure 5C The structure shown, while Figures 8A-8D middle, Figure 8A The structure shown is connected to Figure 7B The structure shown. Therefore, Figures 6A-6D The description and advantages of the operations shown are applicable to Figures 8A-8D .

[0054] Figure 9A , Figure 9B and Figure 9C These are cross-sectional views of semiconductor structures manufactured at various stages according to some embodiments of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure. In some embodiments, Figure 9A , Figure 9B and Figure 9C The operations shown can be used to manufacture Figure 4 Semiconductor device package 4 in the middle. Alternatively, Figure 9A , Figure 9B and Figure 9C The operations shown can be used to manufacture other semiconductor device packages.

[0055] refer to Figure 9A A carrier 10 is provided. A passivation layer 10p is formed on the carrier 10. In some embodiments, the passivation layer 10p is patterned to form one or more openings to expose the carrier 10. A conductive material is disposed or formed within the openings to form conductive pillars 12. In some embodiments, the conductive material can be formed by, for example, electroplating or any other suitable process. In some embodiments, the height of the conductive pillars 12 is equal to or greater than 200 micrometers.

[0056] refer to Figure 9BA package body 15 covering the conductive pillars 12 is formed on the passivation layer 10p. In some embodiments, the package body 15 is formed by, for example, compression molding, transfer molding, or any other suitable process. A portion of the conductive pillars 12 (e.g., the top surface of the conductive pillars 12) is exposed from the package body 15 for electrical connection.

[0057] Cavity 15c is then formed. In some embodiments, cavity 15c does not penetrate package body 15. For example, package body 15 may form the bottom surface of cavity 15c. In other embodiments, cavity 15c may penetrate package body 15. For example, passivation layer 10p forms the bottom surface of cavity 15c. In some embodiments, cavity 15c may be formed by selective molding. In some embodiments, cavity 15c may be formed by drilling or etching.

[0058] refer to Figure 9C This provides a structure with a circuit layer 16 on which electronic components 11 are mounted. This allows for operation without forming conductive pillars 13 and connecting elements 14. Figure 7B The operation in the process forms the structure described above. Then, with the electronic component 11 located within cavity 15c, it is placed on circuit layer 16. Figure 9B The structure within the package body 15. A portion of the conductive pillar 12 exposed from the package body 15 is electrically connected to the circuit layer 16.

[0059] refer to Figure 9D The carrier 79 is removed from the circuit layer 16 to expose the circuit layer 16. Then, electrical contacts 17 are formed on the interconnect layer of the circuit layer 16 exposed from the dielectric layer to form, as shown... Figure 4 The semiconductor device package 4 shown. In some embodiments, the electrical contacts 17 may be formed by a bumping process or any other suitable process.

[0060] Furthermore, by forming the structure containing the electronic component 11 and the structure containing the conductive pillar 12 separately, it is ensured that the structure containing the conductive pillar 12 functions well before the two structures are connected. This will improve the yield rate of manufacturing the semiconductor device package 4.

[0061] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms can refer to examples of events or situations that occurred precisely or very approximately. For example, when used in conjunction with numerical values, the terms can refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two numerical values ​​can be considered “substantially” or “about” the same or equal. For example, "essentially parallel" can refer to an angle variation of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "essentially perpendicular" can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0062] If the displacement between two surfaces does not exceed 5 µm, 2 µm, 1 µm, or 0.5 µm, the two surfaces may be considered coplanar or substantially coplanar.

[0063] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to conduct electric current. Conductive materials are generally those that exhibit little or no reaction to the flow of electric current. One measure of conductivity is Siemens per meter (S / m). Typically, conductive materials are those with a conductivity greater than approximately 10. 4 S / m (e.g., at least 10) 5 S / m or at least 10 6 A material with an electrical conductivity of (S / m). The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.

[0064] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural indicators. In the description of some embodiments, the phrase “on” or “above” another component may cover situations where the preceding component is directly on the following component (e.g., in physical contact with the following component), and situations where one or more intermediate components are located between the preceding and following components.

[0065] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes may be made and equivalent components may be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. There may be differences between artistic representations in this disclosure and actual devices due to factors such as variables in the manufacturing process. Other embodiments of this disclosure may exist that are not specifically shown. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A semiconductor device package comprising: A conductive layer having a first surface; A first conductive post is disposed on the first surface of the conductive layer; A circuit layer disposed on the conductive layer, the circuit layer having a first surface facing the conductive layer; The second conductive post is disposed on the first surface of the circuit layer. The first conductive post is physically separated from the second conductive post and is electrically connected to the second conductive post; A first conductive adhesive connects the first conductive post to the second conductive post; A third conductive post is disposed on the first surface of the conductive layer; A fourth conductive post is disposed on the first surface of the circuit layer; and A second conductive adhesive connects the third conductive post to the fourth conductive post, wherein the diameter of the third conductive post is different from the diameter of the first conductive post and / or the diameter of the fourth conductive post is different from the diameter of the second conductive post.

2. The semiconductor device package according to claim 1, wherein... The first conductive post has a first surface facing the circuit layer; The second conductive post has a first surface facing the first conductive post and aligned with the first surface of the first conductive post; and The first conductive adhesive connects the first surface of the first conductive post to the first surface of the second conductive post.

3. The semiconductor device package of claim 1, further comprising an electronic component disposed on the first surface of the conductive layer, wherein the electronic component has an active surface facing the circuit layer.

4. The semiconductor device package of claim 3, further comprising a conductive element disposed on the active surface of the electronic component, wherein the surface of the conductive element facing the circuit layer is substantially coplanar with the surface of the first conductive pillar facing the circuit layer.

5. The semiconductor device package of claim 4, further comprising a redistribution layer disposed between the active surface of the electronic component and the conductive element.

6. The semiconductor device package of claim 5, further comprising a fifth conductive post disposed on the first surface of the circuit layer, wherein the fifth conductive post is connected to the conductive element by a third conductive adhesive.

7. The semiconductor device package according to claim 4, further comprising: A bottom filler that covers the electronic components and the first conductive pillar; as well as The encapsulation body covers the bottom filler, the second conductive post, and the first conductive adhesive.

8. The semiconductor device package of claim 7, wherein the surface of the bottom filler facing the circuit layer is substantially coplanar with the surface of the conductive element and the surface of the first conductive pillar.

9. The semiconductor device package of claim 4, further comprising a package body covering the electronic component, the first conductive post, the second conductive post and the first conductive adhesive.

10. The semiconductor device package of claim 1, further comprising an electronic component disposed on the first surface of the circuit layer, wherein the electronic component has an active surface facing the circuit layer and electrically connected to the circuit layer.

11. The semiconductor device package of claim 10, further comprising: A bottom filler that covers the electronic components and the second conductive pillar; as well as The encapsulation body covers the bottom filler, the first conductive post, and the first conductive adhesive.

12. The semiconductor device package of claim 10, further comprising a package body covering the electronic component, the first conductive post, the second conductive post and the first conductive adhesive.

13. A method for manufacturing a semiconductor device package, comprising: (a) A first structure having a conductive layer and a first conductive post and a third conductive post disposed on the conductive layer; (b) A second structure having a circuit layer and a second conductive pillar and a fourth conductive pillar disposed on the circuit layer; as well as (c) Connecting the first conductive post to the second conductive post by a first conductive adhesive; and connecting the third conductive post to the fourth conductive post by a second conductive adhesive, wherein the diameter of the third conductive post is different from the diameter of the first conductive post and / or the diameter of the fourth conductive post is different from the diameter of the second conductive post.

14. The method of claim 13, wherein The first conductive post has a first surface facing the circuit layer; The second conductive post has a first surface facing the first conductive post and aligned with the first surface of the first conductive post; and The first conductive adhesive connects the first surface of the first conductive post to the first surface of the second conductive post.

15. The method of claim 13, wherein operation (c) is performed using flip-chip technology.

16. The method of claim 13, wherein operation (a) further comprises attaching the back surface of the electronic component to the conductive layer.

17. The method of claim 16, wherein the second structure further comprises a fifth conductive post disposed on the circuit layer and electrically connected to the active surface of the electronic component.

18. The method of claim 17, further comprising: A bottom filler is formed to cover the electronic components and the first conductive pillar; as well as An encapsulation body is formed between the first structure and the second structure, covering the bottom filler, the second conductive post, and the first conductive adhesive.

19. The method of claim 17, further comprising forming an encapsulation body covering the electronic component, the first conductive post, the second conductive post, and the first conductive adhesive between the first structure and the second structure.

20. The method of claim 13, wherein operation (b) further comprises connecting an active surface of an electronic component to the circuit layer.

21. The method of claim 20, further comprising: A bottom filler is formed to cover the electronic components and the second conductive pillar; as well as An encapsulation body is formed between the first structure and the second structure, covering the bottom filler, the first conductive post, and the first conductive adhesive.

22. The method of claim 20, further comprising forming an encapsulation body covering the electronic component, the first conductive post, the second conductive post, and the first conductive adhesive between the first structure and the second structure.

Images