Semiconductor package structure

Abstract

A semiconductor package structure includes an organic substrate having a first surface, a first recess recessed from the first surface, a first chip over the first surface and covering the first recess, thereby defining a first cavity enclosed by a back surface of the first chip and the first recess, and a second chip over the first chip. The first cavity is an air cavity or a vacuum cavity.

Description

Technical Field

[0001] This disclosure relates to a semiconductor packaging structure, and more specifically, to a semiconductor packaging structure having an oscillator chip. Background Technology

[0002] A crystal oscillator comprises a crystal cell consisting of a quartz crystal blank (which is hermetically sealed in a container) and an oscillation circuit using the crystal cell. Crystal oscillators are used as a frequency and time reference source in various electronic devices. One type of such crystal oscillator is the oven-controlled crystal oscillator (OCXO), which maintains a constant operating temperature for the crystal cell. Because the operating temperature of the crystal cell is maintained stable regardless of the ambient temperature, the OCXO provides high frequency stability and minimal frequency deviation. For example, such OCXOs are used in communication facilities, such as base stations. Summary of the Invention

[0003] In some embodiments, this disclosure provides a semiconductor package structure comprising: an organic substrate having a first surface; a first recess recessed from the first surface; a first chip situated above the first surface and covering the first recess, thereby defining a first cavity enclosed by the rear surface of the first chip and the first recess; and a second chip situated above the first chip. The first cavity is an air cavity or a vacuum cavity.

[0004] In some embodiments, this disclosure provides a semiconductor package structure comprising: an organic substrate having a first surface; a first chip located above the first surface and connected to the first surface via a spacer pattern, thereby defining a first cavity enclosed by a rear surface of the first chip, the spacer pattern, and the first surface of the organic substrate; and a second chip located above the first chip. The first cavity is an air cavity or a vacuum cavity.

[0005] In some embodiments, this disclosure provides a semiconductor package structure comprising: a substrate having a first surface; a control chip located above the first surface, the control chip having a heat source region adjacent to an active surface of the control chip; an oscillator chip located above the control chip and thermally conductive with the heat source region; and a thermal delay region located below a passive surface of the control chip and overlapping a vertically projected region of the heat source region. The thermal delay region is defined by the passive surface of the control chip and the first surface of the substrate. Attached Figure Description

[0006] The aspects of this disclosure will be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present disclosure.

[0008] Figure 2 A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present disclosure.

[0009] Figure 3 A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present disclosure.

[0010] Figure 4A and Figure 4B This describes the orientation alignment of a cavity with a semiconductor chip from a top view perspective according to some embodiments of this disclosure.

[0011] Figure 5 A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present disclosure.

[0012] Figure 6 A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present disclosure.

[0013] Figure 7A and Figure 7B Each describes, from a top view perspective, the stacked structure of multiple cavities, semiconductor chips, and / or bonding layers in multiple cavities according to some embodiments of the present disclosure.

[0014] Figure 8A A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present disclosure.

[0015] Figure 8B Explanation based on this disclosure Figure 8A The embodiments in the text show the stacked structure of multiple cavities, spacing patterns, and semiconductor chips from a top-view perspective.

[0016] Figure 9A A top view illustrating a semiconductor wafer having multiple bare die regions according to some embodiments of the present disclosure.

[0017] Figure 9B This illustration depicts a patterned design from a top view perspective, according to some embodiments of the present disclosure. Figure 9A One of several nude areas in the image.

[0018] Figure 9C This illustration depicts a patterned design from a cross-sectional view perspective, according to some embodiments of the present disclosure. Figure 9A One of several nude areas in the image.

[0019] Figure 10A A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present disclosure.

[0020] Figure 10B Explanation based on this disclosure Figure 10A The embodiments in the text show the stacked structure of multiple cavities, spacing patterns, and semiconductor chips from a top-view perspective.

[0021] Figure 11A A top view illustrating a semiconductor wafer having multiple bare die regions according to some embodiments of the present disclosure.

[0022] Figure 11B This illustration depicts a patterned design from a top view perspective, according to some embodiments of the present disclosure. Figure 11A One of several nude areas in the image.

[0023] Figure 11C This illustration depicts a patterned design from a cross-sectional view perspective, according to some embodiments of the present disclosure. Figure 11A One of several nude areas in the image.

[0024] Figure 12A A cross-sectional view illustrating a semiconductor package structure according to some embodiments of the present disclosure.

[0025] Figure 12B Explanation based on this disclosure Figure 12A The embodiments in the paper show the spacing pattern and the stacked structure of semiconductor chips from a top view perspective. Detailed Implementation

[0026] Common reference numerals are used throughout the drawings and detailed embodiments to indicate the same or similar components. Embodiments of this disclosure will be readily understood from the following detailed description, taken in conjunction with the accompanying drawings.

[0027] For the orientation of components as shown in the associated diagrams, spatial descriptions are specified with respect to a particular component or group of components, or a plane of a component or group of components, such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual implementations of the structures described herein can be arranged in space in any orientation or manner, provided that the advantages of the embodiments of this disclosure are not deviated from by such arrangement.

[0028] To maintain the crystal cells in an OCXO at a constant temperature, a thermostat is typically used. With the continuous miniaturization of communication devices, smaller OCXOs are needed. OCXOs with microelectromechanical systems (MEMS) oscillators employ complex stacked structures or high-cost materials to enhance temperature control capabilities. For example, the MEMS oscillator and oscillation circuitry can be packaged on a ceramic cavity substrate and hermetically sealed with a cap. This is because ceramics are considered to have high thermal conductivity, for example, greater than 15 W·m. -1 ·K -1 (alumina) or greater than 150 W·m -1 ·K -1 (Aluminum nitride), therefore will have, for example, about 1 W·m -1 ·K -1 An insulating layer with low thermal conductivity (glass) is inserted to separate the MEMS oscillator and oscillation circuitry from the ceramic cavity substrate in order to maintain the crystal cells in the OCXO at a constant temperature. However, the implementation of the ceramic cavity substrate and the additional insulating layer increases manufacturing costs.

[0029] Furthermore, the thermal conductivity of the insulating layer (e.g., glass) is still insufficient to effectively prevent heat loss from the crystal oscillator and oscillation circuit, necessitating the provision of more power to maintain the crystal oscillator and oscillation circuit at a constant temperature.

[0030] This disclosure uses an air cavity or vacuum cavity as a heat conduction retardation zone to prevent heat loss from the crystal oscillator and oscillation circuit. This is because air has a thermal conductivity of approximately 0.026 W·m, substantially lower than that of insulating materials such as glass. -1 ·K -1 The thermal conductivity of the vacuum is lower than that of air, thus effectively reducing heat loss from the crystal oscillator and oscillation circuit. In another aspect of this disclosure, an organic substrate for packaging crystal oscillators and oscillation circuits is provided. The polymer composition of the organic substrate has a thermal conductivity (<1 W·m) lower than that of the ceramic substrate. -1 ·K -1 Furthermore, it is more cost-effective than ceramic cavity substrates and additional insulating layers such as glass. For example, substrates primarily composed of molding materials have a thickness of approximately 0.8 to 1 W·m⁻². -1 ·K -1 The thermal conductivity of the polyimide substrate is approximately 0.1 to 0.2 W·m. -1 ·K -1 The thermal conductivity of the FR-4 substrate is approximately 0.3 W·m. -1 ·K -1 The thermal conductivity of the liquid crystal polymer (LCP) substrate is approximately 0.3 to 0.5 W·m.-1 ·K -1 The thermal conductivity of the solder resist layer on the organic substrate is approximately 0.2 to 0.3 W·m. -1 ·K -1 Thermal conductivity. The combination of an organic substrate and an air cavity not only reduces manufacturing costs but also reduces power consumption in maintaining the crystal oscillator and oscillation circuitry at a constant temperature.

[0031] refer to Figure 1 , Figure 1 The illustration shows a cross-sectional view of a semiconductor package structure 10 according to some embodiments of the present disclosure. The semiconductor package structure 10 includes a substrate 100, such as, but not limited to, an organic substrate comprising, but not limited to, a molding material-based substrate, a polyimide substrate, an FR-4 substrate, a liquid crystal polymer (LCP) substrate, a core substrate, a coreless substrate, or other substrates composed of small organic molecules or polymers. In some embodiments, the polymer composition of the organic substrate has a content of less than about 1 W·m⁻². -1 ·K -1 Thermal conductivity. In some embodiments, the substrate 100 has a first surface 1001 and a recess 1001R recessed from the first surface 1001. Figure 1 Taking the core substrate described herein as an example, substrate 100 includes a core layer 100A, a dielectric layer 100C, and a patterned circuit layer 100B on each of the upper and lower surfaces of the core layer 100A. The polymer composition of the organic substrate includes at least the dielectric layer 100C. The first surface 1001 of substrate 100 may be made of a polymeric material and therefore has a surface area of ​​less than about 1 W·m. -1 ·K -1 Thermal conductivity. The recess 1001R is formed from the first surface 1001 of the substrate 100 by removing a portion of the dielectric layer 100C and a portion of the patterned circuit layer 100B near the first surface 1001.

[0032] A first chip 101 is disposed above a first surface 1001 and covers a recess 1001R. The first chip 101 has a front surface 101A or an active surface facing away from the first surface 1001, and a rear surface 101B or a passive surface facing the first surface 1001. The first chip 101 further includes, for example, control circuitry adjacent to the front surface 101A, configured to control a second chip 102 stacked above the first chip 101. In some embodiments, the first chip 101 further includes a heat source region 101H adjacent to the front surface 101A of the first chip 101. The heat source region 101H may include a resistor pattern exposed from the front surface 101A and prepared to conduct heat to an object with suitable electrical properties in physical contact with it.

[0033] In some embodiments, cavity 103 is defined by the rear surface 101B of the first chip 101 and the first recess 103. A bonding layer 101', such as a die attachment film (DAF), may be positioned at the rear surface 101B of the first chip 101 and further define the boundary of cavity 103. Specifically, cavity 103 is enclosed by dielectric sidewalls (e.g., sidewalls of dielectric layer 100C exposed to cavity 103), conductive sidewalls (e.g., sidewalls of patterned circuit layer 100B exposed to cavity 103), and the upper surface of core layer 100A exposed to cavity 103. In some embodiments, dielectric layer 100C may cover the sidewalls of patterned circuit layer 100B adjacent to cavity 103, and thus cavity 103 may be enclosed only by dielectric sidewalls even though the portion of patterned circuit layer 100B below the projection of the first chip 101 is removed. In some embodiments, the heat source region 101H of the first chip 101 is vertically aligned with the cavity 103 and the second chip 102. The heat source region 101H is configured to conduct heat to the second chip 102, and the cavity 103 acts as a thermal delay region to prevent heat loss from the first chip 101 and the second chip 102. Specifically, the cavity 103 or the thermal delay region overlaps with the vertically projected region of the heat source region 101H to effectively prevent heat loss from the heat source region 101H by thermal conduction. In some embodiments, the cavity 103 may have a thickness from about 30 μm to about 40 μm, depending on the thickness of the dielectric layer 100C and the patterned circuit layer 100B of the substrate 100.

[0034] The second chip 102 is stacked above the front surface 101A of the first chip 101. For example, the second chip is electrically coupled to the first chip 101 via conductive line 111A, and the first chip 101 is electrically coupled to the substrate 100 via conductive line 111B. Other electrical connections, such as vias, conductive pillars, or solder joints, may be applied to electrically connect the first chip 101, the second chip 102, and the substrate 100. In some embodiments, a bonding layer 102' is applied above the rear surface 102B or a passive surface of the second chip 102. The bonding layer 102' may be thin enough to allow effective thermal conduction between the heat source region 101H and the second chip 102. The bonding layer 102' may also be made of a material with high thermal conductivity. For example, the bonding layer 102' may be thinner than the bonding layer 101', and the thermal conductivity of the bonding layer 102' may be greater than that of the bonding layer 101'.

[0035] Electrical connections connect the front surface 102A or active surface of the second chip 102 to the front surface 101A or active surface of the first chip 101. In some embodiments, the first chip 101 is a control chip having circuitry for controlling the second chip 102. For example, the first chip 101 is a CMOS chip. In some embodiments, the second chip 102 is a microelectromechanical system (MEMS) oscillator chip that can be controlled by the control chip below. In some embodiments, the first chip 101 is configured to maintain a constant temperature of the second chip 102 via a heat source region 101H.

[0036] The semiconductor package structure 10 further includes a cap 108 on the substrate 100, which covers the first chip 101, the second chip 102, and the cavity 103. The space defined by the cap 108, the first chip 101, and the second chip 102 is another cavity 109. In some embodiments, the cavity 109 and the cavity 103 are discrete from each other. In some embodiments, the cavity 109 is connected to the cavity 103, as shown in the figure below. Figure 4A and Figure 4B This is explained in the text.

[0037] Figure 2 This illustration shows a cross-sectional view of a semiconductor package structure 20 according to some embodiments of the present disclosure. The semiconductor package structure 20 is similar to the semiconductor package structure 10, except that the patterned circuit layer 100B is not removed from the upper surface of the core layer 100A to form... Figure 2 Outside of cavity 103. In other words, cavity 103 may have a conductive bottom and dielectric sidewalls.

[0038] Figure 3 A cross-sectional view of a semiconductor package structure 30 according to some embodiments of the present disclosure is shown. The semiconductor package structure 30 is similar to the semiconductor package structure 10, except that the bonding layer 101' only contacts the periphery of the bottom surface 101B of the first chip 101. In some embodiments, the bonding layer 101' located at the periphery of the bottom surface 101B of the first chip 101 may be made of epoxy resin. Because the thermal conductivity of epoxy resin is higher than that of air or vacuum, in some embodiments, the bonding layer 101' is avoided from being positioned below the vertical projection of the heat source region 101H. Figure 3 As shown, the bonding layer 101' can form a continuous or discrete pattern on the periphery of the first chip 101 to connect the first chip 101 to the substrate 100.

[0039] Figure 4A and Figure 4B This illustration shows the orientation alignment of a cavity with a semiconductor chip from a top view perspective, according to some embodiments of this disclosure. Figure 4AIn this configuration, the cavity 103 and the first chip 101 may have substantially the same shape, but the first chip 101 may be rotated approximately 45° relative to the cavity 103. Only the four corners of the first chip 101 are in contact with the dielectric layer 100C of the substrate 100. Figure 4B In this process, the cavity 103 and the first chip 101 may have different shapes, for example, the cavity may be quadrilateral or square. Only two sides of the first chip 101 are in contact with the dielectric layer 100C of the substrate 100. Figure 4A Cavity 103 and Figure 4B The cavity 103 appears to be an open cavity where cavity 103 and cavity 109 are connected, as shown in the image. Figure 1 As explained, the first chip 101 does not completely cover the opening of the recess 1001R. In some embodiments, the area of ​​the first chip 101 is smaller than the area of ​​the cavity 103 to allow for perforation between the cavity 103 and the cavity 109. After high-temperature operation (e.g., reflow operation), the air in the cavities 103 and 109 is interconnected to prevent overpressure when using a closed cavity. Severe overpressure can cause the first chip 101 and / or the second chip 102 to detach from the substrate 100.

[0040] Figure 5 A cross-sectional view of a semiconductor package structure 50 according to some embodiments of the present disclosure is shown. The semiconductor package structure 50 is similar to the semiconductor package structure 10, except that, in addition to the first recess 1001R, a second recess 2001R is also recessed from the first surface 1001 of the substrate 100. As... Figure 5 As shown, the second recess 2001R surrounds the first recess 1001R. In some embodiments, the first chip 101 covers the first recess 1001R and may or may not cover the entire width of the second recess 2001R. A cavity 105 is formed between the rear surface 101B of the first chip 101 and the second recess 2001R. Figure 5 In this configuration, bonding layer 101' fills the second cavity 105 and is configured to bond the first chip 101 to the substrate 100. In some embodiments, depending on the amount of bonding material used, excess bonding layer 101' may be observed at the first surface 1001 of the substrate 100. In some embodiments, the second cavity 105 may be presented as a closed trench for accommodating bonding material, thereby preventing bonding material from overflowing from the first surface 1001 of the substrate 100.

[0041] Figure 6 This illustration shows a cross-sectional view of a semiconductor package structure 60 according to some embodiments of the present disclosure. The semiconductor package structure 60 is similar to the semiconductor package structure 50, except that the patterned circuit layer 100B is not removed from the upper surface of the core layer 100A to form... Figure 6In addition to cavity 103. In other words, cavity 103 may have a conductive bottom and dielectric sidewalls, and cavity 105 may have a conductive bottom and dielectric sidewalls.

[0042] Figure 7A and Figure 7B Each describes, from a top view perspective, the stacked structure of multiple cavities, semiconductor chips, and / or bonding layers in multiple cavities according to some embodiments of this disclosure. References Figure 5 And in Figure 7A In this embodiment, substrate 100 includes a first cavity 103 and a second cavity 105 at its first surface 1001. The second cavity 105 forms a closed trench surrounding the first cavity 103. A first chip 101, illustrated in dashed lines, is stacked over the first cavity 103 and partially stacked over the second cavity 105. A bonding layer 101' may be continuously patterned to fill the second cavity 105, the continuous pattern being configured to connect the first chip 101 to the dielectric layer 100C of substrate 100. (Reference) Figure 5 And in Figure 7B In this embodiment, substrate 100 includes a first cavity 103 and a second cavity 105 at its first surface 1001. The second cavity 105 forms a closed trench surrounding the first cavity 103. A first chip 101, illustrated in dashed lines, is stacked above the first cavity 103 and partially stacked above the second cavity 105. From a top view perspective, bonding layer 101' may be discretely patterned, for example, filling the second cavity 105 at the four corners of the second cavity 105, the discrete pattern being configured to connect the first chip 101 to the dielectric layer 100C of substrate 100. In some embodiments, bonding layer 101' may be... Figure 7A and Figure 7B Other patterns not illustrated herein may be filled in the second cavity 105, provided that the bonding strength between the first chip 101 and the dielectric layer 100C of the substrate 100 is sufficient to withstand subsequent operations and perform the desired device functions. For example... Figure 7A and Figure 7B As explained, the first cavity 103 can be a closed cavity, while the second cavity 105 can be an open cavity. The open cavity is perforated using cavity 109, such as... Figure 5 and Figure 6 As explained in the text.

[0043] Figure 8AA cross-sectional view of a semiconductor package structure 80 according to some embodiments of the present disclosure is illustrated. The semiconductor package structure 80 includes a substrate 100. In some embodiments, the substrate 100 includes an organic substrate. A first chip 101 is disposed over a first surface 1001 and covers a first recess 1001R. The first chip 101 is connected to the first surface 1001 of the substrate 100 via a spacer pattern 107. In some embodiments, the spacer pattern 107 is positioned at the periphery of the first chip 101. A cavity 103' is formed between the rear surface 101B of the first chip 101, the spacer pattern 107, and the first surface 1001 of the substrate 100. Figure 8A As shown, the first surface 1001 of the substrate 100 can be the top surface of the dielectric layer 100C or the top surface of the core layer 100A, depending on the location indicated by the substrate 100. For example, the cavity 103' is defined by the back surface 101B of the first chip 101, the spacer pattern 107, and the top surface of the core layer 100A. As previously discussed, the cavity 103' can be an air cavity or a vacuum cavity.

[0044] The semiconductor package structure 80 further includes a second recess 2001R surrounding the first recess 1001R. A spacer pattern is located on a first surface 1001 of the substrate 100 adjacent to the first recess 1001R and the second recess 2001R. In some embodiments, a bonding layer 101' is disposed near the spacer pattern 107, which is configured to connect the first chip 101 and the spacer pattern 107 to the substrate 100. In some embodiments, the spacer pattern 107 is made of a permanent photoresist, such as SU-8. In some embodiments, the spacer pattern 107 is patterned on the back surface 101B of the first chip 101 during wafer-level operations, as shown in the figure. Figure 9A , Figure 9B and Figure 9C As discussed in [the document]. The use of the spacer pattern 107 allows for greater design freedom in separating the rear surface 101B of the first chip 101 from the first surface 1001 of the substrate 100. In some embodiments, the spacer pattern 107 may have a height from about 100 μm to about 200 μm.

[0045] Figure 8B Explanation based on this disclosure Figure 8A The embodiments shown in the image depict the stacked structure of multiple cavities, spacing patterns, and semiconductor chips from a top-view perspective. (See reference...) Figure 8A and Figure 8BThe substrate 100 includes a first cavity 103' and a second cavity 105' at its first surface 1001. The second cavity 105' forms a closed trench surrounding the first cavity 103'. A first chip 101, illustrated in dashed lines, is stacked above the first cavity 103' and partially stacked above the second cavity 105'. The spacing pattern 107 between the first chip 101 and the dielectric layer 100C of the substrate 100 may have, for example, discrete patterns at the four corners near the periphery of the first chip 101. Although Figure 8B Not shown in the figure, but the bonding layer 101' can surround the discrete interval pattern 107.

[0046] Figure 9A The illustration shows a top view of a semiconductor wafer having a plurality of die regions 901 according to some embodiments of the present disclosure. Since the patterning layer 107 can be formed during wafer-level processing, discrete patterns of the patterning layer 107 can be formed in each of the die regions 901 prior to the die sawing operation. Figure 9C The cross-sectional view along the bare area 901 of AA' shows a discretely spaced pattern with the desired aspect ratio.

[0047] Figure 10A This illustration shows a cross-sectional view of a semiconductor package structure 1000 according to some embodiments of the present disclosure. The semiconductor package structure 1000 is similar to the semiconductor package structure 80, except that, from a top view perspective, the spacing pattern 107 is a double-C-shaped pattern surrounding the first cavity 103', as shown... Figure 10B As explained in the document. (Reference) Figure 10A and Figure 10B The substrate 100 includes a first cavity 103' and a second cavity 105' at its first surface 1001. The second cavity 105' forms a closed trench surrounding the first cavity 103'. A first chip 101, illustrated in dashed lines, is stacked over the first cavity 103' and partially stacked over the second cavity 105'. The spacing pattern 107 between the first chip 101 and the dielectric layer 100C of the substrate 100 may have a discrete pattern, such as a double-C pattern. Although Figure 10B Not shown in the figure, but the bonding layer 101' can surround the discrete interval pattern 107.

[0048] Figure 11A The illustration shows a top view of a semiconductor wafer having a plurality of die regions 1101 according to some embodiments of the present disclosure. Since the patterning layer 107 can be formed during wafer-level processing, discrete patterns of the patterning layer 107 can be formed in each of the die regions 1101 prior to the die sawing operation. Figure 11C The cross-sectional view along the bare area 1101 of BB' shows a discretely spaced pattern with the desired aspect ratio.

[0049] Figure 12AThe illustration shows a cross-sectional view of a semiconductor package structure 1200 according to some embodiments of the present disclosure. The semiconductor package structure 1200 is similar to the semiconductor package structure 80, except that, from a top view perspective, the spacing pattern 107 is a closed-loop pattern surrounding the first cavity 103', as shown... Figure 12B As explained in the description. In addition, no recess is formed on the first surface 1001 of the substrate 100. Therefore, the cavity 103' is defined by the rear surface 101B of the first chip 101, the spacer pattern 107 and the dielectric layer 100C of the substrate 100.

[0050] refer to Figure 12A and Figure 12B The substrate 100 includes a first cavity 103' at its first surface 1001. A first chip 101, illustrated in dashed lines, is stacked above the first cavity 103'. The spacing pattern 107 between the first chip 101 and the dielectric layer 100C of the substrate 100 has a continuous pattern, such as a closed quadrilateral shape pattern. Although... Figure 12B Not shown in the figure, but the bonding layer 101' can surround the continuously spaced pattern 107.

[0051] As used herein and unless otherwise defined, the terms “substantially,” “substantially,” “approximately,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may cover situations where the event or situation occurs precisely or very close to occurring. For example, when used in conjunction with numerical values, the terms may cover a range of variation less than or equal to ±10% of the stated value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” may refer to two surfaces that lie within a micrometer along the same plane, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm along the same plane.

[0052] Unless the context clearly specifies otherwise, the singular terms “a” and “described” as used herein may include multiple indicators. In the description of some embodiments, a component positioned “on” or “above” another component may encompass a situation where the preceding component is directly on the following component (e.g., in physical contact with the following component) and a situation where one or more intervening components are located between the preceding and following components.

[0053] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in this disclosure and actual equipment. Other embodiments of this disclosure may exist that are not specifically described. This specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt specific circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, the order and grouping of operations are not limiting unless specifically indicated herein.

Claims

1. A semiconductor package structure comprising: An organic substrate having a first surface; A first recess, which is recessed from the first surface; A first chip is located above the first surface and covers the first recess, thereby defining a first cavity enclosed by the rear surface of the first chip and the first recess, wherein the first cavity is an air cavity or a vacuum cavity. as well as A second chip is positioned above the first chip, wherein the first cavity and the second chip are vertically aligned with the heat source area of ​​the first chip.

2. The semiconductor packaging structure according to claim 1, further comprising a bonding layer between the rear surface of the first chip and the first surface of the organic substrate.

3. The semiconductor packaging structure according to claim 1, wherein the first chip is a control chip and the second chip is a microelectromechanical system (MEMS) oscillator chip.

4. The semiconductor packaging structure according to claim 1, wherein the first cavity is an open cavity.

5. The semiconductor packaging structure of claim 1, further comprising a second recess recessed from the first surface of the organic substrate, the first chip at least partially covering the second recess, thereby forming a second cavity enclosed by the rear surface of the first chip and the second recess.

6. The semiconductor packaging structure according to claim 5, further comprising a bonding layer filling the second cavity.

7. The semiconductor packaging structure according to claim 5, further comprising a bonding layer between the rear surface of the first chip and the first surface of the organic substrate.

8. The semiconductor packaging structure according to claim 5, wherein the second cavity surrounds the first cavity.

9. The semiconductor packaging structure according to claim 1, wherein the thermal conductivity of the first surface of the organic substrate is less than 1 W·m. -1 ·K -1 .

10. A semiconductor package structure comprising: An organic substrate having a first surface; A first chip is located above the first surface and connected to the first surface via a spacer pattern, thereby defining a first cavity enclosed by the rear surface of the first chip, the spacer pattern, and the first surface of the organic substrate, wherein the first cavity is an air cavity or a vacuum cavity. The second chip is located above the first chip; as well as A bonding layer is formed on the first surface of the organic substrate and surrounds the spacing pattern.

11. The semiconductor packaging structure according to claim 10, wherein the first chip is a control chip and the second chip is a microelectromechanical system (MEMS) oscillator chip.

12. The semiconductor packaging structure of claim 10, further comprising a cap on the organic substrate, the cap covering the first chip and the second chip, thereby defining a second cavity connected to the first cavity.

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