Semiconductor device package

Abstract

A semiconductor device package includes a carrier, a first interposer, and a second interposer. The second interposer is stacked on the first interposer, and the first interposer is mounted to the carrier. The combination of the first interposer and the second interposer is substantially T-shaped.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device package, specifically a semiconductor device package having two stacked interposer layers. Background Technology

[0002] To meet the trend towards smaller sizes, semiconductor packaging should make efficient use of its package size to pack as many components as possible. Interposers serve as interconnects between two carriers. However, common interposers occupy a significant amount of space in the semiconductor package, reducing the number of components that can be packaged within it. Summary of the Invention

[0003] According to an exemplary embodiment of this disclosure, a semiconductor device package includes: a carrier having a first surface; a first interposer disposed on the first surface of the carrier; and a second interposer stacked on the first interposer. The second interposer has a second surface and a third surface, the second surface facing the first surface of the carrier and the third surface opposite the second surface. The second interposer includes a plurality of first pads and a plurality of second pads adjacent to the second surface and the plurality of second pads adjacent to the third surface. Further, the spacing between two adjacent second pads is greater than the spacing between two adjacent first pads.

[0004] According to another exemplary embodiment of this disclosure, a semiconductor device package includes: a carrier having a first surface; a first interposer disposed on the first surface of the carrier; and a second interposer stacked on the first interposer. Specifically, a second interposer is stacked only on a first interposer. Further, the cross-sectional width of the second interposer is smaller than the cross-sectional width of the carrier.

[0005] To further understand this disclosure, the following embodiments and descriptions are provided to facilitate understanding of this disclosure; however, the accompanying drawings are provided for reference and illustration only and are not intended to limit the scope of this disclosure. Attached Figure Description

[0006] Figure 1A This is a top view of a semiconductor device package according to an embodiment of the present disclosure.

[0007] Figure 1B Showing along Figure 1A The cross-sectional view of line II in the diagram.

[0008] Figure 2A , Figure 2B , Figure 2C and Figure 2D , Figure 2E , Figure 2F and Figure 2G A method for manufacturing two intermediary layers according to embodiments of the present disclosure is shown.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H A method for manufacturing a semiconductor device package according to another embodiment of the present disclosure is shown.

[0010] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F and Figure 4G A method for manufacturing a semiconductor device package according to another embodiment of the present disclosure is shown.

[0011] Figure 4H yes Figure 4G The enlarged view of part "A" shown in the image.

[0012] Figure 5A , Figure 5B , Figure 5C and Figure 5D A method for manufacturing a semiconductor device package according to another embodiment of the present disclosure is shown.

[0013] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F and Figure 6G A method for manufacturing a semiconductor device package according to another embodiment of the present disclosure is shown. Detailed Implementation

[0014] The above illustrations and the following detailed description are exemplary for the purpose of further explaining the scope of this disclosure. Other objects and advantages relating to this disclosure will be shown in the following description and drawings.

[0015] Unless otherwise stated, spatial descriptions such as “above,” “below,” “upward,” “left,” “right,” “downward,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “above,” and “below” are indications of the orientation shown in the accompanying drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes, and actual embodiments of the structures described herein can be arranged in space in any orientation or manner, provided that such arrangement does not depart from the advantages of the embodiments of this disclosure.

[0016] Figure 1A A top view of a semiconductor device package 1 according to an embodiment of the present disclosure is shown. (See reference...) Figure 1A The semiconductor device package 1 may include a carrier 11. The carrier 11 may be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate. In some embodiments, the carrier 11 may be a single-layer substrate or a multi-layer substrate. A plurality of components 131, 132, 133, 134, and 135 are mounted on the carrier 11. Further, a plurality of lower interposers 12 may be mounted on the carrier 11, and a plurality of upper interposers 14 may be stacked on the lower interposers 12 respectively. Specifically, one upper interposer 14 may be stacked on only one lower interposer 12. The materials of the lower interposers 12 and the upper interposers 14 may be the same as the material of the carrier 11. An upper encapsulation material 13 may be disposed on the carrier 11 and may cover the carrier 11, components 131, 132, 133, 134, and 135, lower interposers 12, and upper interposers 14. The pads 145 of the upper interposers are exposed. Encapsulating materials include epoxy resins (containing fillers), molding materials (e.g., epoxy resin molding materials or other molding materials), polyimides, phenolic materials or materials, materials containing silicone resins dispersed therein, or combinations thereof.

[0017] Figure 1B Showing along Figure 1A Sectional view of line II in the diagram. (Reference) Figure 1B The semiconductor device package 1 may include a carrier 11, and components 131, 132, 133, 134, 135, and 136 may be mounted on the upper surface 111 of the carrier 11. A lower interposer 12 may be mounted on the upper surface 111 of the carrier, and upper interposers 14 may be stacked on the lower interposer 12. An upper encapsulating material 13 may be disposed on the upper surface 111 of the carrier 11 and may cover the upper surface 111 of the carrier 11, components 131, 132, 133, 134, 135, and 136, and the sides 148 and 149 of the lower interposer 12 and the upper interposer 14. (See reference) Figure 1BThe cross-sectional width of the upper interposer layer 14 can be greater than the cross-sectional width of the lower interposer layer 12. That is, the upper interposer layer 14 can have two opposing sides 148 and 149, and the lower interposer layer 12 can have two opposing sides 128 and 129. The distance between sides 148 and 149 of the upper interposer layer 14 is greater than the distance between sides 128 and 129 of the lower interposer layer 12. Furthermore, the cross-sectional width of the upper interposer layer 14 can be smaller than the cross-sectional width of the carrier 11. Additionally, the lower interposer layer 12 may include a conductive via 120 having an hourglass-shaped cross-section.

[0018] Additionally, the lower intermediary layer 12 may have a side surface 127, which may be substantially aligned with the side surface 147 of the upper intermediary layer 14. Further, the lower intermediary layer 72 may have two opposing sides 728 and 729, and the upper intermediary layer may have two opposing sides 748 and 749. The sides 728 and 729 of the lower intermediary layer 72 may be aligned with the sides 748 and 749 of the upper intermediary layer 74, respectively.

[0019] The upper interposer layer 14 may have a lower surface 141 and an upper surface 142, the lower surface facing the upper surface 111 of the carrier 11, and the upper surface opposite the lower surface 141. A plurality of pads 143 may be formed substantially in the lower portion of the upper interposer layer 14 and adjacent to the lower surface 141. A plurality of pads 145 may be formed substantially in the upper portion of the upper interposer layer 14 and adjacent to the upper surface 142. The spacing between two adjacent pads 145 may be 0.6 mm, and the spacing between two adjacent pads 143 may be 0.35 mm. Therefore, the spacing between two adjacent pads 145 may be greater than the spacing between two adjacent pads 143. That is, the distribution density of pads 143 is greater than the distribution density of pads 145. Therefore, the pads 145 of the upper interposer layer can be used to connect another component with a larger connector. Further, the upper interposer layer 14 may include a redistribution layer, and thus the pads 143 and 145 can be electrically connected to each other. The lower interposer layer 12 may have an upper surface 121 and a lower surface 122, the upper surface facing the lower surface 141 of the second interposer layer 14, and the lower surface facing the upper surface 111 of the carrier 11. A plurality of pads 123 may be formed substantially in the upper portion of the lower interposer layer 12 and adjacent to the upper surface 121. The spacing between two adjacent pads 123 of the lower interposer layer 12 may be substantially equal to the spacing between two adjacent pads 143 of the upper interposer layer 14. Therefore, when the upper interposer layer 14 is stacked on the lower interposer layer 12, the pads 123 of the lower interposer layer 12 can be connected to the pads 143 of the upper interposer layer 14. Figure 1BAs shown, the pads 123 of the lower interposer layer 12 can be connected to the pads 143 of the upper interposer layer 14 using solder balls 18. Furthermore, a plurality of pads 124 can be formed substantially at the lower portion of the lower interposer layer 12 and adjacent to the lower surface 122. A plurality of pads 115 can be formed adjacent to the upper surface 111 of the carrier 11. The spacing between two adjacent pads 124 of the lower interposer layer 12 can be substantially equal to the spacing between two adjacent pads 115 of the carrier 11. Therefore, when the upper interposer layer 14 is mounted to the carrier 11, the pads 124 of the lower interposer layer 12 can be connected to the pads 115 of the carrier 11. Figure 1B As shown, the pads 124 of the lower interposer layer 12 can be connected to the pads 115 of the carrier 11 using solder balls 19. Additionally, the lower interposer layer 12 may also include a redistribution layer. Therefore, the spacing between two adjacent pads 123 can be different from the spacing between two adjacent pads 124.

[0020] refer to Figure 1B The combination of the lower interposer 12 and the upper interposer 14 can be substantially T-shaped. Therefore, there may be space between the lower interposer 12 and the upper interposer 14. That is, there may be space below the upper interposer 14, which can accommodate a component or a portion of a component. Therefore, a component or a portion of a component can be arranged in said space and / or below the upper interposer 14. Thus, the semiconductor device package 1 can have more space to accommodate more components. Figure 1B As shown, a portion of component 131 and a portion of component 132 can be arranged below the upper intermediary layer 14. Components 135 and 136 can be arranged entirely below the upper intermediary layer 14. Additionally, component 134, whose height is greater than the height of the lower intermediary layer 12, cannot be arranged below the lower intermediary layer 12.

[0021] Additionally, the carrier may include a lower surface 112 opposite to the upper surface 111. A plurality of components 151, 152, 153, 154, 155, and 156 are mounted on the lower surface 112 of the carrier 11. A lower encapsulating material 15 may be placed on the lower surface 112 of the carrier 11, and may cover the lower surface 112 of the carrier 11 and the components 151, 152, 153, 154, 155, and 156.

[0022] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G A method for manufacturing an upper intermediary layer 24 and a lower intermediary layer 22 according to an embodiment of the present disclosure is shown.

[0023] refer to Figure 2A The substrate 220 may include a plurality of pads 223 and 224. The substrate 220 may include a redistribution layer, and therefore the pads 223 and 224 may be electrically connected to each other. That is, the spacing between two adjacent pads 223 may be different from the spacing between two adjacent pads 224.

[0024] refer to Figure 2B Solder balls 29 can be placed on pads 224 of substrate 220 respectively.

[0025] refer to Figure 2C The substrate 220 can be cut into many segments by sawing. One of these segments will be used as the lower interposer layer 22.

[0026] refer to Figure 2D The substrate 240 may include a plurality of pads 243 and 245. The substrate 240 may include a redistribution layer, and therefore the pads 243 and 245 may be electrically connected to each other. That is, the spacing between two adjacent pads 245 may be different from the spacing between two adjacent pads 243. Specifically, the spacing between two adjacent pads 245 may be greater than the spacing between two adjacent pads 243.

[0027] refer to Figure 2E Solder balls 28 can be placed on pads 243 of substrate 240 respectively.

[0028] refer to Figure 2F The substrate 240 can be cut into many segments by sawing. One of these segments will be used as the upper interposer layer 24.

[0029] refer to Figure 2G A lower interposer layer 22 can be disposed on the upper surface 211 of the carrier 21. Solder balls 29 can be attached to the pads 215 of the carrier 21. An upper interposer layer 24 can be stacked on the lower interposer layer 22 by a flux impregnation process. Solder balls 28 can be attached to the pads 223 of the lower interposer layer 22. After the lower interposer layer 22 has been disposed on the carrier 21 and the upper interposer layer 24 has been stacked on the lower interposer layer 22, the carrier 21, the lower interposer layer 22, and the upper interposer layer 24 can be cured (e.g., by heating or reflowing) so that the lower interposer layer 22 and the upper interposer layer 24 can be mounted onto the carrier 21. In addition, the height of the lower interposer layer 22 can be 0.62 mm, and the height of the upper interposer layer 24 can be 0.16 mm. Furthermore, the cross-sectional width of the upper interposer layer 24 can be greater than the cross-sectional width of the lower interposer layer 22. Therefore, the combination of the lower interposer layer 22 and the upper interposer layer 24 can be substantially T-shaped. In addition, the cross-sectional width of the upper intermediate layer 24 can be smaller than the cross-sectional width of the carrier 21.

[0030] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H A method for manufacturing a semiconductor device package 3 according to another embodiment of the present disclosure is shown.

[0031] refer to Figure 3A Components 351, 352, and 353 can be mounted on the surface 312 of the substrate 310. Specifically, components 351, 352, and 353 can be mounted onto the substrate 310 using SMT (Surface Mount Technology) technology.

[0032] refer to Figure 3B The substrate 310 can be inverted. Then, components 331, 332, and 333 can be mounted on the surface 311 of the substrate 310. Upper interposers 34 can be stacked on lower interposers 32, and the lower interposers 32 can be mounted on the surface 311 of the substrate 310. Specifically, components 331, 332, and 333, as well as the lower interposer 32, can be mounted onto the substrate 310 using an SMT process. Further, as... Figure 3B As shown, an upper interposer layer 34 can be stacked on top of a lower interposer layer 32, and the cross-sectional width of the upper interposer layer 34 can be greater than the cross-sectional width of the lower interposer layer 32. Therefore, the combination of the lower interposer layer 32 and the upper interposer layer 34 can be substantially T-shaped. Additionally, components 331 and 333 are partially arranged below the upper interposer layer 34. Furthermore, the cross-sectional width of the upper interposer layer 34 can be smaller than the cross-sectional width of the carrier 31.

[0033] refer to Figure 3C A cutting machine (not shown) cuts the substrate 310 to form two separate carriers 31.

[0034] refer to Figure 3D The carrier 31 can be inverted and placed on the tape 37 so that the surface 342 of the upper intermediate layer 34 can be attached to the tape 37.

[0035] refer to Figure 3E An encapsulating material 33 can be formed to encapsulate the entire carrier 31, components 331, 332, 333, 351, 352, 353, the lower interposer layer 32, and the side surfaces of the upper interposer layer 34. Since the surface 342 of the upper interposer layer 34 is attached to the tape 37, surface 342 may not be encapsulated by the encapsulating material 33. Furthermore, since the encapsulating material 33 encapsulates the entire carrier 31, the sides of the carrier 31 can be covered by the encapsulating material 33.

[0036] refer to Figure 3F Remove the tape 37 from the surface 342 of the upper interlayer 34, and expose the surface 342 of the upper interlayer 34.

[0037] refer to Figure 3G A cutting machine (not shown) cuts the encapsulating material 33. Thus, as... Figure 3H What is shown is the formation of a semiconductor device package 3.

[0038] refer to Figure 3H The surface 342 of the second interposer 34 is exposed. Furthermore, since the surface 342 of the upper interposer 34 can partially sink into the tape 37 when the tape 37 is attached to the surface 342, the surface 342 of the upper interposer 34 can be higher than the portion of the surface 338 of the encapsulating material adjacent to the surface 342 of the upper interposer 34. Additionally, as... Figure 3H As shown, the sides of the carrier 31 are encapsulated by the encapsulating material 33. In another embodiment, at least one side of one of the sides of the carrier may be exposed from the encapsulating material 33.

[0039] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F and Figure 4G A method for manufacturing a semiconductor device package 4 according to another embodiment of the present disclosure is shown.

[0040] refer to Figure 4A Components 451, 452, 453, and 454 can be mounted on the surface 412 of the carrier 41. Specifically, components 451, 452, and 453 can be mounted onto the carrier 41 using an SMT (Surface Mount Technology) process.

[0041] refer to Figure 4B An encapsulating material 45 can be formed on the surface 412 of the carrier 41, and can cover the surface 412 of the carrier 41 and components 451, 452, 453 and 454.

[0042] refer to Figure 4C The carrier 41 can be inverted. Then, components 431, 432, and 433 can be placed on the surface 411 of the carrier 41. Further, upper interposer layers 44 can be stacked on lower interposer layers 42, and the lower interposer layer 42 can be placed on the surface 411 of the carrier 41. Specifically, components 431, 432, and 433, as well as the lower interposer layer 42, can be mounted to the carrier 41 using an SMT process. Further, as... Figure 4CAs shown, an upper interposer layer 44 can be stacked on top of a lower interposer layer 42, and the cross-sectional width of the upper interposer layer 44 can be greater than the cross-sectional width of the lower interposer layer 42. Therefore, the combination of the lower interposer layer 42 and the upper interposer layer 44 can be substantially T-shaped. Additionally, component 432 is arranged below the upper interposer layer 44. Furthermore, the cross-sectional width of the upper interposer layer 44 can be smaller than the cross-sectional width of the carrier 41.

[0043] refer to Figure 4D Adhesive 47 is applied to the surface 442 of the upper intermediate layer 44 to form a removable / sacrificial layer.

[0044] refer to Figure 4E Encapsulating material 43 can be placed on the surface 411 of carrier 41 and can cover the surface 411 of carrier 41, components 431, 432 and 433, lower intermediary layer 42, upper intermediary layer 44 and adhesive 47.

[0045] refer to Figure 4F A portion of the encapsulating material 43 is removed using a laser process, exposing a portion of the adhesive 47. Since a portion of the encapsulating material 43 is removed by the laser process, a laser groove 439 can be formed on the encapsulating material 43. Specifically, the laser groove 439 can extend from the upper surface 438 of the encapsulating material 43 to the adhesive 47. Therefore, a portion of the adhesive 47 can be exposed.

[0046] refer to Figure 4G The adhesive 47 can be removed by physical or chemical methods (such as a water washing process). Furthermore, a portion of the encapsulating material 43 attached to the adhesive 37 is also removed (e.g., removed simultaneously with the removal of the adhesive 47). After removing the adhesive 47 and the portion of the encapsulating material 43 attached to the adhesive 47, a semiconductor device package 4 is formed. Additionally, since the portion of the encapsulating material 43 attached to the adhesive 47 has been removed, the encapsulating material 43 can have a cavity 437 on its upper surface 438. Furthermore, since the adhesive 47 has been removed, the surface 442 of the upper interposer 44 and the gasket 445 disposed at the upper portion of the upper interposer 44 and adjacent to the surface 442 can be exposed. That is, the surface 442 of the upper interposer 44 and the gasket 445 can be exposed and disposed within the cavity 437.

[0047] Figure 4H yes Figure 4G The enlarged view of part "A" shown in the image. Figure 4H As shown, the distance D1 between the two opposite side surfaces of cavity 437 can be greater than the distance D2 between the two opposite side surfaces of the upper intermediate layer 44. (Reference) Figure 4FA portion of the encapsulating material 43 is removed using a laser process. To expose the entire surface 442 of the upper interposer layer 44 after removing the adhesive 47 and the portion of the encapsulating material 43 attached to the adhesive 47, a laser groove 339 can be formed adjacent to the outer periphery of the upper interposer layer 44. Therefore, after removing the adhesive 47 and the portion of the encapsulating material 43 attached to the adhesive 47 and forming the cavity 437, the distance D1 between the two opposite side surfaces of the cavity 437 can be greater than the distance D2 between the two opposite side surfaces of the upper interposer layer 44.

[0048] Additionally, the upper interposer 44 may have an insulating layer 446 in its upper portion. Furthermore, the upper interposer 44 may also have a plurality of pads 445 in its upper portion, and these pads 445 may be exposed.

[0049] Figure 5A , Figure 5B , Figure 5C and Figure 5D A method for manufacturing a semiconductor device package 5 according to another embodiment of the present disclosure is shown.

[0050] refer to Figure 5A Components 551, 552, and 553 can be mounted on the surface 512 of the carrier 51. Specifically, components 551, 552, and 553 can be mounted onto the carrier 51 using an SMT (Surface Mount Technology) process.

[0051] refer to Figure 5B An encapsulating material 55 can be formed on the surface 512 of the carrier 51, and can cover the surface 512 of the carrier 51 and components 551, 552, and 553.

[0052] refer to Figure 5C The carrier 51 can be inverted. Then, components 531, 532, and 533 can be placed on the surface 511 of the carrier 51. Upper interposers 54 can be stacked on lower interposers 52, and the lower interposer can be placed on the surface 511 of the carrier 51. Specifically, components 531, 532, and 533, along with the lower interposer 52, can be mounted to the carrier 51 using an SMT process. Further, as... Figure 5C As shown, an upper interposer layer 54 can be stacked on top of a lower interposer layer 52, and the cross-sectional width of the upper interposer layer 54 can be greater than the cross-sectional width of the lower interposer layer 52. Therefore, the combination of the lower interposer layer 52 and the upper interposer layer 54 can be substantially T-shaped. Additionally, component 532 is arranged below the upper interposer layer 54. Furthermore, the cross-sectional width of the upper interposer layer 54 can be smaller than the cross-sectional width of the carrier 51.

[0053] refer to Figure 5DAn encapsulating material 53 can be placed on the surface 511 of the carrier 51, and can cover the surface 511 of the carrier 51, the components 531, 532, 533, the lower interposer 52, and the sides of the upper interposer 54. Specifically, the encapsulating material 53 can be formed by a thin-film molding process. Thus, a semiconductor device package 5 is formed.

[0054] like Figure 5D As shown, the upper interposer layer 54 may have a plurality of pads 545 in its upper portion. That is, the pads 545 may be adjacent to the upper surface 542 of the upper interposer layer 54 and may be exposed.

[0055] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F and Figure 6G A method for manufacturing a semiconductor device package 6 according to another embodiment of the present disclosure is shown.

[0056] refer to Figure 6A Components 651, 652, 653, and 654 can be mounted on the surface 612 of the carrier 61. Specifically, components 651, 652, 653, and 654 can be mounted onto the carrier 61 using an SMT (Surface Mount Technology) process.

[0057] refer to Figure 6B Encapsulation material 65 can be placed on the surface 612 of the carrier 61 and can cover the surface 612 of the carrier 61 and components 651, 652, 653 and 654.

[0058] refer to Figure 6C The carrier 61 can be inverted. Then, components 631, 632, and 633 can be placed on the surface 611 of the carrier 61. Upper interposers 64 can be stacked on lower interposers 62, and the lower interposer can be placed on the surface 611 of the carrier 61. Specifically, components 631, 632, and 633, along with the lower interposer 62, can be mounted to the carrier 61 using an SMT process. Further, as... Figure 6C As shown, an upper interposer layer 64 can be stacked on top of a lower interposer layer 62, and the cross-sectional width of the upper interposer layer 64 can be greater than the cross-sectional width of the lower interposer layer 62. Therefore, the combination of the lower interposer layer 62 and the upper interposer layer 64 can be substantially T-shaped. Additionally, component 632 is arranged below the upper interposer layer 64. Furthermore, the cross-sectional width of the upper interposer layer 64 can be smaller than the cross-sectional width of the carrier 61.

[0059] refer to Figure 6DEncapsulating material 63 can be placed on the surface 611 of carrier 61 and can cover the surface 611 of carrier 61, components 631, 632 and 633, lower interposer 62 and upper interposer 64. The upper interposer 64 may have multiple pads 645 in its upper portion. That is, the pads 645 may be adjacent to the upper surface 642 of the upper interposer 64. Encapsulating material 63 may also cover the pads 645 and the upper surface 642 of the upper interposer 64.

[0060] refer to Figure 6E A portion of the encapsulating material 63 is removed by laser drilling. After removing the portion of the encapsulating material 63, the encapsulating material 63 may have a cavity 637, and the gasket 645 may be exposed (e.g., Figure 6F (As shown).

[0061] refer to Figure 6G A conductive layer 639 can be arranged within the cavity 637 and formed on the pad 645. This forms a semiconductor device package 6.

[0062] In this disclosure, the formation or positioning of the first feature on or over the second feature may include embodiments in which the first and second features are formed or arranged in direct contact, and may also include embodiments in which an additional feature may be formed or arranged between the first and second features such that the first and second features are not in direct contact.

[0063] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation was close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%.

[0064] For example, "basically parallel" can refer to an angle range of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "basically perpendicular" can refer to an angle range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0065] If the displacement between two surfaces is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the two surfaces can be considered coplanar or substantially coplanar. If the displacement between the highest and lowest points of a surface is no greater than 5 μm, 2 μm, 1 μm, or 0.5 μm, the surface can be considered substantially flat.

[0066] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural referents.

[0067] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is used for convenience and brevity, and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0068] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and substitutions may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. Illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the process reproduction in this disclosure and actual apparatus. Other embodiments of this disclosure may exist that are not specifically shown. The specification and drawings should be considered illustrative rather than limiting. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. A semiconductor device package comprising: The carrier has a first surface; A first intermediary layer is disposed on the first surface of the carrier; A second interposer layer is stacked on top of a first interposer layer, wherein the cross-sectional width of the second interposer layer is greater than the cross-sectional width of the first interposer layer, and one second interposer layer is stacked on only one first interposer layer; and A first component is disposed on the first surface of the carrier, and at least a portion of the first component is disposed beneath the second interposer layer, wherein the second interposer layer has a second surface and a third surface, the second surface facing the first surface of the carrier and the third surface opposite the second surface, and wherein the second interposer layer includes a plurality of first pads and a plurality of second pads, the plurality of first pads being adjacent to the second surface and the plurality of second pads being adjacent to the third surface, and wherein the spacing between two adjacent second pads is greater than the spacing between two adjacent first pads.

2. The semiconductor device package of claim 1, further comprising a first encapsulating material encapsulating the first surface of the carrier, the first interposer, and the sides of the second interposer, wherein the first encapsulating material includes at least one cavity, and wherein the second liner is disposed within the cavity and exposed.

3. The semiconductor device package of claim 2, wherein the first component at least partially overlaps with the cavity in the vertical direction.

4. The semiconductor device package of claim 2, further comprising an insulating layer disposed within the cavity, wherein the second pad is exposed.

5. The semiconductor device package according to claim 2, wherein the cross-sectional width of the cavity is greater than the cross-sectional width of the second interposer.

6. The semiconductor device package of claim 2, wherein the carrier has a fourth surface opposite to the first surface, and a second encapsulating material encapsulates the fourth surface of the carrier, wherein the first surface of the carrier has a first portion not encapsulated by the first encapsulating material, and the fourth surface of the carrier has a second portion not encapsulated by the second encapsulating material, wherein the first portion and the second portion are configured asymmetrically.

7. The semiconductor device package of claim 6, wherein the second interposer layer at least partially overlaps the second portion in the vertical direction.

8. The semiconductor device package of claim 7, wherein the first interposer layer at least partially overlaps with the side of the second encapsulant in the vertical direction.

9. The semiconductor device package of claim 1, wherein the spacing between two adjacent second pads is 0.6 mm and the spacing between two adjacent first pads is 0.35 mm.

10. The semiconductor device package of claim 1, wherein the first interposer includes a conductive via having an hourglass-shaped cross-section.

11. The semiconductor device package of claim 1, further comprising an encapsulating material encapsulating the first surface of the carrier, the sides of the first interposer and the second interposer, at least one side of the carrier, a fourth surface of the carrier opposite to the first surface, and components disposed on the fourth surface.

12. A semiconductor device package comprising: The carrier has a first surface; A first stacked structure, the first stacked structure being disposed on the first surface of the carrier and comprising: A first interposer layer, wherein the first interposer layer is disposed on the first surface of the carrier; and A second interposer layer is stacked on top of a first interposer layer, wherein one second interposer layer is stacked on only one first interposer layer; and the distance between two opposite sides of the second interposer layer is greater than the distance between two opposite sides of the first interposer layer; and A first component, the first component being disposed on the first surface of the carrier, wherein at least a portion of the first component is disposed beneath the second interposer layer; The cross-sectional width of the second intermediary layer is smaller than the cross-sectional width of the carrier.

13. The semiconductor device package of claim 12, further comprising a second stacking structure, the first stacking structure being disposed on the first surface of the carrier and comprising: A third intermediary layer is disposed on the first surface of the carrier; as well as A fourth interposer layer is stacked on top of a third interposer layer, wherein one fourth interposer layer is stacked on only one third interposer layer; and the distance between two opposite sides of the fourth interposer layer is greater than the distance between two opposite sides of the third interposer layer. The second stacked structure is separate from the first stacked structure.

14. The semiconductor device package of claim 13, further comprising a second component disposed on the first surface of the carrier, wherein at least a portion of the second component is disposed beneath the fourth interposer layer.

15. The semiconductor device package of claim 13, further comprising a third component, wherein the third component is disposed on the first surface of the carrier and located between the first stacked structure and the second stacked structure.

16. The semiconductor device package of claim 15, wherein the height of the third component is greater than the height of the first interposer or the height of the third interposer.

17. The semiconductor device package of claim 13, further comprising a first encapsulating material encapsulating the first surface of the carrier, the first stacked structure, and the second stacked structure; The carrier has a second surface opposite to the first surface, and a second encapsulating material encapsulates the second surface of the carrier, wherein the first surface of the carrier has a first portion that is not encapsulated by the first encapsulating material, and the second surface of the carrier has a second portion that is not encapsulated by the second encapsulating material, wherein the first portion and the second portion are configured asymmetrically.

18. The semiconductor device package of claim 17, wherein the second interposer of the first stacked structure at least partially overlaps the second portion in the vertical direction.

19. The semiconductor device package of claim 18, wherein the first interposer layer at least partially overlaps with the side of the second encapsulant in the vertical direction.

20. The semiconductor device package of claim 19, wherein the first encapsulant includes at least one cavity, wherein the cavity at least partially overlaps with the sidewalls of the second interposer, the first interposer, the first component, the second portion, and the second encapsulant in the vertical direction.

Images