Semiconductor storage devices

Abstract

A semiconductor memory device includes: a peripheral logic structure including peripheral circuitry on a substrate; a horizontal semiconductor layer extending along the top surface of the peripheral logic structure; a plurality of stacked structures arranged on the horizontal semiconductor layer along a first direction; and a plurality of electrode separation regions extending in each of the plurality of stacked structures in a second direction different from the first direction, wherein each of the plurality of stacked structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond a first width of the second electrode pad, the first electrode pad protruding in the second direction beyond a second width of the second electrode pad, the second width being different from the first width.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device, and more specifically, to a three-dimensional (3D) semiconductor memory device including a vertical channel structure with improved reliability and integration density. Background Technology

[0002] To meet consumer demand for high performance and low prices, it is necessary to increase the integration density of semiconductor devices. Since integration density is one of the most important factors determining the price of semiconductor devices, increasing integration density is essential. The integration density of two-dimensional (2D) or planar semiconductor devices is determined by the area occupied by each unit of memory cell, and is therefore significantly affected by fine patterning techniques.

[0003] However, the miniaturization of patterns requires expensive equipment, which limits the increase in integration density of 2D semiconductor devices. Therefore, three-dimensional (3D) semiconductor memory devices, which include memory cells arranged in three dimensions, have been proposed. Summary of the Invention

[0004] According to embodiments of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a peripheral logic structure having peripheral circuitry on a substrate; a horizontal semiconductor layer extending along the top surface of the peripheral logic structure; a plurality of stacked structures arranged on the horizontal semiconductor layer along a first direction; and a plurality of electrode separation regions disposed in each of the plurality of stacked structures to extend in a second direction different from the first direction, wherein each of the plurality of stacked structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond a first width of the second electrode pad, the first electrode pad protruding in the second direction beyond a second width of the second electrode pad, the second width being different from the first width.

[0005] According to the above and other embodiments of this disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a peripheral logic structure having a first peripheral circuit and a second peripheral circuit on a substrate; a first stacked structure and a second stacked structure arranged along a first direction on the peripheral logic structure; a plurality of electrode separation regions disposed in the first stacked structure to extend in a second direction different from the first direction; a plurality of first through-paths arranged along the first direction between the first stacked structure and the second stacked structure to be electrically connected to the first peripheral circuit; and a plurality of second through-paths passing through the first stacked structure to be electrically connected to the second peripheral circuit and arranged along the second direction, wherein at least one of the plurality of first through-paths does not pass through the first stacked structure and the second stacked structure.

[0006] According to the above and other embodiments of this disclosure, a semiconductor memory device is provided, comprising: a peripheral logic structure having a first peripheral circuit and a second peripheral circuit on a substrate; a horizontal semiconductor layer disposed on the peripheral logic structure, the horizontal semiconductor layer including a plurality of openings extending in a first direction; a first stack structure and a second stack structure disposed on the horizontal semiconductor layer and arranged in a second direction such that one of the plurality of openings is inserted therebetween; a plurality of electrode separation regions disposed in the first stack structure and extending in the first direction; a plurality of vertical structures disposed between adjacent electrode separation regions to pass through the first stack structure and be electrically connected to the horizontal semiconductor layer; a bit line disposed on the first stack structure to extend in the second direction and be connected to at least one of the plurality of vertical structures; a plurality of first through-paths passing through the openings and connecting the bit line and the first peripheral circuit; and a plurality of second through-paths passing through the first stack structure and being electrically connected to the second peripheral circuit. Attached Figure Description

[0007] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 A block diagram of a semiconductor memory device according to some embodiments of the present disclosure is shown;

[0009] Figure 2 A perspective view of a semiconductor memory device according to some embodiments of the present disclosure is shown;

[0010] Figure 3 A circuit diagram showing a block of memory cells included in a semiconductor memory device according to some embodiments of the present disclosure;

[0011] Figure 4 A layout diagram of a semiconductor memory device according to some embodiments of the present disclosure is shown;

[0012] Figure 5 Show Figure 4 The plan view of the first stacked structure shown;

[0013] Figure 6 Show along Figure 4 A sectional view taken by line AA;

[0014] Figure 7 Show Figure 6 An enlarged sectional view of part P;

[0015] Figure 8 Show along Figure 4 A sectional view taken by line BB;

[0016] Figure 9 Show along Figure 5 A cross-sectional view taken by line CC;

[0017] Figure 10 A cross-sectional view of a semiconductor memory device according to some embodiments of the present disclosure is shown;

[0018] Figure 11 A cross-sectional view of a semiconductor memory device according to some embodiments of the present disclosure is shown;

[0019] Figure 12 Layout diagrams of semiconductor memory devices according to some embodiments of the present disclosure are shown; and

[0020] Figure 13 Show along Figure 12 The sectional view taken by line DD. Detailed Implementation

[0021] Figure 1 This is a block diagram of a semiconductor memory device according to some embodiments of the present disclosure.

[0022] Reference Figure 1 The semiconductor memory device 10 may include a memory cell array 20 and peripheral circuitry 30.

[0023] The memory cell array 20 may include multiple first memory cell blocks BLK1, second memory cell blocks BLK2 to nth memory cell blocks BLKn. Each of the first memory cell blocks BLK1 to nth memory cell blocks BLKn may include multiple memory cells. The first memory cell blocks BLK1 to nth memory cell blocks BLKn may be connected to the peripheral circuitry 30 via bit lines BL, word lines WL, at least one serial select line SSL, and at least one ground select line GSL.

[0024] Specifically, the first memory cell block BLK1 to the nth memory cell block BLKn can be connected to the row decoder 33 via the word line WL, the serial select line SSL, and the ground select line GSL. Furthermore, the first memory cell block BLK1 to the nth memory cell block BLKn can be connected to the page buffer 35 via the bit line BL.

[0025] Peripheral circuitry 30 can receive address ADDR, command CMD, and control signal CTRL from the external source of semiconductor memory device 10, and can exchange data DATA with external devices. Peripheral circuitry 30 may include control logic 37, a line decoder 33, and a page buffer 35. Peripheral circuitry 30 may also include various sub-circuits, such as input / output (I / O) circuitry, voltage generation circuitry for generating various voltages required for the operation of semiconductor memory device 10, and error correction circuitry for correcting errors in the data DATA read from memory cell array 20.

[0026] Control logic 37 can be connected to line decoder 33, voltage generation circuitry, and I / O circuitry. Control logic 37 can control the general operation of semiconductor memory device 10. Control logic 37 can generate various internal control signals for semiconductor memory device 10 in response to control signal CTRL. For example, control logic 37 can control the voltage supplied to word line WL and bit line BL during memory operations (e.g., programming or erasing operations).

[0027] The row decoder 33 can select at least one of the first memory cell blocks BLK1 to the nth memory cell block BLKn in response to the address ADDR, and can select at least one word line WL, serial select line SSL, and ground select line GSL for the selected memory cell block. The row decoder 33 can provide a voltage to the selected word line WL for the selected memory cell block to perform a memory operation.

[0028] Page buffer 35 can be connected to memory cell array 20 via bit line BL. Page buffer 35 can be used as a write driver or a sense amplifier. Specifically, during programming operations, page buffer 35 can be used as a write driver and can apply a voltage to bit line BL for the data DATA to be written into memory cell array 20. During read operations, page buffer 35 can be used as a sense amplifier and can detect the data DATA stored in memory cell array 20.

[0029] Figure 2 This is a perspective view of a semiconductor memory device according to some embodiments of the present disclosure.

[0030] Reference Figure 2 Semiconductor memory devices may include peripheral logic structures (PS) and cell array structures (CS).

[0031] Cell array structures (CS) can be stacked on peripheral logic structures (PS). That is, the peripheral logic structure (PS) and the cell array structure (CS) can overlap each other in a planar diagram. Semiconductor memory devices can have a cell-on-periphery (COP) structure.

[0032] For example, the cell array structure CS can include Figure 1 The storage cell array 20. The peripheral logic structure PS may include Figure 1 The peripheral circuitry 30. The cell array structure CS may include the first memory cell block BLK1 to the nth memory cell block BLKn disposed on the peripheral logic structure PS.

[0033] Figure 3 This is a circuit diagram illustrating a block of memory cells included in a semiconductor memory device according to some embodiments of the present disclosure.

[0034] Reference Figure 3 The storage cell block may include a common source line CSL, multiple zero bit lines BL0, a first bit line BL1 and a second bit line BL2, and multiple cell strings CSTRs disposed between the common source line CSL and the zero bit lines BL0 to the second bit lines BL2.

[0035] The unit string CSTR can be connected in parallel to each of the zero bit line BL0 to the second bit line BL2. The unit string CSTR can be connected to a common source line CSL. That is, the unit string CSTR can be positioned between the common source line CSL and the zero bit line BL0 to the second bit line BL2. Multiple common source lines CSL can be arranged in two dimensions. Here, the same voltage can be applied to the multiple common source lines CSL, or each of the multiple common source lines CSL can be electrically controlled.

[0036] For example, each cell string CSTR may include a first string select transistor SST1 and a second string select transistor SST2 connected in series, a memory cell MCT connected in series, and a ground select transistor GST. Each memory cell MCT may include a data storage element.

[0037] For example, the second string select transistor SST2 can be connected to the zero bit line BL0 to the second bit line BL2, and the ground select transistor GST can be connected to the common source line CSL. The memory cell MCT can be connected in series between the first string select transistor SST1 and the ground select transistor GST.

[0038] Each cell string (CSTR) may also include a dummy cell (DMC) connected between the first string select transistor (SST1) and the memory cell (MCT). Although not specifically shown, the dummy cell (DMC) may also be provided and connected between the ground select transistor (GST) and the memory cell (MCT). Like the first string select transistor (SST1) and the second string select transistor (SST2), the ground select transistor (GST) may include multiple metal-oxide-semiconductor (MOS) transistors connected in series. Alternatively, each cell string (CSTR) may include a single string select transistor.

[0039] The first string select transistor SST1 can be controlled by the first string select line SSL1, and the second string select transistor SST2 can be controlled by the second string select line SSL2. The memory cell MCT can be controlled by multiple zero-th word lines WL0 to (n-1)-th word lines WLn-1 and the nth word line WLn. The dummy cell DMC can be controlled by the dummy word line DWL. The ground select transistor GST can be controlled by the zero-th ground select line GSL0, the first ground select line GSL1, and the second ground select line GSL2. The common source line CSL can be commonly connected to the source of the ground select transistor GST in the cell string CSTR.

[0040] Each cell string CSTR may include multiple memory cells MCTs spaced at different distances from the common source line CSL. The zero word line WL0 to the nth word line WLn and the dummy word line DWL may be set between the common source line CSL and the zero bit line BL0 to the second bit line BL2.

[0041] The gate electrodes of memory cells MCTs spaced at substantially the same distance from the common source line CSL can be commonly connected to one of the zero word lines WL0 to the nth word line WLn or commonly connected to the dummy word line DWL, thus allowing them to be in an equipotential state. Conversely, even if the gate electrodes of memory cells MCTs are spaced at substantially the same distance from the common source line CSL, the gate electrodes of memory cells MCTs in different rows or columns can be independently controlled.

[0042] The zero-ground selector lines GSL0 to GSL2, as well as the first string selector lines SSL1 and SSL2, may extend in the same direction as, for example, the zero-word lines WL0 to WLn and the dummy word line DWL. The zero-ground selector lines GSL0 to GSL2, positioned at substantially the same level from the common source line CSL, may be electrically isolated from each other. The first string selector lines SSL1 and SSL2, positioned at substantially the same level from the common source line CSL, may be electrically isolated from each other.

[0043] Figure 4 This is a layout diagram of a semiconductor memory device according to some embodiments of the present disclosure. Figure 5 It is shown Figure 4 The diagram shows a plan view of the first stacked structure. Figure 6 It is along Figure 4 The sectional view taken by line AA. Figure 7 It is shown Figure 6 An enlarged sectional view of part P. Figure 8 It is along Figure 4 The sectional view taken by line BB. Figure 9 yes Figure 5 The electrode pad shown along Figure 5 The cross-sectional view is taken by line CC. Note that... Figure 9 Only the electrode pads and electrode separation areas are shown.

[0044] Reference Figures 4 to 9 The semiconductor memory device 10 may include a peripheral logic structure PS and a cell array structure CS.

[0045] The peripheral logic structure PS may include a first peripheral circuit TR1, a second peripheral circuit TR2, a first lower connection wiring body 115, and a second lower connection wiring body 116.

[0046] The first peripheral circuit TR1 and the second peripheral circuit TR2 can be formed on the substrate 100. The first peripheral circuit TR1 can be included in Figure 1 The page buffer 35. The second peripheral circuit TR2 can be included. Figure 1 In line decoder 33.

[0047] The substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Optionally, the substrate 100 may be a silicon substrate, or may include materials other than silicon, such as silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto.

[0048] A peripheral logic insulating film 110 may be formed on the substrate 100. The peripheral logic insulating film 110 may include at least one of silicon oxide, silicon nitride, and silicon nitride, for example.

[0049] The first lower connection wiring 115 and the second lower connection wiring 116 can be formed in the peripheral logic insulating film 110. The first lower connection wiring 115 can be connected to the first peripheral circuit TR1. The second lower connection wiring 116 can be connected to the second peripheral circuit TR2.

[0050] The cell array structure CS can be on the peripheral logic structure PS, and can include multiple horizontal semiconductor layers 150 disposed on the peripheral logic structure PS and multiple zero-thousandth stacked structures ST0 to third-thousandth stacked structures ST3 disposed on each horizontal semiconductor layer 150.

[0051] A horizontal semiconductor layer 150 can be disposed on the peripheral logic structure PS. The horizontal semiconductor layer 150 can extend along the top surface of the peripheral logic structure PS. For example, as... Figure 4 As shown, the plurality of horizontal semiconductor layers 150 can be arranged on the top surface of the peripheral logic structure PS to be spaced apart from each other along two directions (e.g., along the first direction D1 and the second direction D2), while each horizontal semiconductor layer 150 can have a longitudinal direction in the first direction D1.

[0052] Each horizontal semiconductor layer 150 may include a plurality of first openings OP1 and a plurality of second openings OP2. The first openings OP1 and the second openings OP2 may expose portions of the peripheral logic structure PS.

[0053] The first openings OP1 in each horizontal semiconductor layer 150 may be spaced apart from each other in a first direction D1. The first openings OP1 may extend in a second direction D2, for example, the longitudinal direction of each first opening OP1 in the top view may extend in the second direction D2.

[0054] The horizontal semiconductor layers 150 may be spaced apart from each other by a first distance W32 in the first direction D1. The width W31 of the first opening OP1 in the first direction D1 may be the same as or less than the first distance W32, but this disclosure is not limited thereto.

[0055] The second opening OP2 may be arranged along a first side of the horizontal semiconductor layer 150 extending in the first direction D1. For example, the second opening OP2 may have a longitudinal direction along the second direction D2 and may be aligned with each other along each longitudinal side of the corresponding horizontal semiconductor layer 150. A plurality of second openings OP2 are shown arranged in a linear form, but this disclosure is not limited thereto.

[0056] For example, such as Figure 6 As shown, each horizontal semiconductor layer 150 may include a lower support semiconductor layer (LSB) and a common source plate (CSP) disposed on the lower support semiconductor layer (LSB). For example, the horizontal semiconductor layer 150 may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof. The horizontal semiconductor layer 150 may have at least one of, for example, a single-crystal structure, an amorphous structure, and a polycrystalline structure. The common source plate (CSP) can be used as... Figure 3 The common source line CSL.

[0057] In another example, each horizontal semiconductor layer 150 may include only a common source plate CSP without a lower supporting semiconductor layer LSB. In yet another example, a common source line extending in a second direction D2 may be formed in the horizontal semiconductor layer 150 instead of a two-dimensional (2D) planar common source plate.

[0058] The second opening OP2 is shown to be surrounded by a corresponding horizontal semiconductor layer 150, but this disclosure is not limited thereto. That is, the sidewalls of the second opening OP2 extending in the first direction D1 may be open. Therefore, the sidewalls of the horizontal semiconductor layer 150 extending in the first direction D1 may be non-flat.

[0059] The filling insulating film 154 can be formed on the peripheral logic structure PS. The filling insulating film 154 can fill the first opening OP1 and the second opening OP2. The filling insulating film 154 can include, for example, silicon oxide, but this disclosure is not limited thereto.

[0060] The zeroth stack structure ST0 to the third stack structure ST3 can be disposed on each horizontal semiconductor layer 150. The zeroth stack structure ST0 to the third stack structure ST3 can be arranged along the first direction D1, for example, the zeroth stack structure ST0 to the third stack structure ST3 can be adjacent to each other on each horizontal semiconductor layer 150 along the first direction D1.

[0061] The first opening OP1 can be disposed between the zeroth stack structure ST0 to the third stack structure ST3 that are adjacent to each other in the first direction D1. Specifically, each first opening OP1 can be disposed between the zeroth stack structure ST0 and the first stack structure ST1, between the first stack structure ST1 and the second stack structure ST2, and between the second stack structure ST2 and the third stack structure ST3.

[0062] For example, the first stacked structure ST1 and the second stacked structure ST2 may overlap with one of the first openings OP1 in a plan view, but the corresponding first opening OP1 may include portions that do not overlap with the first stacked structure ST1 and the second stacked structure ST2. In another example, in a plan view, at least one of the first stacked structure ST1 and the second stacked structure ST2 may not overlap with one of the first openings OP1.

[0063] Figure 4 Four stacked structures are shown on each horizontal semiconductor layer 150, but this disclosure is not limited thereto. That is, two or more stacked structures may be provided on each horizontal semiconductor layer 150.

[0064] The semiconductor memory device according to this embodiment will be described below using the first stacked structure ST1 as an example. The following description of the first stacked structure ST1 can be directly applied to the zeroth stacked structure ST0, the second stacked structure ST2, and the third stacked structure ST3.

[0065] Reference Figure 5 , Figure 6 and Figure 8 The first stacked structure ST1 may include first electrode pads to eighth electrode pads EP1, EP2, EP3, EP4, EP5, EP6, EP7, and EP8 stacked on a third-direction D3. The first stacked structure ST1 may also include an inter-electrode insulating film (ILD) disposed between the first electrode pads EP1 to the eighth electrode pads EP8, for example, the ILD may be between every two adjacent electrode pads among the first electrode pads EP1 to the eighth electrode pads EP8. The first stacked structure ST1 is shown as including eight electrode pads, but this disclosure is not limited thereto.

[0066] The first electrode pads EP1 to the eighth electrode pads EP8 stacked on the third-party D3 may include Figure 3 The gate electrodes of the first string select transistor SST1, the second string select transistor SST2, and the ground select transistor GST. Furthermore, the first electrode pads EP1 to the eighth electrode pads EP8 stacked on the third-direction D3 may include... Figure 3 The word line of the memory cell MCT.

[0067] For example, the first stack structure ST1 may include a fourth electrode pad EP4 and a fifth electrode pad EP5 that are adjacent to each other on the third direction D3. The fifth electrode pad EP5 may be disposed on the fourth electrode pad EP4.

[0068] The fourth electrode pad EP4 can protrude beyond the first width W1 of the fifth electrode pad EP5 in the first direction D1, such as... Figure 6 As shown. That is, the first sidewalls of the fourth electrode pad EP4 and the fifth electrode pad EP5 facing the second stacked structure ST2 can be spaced apart from each other by a first width W1 in the first direction D1.

[0069] The fourth electrode pad EP4 can protrude beyond the second width W2 of the fifth electrode pad EP5 in the second direction D2, such as... Figure 8 As shown. That is, the second sidewalls of the stacked structure with the fourth electrode pad EP4 and the fifth electrode pad EP5 facing each other in the second direction can be spaced apart from each other by a second width W2 in the second direction D2.

[0070] The first width W1 can be different from the second width W2. For example, the first width W1 can be smaller than the second width W2.

[0071] The first stacked structure ST1 may include a cell region CR and a first cell extension region CER1 extending from the cell region CR in a first direction D1. For example, as Figure 5 As shown, the first cell extension region CER1 may have a longitudinal direction along the second direction D2 to extend along the edge of the cell region CR. For example, the first cell extension region CER1 may be adjacent to the cell region CR along the first direction D1 (e.g., the first cell extension region CER1 may approximately correspond to...). Figure 5 (The dashed rectangles above and below the cell region CR). The first stacked structure ST1 may also include a second cell extension region CER2 extending from the cell region CR in the second direction D2. For example, as Figure 5 As shown, the second unit extension region CER2 can have a longitudinal length along the first direction D1, such that each second unit extension region CER2 can have a unit region CR along its long side and a first unit extension region CER1 along its short side.

[0072] Multiple electrode separation regions (ESRs) can be set in the first stacked structure ST1. (In top view...) Figure 5 When viewed in the image, the electrode separation region ESR can extend in the second direction D2.

[0073] The first stacked structure ST1 may include multiple electrode separation trenches EST. Each electrode separation region ESR may fill the electrode separation trench EST. For example, the electrode separation region ESR may include an insulating material filling the electrode separation trench EST. The electrode separation region ESR may include, for example, silicon oxide.

[0074] In another example, the electrode separation region (ESR) may include a liner formed along the sidewalls of the electrode separation trench (EST) and a filler film formed on the liner to fill the electrode separation trench (EST). For example, the liner may include an insulating material, and the filler film may include a conductive material. In another example, the liner may include a conductive material, and the filler film may include an insulating material.

[0075] like Figure 5 As shown, at least some of the electrode separation regions ESR can have a length in the second direction D2 that is less than the length of the first stacked structure ST1 in the second direction D2. For example, the electrode separation regions ESR can divide the cell regions CR in the first direction D1. However, as Figure 5 As shown, at least some of the electrode separation regions ESR may not divide the portion of each second unit extension region CER2 that overlaps with the second opening OP2.

[0076] The electrode separation region (ESR) may not be located in the first unit extension region (CER1). The electrode separation trench (EST) where the electrode separation region (ESR) is formed may be used to form... Figure 3 It is used in the replacement process of the zero-word line WL0 to the n-word line WL0. That is, the portion of the molded film is removed using an electrode-separated trench EST, and the zero-word line WL0 to the n-word line WLn are formed in the removed portion of the molded film.

[0077] When the molding film is removed using the electrode separation trench EST, the molding film may not be completely removed from the first cell extension region CER1 and may remain in the first cell extension region CER1. The first cell extension region CER1 may include a first molding region EP_M1 extending in the second direction D2. That is, the first stack structure ST1 may include the first molding regions EP_M1 disposed on both sides of the cell region CR in the first direction D1.

[0078] Each of the first electrode pads EP1 to the eighth electrode pads EP8 may include an electrode region EP_E and a first molding region EP_M1. The electrode region EP_E may include, for example, tungsten (W), but this disclosure is not limited thereto.

[0079] For example, refer to Figure 9The electrode pad EP may include an electrode region EP_E and first molded regions EP_M1 disposed on both sides of the electrode region EP_E in a first direction D1. The electrode region EP_E may be divided by a plurality of electrode separating regions ESR extending in a second direction D2. The first molded regions EP_M1 may extend from the electrode region EP_E in the first direction D1.

[0080] The electrode separation region ESR may include a first electrode separation region and a second electrode separation region that are furthest apart from each other in the first direction D1. The electrode region EP_E may be located between the first and second electrode separation regions. A portion of the electrode region EP_E may be located in areas other than the first and second electrode separation regions.

[0081] The width of the first molded region EP_M1 of each of the first electrode pads EP1 to the eighth electrode pad EP8 in the first direction D1 can gradually decrease as it moves away from the peripheral logic structure PS. For example, the width of the first molded region EP_M1 of the fourth electrode pad EP4 in the first direction D1 can be greater than the width of the first molded region EP_M1 of the fifth electrode pad EP5 in the first direction D1.

[0082] For example, such as Figure 6 As shown, the first molding region EP_M1 of the fourth electrode pad EP4 can protrude a first width W1 from the first molding region EP_M1 of the fifth electrode pad EP5 in the first direction D1. In other words, the sidewalls of the first molding regions EP_M1 of the fourth electrode pad EP4 and the fifth electrode pad EP5 facing the second stacked structure ST2 can be spaced apart from each other by a first width W1 in the first direction D1.

[0083] In the sectional view taken along the first direction D1, as shown Figure 6 As shown, the first stacked structure ST1 may have a stepped profile defined by a first molded region EP_M1 of each of the first electrode pads EP1 to the eighth electrode pads EP8.

[0084] Since at least some of the electrode separation regions ESR do not delineate the portion of each second cell extension region CER2 that overlaps with the second opening OP2, each second cell extension region CER2 may include a second molding region EP_M2. The second molding region EP_M2 may at least partially cover the second opening OP2.

[0085] For example, such as Figure 8As shown, the second molding region EP_M2 of the fourth electrode pad EP4 can protrude beyond the second width W2 of the second molding region EP_M2 of the fifth electrode pad EP5 in the second direction D2. In other words, the second molding regions EP_M2 of the fourth electrode pad EP4 and the second molding regions EP_M2 of the fifth electrode pad EP5 can be spaced apart from each other by a second width W2 in the second direction D2.

[0086] That is, in the sectional views taken along the first direction D1 and along the second direction D2, as shown Figure 6 and Figure 8 As shown, the first stacked structure ST1 may have a stepped profile in each of the first direction D1 and the second direction D2, the stepped profile being defined by the first molding region EP_M1 and the second molding region EP_M2 of each of the first electrode pads EP1 to the eighth electrode pads EP8. Figures 4-5 As further shown, this stepped profile overlaps with the edges and interior regions of each horizontal semiconductor layer 150. Furthermore, as... Figure 5 , Figure 6 and Figure 8 As shown, the first opening OP1 and the second opening OP2 in the horizontal semiconductor layer 150 at least partially overlap with the stepped portion of the first stacked structure ST1 to allow electrical connection to the peripheral logic structure PS below the horizontal semiconductor layer 150.

[0087] The first molding region EP_M1 and the second molding region EP_M2 may include, for example, silicon nitride, but this disclosure is not limited thereto.

[0088] Multiple vertical structures VS passing through the first stacked structure ST1 can be disposed between the electrode separation regions ESR. The vertical structures VS can be connected to the horizontal semiconductor layer 150.

[0089] For example, some of the channel regions used as memory cells in the vertical structure VS can be electrically connected to a common source plate CSP of the horizontal semiconductor layer 150. The vertical structure VS can include, for example, semiconductor materials such as Si, Ge, or mixtures thereof. Alternatively, the vertical structure VS can include metal-oxide-semiconductor materials.

[0090] The barrier insulating film (BIL), charge storage film (CIL), and tunnel insulating film (TIL) may be sequentially disposed between the first stacked structure ST1 and the vertical structure VS, but this disclosure is not limited thereto. The vertical insulating film VI may be disposed on the vertical structure VS. The vertical insulating film VI may fill the gap defined by the vertical structure VS.

[0091] The horizontal insulating pattern HP can be disposed between the first electrode pad EP1 and the inter-electrode insulating film ILD, and between the first electrode pad EP1 and the barrier insulating film BIL. The horizontal insulating pattern HP can include, for example, silicon oxide or a high-k dielectric film.

[0092] Each of the barrier insulating film (BIL), charge storage film (CIL), and tunnel insulating film (TIL) can be divided by a contact support film (CSB). The contact support film (CSB) can electrically connect the common source plate (CSP) of the horizontal semiconductor layer 150 to the vertical structure VS. The contact support film (CSB) can include, for example, a semiconductor material, such as Si, Ge, or mixtures thereof.

[0093] A sacrificial insulating film 155 may be disposed between the first stacked structure ST1 and the horizontal semiconductor layer 150, and between the first stacked structure ST1 and the filling insulating film 154. The sacrificial insulating film 155 may be in contact with the contact support film CSB. The sacrificial insulating film 155 may be used as a mold for forming the contact support film CSP. The sacrificial insulating film 155 may be a portion of the molded film that remains unremoved during the process of forming the contact support film CSP. The sacrificial insulating film 155 may include, for example, silicon nitride, but this disclosure is not limited thereto.

[0094] The first interlayer insulating film 151 may be formed on the horizontal semiconductor layer 150. The first interlayer insulating film 151 may cover the first stacked structure ST1 and the second stacked structure ST2. The first interlayer insulating film 151 may include, for example, silicon oxide, but this disclosure is not limited thereto.

[0095] The second interlayer insulating film 152 and the third interlayer insulating film 153 can be sequentially formed on the first interlayer insulating film 151. The electrode separation region ESR can even extend to the second interlayer insulating film 152.

[0096] Bit line BL can be disposed on the first stack structure ST1. Bit line BL can extend in the first direction D1. Bit line BL can be electrically connected to the vertical structure VS.

[0097] Bit lines BL can be formed on the third interlayer insulating film 153. Bit lines BL can be electrically connected to the vertical structure VS via bit line pads BL_PAD and bit line plugs BL_PG.

[0098] like Figure 6 As shown, multiple first through-paths THV_PB can be disposed between adjacent first stacked structures ST1 and second stacked structures ST2. The first through-paths THV_PB can be arranged along a first direction D1, for example, adjacent to each other along the first direction D1.

[0099] The first through-path THV_PB can be electrically connected to the first peripheral circuit TR1 of the peripheral logic structure PS through the first opening OP1. The first through-path THV_PB can be connected to the bit line BL through the first through-path connection line THV_PL.

[0100] At least one of the first through-paths THV_PB arranged along the first direction D1 may not pass through the first stacked structure ST1 and the second stacked structure ST2. That is, the first through-path THV_PB can be electrically connected to the first peripheral circuit TR1 through the space between the first stacked structure ST1 and the second stacked structure ST2.

[0101] like Figure 8 As shown, multiple second through-paths THV_RD can be arranged along the second direction D2, for example, spaced apart from each other along the second direction D2. The second through-paths THV_RD can be electrically connected to the second peripheral circuit TR2 of the peripheral logic structure PS through the second opening OP2. The second through-paths THV_RD can be electrically connected to the electrode regions EP_E of the first electrode pads EP1 to the eighth electrode pads EP8 through the second through-path connection line THV_RL.

[0102] The second through-path THV_RD can pass through the first stacked structure ST1 and be electrically connected to the second peripheral circuit TR2 of the peripheral logic structure PS. The second through-path THV_RD can also pass through the second molding region EP_M2 of each second cell extension region CER2.

[0103] Figure 10 This is a cross-sectional view of a semiconductor memory device according to some embodiments of the present disclosure. It will be described below. Figure 10 Semiconductor memory devices, primarily focusing on those related to semiconductor memory. Figures 4 to 9 Differences in semiconductor memory devices. Figure 10 Corresponding to along Figure 4 The sectional view taken by line AA.

[0104] Reference Figure 10 Some of the multiple first through-paths THV_PB arranged in the first direction D1 (e.g.) Figure 10 The leftmost first through-path (THV_PB) can pass through at least one of the first stack structure ST1 and the second stack structure ST2. Other first through-paths (THV_PB) may not pass through the first stack structure ST1 and the second stack structure ST2.

[0105] Figure 11 This is a cross-sectional view of a semiconductor memory device according to some embodiments of the present disclosure. It will be described below. Figure 11 Semiconductor memory devices, primarily focusing on those related to semiconductor memory. Figures 4 to 9 Differences in semiconductor memory devices. Figure 11 Corresponding to along Figure 4 The sectional view taken by line AA.

[0106] Reference Figure 11 At least one of the first electrode pads EP1 to the eighth electrode pads EP8 may not include the first molding region EP_M1. For example, the eighth electrode pad EP8 at the top of the first stack structure ST1 may include the electrode region EP_E, but does not include the first molding region EP_M1.

[0107] Figure 12 This is a layout diagram of a semiconductor memory device according to some embodiments of the present disclosure. Figure 13 It is along Figure 12 The sectional view taken by line DD. This will be described below. Figure 12 and Figure 13 Semiconductor memory devices, primarily focusing on those related to semiconductor memory. Figures 4 to 9 The differences in semiconductor memory devices. Note the cross-sectional view of the first stacked structure ST1 and the second stacked structure ST2, taken along the first direction D1 and having a first opening OP1 inserted therebetween. Figure 6 Basically the same.

[0108] Reference Figure 12 and Figure 13 The horizontal semiconductor layer 150 may further include a first (1_1) opening OP11 extending in the second direction D2. Unlike the first opening OP1, the first (1_1) opening OP11 may be substantially covered by the first stacked structure. That is, in the plan view, the first (1_1) opening OP11 may not include a portion that does not overlap with the first stacked structure ST1.

[0109] Each of the plurality of first electrode pads EP1 to eighth electrode pads EP8 stacked on third direction D3 in the first stacked structure ST1 may include a first (1_1) molded region EP_M11, which is configured to overlap with the first (1_1) opening OP11 and extend in the first direction D1.

[0110] That is, the (1_1) molding region EP_M11 can be disposed between the electrode regions EP_E. In other words, the electrode regions EP_E can be disposed on both sides of the (1_1) molding region EP_M11 in the first direction D1. The electrode regions EP_E can extend from the (1_1) molding region EP_M11 in the first direction D1. The (1_1) molding region EP_M11 can be disposed between adjacent electrode separation regions ESR in the first direction D1.

[0111] Multiple (1_1) through-paths THV_PBB arranged on the first direction D1 pass through the first stacked structure ST1. The (1_1) through-paths THV_PBB can be electrically connected to the first peripheral circuit TR1 of the peripheral logic structure PS through the (1_1) opening OP11.

[0112] The (1_1) through-path THV_PBB can be connected to the bit line BL via the (1_1) through-path connection line THV_PLL. The (1_1) through-path THV_PBB can pass through the (1_1) molded region EP_M11 of the first stack structure ST1.

[0113] By way of summary and review, embodiments of this disclosure provide a semiconductor memory device including a vertical channel structure with improved reliability and integration density. Specifically, embodiments of this disclosure include a semiconductor memory device having a stack (e.g., a stack of word lines on a cell array region) including a stepped structure (e.g., having a stepped profile) located in an internal chip region, in addition to a stepped structure at the chip edge. Furthermore, through-paths connect the stack having the stepped structure (e.g., both edge and internal regions) to peripheral circuitry beneath the chip.

[0114] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only and not for limiting purposes. In some cases, as will be apparent to those skilled in the art up to the time of filing of this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

[0115] Korean Patent Application No. 10-2019-0091409, filed on July 29, 2019, with the Korean Intellectual Property Office and entitled “Semiconductor Memory Device”, is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a peripheral logic structure including a peripheral circuit on a substrate; a horizontal semiconductor layer extending along a top surface of the peripheral logic structure; a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction; and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction different from the first direction, wherein each of the plurality of stack structures includes: a first electrode pad including a first electrode region and a first molding region, and a second electrode pad on the first electrode pad, the second electrode pad including a second electrode region and a second molding region, wherein the first molding region protrudes beyond the second molding region a first width in the first direction to define a first stepped profile, wherein the first molding region protrudes beyond the second molding region a second width in the second direction to define a second stepped profile, the second width of the second stepped profile being different from the first width of the first stepped profile, wherein the second electrode region overlaps the first electrode region but not the first molding region in a third direction perpendicular to the first and second directions, wherein the second molding region overlaps the first molding region but not the first electrode region in the third direction.

2. The semiconductor memory device of claim 1, wherein the second width is greater than the first width.

3. The semiconductor memory device of claim 1, wherein the plurality of stack structures includes: a first stack structure and a second stack structure adjacent to each other along the first direction, and a plurality of through-vias between the first and second stack structures.

4. The semiconductor memory device of claim 3, wherein the plurality of through-vias do not pass through the first and second stack structures.

5. The semiconductor memory device of claim 3, wherein some of the plurality of through-vias pass through at least one of the first and second stack structures.

6. The semiconductor memory device of claim 3, wherein: the horizontal semiconductor layer includes an opening exposing a portion of the peripheral logic structure, and the plurality of through-vias are electrically connected to the peripheral circuit through the opening.

7. The semiconductor memory device of claim 1, wherein: a third electrode pad is at a top of each of the plurality of stack structures, the third electrode pad includes a third electrode region and does not include a molding region.

8. The semiconductor memory device of claim 1, wherein each of the first and second molding regions extends in the first direction, and the first and second electrode regions extend on both sides of the first and second molding regions and in the first direction.

9. The semiconductor memory device of claim 8, further comprising: at least one through-via passing through the first and second molding regions, ​ wherein the horizontal semiconductor layer includes an opening exposing a portion of the peripheral logic structure, and wherein the at least one through via is electrically connected to the peripheral circuitry through the opening.

10. The semiconductor memory device of claim 1, wherein: each of the plurality of stack structures includes a plurality of electrode separation trenches, and the plurality of electrode separation regions includes insulating material filling the plurality of electrode separation trenches.

11. A semiconductor memory device, comprising: a peripheral logic structure including first and second peripheral circuitry on a substrate; first and second stack structures arranged along a first direction on the peripheral logic structure; a plurality of electrode separation regions in the first stack structure extending in a second direction different from the first direction; a plurality of first through vias arranged along the first direction between the first and second stack structures to electrically connect to the first peripheral circuitry, at least one of the plurality of first through vias not passing through the first and second stack structures; and a plurality of second through vias passing through the first stack structure to electrically connect to the second peripheral circuitry and arranged along the second direction, wherein the first stack structure includes: a first electrode pad including a first electrode region and a first molding region, and a second electrode pad on the first electrode pad, the second electrode pad including a second electrode region and a second molding region, wherein the first molding region protrudes beyond the second molding region a first width in the first direction to define a first stepped profile, wherein the first molding region protrudes beyond the second molding region a second width in the second direction to define a second stepped profile, the second width of the second stepped profile being different from the first width of the first stepped profile, wherein the second electrode region overlaps the first electrode region but not the first molding region in a third direction perpendicular to the first and second directions, wherein the second molding region overlaps the first molding region but not the first electrode region in the third direction.

12. The semiconductor memory device of claim 11, wherein the plurality of first through vias do not pass through the first and second stack structures.

13. The semiconductor memory device of claim 11, wherein: the first stack structure includes a plurality of electrode pads sequentially stacked on the peripheral logic structure, the plurality of electrode pads including the first and second electrode pads, the plurality of electrode separation regions includes a first electrode separation region and a second electrode separation region furthest apart from each other in the first direction, each of the plurality of electrode pads includes an electrode region between the first and second electrode separation regions and a molding region extending from the electrode region in the first direction, and the first stack structure has a stepped profile defined by the molding regions of the plurality of electrode pads.

14. The semiconductor memory device of claim 11, wherein: ​ the first stack structure includes a plurality of electrode pads sequentially stacked on the peripheral logic structure, the plurality of electrode pads including the first electrode pad and the second electrode pad, each of at least some of the plurality of electrode pads includes a molding region, and the plurality of second through-vias pass through the molding region.

15. A semiconductor memory device, comprising: a peripheral logic structure including a first peripheral circuit and a second peripheral circuit on a substrate; a horizontal semiconductor layer on the peripheral logic structure, the horizontal semiconductor layer including a plurality of openings extending in a first direction; a first stack structure and a second stack structure disposed on the horizontal semiconductor layer and in a second direction, one of the plurality of openings between the first stack structure and the second stack structure; a plurality of electrode separation regions in the first stack structure extending in the first direction; a plurality of vertical structures between the plurality of electrode separation regions adjacent to each other to pass through the first stack structure and electrically connected to the horizontal semiconductor layer; a bit line on the first stack structure extending in the second direction and connected to at least one of the plurality of vertical structures; a plurality of first through-vias passing through the plurality of openings and connecting the bit line and the first peripheral circuit; and a plurality of second through-vias passing through the first stack structure electrically connected to the second peripheral circuit, wherein the first stack structure includes: a first electrode pad including a first electrode region and a first molding region, and a second electrode pad on the first electrode pad, the second electrode pad including a second electrode region and a second molding region, wherein the first molding region protrudes beyond the second molding region in the first direction by a first width to define a first stepped profile, wherein the first molding region protrudes beyond the second molding region in the second direction by a second width to define a second stepped profile, the second width of the second stepped profile being different from the first width of the first stepped profile, wherein the second electrode region overlaps the first electrode region but not the first molding region in a third direction perpendicular to the first direction and the second direction, wherein the second molding region overlaps the first molding region but not the first electrode region in the third direction. ​

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