Microelectronic assembly

Abstract

Various embodiments of fan-out packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without intervening adhesive, the microelectronic substrate having a plurality of electrically conductive interconnects on at least one surface of the microelectronic substrate. The method can include applying a molding material to a region of the surface of the carrier encompassing the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at a region of the surface of the carrier and at the molding material to form the microelectronic assembly.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Nonprovisional Patent Application No. 16 / 503,021, filed July 3, 2019, and U.S. Provisional Patent Application No. 62 / 694,543, filed July 6, 2018, the entire contents of which are incorporated herein by reference and for all purposes. Technical Field

[0003] This field relates to microelectronic components, and more particularly to microelectronic components including packages (e.g., fan-out packages or fan-in packages) that include one or more components that are directly bonded to each other without the intervention of adhesives. Background Technology

[0004] In various packaging arrangements, monolithic integrated device dies can be bonded to a carrier such as a tape or film using adhesives. Monolithic integrated device dies can also be overmolded using molding compounds to form what is sometimes called a reconstructed wafer for further processing. The relatively fine-pitch electrical contacts of one or more integrated device dies can be fanned out over the die via a redistribution layer (RDL) to connect to relatively coarse-pitch electrodes or leads of another structure, such as a system substrate or motherboard. The die can then be monolithized from the reconstructed wafer along with some sides molded and covered with the RDL. However, continuous improvement in packaging and the technologies used to form such packages remains necessary. Attached Figure Description

[0005] These and other aspects will become apparent from the following description and accompanying drawings of preferred embodiments, which are intended to illustrate and not limit the invention, wherein...

[0006] Figure 1A This is a schematic side view of a carrier according to various embodiments.

[0007] Figure 1B This is a schematic side view of a partially formed microelectronic assembly, which includes multiple elements directly bonded to a carrier without the intervention of an adhesive.

[0008] Figure 1C It is a schematic side view of a partially formed microelectronic component, in which a molding compound is applied around and between adjacent elements.

[0009] Figure 1D It is a schematic side view of a partially formed microelectronic assembly, wherein a molding compound is applied around and between adjacent elements, and between adjacent interconnects on the front surface of the elements.

[0010] Figure 1EThis is a schematic side view of a partially formed microelectronic component, in which a redistribution layer (RDL) is applied over the upper surface of the molding compound and the front surface of the component.

[0011] Figure 1F It is a schematic side view of a microelectronic component formed after at least a portion of the carrier has been removed.

[0012] Figure 1G It is a schematic side view of multiple microelectronic components after being modularized.

[0013] Figure 1H This is a schematic side view of several microelectronic components in which the carrier has been completely removed from the element.

[0014] Figure 1I It is a schematic side view of multiple microelectronic components including multiple through-mold vias.

[0015] Figure 1J This is a schematic side view illustrating a microelectronic component formed by a stacked structure.

[0016] Figure 1K This is a schematic side view illustrating multiple monolithic microelectronic components including a stacked structure according to various embodiments.

[0017] Figure 2A This is a schematic side view of a carrier according to another embodiment.

[0018] Figure 2B This is a schematic side view of a partially formed microelectronic assembly comprising multiple elements directly bonded to a carrier without the intervention of an adhesive.

[0019] Figure 2C This is a schematic side view showing a molded compound applied on and between multiple elements on a carrier.

[0020] Figure 2D It refers to the molding compound and components after they have been thinned through a thinning process. Figure 2C A schematic side view of a microelectronic component formed from the portion of the structure.

[0021] Figure 2E This is after at least a portion of the carrier has been removed. Figure 2D A schematic side view of a microelectronic component formed from the portion of the structure.

[0022] Figure 2F This is a schematic side view of a microelectronic assembly, including a portion of the redistribution layer (RDL) above the front surface of the component.

[0023] Figure 2G This is a schematic side view showing multiple monolithic microelectronic components according to various embodiments.

[0024] Figure 2H It is a schematic side view of multiple microelectronic components including multiple through-holes.

[0025] Figure 3 This is a schematic diagram of a system incorporating one or more microelectronic components according to various embodiments. Detailed Implementation

[0026] Components, including semiconductor elements such as integrated device dies (or “dies”) or wafers, can be stacked in three dimensions (3D), arranged side-by-side with lateral arrangement relative to each other, or packaged for connection to external systems as part of a variety of microelectronic packaging schemes. This can include layers on which one or more components (e.g., one or more dies, devices, and / or wafers) are stacked on a larger carrier (e.g., a larger base die, device, or wafer); multiple dies or wafers stacked in a vertical or horizontal arrangement; and various combinations thereof. One or more redistribution layers (RDLs) can be provided for these components. Compared to pads on a die, RDLs can provide greater spacing between pads, thereby facilitating connections to other electronic components.

[0027] For example, one or more components (e.g., integrated device dies) can be stacked on a carrier (e.g., a wafer, substrate, etc.) to form a package arrangement that facilitates interconnection of the die with other circuitry, boards, packages, etc. The die can form conductive interconnects with fine pitches and spacing (e.g., less than about 5 micrometers, for example, about 1 micrometer, etc.), which can be densely arranged and exposed on the die's surface. These finely spaced interconnects can be designed to be electrically coupled to similarly finely spaced interconnects in a redistribution layer (RDL), which are electrically coupled to a relatively coarse set of interconnects (fan-out) in the RDL suitable for interconnection with other circuitry, boards, packages, etc. In many cases, the RDL can be formed as one or more metallization layers using photolithography or similar processes. In some embodiments including fan-out packages, the electrical contacts of the RDL can be coarser than the contacts on the component (e.g., the die) and can extend beyond the footprint of the component (e.g., the die). In other embodiments, the package can include a fan-in package, where the electrical contacts of the RDL can be disposed within the footprint of the component (e.g., the die).

[0028] One method of providing an RDL involves wafer-level packaging, in which a die (e.g., an integrated circuit) is monomerized from a wafer on which a die (e.g., an integrated circuit) is formed, and then the die is attached to a carrier using an adhesive or the like. An outer mold can be applied to at least partially cover the carrier between the dies (and in some cases, to cover all or part of the exposed surfaces of the dies) to form a reconstructed substrate (which may include a reconstructed wafer or panel), which may be further processed, such as forming one or more RDL layers for fan-out electrical connections. RDL pads can be fabricated to be larger and / or have a greater pitch than the pads on the die by being spread over adjacent molded parts. However, in some cases, the die may shift position on the carrier during the overmolding process. In those cases, the adhesive may not be able to firmly hold the die in its placement position when the outer mold is applied. Even a small die shift can cause the photomask of the fan-out metallization layer to not match or align with the fine-pitch interconnects on the die. In some cases, increasing the pitch of die interconnects can address die misalignment; however, this can constrain the pitch (and the die coverage area) to a size larger than is desirable for many applications. Furthermore, in some arrangements, components or dies tend to be pressed into a relatively soft adhesive. When the adhesive and carrier are removed (e.g., by UV release), a small step may remain between the component (e.g., die) and the molding compound because the adhesive (now released) is higher than the die. This step creates problems for the RDL formed on the previously covered surface, as the RDL dielectric must be thick enough to overcome this step and form a reliable connection. This, in turn, results in high aspect ratio vias to be filled.

[0029] In the embodiments disclosed herein, the die can be bonded to the carrier using various direct bonding techniques, including direct dielectric bonding, adhesive-free techniques (such as... ) or hybrid bonding techniques (such as Both are available from Invensas Bonding Technologies, Inc. (formerly known as Ziptronix, Inc.), a subsidiary of Xperi Corp. Bonding includes a spontaneous process that occurs under ambient conditions when two prepared surfaces (such as the bonding surface of a die and the prepared surface of a carrier) are placed together (see, for example, U.S. Patent Nos. 6,864,585 and 7,485,968, the entire contents of which are incorporated herein by reference). In some examples, such as when the die is bonded with the die arranged "face down," the corresponding mating surfaces of the bonding die and carrier may include a finely spaced conductive interconnect structure of the die.

[0030] When bonding a die to a carrier using direct or hybrid bonding techniques, it is desirable that the surfaces of both the die and the carrier be extremely flat and smooth. For example, generally, the surfaces should have very low variations in surface topology (i.e., nanoscale variations, e.g., less than 2 nm, preferably less than 0.5 nm) to allow for a tight fit and durable bond. Various conventional processes, such as chemical mechanical polishing (CMP), can be used to achieve low surface roughness. Typically, it is also desirable that the surface be clean and contain few impurities, particles, or other residues that are large enough to introduce bonding voids that could cause electrical continuity failures or other bonding defects.

[0031] In the various embodiments disclosed herein, under environmental conditions and using non-interventional adhesives (such as, for example, or Direct bonding technology bonds the die to a carrier, allowing the die to be locked in place on the wafer and remain coplanar. Under this locking condition, the die cannot be displaced during overmolding or any other process step. Therefore, the photolithographic mask used for the fan-out metallization layer is highly likely to match and align with the fine-pitch interconnects on the die, which can be formed with the pitch as fine as desired for the intended application.

[0032] In various implementations, the die can be processed simultaneously with bonding to the carrier. For example, this processing may include overmolding, adding a metal fan-out layer (e.g., RDL), and monomerization with or without removal of the carrier. In some implementations, holes or openings (e.g., cavities) can be formed in the molded part, and these holes or openings may be filled with a metallic or other conductive material to form vias, contact pads, etc.

[0033] Following processing, the carrier can be thinned, etched, or ground away. In one implementation, carrier removal can expose metal interconnects on the die surface for use by the RDL (e.g., when the die is bonded "face-down"). Additional wiring layers can be added to the exposed metal interconnects if needed. In the case of carrier removal, added vias may also be exposed on the die or molded surface. In some implementations, a portion of the carrier can be allowed to remain bonded to the die to act as a heatsink, handle, or structural support. Before or after carrier removal, the die can be monolithically separated at the molded area outside the die's periphery to form the desired package arrangement.

[0034] Figures 1A to 1I The illustration shows a face-up method for forming a microelectronic component 1 according to various embodiments. Figure 1AThis is a schematic side view of the carrier 2 according to various embodiments. The carrier 2 may include any suitable support structure, such as an integrated device die, interposer, packaging substrate, electronic device, optical device, wafer, glass substrate, silicon-on-insulator (SOI) substrate, etc., to which the die can be directly bonded. Using silicon, glass, or other semiconductor materials as the carrier 2 advantageously allows the carrier 2 to be polished to a very low surface roughness for direct bonding to other components, such as integrated device dies. However, in other embodiments, the carrier 2 may include a substrate of other materials (e.g., a ceramic substrate, polymer substrate, or any other suitable substrate) on which a direct bonding layer of a suitable material can be formed or polished. In some embodiments, the carrier 2 may include an active electronic circuit system. In other embodiments, the carrier 2 may not include an active circuit system.

[0035] Figure 1B This is a schematic side view of a partially formed microelectronic assembly 1, which includes multiple elements 3 directly bonded to a carrier 2 without the intervention of an adhesive. Elements 3 may include, for example, thinned integrated device dies. Elements 3 may include any suitable type of element, such as integrated device dies, optics, etc. Elements 3 may include a microelectronic substrate in which one or more active devices are formed. For example, each element 3 may include a processor die, a memory die, a microelectromechanical system (MEMS) die, a passive component, an optics device, or any other suitable type of device die. In various embodiments, circuitry (such as active components like transistors) may be patterned at or near the active surface of the element 3. Although Figure 1B Only three components 3 are shown, but it should be understood that three or more components 3 may be mounted onto the carrier 2. Further, in some embodiments, the appropriate electrical functionality of the components 3 may be tested before mounting them onto the carrier 2. In some embodiments, only known good die (KGD) may be selected for mounting onto the carrier 2. In other embodiments, the electrical functionality of the die is tested after mounting the die 3 onto the carrier 2 or after forming the RDL. Figure 1B Element 3 includes an integrated device die having various active (and / or passive) components. In other embodiments, one or more discrete passive devices may be mounted to the substrate without being formed as part of the integrated device die.

[0036] Component 3 can be attached to carrier 2 using any suitable direct bonding technique, directly bonding to carrier 2 without the need for an adhesive. For example... Figure 1B As shown, for example, element 3 may include a front surface 4 and a rear surface 5, the rear surface being opposite to the front surface 4. Figure 1BIn some embodiments, the rear surface 5 can be directly bonded to the carrier 2, such that the front surface 4 faces away from the carrier 2. In various embodiments, the front surface 4 of the element 2 may include multiple conductive interconnects (e.g., metal pads or traces) to provide electrical communication between the element 3 and other devices. Typically, active circuitry or devices are disposed on or near the front surface 4. In some embodiments, active circuitry or devices may also be disposed on or near the rear surface 5, or between the front surface 4 and the rear surface 5. Figure 1B In this process, the non-conductive field region on the rear surface 5 of element 3 can directly contact the corresponding non-conductive region of carrier 2 and bond directly with it.

[0037] To achieve direct bonding, in some embodiments, the bonding surfaces of element 3 (e.g., back surface 5) and carrier 2 can be prepared for bonding. Element 3 can be planarized and / or polished to a very high smoothness (e.g., surface roughness less than 20 nm, or more specifically, surface roughness less than 5 nm, surface roughness less than 2 nm, or surface roughness less than 0.5 nm). In some embodiments, a bonding layer (e.g., a dielectric such as silicon oxide) can be disposed on the bonding side, for example, on the back surface 5 of element 3 and / or the front surface of carrier 2, and polished to a very high smoothness. In some embodiments, the bonding surfaces can be fluorinated to improve bonding. The bonding surfaces can also include conductive features, such as bonding pads, in various arrangements. In some embodiments, the surfaces to be bonded can be end-capped with a suitable material and activated prior to bonding. For example, in some embodiments, the surfaces to be bonded can be very lightly etched for activation and exposed to a nitrogen-containing solution and end-capped with a nitrogen-containing material. As an example, the surfaces to be bonded can be exposed to ammonia immersion after very slight etching, and / or (with or without separate etching) exposed to nitrogen-containing plasma.

[0038] Once the surfaces are prepared, the non-conductive field region on the rear surface 5 of element 3 can be brought into contact with the corresponding non-conductive region of carrier 2. The interaction of the activated surfaces allows direct bonding between the non-conductive region of element 3 and the corresponding non-conductive region of carrier 2 at room temperature, without the need for an intervening adhesive along the bonding interface 9, without applied external pressure, without applied voltage, and at room temperature. This room temperature, atmospheric pressure, or depressurized bonding can result in a bond strength of approximately 500 mJ / m. 2 At least 1000mJ / m 2 or at least 2000 mJ / m 2 For example, at 500mJ / m 2 Up to 2000mJ / m 2Within a certain range. In various embodiments, the carrier 2 and element 3 can be heated after bonding to strengthen the bonding between non-conductive regions, thereby bonding element 3 to carrier 2. After annealing, the bond strength can be increased to 2000 mJ / m. 2 For example, approximately 2500 mJ / m 2 Further details of the direct bonding process can be found in all of U.S. Patent Nos. 7,126,212; 8,153,505; 7,622,324; 7,602,070; 8,163,373; 8,389,378; 8,735,219; 9,953,941; and 10,204,893, the entire contents of which are incorporated herein by reference for all purposes.

[0039] Figure 1C and Figure 1D The illustration shows the process of molding. Figure 1B An alternative method for forming a microelectronic component 1. For example, Figure 1C This is a schematic side view of a partially formed microelectronic component 1, wherein an outer mold or molding compound 6 is provided on the surface of a carrier 2 located between and around the elements 3. A plate (not shown) may be provided on the front surface 4 of the elements 3, and the molding compound 6 may flow between the plate and the carrier 2 such that the molding compound 6 does not fill the space or gap between adjacent elements 3 and under the plate. Thus, the molding compound 6 may be applied to the area surrounding the elements 3 on the exposed surface of the carrier 2. Further, as shown, the molding compound 6 may be disposed along and may contact the side surface 7 of the elements 3, which may be defined by a bulk semiconductor material. The plate may ensure that the upper surface 12 of the molding compound 6 is substantially coplanar or flush with the front surface 4 of the elements 3 (e.g., within 1 μm or within 0.25 μm), while directly bonding the elements 3 to the carrier 2 may ensure that the rear surface 5 is flush with the molding compound 6. For example, in various embodiments, the upper surface 12 of the molding compound 6 may be coplanar with the front surface 4 of the elements 3 within a range of approximately 1 μm. Significantly, because direct bonding replaces the adhesive, the rear surface 13 of the molding compound 6 can be coplanar with the rear surface of the element 3 within approximately 1 μm. In some embodiments, the coplanarity can be within approximately 0.05 μm to approximately 0.15 μm.

[0040] The molding compound 6 may include an organic filler material (such as epoxy resin, resin, etc.) that can be in a flowable state where the molding compound 6 flows between the elements 3. The molding compound 6 may be cured to form a hardened or cured state. In various embodiments, the molding compound may include an epoxy resin, for example, an epoxy resin having filler particles (e.g., silica filler particles). As explained above, in other processes in which the element 3 is bonded to the carrier 2 using an adhesive, the overmolding process may cause the element 3 to shift, which can cause misalignment when pads are attached to the fan-out metallization layer. Advantageously, the embodiments disclosed herein avoid such lateral shift of the element 3 during overmolding because the direct bonding between the element 3 and the carrier 2 effectively locks the element 3 laterally in place. Moreover, as explained above, direct bonding advantageously avoids the use of an adhesive, which can prevent steps and loss of coplanarity due to the element 3 sinking into the adhesive.

[0041] exist Figure 1D In the variant shown, conductive interconnects 8 (e.g., pads) can be provided on the front surface 4 of component 3 and can extend thereover there. Figure 1D In this configuration, a plate can be provided on top of the conductive interconnect 8, and the molding compound 6 can flow over the region surrounding the element 3 on the surface of the carrier 2. Figure 1C Similarly, in Figure 1D In this process, the molding compound 6 can extend along and contact the side surface 7 of the element 3. Furthermore, the molding compound 6 can flow between adjacent conductive interconnects 8 at the front surface 4 of the element 3. Figure 1C As shown, the direct bonding between element 3 and carrier 2 prevents element 3 from shifting during overmolding. It also prevents the formation of steps between element 3 and molding compound 6.

[0042] Go to Figure 1EA redistribution layer (RDL) 10 may be provided over the upper surface 12 of the molding compound 6 and the front surface 4 of the element 3. The RDL 10 may include a first surface 13 having finely spaced electrical interconnects (not shown) that are electrically coupled at the front surface 4 of the element 3 to similarly finely spaced conductive interconnects (such as interconnects 8). The finely spaced interconnects of the RDL 10 may be electrically connected to a relatively coarse set of interconnects (fan-out) at a second surface 14 of the RDL 10. The relatively coarse set of interconnects may be suitable for interconnection with other circuits, boards, packages, etc. In many cases, the RDL 10 may be formed as one or more metallization layers using a photolithography process. In other embodiments, the RDL 10 may be part of a structure directly bonded to the front surface 4 of the element 3 without the intervention of an adhesive. In various embodiments, the RDL 10 may be electrically connected to other devices stacked on one or more elements 3. In some embodiments, adjacent elements 3 may remain adjacent to each other after monomerization and be connected together to RDL 10. In this case, RDL 10 may electrically interconnect adjacent elements 3, such as a first microelectronic substrate and a second microelectronic substrate.

[0043] therefore, Figure 1E The RDL 10 allows electrical signals to fan out from finely spaced interconnects on the front surface 4 of element 3 to coarser interconnects on the second surface 14 of RDL 10. For example, the interconnects (such as interconnects 8) on the front surface 4 of element 3 can be spaced less than 20 μm, less than 15 μm, or less than 5 μm, for example, in the range of 1 μm to 20 μm. The spacing of the coarser interconnects on the second surface 14 of RDL 10 may be in the range of 5 μm to 20 μm. Furthermore, due to the coplanarity provided by direct bonding, RDL 10 can be made thinner than RDLs of other technologies. For example, the RDL 10 of the disclosed embodiments may include a metal layer on or within a dielectric layer that is less than about 5 μm, such as 1 μm to 4 μm, or in some embodiments, less than about 1 μm. Moreover, the pitch of the RDL metal lines is very fine using current RDL metallization techniques, such as about 10 μm, but may be even finer for future technologies, given the precision provided by direct bonding.

[0044] Go to Figure 1F The rear side 15 of carrier 2 can be removed (see...) Figure 1E At least a portion of ) to form the flattened rear side 15' (see Figure 1F ).exist Figure 1FIn some embodiments, only a portion of the thickness of carrier 2 is removed. The remaining portion of carrier 2 can be used as at least one of the following: a heat sink, a handle, or a structural support. In various embodiments, at least a portion of the rear side 15 can be removed by grinding, etching, polishing, or any other suitable removal technique. In other embodiments, carrier 2 can be sacrificial, allowing the entire carrier 2 to be removed from the molding compound 6 and element 3. In embodiments where the entire carrier 2 has been removed, the bonding layer of element 3 (such as a silicon oxide layer) and / or molding compound 6 can be used as a stop to the removal process (e.g., an etching stop, etc.). In any case, at least partial removal of carrier 2 can result in a flat rear side of microelectronic component 1 (e.g., a flattened rear side 15' of carrier 2 or a flat bonding surface of element 3 and a rear surface of molding compound 6). The flat rear side of microelectronic component 1 can be directly bonded to other devices or elements without the intervention of adhesives.

[0045] exist Figure 1G In this process, microelectronic component 1' can be monomerized via carrier 2 and molding compound 6 to form multiple microelectronic components 1. For example, microelectronic component 1' can be monomerized by sawing through carrier 2 and molding compound 6, or by sawing through molding compound 6 only if carrier is completely removed. After monomerization, molding compound 6 and RDL 10 may include one or more monomerized side surfaces 17, which include markings indicating the monomerization process. For example, monomerized side surfaces 17 may include saw marks. It should be understood that, although Figure 1G Each monolithic microelectronic component 1 includes a single element 3, but in other arrangements, component 1 may include multiple elements 3 to form a system-in-package. For example, component 1 may include multiple elements 3 stacked on top of each other and / or arranged laterally adjacent to each other.

[0046] Figure 1H The illustration shows an arrangement in which the carrier 2 has been completely removed from the molding compound 6 and the element 3. In some embodiments, in addition to the bonding layer, which may include conductive interconnects embedded in non-conductive or dielectric regions, most of the carrier 2 can be removed. Prior to monomerization, for example, in Figure 1G Before the steps shown, carrier 2 can be removed. In other embodiments, carrier 2 can be removed after monomerization. Figure 1H In this configuration, each monolithic microelectronic component 1 can be connected to other structures. For example, each microelectronic component 1 can be electrically connected to other structures on the top or bottom surface of component 1. For instance, the RDL 10 on the top surface of microelectronic component 1 can be electrically connected (e.g., by wire bonding, flip-chip bonding, or direct hybrid bonding) to other structures, such as other packages, other carriers, other device dies, etc. See, for example. Figure 1JThe following text describes it in detail.

[0047] Furthermore, the rear surface 5 of element 3 can also be electrically connected (e.g., directly bonded) to other structures. In such an arrangement, the rear surface 5 of element 3 can be electrically connected (e.g., directly bonded) to other structures, such as other packages, other dies, other carriers, etc. For example, in various embodiments, a monolithic package or microelectronic assembly 1 may include multiple elements (e.g., dies) that can be electrically connected to each other by means of conductive traces and contacts of RDL 10. In some embodiments, the rear surface 5 may include a bonding layer comprising a non-conductive field region defining conductive interconnects therein or on it. The bonding layer (e.g., non-conductive field region and conductive interconnect) can be directly bonded to corresponding non-conductive field regions and conductive interconnects of other structures without the intervention of adhesives. In various embodiments, for example, a bonding layer can be provided at the rear surface 5 of element 3 by providing the bonding layer at the rear surface 5. In other embodiments, the bonding layer of carrier 2 (which may include non-conductive field regions and conductive contacts) may be retained after at least a portion of carrier 2 has been removed. In this arrangement, the remaining bonding layer of carrier 2 can be used for electrical connections to other structures. In yet another embodiment, in which a portion of carrier 2 remains connected to element 3 and molding compound 6, carrier 2 can serve as an intermediary layer for connection to other structures.

[0048] Figure 1I This is a schematic side view of a plurality of microelectronic components 1 including via 11, which extends from RDL 10 through molding compound 6 to the rear surface of molding compound 6. Therefore, the illustrated via 11 can be referred to as a through-mold via. To form via 11, one or more cavities can be formed (e.g., etched), and conductive material can be provided in the cavities to form a conductive via 11. Via 11 can provide electrical communication between RDL 10 and other structures (not shown), which can be electrically connected to the rear side of molding compound 6 and component 3. It can be used with... Figure 1E The RDL layer 10 shown also forms vias 11. Advantageously, using through-substrate vias 11 may be less expensive and less complex to manufacture than through-substrate vias (e.g., vias through element 3). In some embodiments, element 3 may not include through-substrate vias. In other embodiments, element 3 may include through-substrate vias.

[0049] For example, such as Figure 1J As shown, the microelectronic component 1' may include multiple elements 3 stacked on top of each other. For example, in Figure 1JIn some embodiments, elements 3 can be stacked prior to monomerization. Additional elements 3 can be stacked on top of the underlying element 3 and directly bonded to RDL 10. As explained above, molding compounds can be applied between adjacent elements 3, and RDL 10 can be provided on top of the stacked structure. In various embodiments, adjacent molding compounds can be bonded using any suitable technique, such as thermoforming, direct bonding without adhesives, etc. In various embodiments where molding compound 6 is directly bonded to vertically adjacent molding compounds, a bonding layer (such as a silicon oxide bonding layer) can be applied between adjacent portions of molding compound 6.

[0050] In another embodiment, two reconstructed wafers can be formed, including the formation of RDLs, and directly and hybridically bonded to each other. Any suitable number of elements 3 can be stacked on top of each other. Subsequently, as... Figure 1K As shown, component 1' can be modularized into multiple modular microelectronic components 1. Furthermore, as described above, in some embodiments, the carrier 2 can be completely removed, such as... Figure 1K The carrier shown. In other embodiments, at least a portion of the carrier 2 may remain bonded to the underlying element 3. Although Figure 1J The illustration shows stacked elements 3, but in other embodiments, elements 3 may not be stacked. For example, in other embodiments, the monolithized component 1 may include laterally spaced elements 3 after monolithization, or may include only one element 3.

[0051] Figures 2A to 2H The illustration shows a face-down method for forming a microelectronic component 1 according to various embodiments. Unless otherwise stated, Figures 2A to 2H The components can be with Figures 1A to 1I Components with the same number are identical or substantially similar. For example, with Figure 1A Same, Figure 2A Carrier 2 is provided. As explained above, carrier 2 can provide any suitable carrier. Figure 2B In this process, multiple components 3 can be directly bonded to the carrier 2. However, with Figure 1B The implementation methods differ, in Figure 2B In this configuration, the front surface 4 of element 3 can be directly bonded to the carrier 2 without the need for an adhesive. As explained above, the front surface 4 of element 3 may include conductive interconnects. Figure 2B (Not shown in the image), the conductive interconnect is embedded in or surrounded by a non-conductive field region. The conductive interconnect and the non-conductive field region can be directly mixed and bonded to the corresponding conductive interconnect and the non-conductive field region of the carrier 2 along the bonding interface 9. Therefore, in Figure 2B In this configuration, the front surface 4 of element 3 can face and be directly bonded to carrier 2, while the rear surface 5 can be away from carrier 2.

[0052] Go to Figure 2C The molding compound 6 can be applied over the element 3 and over the area of ​​the carrier 2 located between adjacent elements 3. As described, the molding compound 6 can be applied along the upper surface of the carrier 2 and along the side surface 7 of the element 3. In various embodiments, the molding compound 6 may include a filler material, such as a curable epoxy resin. Advantageously, as explained above, using direct bonding to mount the element 3 to the carrier 2 can prevent lateral displacement of the element during overmolding and can contribute to the coplanarity of the molding compound with the element surface.

[0053] exist Figure 2D During the thinning process, element 3 and molding compound 6 can be thinned. For example, in various embodiments, the rear surface 5 of element 3 and the upper surface 12 of molding compound 6 can be ground, milled, or thinned to form a thinned rear surface 5' of element 3 and upper surface 12' of molding compound 6. Figures 1A to 1K As in the previous embodiment, the rear surface 5' of element 3 can be substantially coplanar with the upper surface 12' of molding compound 6, while direct bonding also contributes to the coplanarity between the lower surface 13' of molding compound 6 and the front surface 4 of element 3. Coplanarity can be, for example, within about 1 μm, e.g., within 0.1 μm.

[0054] Go to Figure 2E At least a portion of the carrier 2 can be removed from the front surface 4 of the element 3 and the lower surface of the molding compound 6. In some embodiments, the carrier 2 can be completely removed, for example, removing the oxide layer other than the natural oxide layer on the upper surface of the carrier 2. In some embodiments, the carrier 2 can be removed, for example, by etching. In such an arrangement, the natural oxide layer can be used as a stop for the removal process (e.g., an etching stop). The thickness of the remaining natural oxide layer can be less than 5 nm, for example, 2 nm or less. In other embodiments where the carrier 2 includes a relatively thick bonding layer (such as an oxide layer), most of the carrier 2 (e.g., a silicon substrate) can be removed, leaving the bonding layer bonded to the element 3 and the molding compound 6. In such an arrangement, the bonding layer can include contacts or traces within the oxide layer (or other dielectric layer) to serve as a wiring layer that can be connected to the structure beneath the front surface 4 of the element 3. Once at least a portion of the carrier 2 has been removed, the exposed front surface 4 can be flat, for example, having a surface roughness of less than about 1 micrometer. Moreover, as noted above, the front surface of element 3 can be substantially coplanar with the exposed lower surface 13' of molding compound 6.

[0055] exist Figure 2F In this context, RDL 10 can be provided above the front surface 4 of element 3 and above the lower surface 13' of molding compound 6. RDL 10 is in conjunction with the above. Figures 1A to 1KThe described RDL 10 is largely similar and can provide a fan-out electrical connection from relatively fine-pitch contacts on element 3 to relatively coarse-pitch contacts on the lower surface of RDL 10. Figure 2G middle, Figure 2F The partially formed microelectronic component 1' can be related to the above-mentioned microelectronic components. Figures 1A to 1K The same method explained is used to monomerize multiple microelectronic components 1. For example, molding compound 6 and RDL 10 may include one or more side surfaces 17 having markings indicating the monomerization process, such as saw marks. Further, as Figure 2H As shown, in some embodiments, multiple through-holes 11 may be provided to provide electrical connectivity through the molding compound 6. The microelectronic components 1 of Figures 2I to 2J can be stacked or arranged in any other combination, as described above regarding... Figures 1A to 1K The explanation given.

[0056] Figure 3 This is a schematic diagram of a system 80 incorporating one or more microelectronic components 1 according to various embodiments. System 80 may include any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, tablet computer, laptop computer, etc.), a desktop computer, an automobile or a component thereof, a stereo system, a medical device, a camera, or any other suitable type of system. In some embodiments, the electronic device may include a microprocessor, a graphics processor, an electronic recording device, or digital memory. System 80 may include one or more device packages 82, which are mechanically and electrically connected to system 80, for example, by means of one or more motherboards. Each package 82 may include one or more microelectronic components 1. Figure 3 The microelectronic component 1 shown may include the above-described combination of... Figures 1A to 2H Any of the microelectronic components shown and described in microelectronic component 1. Microelectronic component 1 may include one or more integrated device dies that perform various functions for system 80.

[0057] In one embodiment, a method for forming a microelectronic component is disclosed. The method may include: bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without the intervention of an adhesive, the microelectronic substrate having a plurality of conductive interconnects on at least one surface of the microelectronic substrate. The method may include: applying a molding material to a region of the carrier surrounding the surface of the microelectronic substrate to form a reconstructed substrate. The method may include: processing the microelectronic substrate. The method may include: monomerizing the reconstructed substrate at a region on the surface of the carrier and at the molding material to form the microelectronic component.

[0058] In another embodiment, a microelectronic component is disclosed. The microelectronic component may include an element having a front surface and a rear surface opposite to the front surface, at least one of the front and rear surfaces including a planarized direct-bonding surface. The microelectronic component may include a molding compound disposed around the element along a side surface of the element, the molding compound including a first surface and a second surface opposite to the first surface. The microelectronic component may include a redistribution layer (RDL) disposed over and electrically connected to the front surface of the element. The first surface of the molding compound may be substantially coplanar with the planarized direct-bonding surface.

[0059] In another embodiment, a method for forming a microelectronic component is disclosed. The method may include: directly bonding a first surface of a component to a carrier without the intervention of an adhesive, the component having a plurality of exposed conductive interconnects on at least one surface of the component. The method may include: applying a molding compound around the component and along the side edges of the component. The method may include: providing a redistribution layer (RDL) on and electrically connected to at least one surface of the component. The method may include: monomerizing via the RDL and the molding compound to form the microelectronic component.

[0060] In order to summarize the disclosed embodiments and advantages relative to prior art implementations, certain objects and advantages have been described herein. It should be understood, of course, that not all of these objects or advantages may necessarily be achieved according to any particular embodiment. Therefore, for example, those skilled in the art will recognize that the disclosed implementations may be embodied or performed in a manner that implements or optimizes one or more of the objects or advantages taught or suggested herein, without necessarily achieving other objects or advantages that may be taught or suggested herein.

[0061] All these embodiments are intended to be within the scope of this disclosure. These and other embodiments will become apparent to those skilled in the art from the following detailed description of the embodiments with reference to the accompanying drawings, and the claims are not limited to one or more of any particular embodiments disclosed. Although certain embodiments and examples have been disclosed herein, it will be understood by those skilled in the art that the disclosed implementations extend beyond the specific disclosed embodiments to other alternative embodiments and / or uses and their obvious modifications and equivalents. Furthermore, although several variations have been shown and described in detail, other modifications will be apparent to those skilled in the art based on this disclosure. It is also contemplated that various combinations or sub-combinations of specific features and aspects of the embodiments may be made, and these still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments may be combined or substituted with each other to form variations of the disclosed implementations. Therefore, it is intended that the scope of the subject matter disclosed herein should not be limited to the specific disclosed embodiments described above, but should be determined only by a fair reading of the appended claims.

Claims

1. A method for forming a microelectronic component, comprising: Using direct bonding technology, at least one first surface of a microelectronic substrate is bonded to the surface of a carrier without the need for an adhesive, wherein the microelectronic substrate has a plurality of conductive interconnects on at least one surface of the microelectronic substrate. A molding material is applied to the region surrounding the microelectronic substrate on the surface of the carrier to form a reconstructed substrate; After the reconstruction substrate is formed, the microelectronic substrate is thinned from a second surface of the at least one microelectronic substrate opposite to the first surface to form a thinned microelectronic substrate having a thinned surface opposite to the first surface. Remove the carrier from the thinned microelectronic substrate; as well as After the carrier is removed from the thinned microelectronic substrate, the reconstructed substrate is monolithized using the molding material and around the outer periphery of the thinned microelectronic substrate to form the microelectronic component.

2. The method for forming a microelectronic component according to claim 1, further comprising: Planarization is performed on the first surface of the microelectronic substrate and / or the surface of the carrier in preparation for the direct bonding technique.

3. The method for forming a microelectronic component according to claim 1, wherein bonding the microelectronic substrate to the surface of the carrier comprises: The plurality of conductive interconnects are positioned away from the surface of the carrier.

4. The method for forming a microelectronic component according to claim 1, wherein bonding the microelectronic substrate to the surface of the carrier comprises: The plurality of conductive interconnects are oriented toward the surface of the carrier.

5. The method for forming a microelectronic component according to claim 1, further comprising: The molding material is applied to at least a portion of the second surface of the microelectronic substrate.

6. The method for forming a microelectronic component according to claim 1, further comprising: One or more cavities are formed in the molding material, and the one or more cavities are filled with a conductive material to form one or more conductive vias.

7. The method for forming a microelectronic component according to claim 1, further comprising: Without the need for adhesives, the direct bonding technique prevents the microelectronic substrate from shifting position relative to the surface of the carrier during the thinning process.

8. The method for forming a microelectronic component according to claim 1, further comprising: A redistribution layer (RDL) is formed, which is coupled to a plurality of exposed conductive interconnects.

9. The method of forming a microelectronic component according to claim 8, further comprising at least a first microelectronic substrate and a second microelectronic substrate, wherein the redistribution layer electrically interconnects the first microelectronic substrate and the second microelectronic substrate.

10. The method for forming a microelectronic component according to claim 1, wherein the carrier comprises a sacrificial carrier.

11. The method for forming a microelectronic component according to claim 10, further comprising: A wiring layer is added to the thinned surface.

12. The method of forming a microelectronic component according to claim 1, wherein the spacing between adjacent interconnects of the plurality of conductive interconnects on the microelectronic substrate is less than 5 micrometers.

13. The method for forming a microelectronic component according to claim 5, further comprising: Remove the molding material on the microelectronic substrate to expose a portion of the second surface.

14. A method for forming a microelectronic component, comprising: In a process whereby a first surface of a component is directly bonded to a carrier without the need for an adhesive, the component having a plurality of exposed conductive interconnects on at least one surface of the component; A reconstructed substrate is formed on the surface of the carrier, wherein the reconstructed substrate includes the element and a molding material, wherein the molding material is located on the surface of the carrier and surrounds the element; The element is thinned from a second surface opposite to the first surface to form a thinned element having a thinned surface opposite to the first surface; A redistribution layer (RDL) is provided on at least one surface of the element and is electrically connected to at least one surface of the element; Remove at least a portion of the carrier; as well as After removing at least a portion of the carrier, the microelectronic component is monolithized through the redistribution layer and around the periphery of the thinned element using the molding material to form the microelectronic component.

15. The method of claim 14, further comprising: With the plurality of exposed conductive interconnects facing away from the carrier, the element is bonded to the carrier.

16. The method of claim 14, further comprising: With the plurality of exposed conductive interconnects facing the carrier, the element is bonded to the carrier.

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