Semiconductor memory devices

Abstract

A semiconductor memory device includes: a substrate having a cell region and a contact region, the contact region having a peripheral circuit region; a first stack and a second stack on the cell region; and a first peripheral transistor on the peripheral circuit region. Each of the first stack and the second stack includes: a semiconductor pattern stacked on the cell region in a vertical direction; a bit line stacked on the cell region in a vertical direction and connected to a first end of the semiconductor pattern, each bit line extending from the cell region to the contact region in a horizontal direction relative to an upper surface of the substrate; and a word line disposed adjacent to the semiconductor pattern and extending from the cell region of the substrate in a vertical direction. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

Description

Technical Field

[0001] The present disclosure relates to semiconductor memory devices, and more particularly, to three-dimensional semiconductor memory devices with increased integration density. Background Art

[0002] For excellent performance and low price, higher integration of semiconductor devices is desired. In the case of semiconductor devices, since their integration is an important factor in determining the price of the product, increased integration is particularly desired. In the case of two-dimensional or planar semiconductor devices, since their integration is mainly determined by the area occupied by the unit memory cell, the integration is greatly affected by the level of fine pattern formation technology. However, the extremely expensive process equipment required to achieve fine patterns sets practical limitations on increasing the integration of two-dimensional or planar semiconductor devices. In order to overcome these limitations, a three-dimensional semiconductor memory device including a three-dimensionally arranged memory cell has recently been proposed. Summary of the invention

[0003] An embodiment of the inventive concept provides a three-dimensional semiconductor memory device having increased integration density.

[0004] According to an exemplary embodiment of the present invention, a semiconductor memory device includes: a substrate having a cell region and a contact region, the contact region including a peripheral circuit region; a first stack and a second stack on the cell region of the substrate; and a first peripheral transistor on the peripheral circuit region. Each of the first stack and the second stack includes: a semiconductor pattern stacked on the cell region in a vertical direction relative to an upper surface of the substrate; bit lines stacked on the cell region in a vertical direction and respectively connected to a first end of the semiconductor pattern, each bit line extending from the cell region to the contact region in a horizontal direction relative to an upper surface of the substrate; and a word line disposed adjacent to the semiconductor pattern and extending from the cell region of the substrate in a vertical direction. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

[0005] According to an exemplary embodiment of the present invention, a semiconductor memory device includes: a substrate including a cell region and a peripheral circuit region; a stack on the cell region; and a peripheral transistor on the peripheral circuit region. The stack includes: a semiconductor pattern stacked on the cell region in a vertical direction relative to an upper surface of the substrate; bit lines stacked on the cell region in a vertical direction and respectively connected to the semiconductor pattern, each bit line extending in a horizontal direction relative to an upper surface of the substrate; and a word line disposed adjacent to the semiconductor pattern and extending from the cell region in a vertical direction. The peripheral transistor includes an active pattern stacked on the peripheral circuit region in a vertical direction and a peripheral gate electrode disposed adjacent to the active pattern and extending from the peripheral circuit region in a vertical direction.

[0006] According to an exemplary embodiment of the present invention, a semiconductor memory device includes: a substrate having a cell region and a contact region; a first stack and a second stack on the cell region of the substrate; and a peripheral transistor on the contact region. Each of the first stack and the second stack includes: a semiconductor pattern stacked on the cell region in a vertical direction relative to an upper surface of the substrate; a bit line stacked on the contact region in a vertical direction and connected to a first end of the semiconductor pattern, each bit line extending from the cell region to the contact region in a horizontal direction relative to an upper surface of the substrate; and a word line disposed adjacent to the semiconductor pattern and extending from the semiconductor region in a vertical direction. The bit line has a stepped structure on the contact region. The peripheral transistor is disposed between the stepped structure of the first stack and the stepped structure of the second stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0008] Figure 1 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0009] Figure 2 is a perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0010] Figure 3 It is shown Figure 2 A plan view of a semiconductor memory device.

[0011] Figure 4A is along Figure 3 A cross-sectional view taken along line AA'.

[0012] Figure 4B is along Figure 3 A cross-sectional view taken along line BB'.

[0013] Figure 4C is along Figure 3 A cross-sectional view taken along lines CC' and D-D'.

[0014] Figure 4D is along Figure 3 A cross-sectional view taken along line EE'.

[0015] Figures 5 to 8 is along Figure 3 sectional views taken along lines CC′ and DD′ to illustrate a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0016] Fig. 9 is along Figure 3 sectional views taken along lines CC′ and DD′ to illustrate a method of manufacturing a three-dimensional semiconductor memory device according to another embodiment of the inventive concept.

[0017] Fig.10 is along Figure 3 A cross-sectional view taken along line EE'.

[0018] Fig.11 is along Figure 3 A cross-sectional view taken along line D-D'.

[0019] Fig.12 is along Figure 3 A cross-sectional view taken along line D-D'.

[0020] Fig.13A is along Figure 3 A cross-sectional view taken along line D-D'.

[0021] Fig. 13B is along Figure 3 A cross-sectional view taken along line EE'.

[0022] Fig. 13C is a perspective view illustrating a peripheral transistor according to an embodiment of the inventive concept.

[0023] Fig.14 is along Figure 3 A cross-sectional view taken along lines CC' and D-D'.

[0024] Fig.15 is along Figure 3 The cross-sectional view taken along the lines C-C' and D-D' is shown in order to illustrate the manufacturing method according to Fig.14 A method of implementing a three-dimensional semiconductor memory device.

[0025] Fig.16 is a plan view illustrating a semiconductor memory device according to an embodiment of the inventive concept.

[0026] Fig.17A is along Fig.16 A cross-sectional view taken along lines AA' and BB'.

[0027] Fig. 17B is along Fig.16 A cross-sectional view taken along line CC'.

[0028] Fig.18 is along Fig.16 A cross-sectional view taken along line CC'.

[0029] Fig.19is a perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0030] Fig. 20 is along Fig.19 A cross-sectional view taken along line AA'.

[0031] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, these figures are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range of values ​​or performances included in the example embodiments. For example, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0032] Figure 1 is a circuit diagram schematically illustrating a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0033] Reference Figure 1 , a cell array of a three-dimensional semiconductor memory device according to an embodiment of the inventive concept may include a plurality of sub-cell arrays SCA. The sub-cell arrays SCA may be arranged in the second direction D2.

[0034] Each sub-cell array SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cell transistors MCT. Each memory cell transistor MCT may be disposed between a corresponding one of the word lines WL and a corresponding one of the bit lines BL.

[0035] The bit lines BL may be conductive patterns (eg, metal lines) spaced apart from and stacked on the substrate. The bit lines BL may extend in the first direction D1. The bit lines BL in each subcell array SCA may be spaced apart from each other in a vertical direction (eg, a third direction D3).

[0036] The word lines WL may be conductive patterns (eg, metal lines) extending from the substrate in a vertical direction (eg, in the third direction D3 ). The word lines WL in each subcell array SCA may be spaced apart from each other in the first direction D1 .

[0037] The gate electrode of the memory cell transistor MCT may be connected to the word line WL, and the source electrode of the memory cell transistor MCT may be connected to the bit line BL. Each memory cell transistor MCT may include a data storage element DS. In an example embodiment, the data storage element DS may be a capacitor (e.g., a dynamic random access memory (DRAM) cell capacitor). For example, the data storage element DS may include: a first electrode connected to the drain electrode of the memory cell transistor MCT; a second electrode of the capacitor connected to the ground line PP; and a dielectric layer interposed between the first electrode and the second electrode.

[0038] Figure 2 is a perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Figure 3 It is shown Figure 2 A plan view of a semiconductor memory device. Figure 4A is along Figure 3 A cross-sectional view taken along line AA'. Figure 4B is along Figure 3 A cross-sectional view taken along line BB'. Figure 4C is along Figure 3 A cross-sectional view taken along lines CC' and D-D'. Figure 4D is along Figure 3 A cross-sectional view taken along line EE'.

[0039] Reference Figure 2 , Figure 3 and 4A to 4D , a substrate SUB including a cell region CAR and a contact region CTR may be provided. A first interlayer insulating layer ILD1 may be provided on the substrate SUB. The substrate SUB may be a silicon wafer, a germanium wafer, or a silicon germanium wafer.

[0040] The first to fourth stacks SS1-SS4 may be provided on the cell region CAR of the substrate SUB (eg, see Figure 3 ). The first to fourth stacks SS1-SS4 may be vertically spaced apart from the substrate SUB, and the first interlayer insulating layer ILD1 may be interposed therebetween. The first to fourth stacks SS1-SS4 may extend in the first direction D1 and may be parallel to each other. The first to fourth stacks SS1-SS4 may be arranged in the second direction D2. Each of the first to fourth stacks SS1-SS4 may include the previously referenced Figure 1 Describe the subcell array SCA.

[0041] Each of the first to fourth stacks SS1-SS4 may include semiconductor patterns SP and insulating layers IL alternately stacked on the cell region CAR. In each of the first to fourth stacks SS1-SS4, the semiconductor patterns SP may be vertically spaced apart from each other by the insulating layers IL. Each of the insulating layers IL may be interposed between a corresponding pair of semiconductor patterns vertically adjacent to each other among the semiconductor patterns SP. The insulating layer IL may be formed of at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon, or may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxide containing carbon, silicon nitride containing carbon, and silicon oxynitride containing carbon.

[0042] Each semiconductor pattern SP may be a linear, stripe or columnar pattern extending in the second direction D2. In one embodiment, the semiconductor pattern SP may be formed of or include at least one of silicon, germanium, silicon germanium and indium gallium zinc oxide (IGZO). In one embodiment, the semiconductor pattern SP may be formed of or include single crystal silicon. Each semiconductor pattern SP may include a first impurity region SD1, a second impurity region SD2 and a channel region CH.

[0043] The channel region CH may be provided between the first impurity region SD1 and the second impurity region SD2. The first impurity region SD1 and the second impurity region SD2 may be doped to have a first conductivity type (e.g., n-type). The channel region CH may be undoped or may be doped to have a second conductivity type (e.g., p-type) different from the first conductivity type.

[0044] The channel region CH may correspond to Figure 1 The first impurity region SD1 and the second impurity region SD2 may correspond to the channel region of the memory cell transistor MCT. Figure 1 The source electrode and the drain electrode of the memory cell transistor MCT.

[0045] The semiconductor pattern SP may be provided on the unit area CAR of the substrate SUB. For example, each of the first to fourth stacks SS1-SS4 may include first to fourth rows R1-R4 of semiconductor patterns SP. Each of the first to fourth rows R1-R4 may include semiconductor patterns SP vertically stacked to overlap each other. Although each of the first to fourth rows R1-R4 is shown as having six vertically stacked semiconductor patterns SP, the inventive concept is not limited to this example. The first to fourth rows R1-R4 may be spaced apart from each other in the first direction D1.

[0046] Each of the first to fourth stacks SS1-SS4 may further include first conductive lines CL1 vertically stacked on the substrate SUB. In each of the first to fourth stacks SS1-SS4, the first conductive lines CL1 may be vertically spaced apart from each other by the insulating layer IL. Each insulating layer IL may be interposed between a corresponding pair of first conductive lines vertically adjacent to each other among the first conductive lines CL1.

[0047] The first conductive line CL1 may be provided to have a linear or bar structure extending in the first direction D1. The first conductive line CL1 may extend from the cell region CAR of the substrate SUB to the contact region CTR.

[0048] The first conductive lines CL1 may be in direct contact with the semiconductor patterns SP, respectively. As an example, each first conductive line CL1 may be positioned at substantially the same height as a corresponding one of the semiconductor patterns SP connected thereto. In an example embodiment, each first conductive line CL1 may be in contact with a first end of a corresponding one of the semiconductor patterns SP. Unless the context otherwise indicates, the term "contact" as used herein refers to direct connection (i.e., touching). Each first conductive line CL1 may be connected to a first impurity region SD1 of a corresponding one of the semiconductor patterns SP. Each semiconductor pattern SP in the first to fourth rows R1-R4 located at the same height as a corresponding one of the first conductive lines CL1 may extend from the first conductive line CL1 in the second direction D2.

[0049] Reference Figure 4B , each of the first to fourth stacks SS1-SS4 may have a stepped structure on the contact region CTR of the substrate SUB. In other words, the first conductive line CL1 stacked on the contact region CTR may have a stepped structure. The length of the first conductive line CL1 in the first direction D1 may decrease as the distance from the top surface of the substrate SUB increases. For example, the length of the lowest first conductive line among the first conductive lines CL1 may be longer than the lengths of the other first conductive lines. The length of the highest first conductive line among the first conductive lines CL1 may be shorter than the lengths of the other first conductive lines.

[0050] The contact CNT may be provided on the stepped structure of the first conductive line CL1. One end of each first conductive line CL1 may be exposed through the stepped structure. The contact CNT may be connected to the first conductive lines CL1, respectively. Each contact CNT may be connected to an exposed end of a corresponding one of the first conductive lines CL1.

[0051] The first conductive line CL1 may be formed of or include a conductive material. For example, the conductive material may be one of a doped semiconductor material (doped silicon, doped germanium, etc.), a conductive metal nitride (titanium nitride, tantalum nitride, etc.), a metal material (tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, etc.). The first conductive line CL1 may be used as a reference. Figure 1 The bit line BL is described.

[0052] Each of the first to fourth stacks SS1-SS4 may further include a data storage element DS vertically stacked on the cell region CAR of the substrate SUB. The data storage elements DS stacked on the substrate SUB may be vertically spaced apart from each other by the insulating layer IL. Each data storage element DS may extend in the second direction D2 from the semiconductor pattern SP connected thereto.

[0053] Each data storage element DS may be in direct contact with the semiconductor pattern SP connected thereto. As an example, each data storage element DS may be located at substantially the same height as the semiconductor pattern SP connected thereto. In an example embodiment, each data storage element DS may be in contact with a second end of a corresponding one of the semiconductor patterns SP opposite to the first end. The data storage element DS may be connected to the second impurity region SD2 of the semiconductor pattern SP.

[0054] Reference Figure 4A Each data storage element DS may include a first electrode EL1, a dielectric layer DL, and a second electrode EL2. For example, the data storage element DS according to an embodiment of the inventive concept may be a capacitor (eg, a DRAM cell capacitor).

[0055] The first electrode EL1 may be directly connected to the second impurity region SD2 of the semiconductor pattern SP. The first electrode EL1 may have a hollow cylindrical shape. The first electrode EL1 may be formed of at least one of a metal material, a metal nitride, and a metal silicide, or include at least one of a metal material, a metal nitride, and a metal silicide. For example, the first electrode EL1 may be formed of at least one of a refractory metal (e.g., cobalt, titanium, nickel, tungsten, or molybdenum), or include at least one of a refractory metal (e.g., cobalt, titanium, nickel, tungsten, or molybdenum). The first electrode EL1 may be formed of at least one of a metal nitride (e.g., titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, or tungsten nitride), or include at least one of a metal nitride (e.g., titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, or tungsten nitride).

[0056] The dielectric layer DL may be interposed between the first electrode EL1 and the second electrode EL2. The dielectric layer DL may be provided to directly cover the inner surface of the first electrode EL1. For example, the dielectric layer DL may be made of a metal oxide (e.g., hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide, and titanium oxide) and a perovskite dielectric material (e.g., SrTiO 3 (STO), ((Ba, Sr)TiO 3 (BST), BaTiO 3 , PZT and PLZT), or includes metal oxides (e.g., hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, tantalum oxide and titanium oxide) and perovskite dielectric materials (e.g., SrTiO 3 (STO), (Ba, Sr)TiO 3 (BST), BaTiO 3 , PZT and PLZT).

[0057] The second electrode EL2 may be provided on the dielectric layer DL. The second electrode EL2 may be provided to fill the cylindrical inner space of the first electrode EL1. The second electrode EL2 may be connected to a third conductive line CL3 to be described below. The second electrode EL2 may be formed of or include at least one of doped silicon, a metal material, a metal nitride, and a metal silicide. As an example, the second electrode EL2 may include substantially the same material as the first electrode EL1.

[0058] The second conductive line CL2 may be provided on the cell region CAR of the substrate SUB to penetrate the first to fourth stacks SS1-SS4. The second conductive line CL2 may be a column or bar pattern extending in a direction perpendicular to the top surface of the substrate SUB (ie, in the third direction D3).

[0059] For example, refer to Figure 3 and Figure 4C , the second conductive lines CL2 penetrating the third stack SS3 may be arranged in the first direction D1. The second conductive lines CL2 penetrating the third stack SS3 may be disposed adjacent to the first to fourth rows R1-R4 of the third stack SS3, respectively. A first pair of second conductive lines among the second conductive lines CL2 penetrating the third stack SS3 may be adjacent to the side surface of the semiconductor pattern SP of the first row R1. The first pair of second conductive lines may extend vertically on the side surface of the semiconductor pattern SP of the first row R1. A second pair of second conductive lines among the second conductive lines CL2 penetrating the third stack SS3 may be adjacent to the side surface of the semiconductor pattern SP of the second row R2. The second pair of second conductive lines may extend vertically on the side surface of the semiconductor pattern SP of the second row R2.

[0060] Each second conductive line CL2 may be disposed on a channel region CH of a corresponding one of the semiconductor patterns SP. The second conductive line CL2 may function as a gate electrode. For example, the second conductive line CL2 may function as a gate electrode. Figure 1 The gate electrode of the memory cell transistor MCT of the semiconductor pattern SP may be provided between each second conductive line CL2 and the channel region CH of the corresponding one of the semiconductor patterns SP. The gate insulating layer GI may be a single-layer or multi-layer structure formed of or including at least one of a high-k dielectric material, silicon oxide, silicon nitride, and silicon oxynitride. In one embodiment, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0061] The second conductive line CL2 may be formed of or include a conductive material, and the conductive material may be one of a doped semiconductor material, a conductive metal nitride, a metal material, and a metal semiconductor compound. The second conductive line CL2 may be used as a reference. Figure 1 Described word line WL.

[0062] The third conductive lines CL3 may be provided on the cell region CAR of the substrate SUB to extend in parallel with the first to fourth stacks SS1-SS4 or in the first direction D1. A first one of the third conductive lines CL3 may be provided between the first stack SS1 and the second stack SS2, and a second one of the third conductive lines CL3 may be provided between the third stack SS4 and the fourth stack SS4.

[0063] The third conductive line CL3 may be electrically connected to the second electrode EL2 of the data storage element DS. A first one of the third conductive lines CL3 may be commonly connected to the second electrode EL2 of the first stack SS1 and the second electrode EL2 of the second stack SS2. A second one of the third conductive lines CL3 may be commonly connected to the second electrode EL2 of the third stack SS3 and the second electrode EL2 of the fourth stack SS4.

[0064] The third conductive line CL3 may be formed of or include a conductive material, and the conductive material may be one of a doped semiconductor material, a conductive metal nitride, a metal material, and a metal semiconductor compound. The third conductive line CL3 may be used as a reference. Figure 1 Described ground wire PP.

[0065] A second interlayer insulating layer ILD2 may be provided on the first interlayer insulating layer ILD1 to cover the first to fourth stacks SS1-SS4. A third interlayer insulating layer ILD3 may be provided on the second interlayer insulating layer ILD2. Each of the first to third interlayer insulating layers ILD1, ILD2, and ILD3 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0066] In one embodiment, the first stack SS1 and the second stack SS2 may have a structure substantially the same as the third stack SS3 and the fourth stack SS4. The first and second stacks SS1 and SS2 and the third and fourth stacks SS3 and SS4 may be provided to be symmetrical to each other. The first stack SS1 and the second stack SS2 may be provided to have mirror symmetry with respect to the third conductive line CL3. The third stack SS4 and the fourth stack SS4 may be provided to have mirror symmetry with respect to the third conductive line CL3. The second stack SS2 and the third stack SS3 may be provided to have mirror symmetry with respect to the second interlayer insulating layer ILD2 interposed therebetween.

[0067] The contact region CTR of the substrate SUB may include a first peripheral circuit region PER1 and a second peripheral circuit region PER2. When viewed in a plan view, the first peripheral circuit region PER1 may be provided between the stepped structure of the first stack SS1 and the stepped structure of the second stack SS2. When viewed in a plan view, the second peripheral circuit region PER2 may be provided between the stepped structure of the third stack SS3 and the stepped structure of the fourth stack SS4.

[0068] The first and second peripheral circuit regions PER1 and PER2 may include peripheral transistors PTR, resistors, and capacitors electrically connected to the memory cell array. As an example, the first and second peripheral circuit regions PER1 and PER2 may include sense amplifiers connected to first conductive lines CL1 (ie, bit lines) of the cell region CAR.

[0069] In the following, reference will be made to Figure 2 , Figure 3 , Figure 4C and Figure 4D The peripheral transistors PTR on the first peripheral circuit region PER1 and the second peripheral circuit region PER2 are described in more detail.

[0070] The peripheral transistor PTR may include active patterns PCH and insulating layers IL alternately stacked on the first or second peripheral circuit region PER1 or PER2. The stacked active patterns PCH may be vertically spaced apart from each other by the insulating layer IL.

[0071] Reference Figure 4C, each stacked active pattern PCH may be disposed at the same height as a corresponding one of the semiconductor patterns SP stacked on the cell area CAR. The stacked active pattern PCH may be formed of the same material as the stacked semiconductor pattern SP, or include the same material as the stacked semiconductor pattern SP. For example, each semiconductor pattern SP and a corresponding one of the active patterns PCH may be disposed at the same height and may be simultaneously formed by a single semiconductor layer.

[0072] The peripheral transistor PTR may further include a pair of peripheral gate electrodes PG. The peripheral gate electrode PG may be a columnar or stripe pattern extending in the third direction D3. For example, the peripheral gate electrode PG may be formed of the same material as the second conductive line CL2, or include the same material as the second conductive line CL2. In one embodiment, the peripheral gate electrode PG and the second conductive line CL2 may be formed simultaneously.

[0073] A pair of peripheral gate electrodes PG may be provided at opposite sides of each active pattern PCH, respectively. A peripheral gate insulating layer PGI may be interposed between the peripheral gate electrode PG and each active pattern PCH. For example, the peripheral gate insulating layer PGI may be formed of the same material as the gate insulating layer GI, or include the same material as the gate insulating layer GI.

[0074] The peripheral transistor PTR may further include a pair of source / drain contacts SDC penetrating the stacked active pattern PCH. The pair of source / drain contacts SDC may be used as a source electrode and a drain electrode of the peripheral transistor PTR, respectively. When the peripheral transistor PTR is in an on state, carriers may move from one source / drain contact SDC to another source / drain contact SDC through the active pattern PCH.

[0075] The stacked active pattern PCH of the peripheral transistor PTR can be used as a channel region of the peripheral transistor PTR. In other words, the peripheral transistor PTR according to the present embodiment can be a multi-bridge channel field effect transistor (MBCFET). In more detail, the peripheral transistor PTR according to the present embodiment can be a dual-gate MBCFET including a pair of peripheral gate electrodes PG, and the pair of peripheral gate electrodes PG are respectively provided on opposite sides of each active pattern PCH.

[0076] Meanwhile, although not shown, the substrate SUB may further include a third peripheral circuit region. The third peripheral circuit region may include a row decoder and / or a sub-word line driver connected to the second conductive line CL2 (ie, word line) of the cell region CAR. The above-mentioned peripheral transistor PTR may be provided on the third peripheral circuit region.

[0077] Return to reference Figure 2 , Figure 3 and 4A to 4D A plurality of interconnection lines ML may be provided in the third interlayer insulating layer ILD3. The interconnection lines ML may be formed of or include at least one of metal materials (eg, aluminum, copper, tungsten, molybdenum, or cobalt).

[0078] Some of the interconnection lines ML may be electrically connected to the first conductive line CL1 through the via VI and the contact CNT (see, for example, Figure 4B Some of the interconnection lines ML may be electrically connected to the second conductive line CL2 through the via VI (eg, see Figure 4C Some of the interconnection lines ML may be electrically connected to the peripheral gate electrode PG through the via VI (eg, see Figure 4C Some of the interconnects ML may be electrically connected to the source / drain contacts SDC through vias VI (see, for example, Figure 4D ).

[0079] Although not shown, the interconnection line ML may be composed of a plurality of stacked metal layers. In one embodiment, the first conductive line CL1 on the cell region CAR may be electrically connected to the peripheral transistors PTR on the first and second peripheral circuit regions PER1 and PER2 through the interconnection line ML.

[0080] Figures 5 to 8 is along Figure 3 sectional views taken along lines CC′ and DD′ to illustrate a method of manufacturing a three-dimensional semiconductor memory device according to an embodiment of the inventive concept.

[0081] Reference Figure 3 and Figure 5 , a buffer layer SRB may be formed on the entire top surface of the substrate SUB. The buffer layer SRB may be formed on the cell region CAR and the contact region CTR including the first peripheral circuit region PER1 and the second peripheral circuit region PER2.

[0082] For example, the substrate SUB may be a single crystal silicon wafer. The buffer layer SRB may be formed of or include silicon germanium (SiGe). The concentration of germanium in the buffer layer SRB may be in the range of 10 at% to 20 at%. The buffer layer SRB may be formed by a selective epitaxial growth process. The buffer layer SRB may grow along the crystal structure of the substrate SUB. For example, the buffer layer SRB may have the same crystal structure (i.e., a single crystal structure) as the substrate SUB. The buffer layer SRB may be formed to have a thickness in the range of 200 nm to 1000 nm.

[0083] Before forming the buffer layer SRB, a cleaning process may be performed on the substrate SUB. The cleaning process may include a wet etching process using HF, a wet etching process using NF3 dry etching process or a combination thereof.

[0084] Reference Figure 3 and Figure 6 , a first semiconductor layer SL1 may be formed on the buffer layer SRB. The first semiconductor layer SL1 may be formed of or include silicon (Si). The first semiconductor layer SL1 may be formed by a selective epitaxial growth process. The first semiconductor layer SL1 may grow along the crystal structure of the buffer layer SRB. Therefore, the first semiconductor layer SL1 may include single crystal silicon (Si).

[0085] The buffer layer SRB may prevent crystal defects from being formed in the first semiconductor layer SL1. The buffer layer SRB may be formed on the substrate SUB in a manner that gradually reduces the lattice mismatch between the buffer layer SRB and the substrate SUB, thereby reducing the threading dislocation density in the buffer layer SRB. The buffer layer SRB may serve as a buffer layer that relieves stress caused by the difference in lattice structure between the substrate SUB and the buffer layer SRB.

[0086] During the formation of the first semiconductor layer SL1, the first semiconductor layer SL1 may be doped with impurities in an in-situ manner. For example, the first semiconductor layer SL1 may be doped with impurities at 1E17 / cm 3 To 1E18 / cm 3 The concentration is doped with boron (B) atoms.

[0087] The second semiconductor layer SL2 may be formed on the first semiconductor layer SL1. The second semiconductor layer SL2 may be formed of or include silicon germanium (SiGe). The concentration of germanium in the second semiconductor layer SL2 may be in the range of 15 at % to 35 at %. The concentration of germanium in the second semiconductor layer SL2 may be higher than the concentration of germanium in the buffer layer SRB.

[0088] The second semiconductor layer SL2 may be formed by a selective epitaxial growth process. The second semiconductor layer SL2 may be grown along the crystal structure of the first semiconductor layer SL1. The second semiconductor layer SL2 may be formed to have a thickness in the range of 10 nm to 30 nm.

[0089] Reference Figure 3 and Figure 7 , a cyclic process of forming the first semiconductor layer SL1 and the second semiconductor layer SL2 may be performed multiple times to form a semiconductor stack SLS. The semiconductor stack SLS may include a buffer layer SRB on a substrate SUB and first and second semiconductor layers SL1 and SL2 alternately stacked on the buffer layer SRB. All processes of forming the semiconductor stack SLS may be performed in-situ in a single chamber. The first semiconductor layer SL1 in the semiconductor stack SLS may include single crystal silicon (Si).

[0090] Reference Figure 3 and Figure 8 , the second semiconductor layer SL2 of the semiconductor stack SLS may be replaced with the insulating layer IL. For example, the second semiconductor layer SL2 may be selectively etched to leave the first semiconductor layer SL1. The insulating layer IL may be formed between the first semiconductor layers SL1. The buffer layer SRB of the semiconductor stack SLS may be replaced with the first interlayer insulating layer ILD1.

[0091] Thereafter, as previously referred to Figure 2 , Figure 3 and 4A to 4D As described above, the first to fourth stacks SS1 - SS4 may be formed of the semiconductor stack SLS on the cell region CAR and the contact region CTR. For example, the semiconductor pattern SP may be formed of the first semiconductor layer SL1 on the cell region CAR.

[0092] The peripheral transistor PTR may be formed of a semiconductor stack SLS on the first and second peripheral circuit regions PER1 and PER2. For example, the active pattern PCH may be formed of a first semiconductor layer SL1 on the first and second peripheral circuit regions PER1 and PER2.

[0093] Fig. 9 is along Figure 3 2 is a cross-sectional view taken along lines CC' and DD' to illustrate a method of manufacturing a three-dimensional semiconductor memory device according to another embodiment of the inventive concept. Figure 3 and Fig. 9 , a trench TR may be formed on the substrate SUB. A buffer layer SRB may be formed on the entire top surface of the substrate SUB. The buffer layer SRB may cover the trench TR. In an example embodiment, the buffer layer SRB may fill the trench TR.

[0094] When the buffer layer SRB is formed, a lattice defect LD may be generated due to the difference in lattice structure between the substrate SUB and the buffer layer SRB. For example, the lattice defect LD may be formed in a portion of the buffer layer SRB in the trench TR, but the lattice defect LD may not be generated in other portions of the buffer layer SRB disposed at a height higher than the trench TR. In other words, the stress between the substrate SUB and the buffer layer SRB may be more effectively relieved by the trench TR.

[0095] Hereinafter, various embodiments of the present invention will be described below. In the following description, the previous reference Figure 2 , Figure 3 and 4A to 4D The described elements may be denoted by the same reference numerals without repeating their repeated descriptions, and the elements without reference will be described in more detail. Figure 2 , Figure 3 and 4A to 4D Describes an element or feature.

[0096] Fig.10 is along Figure 3 A cross-sectional view taken along line EE'. Figure 3 and Fig.10 The peripheral transistor PTR may include a first peripheral transistor PTR1 and a second peripheral transistor PTR2 adjacent to each other in the second direction D2. The first peripheral transistor PTR1 may include a pair of first source / drain contacts SDC1, and the second peripheral transistor PTR2 may include a pair of second source / drain contacts SDC2.

[0097] The first source / drain contact SDC1 may have a bottom surface located at a height different from that of the bottom surface of the second source / drain contact SDC2. For example, the bottom surface of the first source / drain contact SDC1 may be lower than the bottom surface of the second source / drain contact SDC2. Therefore, the number of active patterns PCH connected to the first source / drain contact SDC1 may be greater than the number of active patterns PCH connected to the second source / drain contact SDC2.

[0098] Since there are more active patterns PCH connected to the first source / drain contact SDC1 than active patterns PCH connected to the second source / drain contact SDC2, the number of active patterns PCH used as the channel region in the first peripheral transistor PTR1 may be greater than the number of active patterns PCH used as the channel region in the second peripheral transistor PTR2. In other words, the size (e.g., channel width) of the channel region of the first peripheral transistor PTR1 may be greater than the size (e.g., channel width) of the channel region of the second peripheral transistor PTR2.

[0099] That is, according to this embodiment, by adjusting the depth of the source / drain contact SDC in the peripheral transistor PTR, the channel size (eg, channel width) of the peripheral transistor PTR can be controlled. Therefore, the peripheral transistor PTR having various channel widths can be easily implemented.

[0100] Fig.11 is along Figure 3 A cross-sectional view taken along the line D-D'. Figure 3 and Fig.11, the peripheral transistor PTR may include a first peripheral transistor PTR1 and a second peripheral transistor PTR2, which are adjacent to each other in the first direction D1. A shielding line SM may be provided between the first peripheral transistor PTR1 and the second peripheral transistor PTR2. In detail, the shielding line SM may be interposed between the peripheral gate electrode PG of the first peripheral transistor PTR1 and the peripheral gate electrode PG of the second peripheral transistor PTR2. The shielding line SM may be a linear or columnar pattern extending in the third direction D3.

[0101] The second interlayer insulating layer ILD2 may be interposed between the shielding wire SM and the peripheral gate electrode PG, and thus the shielding wire SM may be spaced apart from the peripheral gate electrode PG. The shielding wire SM may reduce the coupling capacitance caused by interference between the peripheral gate electrode PG of the first peripheral transistor PTR1 and the peripheral gate electrode PG of the second peripheral transistor PTR2. As an example, the shielding wire SM may be connected to a node to which a ground voltage is applied.

[0102] Fig.12 is along Figure 3 A cross-sectional view taken along the line D-D'. Figure 3 and Fig.12 , the peripheral transistor PTR may include a peripheral gate electrode PG adjacent to one side of each active pattern PCH and a body contact line BCL adjacent to the opposite side of each active pattern PCH. The body contact line BCL may contact each stacked active pattern PCH. As shown in the figure, no insulating layer is interposed between the body contact line BCL and the stacked active pattern PCH.

[0103] The body contact line BCL may contact each of the stacked active patterns PCH and thus may serve as a body contact. The body contact line BCL may prevent a floating body effect from occurring in the peripheral transistor PTR.

[0104] Fig.13A is along Figure 3 A cross-sectional view taken along line D-D'. Fig. 13B is along Figure 3 A cross-sectional view taken along line EE'. Fig. 13C 2 is a perspective view showing a peripheral transistor according to an embodiment of the inventive concept. Figure 3 , Fig.13A , Fig. 13B and Fig. 13C , the peripheral transistor PTR according to the present embodiment may be a gate-all-around field effect transistor (GAAFET).

[0105] In detail, the peripheral gate electrode PG of the peripheral transistor PTR may be provided to surround each active pattern PCH. For example, the peripheral gate electrode PG may be provided on the top, bottom, and opposite side surfaces of each active pattern PCH (eg, see Fig.13A ). A peripheral gate insulating layer PGI may cover the top, bottom, and opposite side surfaces of each active pattern PCH, and a peripheral gate electrode PG may be provided on the peripheral gate insulating layer PGI.

[0106] Fig.14 is along Figure 3 The cross-sectional view taken along the lines C-C' and D-D'. Figure 3 and Fig.14 , the peripheral transistor PTR may include an active pattern PCH and a second semiconductor layer SL2 alternately stacked on the first peripheral circuit region PER1 or the second peripheral circuit region PER2. Each second semiconductor layer SL2 may be formed of or include silicon germanium (SiGe). The concentration of germanium in the second semiconductor layer SL2 may be in the range of 15at% to 35at%.

[0107] The buffer layer SRB may be interposed between the peripheral transistor PTR and the substrate SUB. Each of the stacked active patterns PCH may be disposed at the same height as a corresponding one of the semiconductor patterns SP stacked on the cell region CAR. Each of the stacked second semiconductor layers SL2 may be disposed at the same height as a corresponding one of the insulating layers IL stacked on the cell region CAR.

[0108] Fig.15 is along Figure 3 The cross-sectional view taken along the lines C-C' and D-D' is shown in order to illustrate the manufacturing method according to Fig.14 A method of implementing a three-dimensional semiconductor memory device. Figure 3 and Fig.15 , in the formation Figure 7 After the resultant structure is obtained, the second semiconductor layer SL2 on the cell region CAR may be replaced with the insulating layer IL. However, the second semiconductor layer SL2 and the buffer layer SRB on the first peripheral circuit region PER1 and the second peripheral circuit region PER2 may not be replaced with the insulating layer but may remain on Fig.14 The semiconductor stack SLS on the first and second peripheral circuit regions PER1 and PER2 may be used as a channel region of the peripheral transistor PTR.

[0109] Fig.16 is a plan view illustrating a semiconductor memory device according to an embodiment of the inventive concept. Fig.17A is along Fig.16 A cross-sectional view taken along lines AA' and BB'. Fig. 17Bis along Fig.16 A cross-sectional view taken along line CC'. Fig.16 , Fig.17A and Fig. 17B , the semiconductor stack SLS may be provided on the first peripheral circuit region PER1 and the second peripheral circuit region PER2. The semiconductor stack SLS may be a semiconductor stack SLS remaining on the first peripheral circuit region PER1 and the second peripheral circuit region PER2, as previously described with reference to Fig.15 The upper semiconductor layer SEL may be provided on the semiconductor stack SLS of the first peripheral circuit region PER1 and the second peripheral circuit region PER2. The upper semiconductor layer SEL may be located at a height higher than the uppermost pattern among the semiconductor patterns SP stacked on the cell region CAR. A plurality of peripheral transistors PTR may be provided on the upper semiconductor layer SEL. Unlike the above-mentioned three-dimensional transistor (e.g., MBCFET or GAAFET), the peripheral transistor PTR according to the present embodiment may be a planar FET. The peripheral transistor PTR according to the present embodiment may be located at a height higher than the first to fourth stacks SS1-SS4 on the cell region CAR.

[0110] In detail, a device isolation layer ST may be provided on the upper semiconductor layer SEL to define an active pattern PCH of the peripheral transistor PTR. A peripheral gate electrode PG may be provided on each active pattern PCH. A pair of source / drain contacts SDC may be provided to be respectively coupled to a source region and a drain region of each active pattern PCH.

[0111] A third interlayer insulating layer ILD3 may be provided on the upper semiconductor layer SEL to cover the peripheral transistor PTR. A fourth interlayer insulating layer ILD4 may be provided on the third interlayer insulating layer ILD3. A plurality of interconnection lines ML may be provided in the fourth interlayer insulating layer ILD4.

[0112] Fig.18 is along Fig.16 A cross-sectional view taken along line CC'. Fig.16 and Fig.18 , an upper semiconductor layer SEL may be provided on the first peripheral circuit region PER1 and the second peripheral circuit region PER2. The upper semiconductor layer SEL may be directly formed on the substrate SUB. That is, Fig.18 In the semiconductor memory device, the semiconductor stack SLS on the first peripheral circuit region PER1 and the second peripheral circuit region PER2 may be omitted.

[0113] Fig.19 is a perspective view illustrating a three-dimensional semiconductor memory device according to an embodiment of the inventive concept. Fig. 20 is along Fig.19In the following description, the previous reference Figure 2 , Figure 3 and 4A to 4D The described elements may be denoted by the same reference numerals without repeating overlapping descriptions thereof.

[0114] Reference Fig.19 and Fig. 20 , a first substrate SUB1 including a cell region CAR and a contact region CTR may be provided. The first substrate SUB1 may be a silicon wafer, a germanium wafer, or a silicon-germanium wafer.

[0115] The first to fourth stacks SS1-SS4 may be provided on the first substrate SUB1. The third interlayer insulating layer ILD3 may be provided on the first to fourth stacks SS1-SS4. A plurality of first interconnection lines ML1 may be provided in the third interlayer insulating layer ILD3. At least one of the first interconnection lines ML1 may be electrically connected to the first conductive line CL1 through the first via VI1 and the contact CNT.

[0116] A fourth interlayer insulating layer ILD4 may be provided on the third interlayer insulating layer ILD3. A second interconnection line ML2 may be provided in the fourth interlayer insulating layer ILD4. The second interconnection line ML2 may be electrically connected to the first interconnection line ML1 through a second via VI2.

[0117] A second substrate SUB2 including a peripheral circuit region PER may be provided on the fourth interlayer insulating layer ILD4. The peripheral circuit region PER of the second substrate SUB2 may vertically overlap the cell region CAR and the contact region CTR of the first substrate SUB1. Although not shown, an adhesive layer may be interposed between the second substrate SUB2 and the fourth interlayer insulating layer ILD4. The adhesive layer may be used to bond the second substrate SUB2 to the fourth interlayer insulating layer ILD4. The second substrate SUB2 may be a silicon wafer, a germanium wafer, or a silicon germanium wafer. For example, the second substrate SUB2 may be a single crystal silicon wafer.

[0118] A plurality of peripheral transistors PTR may be provided on the second substrate SUB2. In detail, a device isolation layer ST may be provided on the second substrate SUB2 to define an active pattern PCH of the peripheral transistors PTR. A peripheral gate electrode PG may be provided on each active pattern PCH. A pair of source / drain contacts SDC may be provided to be respectively connected to the source region and the drain region of each active pattern PCH.

[0119] A fifth interlayer insulating layer ILD5 and a sixth interlayer insulating layer ILD6 may be provided on the second substrate SUB2 to cover the peripheral transistor PTR. A plurality of third interconnection lines ML3 may be provided in the sixth interlayer insulating layer ILD6. Each third interconnection line ML3 may be electrically connected to the source / drain contact SDC or the peripheral gate electrode PG through a third via VI3.

[0120] A through via THV may be provided to penetrate the fifth interlayer insulating layer ILD5 and the second substrate SUB2, and in one embodiment, the second interconnection line ML2 and the third interconnection line ML3 may be vertically connected to each other through the through via THV. For example, the first conductive line CL1 on the first substrate SUB may be electrically connected to the peripheral transistor PTR on the second substrate SUB2 through the through via THV. Although not shown, an insulating spacer may be interposed between the through via THV and the second substrate SUB2.

[0121] In a three-dimensional semiconductor memory device according to an embodiment of the present invention, the peripheral circuit region may include a stepped structure on the contact region of the substrate. Therefore, the area of ​​the semiconductor memory device can be reduced. The peripheral transistor on the peripheral circuit region can be formed simultaneously with the stack on the cell region. Therefore, the manufacturing process can be simplified and the process efficiency can be improved. The peripheral transistor can have a multi-channel structure, such as the stack on the cell region. Therefore, the effective width of the channel region of the peripheral transistor can be increased on a given small area.

[0122] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the claims.

[0123] This application claims the priority of Korean Patent Application No. 10-2019-0101321 filed on August 19, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: a substrate having a cell region and a contact region, the contact region including a peripheral circuit region; a first stack and a second stack on the unit area of ​​the substrate; as well as a first peripheral transistor on the peripheral circuit region, wherein each of the first stack and the second stack comprises: a semiconductor pattern stacked on the unit region in a vertical direction relative to an upper surface of the substrate; bit lines stacked on the cell region in the vertical direction and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending from the cell region to the contact region in a horizontal direction relative to the upper surface of the substrate; and a word line disposed adjacent to the semiconductor pattern and extending from the cell region of the substrate in the vertical direction, and The first peripheral transistor is disposed between the bit line of the first stack and the bit line of the second stack.

2. The semiconductor memory device according to claim 1, wherein: The first peripheral transistor comprises: a first active pattern stacked on the peripheral circuit region in the vertical direction; and A peripheral gate electrode is disposed adjacent to the first active pattern and extends from the peripheral circuit region in the vertical direction.

3. The semiconductor memory device according to claim 2, wherein: The peripheral gate electrode includes a pair of a first peripheral gate electrode and a second peripheral gate electrode, and the first peripheral gate electrode and the second peripheral gate electrode are respectively disposed at opposite sides of each of the active patterns.

4. The semiconductor memory device according to claim 2, wherein: The peripheral gate electrode surrounds each of the active patterns.

5. The semiconductor memory device according to claim 2, wherein: The first peripheral transistor further includes a body contact line connected to each of the active patterns and extending from the peripheral circuit region in the vertical direction.

6. The semiconductor memory device according to claim 2, further comprising: a second peripheral transistor disposed on the peripheral circuit region and adjacent to the first peripheral transistor; as well as A shielding line is provided on the peripheral circuit region and is interposed between the peripheral gate electrode of the first peripheral transistor and the peripheral gate electrode of the second peripheral transistor.

7. The semiconductor memory device according to claim 2, further comprising: A second peripheral transistor is disposed on the peripheral circuit region and adjacent to the first peripheral transistor, Wherein, the first peripheral transistor further includes a first source / drain contact penetrating the first active pattern, The second peripheral transistor includes a second active pattern and a second source / drain contact penetrating the second active pattern, and A vertical height of a bottom surface of the first source / drain contact is different from a vertical height of a bottom surface of the second source / drain contact.

8. The semiconductor memory device according to claim 2, wherein: The first peripheral transistor further includes a semiconductor layer, Each of the active patterns and each of the semiconductor layers are alternately stacked on the peripheral circuit region in the vertical direction, The active pattern includes silicon, and The semiconductor layer includes silicon germanium.

9. The semiconductor memory device according to claim 1, further comprising: interconnect lines on the first stack and the second stack, Wherein, at least one of the bit lines is electrically connected to the first peripheral transistor through the interconnection line.

10. The semiconductor memory device according to claim 1, wherein Each of the first stack and the second stack further includes capacitors connected to second ends of the semiconductor patterns, respectively.

11. A semiconductor memory device comprising: A substrate, including a cell region and a peripheral circuit region; stacking on said unit area; as well as a peripheral transistor on the peripheral circuit region, The stack comprises: a semiconductor pattern stacked on the unit region in a vertical direction relative to an upper surface of the substrate; bit lines stacked on the cell regions in the vertical direction and respectively connected to the semiconductor patterns, each of the bit lines extending in a horizontal direction relative to the upper surface of the substrate; and a word line disposed adjacent to the semiconductor pattern and extending from the cell region in the vertical direction, and Wherein, the peripheral transistor comprises: an active pattern stacked on the peripheral circuit region in the vertical direction; and A peripheral gate electrode is disposed adjacent to the active pattern and extends from the peripheral circuit region in the vertical direction.

12. The semiconductor memory device according to claim 11, wherein: Each of the active patterns is located at the same vertical height as a corresponding one of the semiconductor patterns.

13. The semiconductor memory device according to claim 11, wherein: The peripheral gate electrode includes a pair of first peripheral gate electrodes and a second peripheral gate electrode, and The first peripheral gate electrode and the second peripheral gate electrode are disposed at opposite sides of each of the active patterns, respectively.

14. The semiconductor memory device according to claim 11, wherein: The peripheral gate electrode surrounds each of the active patterns.

15. The semiconductor memory device according to claim 11, wherein The peripheral transistor further includes: a semiconductor layer stacked on the peripheral circuit region in the vertical direction; and wherein each of the active patterns and each of the semiconductor layers are alternately stacked on the peripheral circuit region in the vertical direction, The active pattern includes silicon, and The semiconductor layer includes silicon germanium.

16. A semiconductor memory device comprising: a substrate having a cell region and a contact region; a first stack and a second stack on the unit area of ​​the substrate; as well as a peripheral transistor on the contact region, wherein each of the first stack and the second stack comprises: a semiconductor pattern stacked on the unit region in a vertical direction relative to an upper surface of the substrate; bit lines stacked on the contact regions in the vertical direction and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending from the cell region to the contact region in a horizontal direction relative to the upper surface of the substrate; and a word line disposed adjacent to the semiconductor pattern and extending from the cell region in the vertical direction, wherein the bit line has a stepped structure on the contact area, and The peripheral transistor is disposed between the stepped structure of the first stack and the stepped structure of the second stack.

17. The semiconductor memory device according to claim 16, wherein: The peripheral transistor comprises: an active pattern stacked on the contact region of the substrate in the vertical direction; and A peripheral gate electrode is disposed adjacent to the active pattern and extends from the contact region in the vertical direction.

18. The semiconductor memory device according to claim 17, wherein: The peripheral gate electrode includes a pair of first peripheral gate electrodes and a second peripheral gate electrode, and The first peripheral gate electrode and the second peripheral gate electrode are disposed at opposite sides of each of the active patterns, respectively.

19. The semiconductor memory device according to claim 17, wherein: The peripheral gate electrode is provided to surround each of the active patterns.

20. The semiconductor memory device according to claim 17, wherein: The peripheral transistor further includes a semiconductor layer, Each of the active patterns and each of the semiconductor layers are alternately stacked on the contact region of the substrate in the vertical direction, The active pattern includes silicon, and The semiconductor layer includes silicon germanium.

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