Display device and method of manufacturing the same

Abstract

A display device and a method of manufacturing the display device are provided. The display device includes a substrate; a first semiconductor pattern disposed on the substrate; a first gate insulating film disposed on the first semiconductor pattern; a first conductive layer disposed on the first gate insulating film and including a first gate electrode and a first electrode of a capacitor connected to the first gate electrode; a first interlayer insulating film disposed on the first conductive layer; a second semiconductor pattern disposed on the first interlayer insulating film; a second gate insulating film disposed on the second semiconductor pattern; a second gate electrode disposed on the second gate insulating film; a second interlayer insulating film disposed on the second gate electrode; and a second conductive layer disposed on the second interlayer insulating film and including a first source / drain electrode, a second source / drain electrode, and a second electrode of the capacitor, wherein the second electrode of the capacitor is disposed in a trench structure in which the second interlayer insulating film is at least partially removed.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2019-0100276, filed on August 16, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device. Background Technology

[0003] With the development of multimedia, display devices have become increasingly important. In response to this development, various types of display devices are being developed, such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, and other types of displays. Among these display devices, OLED displays use OLEDs to display images by causing electrons and holes to recombine and generate light. OLED displays may include transistors that can provide driving current to the OLED.

[0004] It should be understood that this background section in the technical section is partly intended to provide useful context for understanding the technology. However, this background section in the technical section may also include ideas, concepts, or knowledge that were not known or understood by a person skilled in the art prior to the relevant valid submission date of the subject matter disclosed herein. Summary of the Invention

[0005] Several aspects of the disclosure provide a display device in which the number of masks used in the manufacturing process can be reduced.

[0006] Several disclosed aspects also provide a method for manufacturing a display device in which the number of masks used in the manufacturing process can be reduced.

[0007] However, the scope of disclosure is not limited to the above purposes, and other aspects and purposes will become clear to those skilled in the art from the following description.

[0008] Embodiments of the display device may include transistors and capacitors. The display device may include: a substrate; a first semiconductor layer disposed on the substrate and including a semiconductor pattern of a first transistor; a first gate insulating film disposed on the first semiconductor layer; a first conductive layer disposed on the first gate insulating film and including a gate electrode of the first transistor and a first electrode of the capacitor connected to the gate electrode of the first transistor; a first interlayer insulating film disposed on the first conductive layer; a second semiconductor layer disposed on the first interlayer insulating film and including a semiconductor pattern of a second transistor; a second gate insulating film disposed on the second semiconductor layer; a second conductive layer disposed on the second gate insulating film and including a gate electrode of the second transistor; a second interlayer insulating film disposed on the second conductive layer; and a third conductive layer disposed on the second interlayer insulating film and including a first source / drain electrode of the first transistor, a second source / drain electrode of the first transistor, a first source / drain electrode of the second transistor, a second source / drain electrode of the second transistor, a second source / drain electrode of the second transistor, and a second electrode of the capacitor, wherein the second electrode of the capacitor is disposed in a trench structure in which the second interlayer insulating film is at least partially removed.

[0009] In an embodiment, the first transistor and the second transistor may each include channels that can be formed from different semiconductor layers.

[0010] In one embodiment, a first interlayer insulating film may be provided between the first electrode and the second electrode of the capacitor, but no second interlayer insulating film is provided.

[0011] In an embodiment, the thickness of the first interlayer insulating film between the first and second electrodes of the capacitor may be less than the thickness of the first interlayer insulating film in the region where the first interlayer insulating film is not stacked with the third conductive layer.

[0012] In an embodiment, the thickness of the second interlayer insulating film between the first and second electrodes of the capacitor may be less than the thickness of the second interlayer insulating film in the region where the second interlayer insulating film is not stacked with the third conductive layer.

[0013] In one embodiment, the sidewalls of the trench structure may be formed by a second interlayer insulating film; and the bottom surface of the trench structure may be formed by a portion of the first interlayer insulating film.

[0014] In one embodiment, the sidewalls and bottom surface of the trench structure may be formed of a second interlayer insulating film.

[0015] In an embodiment, the first conductive layer may further include a light-shielding pattern that can be superimposed on the semiconductor pattern of the second transistor.

[0016] In an embodiment, the light-shielding pattern may be connected to the gate electrode of the second transistor or to one of the first source / drain electrodes and the second source / drain electrode of the second transistor.

[0017] In an embodiment, the second semiconductor layer may include an etch stop pattern, the bottom surface of the trench structure may be formed by the etch stop pattern, and the etch stop pattern may contact the second electrode of the capacitor and may be disposed between the second electrode of the capacitor and the first interlayer insulating film.

[0018] In an embodiment, the semiconductor pattern of the second transistor may include: a channel region that may be superimposed on the gate electrode of the second transistor; and a source / drain region disposed on the outside of the gate electrode of the second transistor, and the source / drain region and the etch stop pattern of the second transistor may have a higher conductivity than the channel region of the second transistor.

[0019] In an embodiment, the etch stop pattern may have the same conductivity as the source / drain region of the second transistor.

[0020] In an embodiment, the display device may include: a first transistor, including a non-oxide semiconductor; a second transistor, including an oxide semiconductor disposed on a different layer from the non-oxide semiconductor; a capacitor; a first conductive layer, including a first electrode of the capacitor and a gate electrode of the first transistor; a second conductive layer, including a gate electrode of the second transistor; and a third conductive layer, including a source / drain electrode of the first transistor, a source / drain electrode of the second transistor, and a second electrode of the capacitor; wherein the second electrode of the capacitor may be disposed in a trench structure formed by an insulating layer.

[0021] In an embodiment, one of the first transistor and the second transistor may be a p-type metal-oxide-semiconductor (PMOS) transistor, and the other of the first transistor and the second transistor may be an n-type metal-oxide-semiconductor (NMOS) transistor.

[0022] In an embodiment, the insulating layer may include: a first insulating layer; and a second insulating layer disposed on the first insulating layer, and the trench structure may include: a sidewall formed by the second insulating layer; and a bottom surface formed by a portion of the first insulating layer.

[0023] An embodiment of a method for manufacturing a display device may include the following steps: forming a first semiconductor pattern including a semiconductor pattern of a first transistor on a substrate; forming a first gate insulating film on the semiconductor pattern of the first transistor; forming a first conductive layer on the first gate insulating film, which may include a gate electrode forming the first transistor and a first electrode forming a capacitor connected to the gate electrode of the first transistor; forming a first interlayer insulating film on the gate electrode of the first transistor and the first electrode of the capacitor; forming a second semiconductor pattern including a semiconductor pattern of a second transistor on the first interlayer insulating film; forming an insulating layer of the second gate insulating film on the semiconductor pattern of the second transistor; forming a second conductive layer on the insulating layer of the second gate insulating film; and etching the second conductive layer and the insulating layer of the second gate insulating film using a first etch mask. The process involves: forming a first interlayer insulating film on the gate electrode of the second transistor; forming a second interlayer insulating film on the gate electrode of the second transistor; etching the second interlayer insulating film, the first interlayer insulating film, and the first gate insulating film using a second etch mask, and forming contact holes for the source / drain regions of the semiconductor pattern of the first transistor; etching the second interlayer insulating film using a third etch mask, and forming a trench structure superimposed on the first electrode of the capacitor and contact holes for the source / drain regions of the semiconductor pattern of the second transistor; and forming a third conductive layer on the second interlayer insulating film, including the first and second source / drain electrodes of the first transistor, the first and second source / drain electrodes of the second transistor, and the second electrode of the capacitor disposed in the trench structure.

[0024] In an embodiment, the step of forming the first interlayer insulating film may include: forming the first interlayer insulating film between the first electrode and the second electrode of the capacitor without forming the second interlayer insulating film.

[0025] In an embodiment, the step of forming the first interlayer insulating film may include: forming the thickness of the first interlayer insulating film between the first electrode and the second electrode of the capacitor to be less than the thickness of the first interlayer insulating film in the region in which the first interlayer insulating film is not stacked with the third conductive layer.

[0026] In an embodiment, the step of forming the second semiconductor pattern may include forming an etch stop pattern that can be superimposed on the first electrode of the capacitor.

[0027] In one embodiment, the step of forming the trench structure may include exposing an etch stop pattern.

[0028] In an embodiment, the step of forming a second electrode of the capacitor may include forming a second electrode of the capacitor that is in contact with the etch stop pattern.

[0029] According to the display device and the method for manufacturing the display device according to the embodiments, the number of masks can be reduced, thereby reducing process costs and improving process efficiency.

[0030] The effects of the disclosed embodiments are not limited to the above-described examples, and many more effects are included within the spirit and scope of the specification. Attached Figure Description

[0031] The above and other aspects and features of the disclosure will become clearer by referring to the accompanying drawings, which describe the disclosed embodiments in detail:

[0032] Figure 1 This is a plan view of the display device according to an embodiment;

[0033] Figure 2 yes Figure 1 A side view of the display device;

[0034] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to an embodiment;

[0035] Figure 4 It is a schematic cross-sectional view showing a pixel and the periphery of a curved area;

[0036] Figure 5 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment;

[0037] Figures 6 to 21 This is a schematic cross-sectional view illustrating the process operations of a method for manufacturing a display device according to an embodiment;

[0038] Figure 22 This is a schematic cross-sectional view of a display device according to an embodiment;

[0039] Figure 23 This is a schematic cross-sectional view of a display device according to an embodiment;

[0040] Figure 24 This is a schematic cross-sectional view of a display device according to an embodiment;

[0041] Figure 25 This is a schematic cross-sectional view of a display device according to an embodiment;

[0042] Figure 26 This is a schematic cross-sectional view of a display device according to an embodiment;

[0043] Figure 27 It shows the manufacturing basis. Figure 26 A flowchart of a method for displaying a device according to an embodiment; and

[0044] Figures 28 to 30 It shows the manufacturing basis. Figure 26 A schematic cross-sectional view of the process operation of the method of the display device in an embodiment. Detailed Implementation

[0045] The disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] In order to describe the disclosed embodiments, some parts (components) that are not related to the description may be omitted, and the same reference numerals denote the same elements throughout the specification.

[0047] In the accompanying drawings, the dimensions and thicknesses of elements may be enlarged for better understanding, clarity, and ease of description. However, the disclosure is not limited to the dimensions and thicknesses shown. In the accompanying drawings, the thicknesses of layers, films, panels, regions, and other elements may be exaggerated for clarity. In the accompanying drawings, the thicknesses of some layers and regions may be exaggerated for better understanding and ease of description.

[0048] Furthermore, in the instruction manual, the phrase "in a plan view" refers to the situation when viewing the target part from above, and the phrase "in a schematic sectional view" refers to the situation when viewing a schematic section taken by vertically cutting the target part from the side.

[0049] Additionally, the term "overlay" or variations thereof means that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlay" may include stacking, overlapping, facing or oriented towards, extending over, covering or partially covering, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented towards" mean that the first element may be directly or indirectly opposite the second element. In the case where a third element is inserted between the first and second elements, the first and second elements may be understood as indirectly opposite each other, but still facing each other. When an element is described as "not overlaying" or "not" overlaying another element, this may include elements separated from each other, offset from each other, or separated from each other, or any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0050] When a layer, film, region, substrate, or area is referred to as being "on" another layer, film, region, substrate, or area, the layer, film, region, substrate, or area may be directly on the other layer, film, region, substrate, or area, or an intermediate layer, film, region, substrate, or area may exist between them. Conversely, when a layer, film, region, substrate, or area is referred to as being "directly on" another layer, film, region, substrate, or area, no intermediate layer, film, region, substrate, or area may exist between them. Furthermore, when a layer, film, region, substrate, or area is referred to as being "below" another layer, film, region, substrate, or area, the layer, film, region, substrate, or area may be directly below the other layer, film, region, substrate, or area, or an intermediate layer, film, region, substrate, or area may exist between them. Conversely, when a layer, film, region, substrate, or area is referred to as being "directly below" another layer, film, region, substrate, or area, no intermediate layer, film, region, substrate, or area may exist between them. Furthermore, "above" or "on" can include being positioned on or below an object and does not necessarily imply a direction based on gravity.

[0051] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that spatial relative terms are intended to cover not only the orientation depicted in the figures but also different orientations of the device during use or operation. For example, in the case where the device shown in the figures is flipped, a device positioned “below” or “under” another device may be placed “above” said other device. Therefore, the exemplary term “below” can include both a lower and an upper position. The device may also be positioned in other directions; therefore, spatial relative terms may be interpreted differently depending on the orientation.

[0052] Throughout this specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to the other element or “indirectly connected” to the other element with one or more intermediate elements interposed between them. It will also be understood that when the terms “comprising,” “including,” and / or variations thereof are used in this specification, these terms or the term itself may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combinations thereof.

[0053] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Therefore, a first element discussed below may be referred to as a second element without departing from the teachings of one or more embodiments. Describing an element as a “first” element does not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish different classes or groups of elements. For brevity, the terms “first,” “second,” etc., may respectively represent “first class (or first group),” “second class (or second group),” etc.

[0054] As used herein, “about” or “approximately” includes the stated value and means: within an acceptable range of deviation for a particular value, taking into account the measurement mentioned and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system), as determined by a person of ordinary skill in the art. For example, “about” can mean within one or more standard deviations, or within ±30%, ±20%, ±5% of the stated value.

[0055] In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in a connected or separate sense and can be understood to be equivalent to "and / or". In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one(a) selected from the group consisting of...". For example, "at least one(a) of A and B" can be understood to mean "A, B, or A and B".

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formalized sense unless clearly defined in the specification.

[0057] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the disclosed principles. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for limiting purposes.

[0058] In the following description, the disclosed embodiments will be illustrated with reference to the accompanying drawings.

[0059] Figure 1 This is a plan view of a display device according to an embodiment. Figure 2 yes Figure 1 A side view of the display device. Figure 2 The shape of the side surface of the display device, which is curved in its thickness direction, is shown.

[0060] Display device 1 can be a device for displaying moving or still images. It can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), and for display screens in various products such as televisions, laptops, monitors, billboards, and the Internet of Things. However, the disclosure is not limited thereto. Other display devices may also be included within the spirit and scope of this disclosure.

[0061] The display device 1 according to the embodiment may have a substantially rectangular shape in a plan view. The display device 1 may have a rectangular shape in a plan view where its corners can be right angles. However, the disclosure is not limited thereto, and the display device 1 may have a rectangular shape in a plan view where its corners can be rounded.

[0062] In the accompanying drawings, the first direction DR1 can represent the lateral direction of the display device 1 in the plan view, and the second direction DR2 can represent the longitudinal direction of the display device 1 in the plan view. The third direction DR3 can represent the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 can intersect each other perpendicularly, and the third direction DR3 can be a direction that intersects with the plane in which the first direction DR1 and the second direction DR2 are placed, and can also intersect both the first direction DR1 and the second direction DR2 perpendicularly. However, the directions described in the embodiments should be understood as relative directions, and the embodiments are not limited to the described directions.

[0063] Unless otherwise defined, in this specification, the terms “upper,” “upper surface,” or “upper side,” as used in relation to a third party to DR3, may refer to one side of the display surface relative to the display panel 100, and the terms “lower,” “lower surface,” or “lower side” may refer to the opposite side of the display surface relative to the display panel 100.

[0064] Reference Figure 1 and Figure 2 The display device 1 may include a display panel 100. The display panel 100 may be a flexible substrate comprising a flexible polymer material such as polyimide or other materials within the disclosed scope. Therefore, the display panel 100 may be flexible, bendable, foldable, or rollable.

[0065] Display panel 100 may be an organic light-emitting display panel. In the following embodiments, an example of an organic light-emitting display panel being used as display panel 100 is shown, but the disclosure is not limited thereto. Other types of display panels (such as liquid crystal display (LCD) panels, quantum dot organic light-emitting display (QD-OLED) panels, quantum dot LCD (QD-LCD) panels, quantum nano-light-emitting display panels (nano-light-emitting display (NED) panels), micro LED panels, and other types of display panels) may be used as display panel 100.

[0066] Display panel 100 may include a display area DA where one or more images can be displayed on a screen, and a non-display area NDA where one or more images are not displayed on the screen. Display panel 100 can be divided into display area DA and non-display area NDA in a plan view. Non-display area NDA may be positioned or configured to surround display area DA. Non-display area NDA may form a border or edge.

[0067] The display area DA in the planar view can be a rectangle with right-angled corners or a rectangle with rounded corners. The display area DA can have a short side and a long side. The short side of the display area DA can be an edge extending in the first direction DR1. The long side of the display area DA can be an edge extending in the second direction DR2. However, the planar shape of the display area DA is not limited to a rectangle, but can be a circle, an ellipse, or various other shapes.

[0068] The display area DA may include pixels. Pixels may be arranged in a matrix or in a shape. Each pixel may include a light-emitting layer and a circuit layer that can control the amount of light emitted by the light-emitting layer. The circuit layer may include lines, electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed with an encapsulation film. The detailed structure of a pixel will be described below.

[0069] The non-display area NDA can be positioned or configured to be adjacent to the two short sides and two long sides of the display area DA. In this case, the non-display area NDA can surround all the sides of the display area DA and form the edge of the display area DA. However, the disclosure is not limited thereto, and the non-display area NDA can be positioned or configured to be adjacent only to the two short sides or two long sides of the display area DA.

[0070] The display panel 100 may include a main region MA and a curved region BA connected to one side of the main region MA in a second direction DR2. The display panel 100 may include a sub-region SA, one side of which may be connected to the curved region BA in the second direction DR2, and the sub-region SA may be curved in its thickness direction to overlap or partially overlap with the main region MA in the thickness direction.

[0071] The display area DA can be located or set within the main area MA. The non-display area NDA can be located or set within the outer edge of the display area DA of the main area MA.

[0072] The main region MA in the plan view may have a shape similar to the external shape of the display device 1. The main region MA may be a flat area located or disposed in a surface or on a surface. However, the disclosure is not limited thereto, and at least one of the remaining edges of the main region MA other than the edge (or side) connected to the curved region BA may be curved to form a curved surface or may be curved in the vertical direction.

[0073] When at least one of the remaining edges, other than the edge (or side) of the main area MA that connects to the curved area BA, is bent or flexed, the display area DA may also be positioned or set at the corresponding edge. However, the disclosure is not limited thereto, wherein a non-display area NDA, which may not be displayed on the screen, may be positioned or set at the bent or flexed edge, or the display area DA and the non-display area NDA may be positioned or set together at the bent or flexed edge.

[0074] The non-display area NDA of the main area MA can be placed in the area extending from the outer boundary of the display area DA to the edge of the display panel 100. Signal lines or drive circuits for applying signals to the display area DA can be located or set in the non-display area NDA of the main area MA.

[0075] The curved region BA can be connected to a short side of the main region MA. The width of the curved region BA (width in the first direction DR1) can be smaller than the width of the main region MA (width of the short side). The connection between the main region MA and the curved region BA can have an L-shaped cut to reduce the width of the border.

[0076] Within the bending region BA, the display panel 100 can be bent with a certain curvature in a direction opposite to the direction of its display surface. Because the display panel 100 can be bent within the bending region BA, the surface of the display panel 100 can be reversed. For example, an upward-facing surface of the display panel 100 can be turned to face the outside of a side surface of the display panel 100 through the bending region BA, and then changed to face downwards.

[0077] Sub-region SA can extend from curved region BA. Sub-region SA can extend from the curved end in a direction parallel to the main region MA. Sub-region SA can be superimposed on the main region MA in the thickness direction of display panel 100. Sub-region SA can be superimposed on non-display region NDA at the edge of main region MA, and can also be superimposed on display region DA of main region MA. The width of sub-region SA can be equal to or similar to the width of curved region BA, but the disclosure is not limited thereto.

[0078] Pad portions (or "solder pads") may be positioned or disposed in sub-regions SA of the display panel 100. External devices may be mounted on (or attached to) the pad portions. Examples of external devices may include a driver chip 200, a driver substrate 300 formed as a flexible or rigid printed circuit board, etc. For example, wire connection films, connectors, or other external devices may be mounted on the pad portions as external devices. One or more external devices may be mounted in the sub-regions SA. For example, such as... Figure 1 and Figure 2 As shown, the driving chip 200 can be positioned or disposed in a sub-region SA of the display panel 100, and the driving substrate 300 can be attached to an end of the sub-region SA. As an example, the display panel 100 may include both a pad connected to the driving chip 200 and a pad connected to the driving substrate 300. As an example, the driving chip 200 can be mounted on a film, and the film can be attached to the sub-region SA of the display panel 100.

[0079] The driver chip 200 can be mounted on a surface that is coplanar with the display surface of the display panel 100. As described above, since the curved region BA can be bent and / or reversed, the driver chip 200 can be mounted on the surface of the display panel 100 that faces downward in the thickness direction, so the upper surface of the driver chip 200 can face downward.

[0080] For example, the driver chip 200 can be attached to the display panel 100 using an anisotropic conductive film, or it can be attached to the display panel 100 by ultrasonic bonding. The lateral width of the driver chip 200 can be smaller than the lateral width of the display panel 100. The driver chip 200 can be positioned or disposed in the center of the sub-region SA in the lateral direction (first direction DR1), and the left and right edges of the driver chip 200 can be separated from the left and right edges of the sub-region SA, respectively.

[0081] The driver chip 200 may include an integrated circuit capable of driving the display panel 100. In one embodiment, the integrated circuit may be a data driver integrated circuit capable of generating and providing data signals, but the disclosure is not limited thereto. The driver chip 200 may be connected to line pads (not shown) disposed on a pad portion of the display panel 100 to provide data signals to the line pads (not shown). Lines connected to the line pads (not shown) may extend to pixels to apply data signals to the corresponding pixels.

[0082] Figure 3 This is an equivalent circuit diagram of the pixels of a display device according to an embodiment.

[0083] Reference Figure 3 The circuitry of a pixel in an organic light-emitting display device may include an organic light-emitting diode (OLED), transistors T1 to T7, and a capacitor Cst. Data signals DATA, a first scan signal Gw-p, a second scan signal Gw-n, a third scan signal GI, a light emission control signal EM, a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT may be applied to the pixel circuitry.

[0084] An organic light-emitting diode (OLED) may include an anode electrode and a cathode electrode. A capacitor Cst may include a first electrode and a second electrode.

[0085] The transistors may include a first transistor T1 through a seventh transistor T7. Each of transistors T1 through T7 may include a gate electrode, a first source / drain electrode, and a second source / drain electrode. Either the first source / drain electrode or the second source / drain electrode of each of transistors T1 through T7 may become a source electrode, and the other may become a drain electrode.

[0086] Each of transistors T1 to T7 can be a thin-film transistor. Each of transistors T1 to T7 can be either a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In an embodiment, the first transistor T1, used as a driving transistor, the second transistor T2, used as a data transmission transistor, the fifth transistor T5, used as a first light-emitting control transistor, and the sixth transistor T6, used as a second light-emitting control transistor, can be PMOS transistors. On the other hand, the third transistor T3, used as a compensation transistor, the fourth transistor T4, used as a first initialization transistor, and the seventh transistor T7, used as a second initialization transistor, can be NMOS transistors. PMOS transistors and NMOS transistors can have different characteristics. The third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be formed as NMOS transistors with relatively high cutoff characteristics, thus reducing leakage of driving current during the emission period of the organic light-emitting diode (OLED). However, the disclosure is not limited thereto. Within the spirit and scope of the disclosure, transistors can be any combination of NMOS and / or PMOS.

[0087] The components will be described in detail below.

[0088] The gate electrode of the first transistor T1 can be connected to the first electrode of the capacitor Cst. The first source / drain electrode of the first transistor T1 can be connected to the terminal of the first power supply voltage ELVDD via the fifth transistor T5. The second source / drain electrode of the first transistor T1 can be connected to the anode electrode of the organic light-emitting diode (OLED) via the sixth transistor T6. The first transistor T1 can receive the data signal DATA according to the switching operation of the second transistor T2 and supply drive current to the OLED.

[0089] The gate electrode of the second transistor T2 can be connected to the terminal of the first scan signal Gw-p. The first source / drain electrode of the second transistor T2 can be connected to the terminal of the data signal DATA. The second source / drain electrode of the second transistor T2 can be connected to the terminal of the first power supply voltage ELVDD via the fifth transistor T5 while being connected to the first source / drain electrode of the first transistor T1. The second transistor T2 can be turned on according to the first scan signal Gw-p to perform a switching operation in which the data signal DATA can be transmitted to the first source / drain electrode of the first transistor T1.

[0090] The gate electrode of the third transistor T3 can be connected to the terminal of the second scan signal Gw-n. The first source / drain electrode of the third transistor T3 can be connected to the second source / drain electrode of the first transistor T1, while simultaneously being connected to the anode electrode of the organic light-emitting diode (OLED) via the sixth transistor T6. The second source / drain electrode of the third transistor T3 can be connected to the first electrode of the capacitor Cst, the first source / drain electrode of the fourth transistor T4, and the gate electrode of the first transistor T1. The third transistor T3 can be turned on according to the second scan signal Gw-n, connecting the gate electrode of the first transistor T1 to the second source / drain electrode and the diode to the first transistor T1. Therefore, a voltage difference can be generated between the first source / drain electrode and the gate electrode of the first transistor T1 by the threshold voltage of the first transistor T1. Thus, a data signal DATA, whose threshold voltage can be compensated, can be supplied to the gate electrode of the first transistor T1 to compensate for the deviation of the threshold voltage of the first transistor T1.

[0091] The gate electrode of the fourth transistor T4 can be connected to the terminal of the third scan signal GI. The second source / drain electrode of the fourth transistor T4 can be connected to the terminal of the initialization voltage VINT. The first source / drain electrode of the fourth transistor T4 can be connected to the first electrode of capacitor Cst, the second source / drain electrode of the third transistor T3, and the gate electrode of the first transistor T1. The fourth transistor T4 can be turned on according to the third scan signal GI to perform the operation in which the initialization voltage VINT can be transmitted to the gate electrode of the first transistor T1, so that the voltage of the gate electrode of the first transistor T1 can be initialized.

[0092] The gate electrode of the fifth transistor T5 can be connected to the terminal of the light emission control signal EM. The first source / drain electrode of the fifth transistor T5 can be connected to the terminal of the first power supply voltage ELVDD. The second source / drain electrode of the fifth transistor T5 can be connected to the first source / drain electrode of the first transistor T1 and the second source / drain electrode of the second transistor T2.

[0093] The gate electrode of the sixth transistor T6 can be connected to the terminal of the light emission control signal EM. The first source / drain electrode of the sixth transistor T6 can be connected to the second source / drain electrode of the first transistor T1 and the first source / drain electrode of the third transistor T3. The second source / drain electrode of the sixth transistor T6 can be connected to the anode electrode of the organic light-emitting diode (OLED).

[0094] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously according to the light emission control signal EM, so that the driving current can flow into the organic light-emitting diode (OLED).

[0095] The gate electrode of the seventh transistor T7 can be connected to the terminal of the light emission control signal EM. The first source / drain electrode of the seventh transistor T7 can be connected to the anode electrode of the organic light-emitting diode (OLED). The second source / drain electrode of the seventh transistor T7 can be connected to the terminal of the initialization voltage VINT. The seventh transistor T7 can be turned on according to the light emission control signal EM to initialize the anode electrode of the OLED.

[0096] The seventh transistor T7 can receive the same emission control signal EM as the fifth transistor T5 and the sixth transistor T6. However, since the seventh transistor T7 can be an NMOS transistor, while the fifth transistor T5 and the sixth transistor T6 can be PMOS transistors, the seventh transistor T7 can be turned on with a different timing than the fifth transistor T5 and the sixth transistor T6. For example, when the emission control signal EM can be high, the seventh transistor T7 can be turned on and the fifth transistor T5 and the sixth transistor T6 can be turned off. When the emission control signal EM can be low, the seventh transistor T7 can be turned off and the fifth transistor T5 and the sixth transistor T6 can be turned on. Therefore, the initialization operation through the seventh transistor T7 can be omitted at the emission time when the fifth transistor T5 and the sixth transistor T6 can be turned on, and the initialization operation through the seventh transistor T7 can be performed at the non-emission time when the fifth transistor T5 and the sixth transistor T6 can be turned off.

[0097] In one embodiment, an example is shown where the gate electrode of the seventh transistor T7 can receive the light emission control signal EM. However, as an example, the pixel circuitry can be configured such that the gate electrode of the seventh transistor T7 can receive the third scan signal GI.

[0098] The second electrode of capacitor Cst can be connected to the terminal of the first power supply voltage ELVDD. The first electrode of capacitor Cst can be connected to the gate electrode of the first transistor T1, the second source / drain electrode of the third transistor T3, and the first source / drain electrode of the fourth transistor T4. The cathode electrode of the organic light-emitting diode (OLED) can be connected to the terminal of the second power supply voltage ELVSS. The OLED can receive drive current from the first transistor T1 and can emit light to display an image.

[0099] In the following text, reference will be made to Figure 4 A schematic cross-sectional structure of the display panel 100 is described in detail. Figure 4 An example of a schematic cross-sectional structure of the display area DA of the display panel 100, including the non-display area NDA, which includes the curved area BA.

[0100] Figure 4 It is a schematic cross-sectional view showing the pixels of the display area and the periphery of the curved area.

[0101] Reference Figure 4 Describes the display area DA of the display panel 100.

[0102] The display area DA may include a silicon transistor area AR1 and an oxide transistor area AR2. A non-oxide inorganic semiconductor transistor (hereinafter referred to as "silicon transistor") of polycrystalline silicon used as a channel may be located or disposed in the silicon transistor area AR1, and an oxide semiconductor transistor (hereinafter referred to as "oxide transistor") of oxide semiconductor used as a channel may be located or disposed in the oxide transistor area AR2. The silicon transistor located or disposed in the silicon transistor area AR1 may be a PMOS transistor. Figure 4 In the diagram, the first transistor T1, used as the driving transistor, can be shown as an example of a silicon transistor. The oxide transistor positioned or disposed in the oxide transistor region AR2 can be an NMOS transistor. Figure 4 In the diagram, the third transistor T3, used as a compensation transistor, can be shown as an example of an oxide transistor. Although in Figure 4 The second transistor T2, fifth transistor T5, and sixth transistor T6, which may be other silicon transistors located or disposed in the silicon transistor region AR1, can have a stacking structure substantially the same as that of the first transistor T1. The fourth transistor T4 and seventh transistor T7, which may be other oxide transistors located or disposed in the oxide transistor region AR2, can have a stacking structure substantially the same as that of the third transistor T3. A detailed description of the silicon transistors and oxide transistors will be described below.

[0103] The substrate 101, barrier layer 102, buffer layer 103, silicon semiconductor layer 105, first gate insulating film GI1, first conductive layer 120, first interlayer insulating film ILD1, oxide semiconductor layer 135, second gate insulating film GI2, second conductive layer 140, second interlayer insulating film ILD2, third conductive layer 150, first via layer VIA1, fourth conductive layer 160, second via layer VIA2, pixel electrode ANO (or "anode electrode ANO"), and pixel defining film PDL can be sequentially positioned or disposed in the display area DA of the display panel 100. Each of the above layers can be formed as a single film or as a stacked film including multiple films. Another layer can be positioned or disposed between the layers.

[0104] The substrate 101 can support, position, or be disposed above various layers. The substrate 101 can be made of, for example, an insulating material (such as a polymeric resin or other suitable material). Examples of polymeric materials may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl compounds, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The substrate 101 may include a metallic material.

[0105] The substrate 101 may be a flexible substrate, which may be bendable, foldable, or rollable. Examples of materials used to make the flexible substrate may include PI, but the disclosure is not limited thereto, and any other materials that can be bent, folded, or rolled may be included within the spirit and scope of the disclosure.

[0106] When the organic light-emitting display device is a back-emitting or dual-emitting type, a transparent substrate can be used. When the organic light-emitting display device is a top-emitting type, not only a transparent substrate, but also a translucent or opaque substrate can be used.

[0107] The barrier layer 102 can be positioned or disposed on the substrate 101. The barrier layer 102 can prevent the diffusion of impurity ions, prevent the penetration of moisture or external air, and perform surface planarization. The barrier layer 102 may include silicon nitride, silicon oxide, silicon oxynitride, or other materials. The barrier layer 102 may be omitted depending on the type of substrate 101, process conditions, or other conditions.

[0108] Buffer layer 103 may be positioned or disposed on barrier layer 102. Buffer layer 103 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and other materials. Buffer layer 103 may be omitted depending on the type of substrate 101, process conditions, or other conditions.

[0109] The silicon semiconductor layer 105 can be positioned or disposed on the buffer layer 103. The silicon semiconductor layer 105 can be positioned or disposed in the silicon transistor region AR1.

[0110] The silicon semiconductor layer 105 can be made of polycrystalline silicon, monocrystalline silicon, amorphous silicon, or other suitable materials. When the silicon semiconductor layer 105 is made of polycrystalline silicon, polycrystalline silicon can be formed by crystallizing amorphous silicon using crystallization methods such as rapid thermal annealing (RTA), solid-state crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), sequential lateral curing (SLS), or other suitable methods disclosed in the spirit and scope of this publication.

[0111] The silicon semiconductor layer 105 may include a channel region 105c and a first source / drain region 105a and a second source / drain region 105b. The channel region 105c may be positioned or configured to overlap with the first gate electrode 121 above it in its thickness direction. The first source / drain region 105a and the second source / drain region 105b may be positioned or disposed on one side and the other side (or opposite side) of the channel region 105c, respectively. The first source / drain region 105a and the second source / drain region 105b of the silicon semiconductor layer 105 may include current-carrying ions, and therefore may have higher conductivity and lower resistance than the channel region 105c.

[0112] The silicon semiconductor layer 105 can be the semiconductor layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 mentioned above, and can form the channel of the corresponding transistor.

[0113] The first gate insulating film GI1 can be positioned or disposed on the silicon semiconductor layer 105. The first gate insulating film GI1 can cover the upper surface of the silicon semiconductor layer 105 except for the portion on which contact holes CNT1 and CNT2 can be formed, and can also cover the side surface of the silicon semiconductor layer 105. The first gate insulating film GI1 can be positioned or disposed on approximately the entire surface of the substrate 101.

[0114] The first gate insulating film GI1 may include silicon compounds, metal oxides, or other materials. For example, the first gate insulating film GI1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or other materials. These materials may be used individually or in combination. The first gate insulating film GI1 may be a single film or a multilayer film formed as stacked films of different materials.

[0115] The first conductive layer 120 may be positioned or disposed on the first gate insulating film GI1. The first conductive layer 120 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 120 may be a single film or a multilayer film.

[0116] The first conductive layer 120 may include a first gate electrode 121 positioned or disposed in the silicon transistor region AR1 and a light-shielding pattern 122 positioned or disposed in the oxide transistor region AR2. The first gate electrode 121 and the light-shielding pattern 122 may include the same or similar materials.

[0117] The first gate electrode 121 may be the gate electrode of a silicon transistor. The first gate electrode 121 may be connected to the first electrode of the capacitor Cst. The first electrode of the capacitor Cst may be formed using the first gate electrode 121 itself, or it may be formed using a portion extending from the first gate electrode 121. For example, a portion of the pattern of the first conductive layer 120 may be stacked with the silicon semiconductor layer 105 to serve as the first gate electrode 121 at a corresponding portion, and another portion of the pattern of the first conductive layer 120 may not be stacked with the silicon semiconductor layer 105 to serve as the first electrode of the capacitor Cst, and the first electrode of the capacitor Cst may be stacked with the second electrode 155 of the capacitor Cst above it.

[0118] The light-shielding pattern 122 can be used to prevent light that may be incident from the bottom of the display panel 100 from entering the oxide semiconductor layer 135 positioned or disposed above the light-shielding pattern 122. The light-shielding pattern 122 can be superimposed on the channel region 135c of the oxide semiconductor layer 135.

[0119] In an embodiment, the light-shielding pattern 122 can be used as another gate electrode of the oxide transistor. For example, the light-shielding pattern 122 can be electrically connected to either the first source / drain electrode 153 or the second source / drain electrode 154 of the transistor located or disposed in the oxide transistor region AR2, or to the second gate electrode 142.

[0120] The first interlayer insulating film ILD1 can be positioned or disposed on the first conductive layer 120. The first interlayer insulating film ILD1 may include silicon compounds, metal oxides, or other materials. For example, the first interlayer insulating film ILD1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or other materials. These materials may be used individually or in combination. The first interlayer insulating film ILD1 may be a single film or a multilayer film formed as a stack of different materials.

[0121] The oxide semiconductor layer 135 may be positioned or disposed on the first interlayer insulating film ILD1. The oxide semiconductor layer 135 may be positioned or disposed in the oxide transistor region AR2. The oxide semiconductor layer 135 may include an oxide semiconductor. The oxide semiconductor may include one or more oxides selected from one or more elements selected from zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), and hafnium (Hf). The oxide semiconductor may include at least one of indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), and other suitable materials.

[0122] The oxide semiconductor layer 135 may include a channel region 135c and a first source / drain region 135a and a second source / drain region 135b. The channel region 135c is positioned or configured to be stacked on top of the second gate electrode 142 in its thickness direction. The first source / drain region 135a and the second source / drain region 135b are respectively positioned on one side and the other side (or opposite sides) of the channel region 135c. The first source / drain region 135a and the second source / drain region 135b of the oxide semiconductor layer 135 may be conductive regions and may have higher conductivity and lower resistance than the channel region 135c.

[0123] The oxide semiconductor layer 135 can be the semiconductor layer of each of the third transistor T3, the fourth transistor T4 and the seventh transistor T7 mentioned above, and can form the channel of the corresponding transistor.

[0124] The second gate insulating film GI2 may be positioned or disposed on the oxide semiconductor layer 135. The second gate insulating film GI2 may be positioned or disposed in a portion of the region, or, unlike the first gate insulating film GI1, may be positioned or disposed only in a portion of the region. For example, the second gate insulating film GI2 may cover the channel region 135c of the oxide semiconductor layer 135 to expose the upper and side surfaces of the first source / drain region 135a and the second source / drain region 135b. The second gate insulating film GI2 may have a pattern shape substantially the same as the pattern shape of the second gate electrode 142 above it.

[0125] The second gate insulating film GI2 may include silicon compounds, metal oxides, or other materials. For example, the second gate insulating film GI2 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or other materials. The above materials may be used alone or in combination. The second gate insulating film GI2 may be a single film or a multilayer film formed as stacked films of different materials.

[0126] The second conductive layer 140 may be positioned or disposed on the second gate insulating film GI2. The second conductive layer 140 may include the second gate electrode 142 of the transistor positioned or disposed in the oxide transistor region AR2. The second conductive layer 140 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The second conductive layer 140 may be a single film or a multilayer film.

[0127] The second interlayer insulating film ILD2 can be positioned or disposed on the second conductive layer 140. The second interlayer insulating film ILD2 may include silicon compounds, metal oxides, or other materials. For example, the second interlayer insulating film ILD2 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or other materials. These materials may be used individually or in combination. The second interlayer insulating film ILD2 may be a single film or a multilayer film formed as a stack of different materials.

[0128] The trench structure OP1 can be formed in the second interlayer insulating film ILD2. The sidewalls of the trench structure OP1 can be formed by the second interlayer insulating film ILD2, and the bottom surface of the trench structure OP1 can be formed by the first interlayer insulating film ILD1. For example, the trench structure OP1 can be formed such that the opening of the second interlayer insulating film ILD2 partially exposes the first interlayer insulating film ILD1. Even when the second interlayer insulating film ILD2 can be stacked with the trench structure OP1, the portion of the first interlayer insulating film ILD1 that can be stacked with the first gate electrode 121 can still be exposed.

[0129] The thickness of the second interlayer insulating film ILD2 can be greater than the thickness of each of the first gate insulating film GI1, the second gate insulating film GI2, and the first interlayer insulating film ILD1 described above. The second interlayer insulating film ILD2 can be formed of the same or similar material as the first interlayer insulating film ILD1, but the disclosure is not limited thereto.

[0130] The third conductive layer 150 may be positioned or disposed on the second interlayer insulating film ILD2. The third conductive layer 150 may include one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The third conductive layer 150 may be a single film or a multilayer film.

[0131] The third conductive layer 150 may include a first source / drain electrode 151 and a second source / drain electrode 152 of a transistor located or disposed in the silicon transistor region AR1, a second electrode 155 of a capacitor Cst, and a first source / drain electrode 153 and a second source / drain electrode 154 of a transistor located or disposed in the oxide transistor region AR2. For example, the second electrode 155 of the capacitor Cst may be formed on the same layer on which the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor located or disposed in the silicon transistor region AR1, and the first source / drain electrode 153 and the second source / drain electrode 154 of the transistor located or disposed in the oxide transistor region AR2.

[0132] In the transistor positioned or disposed in the silicon transistor region AR1, the first source / drain electrode 151 can be connected to the first source / drain region 105a of the silicon semiconductor layer 105 through the first contact hole CNT1. The first contact hole CNT1 can pass through the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the first gate insulating film GI1 and can expose the first source / drain region 105a of the silicon semiconductor layer 105. The second source / drain electrode 152 can be connected to the second source / drain region 105b of the silicon semiconductor layer 105 through the second contact hole CNT2. The second contact hole CNT2 can pass through the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the first gate insulating film GI1 and can expose the second source / drain region 105b of the silicon semiconductor layer 105.

[0133] In the transistor positioned or disposed in the oxide transistor region AR2, the first source / drain electrode 153 can be connected to the first source / drain region 135a of the oxide semiconductor layer 135 through a third contact hole CNT3. The third contact hole CNT3 can pass through the second interlayer insulating film ILD2 and can expose the first source / drain region 135a of the oxide semiconductor layer 135. The second source / drain electrode 154 can be connected to the second source / drain region 135b of the oxide semiconductor layer 135 through a fourth contact hole CNT4. The fourth contact hole CNT4 can pass through the second interlayer insulating film ILD2 and can expose the second source / drain region 135b of the oxide semiconductor layer 135.

[0134] The second electrode 155 of capacitor Cst can be positioned or disposed on the second interlayer insulating film ILD2. The second electrode 155 of capacitor Cst can be positioned or disposed at a level higher than the second gate electrode 142 of the transistor positioned or disposed in the oxide transistor region AR2. In other words, the second gate electrode 142 can be positioned or disposed on the oxide semiconductor layer 135, which is positioned or disposed on the first interlayer insulating film ILD1, and the second interlayer insulating film ILD2 can be formed on the second gate electrode 142. The second electrode 155 of capacitor Cst can be positioned or disposed on the second interlayer insulating film ILD2.

[0135] A portion of the second electrode 155 of the capacitor Cst, positioned or disposed on the second interlayer insulating film ILD2, can be positioned or disposed within the trench structure OP1. The second electrode 155 of the capacitor Cst can be in direct contact with the upper surface of the bottom surface of the first interlayer insulating film ILD1, which can be formed inside the trench structure OP1. The portion of the second electrode 155 of the capacitor Cst in the trench structure OP1 and the first electrode of the capacitor Cst (the first electrode is connected to the first gate electrode 121 below the second electrode 155) can form the capacitor Cst, and the first interlayer insulating film ILD1 is interposed between the second electrode 155 and the first electrode.

[0136] As described above, although the second electrode 155 of the capacitor Cst can be positioned or disposed on the same layer as the layer on which the first source / drain electrodes 151 and 152 of the transistors positioned or disposed in the silicon transistor region AR1, and the first source / drain electrodes 153 and 154 of the transistors positioned or disposed in the oxide transistor region AR2, the capacitor Cst can be held solely by the first interlayer insulating film ILD1, which serves as the dielectric of the capacitor Cst, instead of the second interlayer insulating film ILD2, through the trench structure OP1. Therefore, the spacing between the second electrode 155 of the capacitor Cst and the first gate electrode 121 can be reduced, thereby increasing the capacitance of the capacitor Cst.

[0137] As an example, since the second electrode 155 of capacitor Cst can be positioned or disposed on the second interlayer insulating film ILD2, two insulating layers (e.g., the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2) can be positioned or disposed between the second electrode 155 of capacitor Cst and the first gate electrode 121. However, since the second electrode 155 of capacitor Cst can be positioned or disposed on the first interlayer insulating film ILD1 through the trench structure OP1 to form capacitor Cst in the corresponding region, only one insulating layer (e.g., the first interlayer insulating film ILD1) can be positioned or disposed between the second electrode 155 of capacitor Cst and the first gate electrode 121, so that the capacitance of capacitor Cst can be further increased.

[0138] As an example, in one embodiment, a portion of the upper side of the first interlayer insulating film ILD1 can also be etched simultaneously with the formation of the trench structure OP1. In this case, the thickness of the dielectric of the capacitor Cst can be reduced, thereby allowing for a further increase in the capacitance of the capacitor Cst.

[0139] The second electrode 155 of capacitor Cst can be formed simultaneously using a mask with the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor located or disposed in silicon transistor region AR1, and with the first source / drain electrode 153 and the second source / drain electrode 154 of the transistor located or disposed in oxide transistor region AR2. As described above, since the second electrode 155 of capacitor Cst can be formed simultaneously with another source / drain electrode using the same mask instead of forming it using a separate mask process for a separate conductive layer, the number of mask processes can be reduced.

[0140] The first via layer VIA1 may be positioned or disposed on the third conductive layer 150. The first via layer VIA1 may comprise an inorganic insulating material or an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) resin, or other materials. The first via layer VIA1 may be a single film or a multilayer film formed as stacked films of different materials.

[0141] The fourth conductive layer 160 may be positioned or disposed on the first via layer VIA1. The fourth conductive layer 160 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The fourth conductive layer 160 may be a single film or a multilayer film.

[0142] The fourth conductive layer 160 may include a connection electrode 161. A fifth contact hole CNT5, which may expose a second source / drain electrode 152 of a transistor located or disposed in the silicon transistor region AR1, may be located or disposed in the first via layer VIA1, and the connection electrode 161 may be connected to the second source / drain electrode 152 through the fifth contact hole CNT5.

[0143] The second via layer VIA2 can be positioned or disposed on the connecting electrode 161. The second via layer VIA2 may comprise an inorganic insulating material or an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, BCB resin, or other materials. The second via layer VIA2 can be a single film or a multilayer film formed as stacked films of different materials.

[0144] Pixel electrode ANO can be positioned or disposed on the second via layer VIA2. Pixel electrode ANO can be an anode electrode. Pixel electrode ANO can be positioned or disposed individually for each pixel. Pixel electrode ANO can be electrically connected to connection electrode 161 through a sixth contact hole CNT6, which can pass through the second via layer VIA2 and expose a portion of connection electrode 161.

[0145] The pixel electrode ANO is not limited to this and may have a stacked film structure in which layers of materials with high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and reflective material layers, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof, are stacked. The layer with high work function may be positioned or disposed above the reflective material layer and may be positioned or disposed close to the light-emitting layer EL. The pixel electrode ANO may have multilayer structures of ITO / Mg, ITO / MgF2, ITO / Ag, and ITO / Ag / ITO, but the disclosure is not limited thereto.

[0146] A pixel defining film (PDL) can be positioned or disposed on a pixel electrode (ANO). The PDL may include openings that partially expose the pixel electrode (ANO). The PDL may be made of organic or inorganic insulating materials. For example, the PDL may include at least one of polyimide resin, acrylic resin, silicone compound, polyacrylic resin, and other materials.

[0147] The light-emitting layer (EL) can be positioned or disposed on the pixel electrode (ANO) exposed by the pixel defining film (PDL). The light-emitting layer (EL) may include an organic material layer. The organic material layer of the light-emitting layer may include an organic light-emitting layer and may include a hole injection layer / hole transport layer and / or an electron injection layer / electron transport layer.

[0148] The cathode electrode (CAT) can be positioned or disposed on the light-emitting layer (EL). The cathode electrode (CAT) can be positioned or disposed on the entire pixel without distinguishing pixels as a common electrode, or positioned or disposed as a continuous layer. Each of the pixel electrode (ANO), the light-emitting layer (EL), and the cathode electrode (CAT) can form an organic light-emitting diode (OLED).

[0149] The cathode electrode CAT may comprise a layer of material with low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF2, Ba, compounds thereof, or mixtures thereof (e.g., mixtures of Ag and Mg or other materials). The cathode electrode CAT may also comprise a transparent metal oxide layer positioned or disposed on the material layer with low work function.

[0150] Pixel electrode (ANO), emissive layer (EL), and cathode electrode (CAT) can constitute an organic light-emitting diode (OLED).

[0151] A thin-film encapsulation layer 170, comprising a first inorganic film 171, a first organic film 172, and a second inorganic film 173, can be positioned or disposed above the cathode electrode CAT. The first inorganic film 171 and the second inorganic film 173 can contact each other at their ends. The first organic film 172 can be sealed by the first inorganic film 171 and the second inorganic film 173.

[0152] Each of the first inorganic membrane 171 and the second inorganic membrane 173 may include silicon nitride, silicon oxide, silicon oxynitride, or other materials. The first organic membrane 172 may include an organic insulating material.

[0153] The non-display area NDA will be described below.

[0154] The substrate 101, barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, second interlayer insulating film ILD2, first via layer VIA1, fourth conductive layer 160, second via layer VIA2, and pixel defining film PDL can be sequentially positioned or disposed in the non-display area NDA of the display panel 100. Each of the above layers can be formed as a single film or as a stacked film including multiple films. Another layer can be positioned or disposed between the layers.

[0155] The non-display area NDA may include the curved area BA and the curved opening OP2.

[0156] The curved region BA can be a region of the non-display region NDA that may not be positioned or may be provided with a barrier layer 102, a buffer layer 103, a first gate insulating film GI1, a first interlayer insulating film ILD1 and a second interlayer insulating film ILD2, as well as a region in which the upper surface of the substrate 101 may be exposed.

[0157] In the non-display area NDA, the bent opening OP2 can pass through the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, and second interlayer insulating film ILD2, and a portion of the substrate 101 can be exposed through the bent opening OP2. In the bent opening OP2, the side surfaces of the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, and second interlayer insulating film ILD2 can be exposed. The exposed side surfaces of the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, and second interlayer insulating film ILD2 can be stacked as follows: Figure 4 The arrangement shown is not limited to this.

[0158] The curved opening OP2 can be formed by the processes of forming the first contact holes CNT1 to the fourth contact holes CNT4 and forming the groove structure OP1 (which will be described below). Due to the formation of the curved opening OP2, bending stress that may occur when the above-mentioned display device 1 can be bent in the bending region BA can be prevented.

[0159] The curved opening OP2 can be filled with a first via layer VIA1. The first via layer VIA1 can be positioned in the non-display area NDA or disposed on the second interlayer insulating film ILD2, and can be positioned in the curved area BA or disposed on the exposed side surfaces of the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1 and second interlayer insulating film ILD2. The first via layer VIA1 can be in direct contact with the exposed upper surface of the substrate 101.

[0160] In the non-display area NDA and the curved area BA, the connecting line 165 can be positioned or disposed on the first via layer VIA1. The connecting line 165 can be formed by the fourth conductive layer 160. The connecting line 165 can be formed together with the connecting electrode 161 described above, and can be made of the same or similar material as the material forming the connecting electrode 161.

[0161] The second via layer VIA2 and the pixel defining film PDL can be positioned or disposed on the connecting line 165. In the non-display area NDA, at least one of the second via layer VIA2 and the pixel defining film PDL can be omitted.

[0162] In the following, a method for manufacturing a display device according to an embodiment will be described.

[0163] Figure 5 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment. Figures 6 to 21 This is a schematic cross-sectional view illustrating the process operation of a method for manufacturing a display device according to an embodiment.

[0164] Reference Figure 5 and Figure 6 First, a display area DA including a silicon transistor region AR1 and an oxide transistor region AR2 can be defined, as well as a non-display area NDA positioned or disposed around the display area DA, and a substrate 101 (S01) on which a silicon semiconductor layer 105 can be positioned or disposed can be provided in the silicon transistor region AR1.

[0165] like Figure 6 As shown, a barrier layer 102 and a buffer layer 103 can be sequentially stacked on a substrate 101. A silicon semiconductor layer can be formed on the buffer layer 103, and then the silicon semiconductor layer can be patterned by a photolithography process to form a silicon semiconductor layer 105.

[0166] Reference Figure 7 and Figure 8 A first gate insulating film GI1 can be formed on the silicon semiconductor layer 105, and a first conductive layer 120 (S02) including a first gate electrode 121 and a light-shielding pattern 122 can be formed on the first gate insulating film GI1.

[0167] A first gate insulating film GI1 can be formed on the entire surface of a buffer layer 103 on which a silicon semiconductor layer 105 can be formed. A first gate electrode 121 and a light-shielding pattern 122 can be formed simultaneously on the first gate insulating film GI1. The patterned first gate electrode 121 and the patterned light-shielding pattern 122 can be formed using a single mask process. For example, as... Figure 8 As shown, a material layer for the first conductive layer 120 can be deposited on the entire surface of the first gate insulating film GI1, and then the material layer can be patterned by photolithography to form the first gate electrode 121 and the light-shielding pattern 122.

[0168] Reference Figure 9 and Figure 10A first interlayer insulating film ILD1 can be formed on the first gate electrode 121 and the light-shielding pattern 122, and an oxide semiconductor layer 135 (S03) can be formed on the first interlayer insulating film ILD1.

[0169] A first interlayer insulating film (ILD1) can be formed on the entire surface of the first gate insulating film GI1, on which the first gate electrode 121 and the light-shielding pattern 122 can be formed. An oxide semiconductor layer 135 can be formed on the first interlayer insulating film ILD1. The oxide semiconductor layer 135 can be formed using a mask process. For example, as... Figure 10 As shown, a material layer for the oxide semiconductor layer 135 can be deposited on the entire surface of the first interlayer insulating film ILD1, and then the material layer can be patterned by a photolithography process to form the oxide semiconductor layer 135.

[0170] Reference Figure 11 A second gate insulating film GI2 can be formed on the oxide semiconductor layer 135, and a second gate electrode 142 can be formed on the second gate insulating film GI2 (S04).

[0171] A patterned second gate insulating film GI2 and a patterned second gate electrode 142 can be formed using a mask process. A material layer for the second gate insulating film GI2 can be deposited on the entire surface of a first interlayer insulating film ILD1 on which an oxide semiconductor layer 135 can be formed. Subsequently, a material layer for the second gate electrode 142 can be deposited on the entire surface of the material layer for the second gate insulating film GI2. The material layer for the second gate electrode 142 can be coated with a photoresist layer. A photoresist pattern can be formed by exposure and development, and the photoresist pattern can be used as an etching mask to sequentially etch the material layers for the second gate electrode 142 and the second gate insulating film GI2. The photoresist pattern can then be removed by a stripping or ashing process. The above describes a case where the photoresist pattern is used as an etching mask until the second gate insulating film GI2 can be patterned. However, when the lower layer is etched through a patterned upper layer, the upper layer can be used as a hard mask. In this case, the photoresist pattern can be used together with the hard mask as an etching mask. As an example, after forming a hard mask, the photoresist pattern can be removed, and the hard mask can be used as an etching mask to etch the underlying layer.

[0172] Reference Figure 12 and Figure 13 A second interlayer insulating film ILD2 can be stacked on the second gate electrode 142, and a first contact hole CNT1 and a second contact hole CNT2 (S05) that can expose a portion of the silicon semiconductor layer 105 can be formed in the display area DA.

[0173] Contact holes CNT1 and CNT2 can be formed using a single mask process. The first contact hole CNT1 and the second contact hole CNT2 can be formed simultaneously using the same mask. For example, an insulating layer for the second interlayer insulating film ILD1 can be deposited on the entire surface of the first interlayer insulating film ILD1, on which the oxide semiconductor layer 135, the second gate insulating film GI2, and the second gate electrode 142 can be formed. A first photoresist pattern PR1 that exposes a portion of the silicon semiconductor layer 105 can be formed on the insulating layer for the second interlayer insulating film ILD2, and the first photoresist pattern PR1 can be used as an etching mask to etch the insulating layer for the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the first gate insulating film GI1, thereby forming the first contact hole CNT1 and the second contact hole CNT2 that expose portions of the silicon semiconductor layer 105.

[0174] A bent opening OP2 can be formed in the non-display area NDA without any additional processes, through operations S05 of forming the first contact hole CNT1 and the second contact hole CNT2 and operations S06 of forming the trench structure OP1 (the trench structure OP1 can expose a portion of the first interlayer insulating film ILD1), the third contact hole CNT3 and the fourth contact hole CNT4 (which will be described below). A portion of the bent opening OP2 can be formed through operations S05 of forming the first contact hole CNT1 and the second contact hole CNT2.

[0175] The first photoresist pattern PR1 can be formed to expose a portion of the silicon semiconductor layer 105 and the curved opening OP2 of the curved region BA. When etching is performed using the first photoresist pattern PR1, the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the first gate insulating film GI1 in the curved region BA can be etched simultaneously in operation S05, which forms the first contact hole CNT1 and the second contact hole CNT2, thus exposing a portion of the buffer layer 103 in the corresponding region. Since the first contact hole CNT1 and the second contact hole CNT2 can be etched in operation S05 to expose a portion of the silicon semiconductor layer 105, the silicon semiconductor layer 105 may also be partially etched or damaged during the etching process. To minimize the damage that may be applied to the silicon semiconductor layer 105, operation S05 can be performed to etch only the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the first gate insulating film GI1 in the curved region BA. Therefore, in operation S05, the buffer layer 103 of the non-display region NDA can be retained without being removed. The process of forming the curved opening OP2 that can expose the surface of the substrate 101 can be accomplished by forming the third contact hole CNT3, the fourth contact hole CNT4 and the trench structure OP1 in operation S06 (which will be described below).

[0176] Reference Figure 14 A trench structure OP1 (S06) can be formed that can expose a portion of the oxide semiconductor layer 135, including a third contact hole CNT3 and a fourth contact hole CNT4, as well as a portion of the first interlayer insulating film ILD1.

[0177] Contact holes CNT3 and CNT4, trench structure OP1, and bent opening OP2 can be formed using a mask process. The third contact hole CNT3, the fourth contact hole CNT4, and trench structure OP1 can be formed simultaneously using the same mask. For example, a second photoresist pattern PR2 can be formed on the second interlayer insulating film ILD2, in which the first contact hole CNT1 and the second contact hole CNT2 can be formed, exposing portions of the oxide semiconductor layer 135 and the first interlayer insulating film ILD1. The second photoresist pattern PR2 can be used as an etching mask to etch the second interlayer insulating film ILD2, thereby forming the third contact hole CNT3 and the fourth contact hole CNT4 exposing portions of the oxide semiconductor layer 135, and the trench structure OP1 exposing portions of the first interlayer insulating film ILD1. Using the above process, the upper portion of the first interlayer insulating film ILD1 can also be etched in the region where the trench structure OP1 can be formed.

[0178] The process of forming a curved opening OP2 in the non-display area NDA can be completed by operation S06. The buffer layer 103 and the barrier layer 102 in the non-display area NDA that were not etched in operation S05 (forming the first contact hole CNT1 and the second contact hole CNT2) can be etched in operation S06. Therefore, the process of forming a curved opening OP2 that exposes a portion of the substrate 101 can be completed.

[0179] The thicknesses of the buffer layer 103 and the barrier layer 102 can be similar to the thickness of the second interlayer insulating film ILD2. For example, when etching the buffer layer 103 and the barrier layer 102, the method of etching the two components can be substantially the same as the method of etching the second interlayer insulating film ILD2, and a separate process may be unnecessary. Therefore, the process of forming the curved opening OP2 can be completed by etching the buffer layer 103 and the barrier layer 102 in operation S06.

[0180] Reference Figure 15A patterned third conductive layer 150 can be formed on the second interlayer insulating film ILD2 (S07). The third conductive layer 150 may include a first source / drain electrode 151 and a second source / drain electrode 152 of a transistor positioned or disposed in the silicon transistor region AR1, a first source / drain electrode 153 and a second source / drain electrode 154 of a transistor positioned or disposed in the oxide transistor region AR2, and a second electrode 155 of a capacitor Cst. The patterned third conductive layer 150 can be formed by a mask process. For example, a material layer for the third conductive layer 150 can be deposited on the entire surface of the second interlayer insulating film ILD2. In the deposition process, the material layer for the third conductive layer 150 can be positioned or deposited on the inner side of the first contact holes CNT1 to the fourth contact holes CNT4 and on the inner side of the trench structure OP1. Therefore, the first source / drain electrode 151 and second source / drain electrode 152 of the transistor located or disposed in the silicon transistor region AR1, the first source / drain electrode 153 and second source / drain electrode 154 of the transistor located or disposed in the oxide transistor region AR2, and the second electrode 155 of the capacitor Cst can be respectively connected to the silicon semiconductor layer 105, the oxide semiconductor layer 135, and the first interlayer insulating film ILD1. A material layer for the third conductive layer 150 can be coated with a photoresist layer. A photoresist pattern can be formed by exposure and development, and then the photoresist pattern can be used as an etching mask to etch the material layer for the third conductive layer 150. Thereafter, as... Figure 15 As shown, the photoresist pattern can be removed by a stripping or ashing process, thus completing the process of forming the patterned third conductive layer 150.

[0181] Reference Figure 16 and Figure 17 A first via layer VIA1 can be formed on the third conductive layer 150, and a fifth contact hole CNT5 (S08) can be formed to expose a portion of the second source / drain electrode 152 of the transistor located or disposed in the silicon transistor region AR1.

[0182] The first via layer VIA1 may include, for example, an organic material comprising a photosensitive material. The first via layer VIA1 may be stacked in the display area DA and the non-display area NDA, and may have a generally flat surface. In this case, the curved opening OP2 of the curved region BA of the non-display area NDA may also be filled with the first via layer VIA1. An organic material layer for the first via layer VIA1 may be applied to the third conductive layer 150, and then a fifth contact hole CNT5 may be formed by exposure and development. The fifth contact hole CNT5 may expose portions of the second source / drain electrodes 152 of the transistor positioned or disposed in the silicon transistor region AR1.

[0183] Reference Figure 18A fourth conductive layer 160 (S09) can be formed on the first via layer VIA1.

[0184] The fourth conductive layer 160 may include a connection electrode 161 positioned or disposed in the display area DA and a connection line 165 positioned or disposed in the non-display area NDA. The patterned fourth conductive layer 160 can be formed by a masking process. For example, a material layer for the fourth conductive layer 160 can be positioned or deposited on the entire surface of the first via layer VIA1. In the deposition process, a material layer for the fourth conductive layer 160 can be deposited on the inside of the fifth contact hole CNT5. Therefore, the connection electrode 161 can be connected to the second source / drain electrode 152 of the transistor positioned or disposed in the silicon transistor region AR1. The material layer for the fourth conductive layer 160 can be coated with a photoresist layer, and a photoresist pattern can be formed by exposure and development. The photoresist pattern can then be used as an etching mask to etch the material layer for the fourth conductive layer 160. Subsequently, the photoresist pattern can be removed by a stripping or ashing process, thus... Figure 18 As shown, a patterned fourth conductive layer 160 can be completely formed.

[0185] Reference Figure 19 A second via layer VIA2 can be formed on the fourth conductive layer 160, and a sixth contact hole CNT6 (S10) can be formed to expose the portion of the connecting electrode 161.

[0186] The second via layer VIA2 may include, for example, an organic material comprising a photosensitive material. The second via layer VIA2 may be stacked in the display area DA and the non-display area NDA, or only in the display area DA, and may have a generally flat surface. An organic material layer for the second via layer VIA2 may be applied to the fourth conductive layer 160, and then a sixth contact hole CNT6 that exposes the portion of the connection electrode 161 may be formed by exposure and development.

[0187] Reference Figure 20 An anode electrode ANO(S11) can be formed on the second via layer VIA2.

[0188] A patterned anode electrode ANO can be formed using a masking process. For example, a material layer for the anode electrode ANO can be deposited on the entire surface of the second via layer VIA2. In the deposition process, the material layer for the anode electrode ANO can be deposited on the inside of the sixth contact hole CNT6 and connected to the connecting electrode 161.

[0189] Reference Figure 21 A patterned pixel-defined film PDL (S12) can be formed on a second via layer VIA2 in which an anode electrode ANO can be formed.

[0190] Pixel-defined films (PDLs) can include, for example, organic materials containing photosensitive materials. In this case, a patterned pixel-defined film (PDL) can be formed by applying an organic material layer for the diaphragm and then performing exposure and development.

[0191] The pixel defining film (PDL) can be formed along the boundary of the pixel and can be partially stacked with the anode electrode (ANO). The pixel defining film (PDL) can be formed to be stacked with the sixth contact hole (CNT6). When the internal space of the sixth contact hole (CNT6) is partially filled by the anode electrode (ANO), the remaining internal space of the sixth contact hole (CNT6) can be completely filled by the pixel defining film (PDL).

[0192] As described above, according to the embodiment, a separate mask process for forming one of the two electrodes of the organic capacitor Cst is unnecessary. Therefore, the number of mask processes can be reduced, thereby improving process efficiency.

[0193] Other embodiments will be described below. In the following embodiments, descriptions of structures identical to those described above may be omitted or simplified, and the differences between the following embodiments and the above embodiments will be described primarily.

[0194] Figure 22 This is a schematic cross-sectional view of a display device according to an embodiment.

[0195] Reference Figure 22 According to the embodiment, the display device 1_1 and Figure 4 The difference in the embodiment of the display device 1 may be that the sidewall of the trench structure OP1_1 may include portions of the second interlayer insulating film ILD2 and the first interlayer insulating film ILD1.

[0196] In the etching process used to form the trench structure OP1_1, the exposed first interlayer insulating film ILD1 can be further etched after etching the second interlayer insulating film ILD2. In this case, the sidewalls of the trench structure OP1_1 can be formed by portions of the second interlayer insulating film ILD2 and the first interlayer insulating film ILD1. The thickness of the first interlayer insulating film ILD1 between the second electrode 155_1 (which can be formed on the trench structure OP1_1) and the first gate electrode 121 of the capacitor Cst can be smaller or thinner than the thickness of the other portion of the first interlayer insulating film ILD1.

[0197] In an embodiment, the gap between the second electrode 155_1 of capacitor Cst and the first electrode of capacitor Cst (the first electrode is connected to the first gate electrode 121) can be further reduced, thereby further increasing the capacitance of capacitor Cst formed between the two electrodes.

[0198] Figure 23 This is a schematic cross-sectional view of a display device according to an embodiment.

[0199] Reference Figure 23 The display device 1_2 according to the embodiment and Figure 4 The difference in the display device 1 in the embodiment may be that the bottom surface of the trench structure OP1_2 may be formed by a second interlayer insulating film ILD2.

[0200] In the embodiments, an example is shown in which the second interlayer insulating film ILD2 can be partially removed when the trench structure OP1_2 can be formed, and the second interlayer insulating film ILD2 can be retained with a small thickness. In this case, the trench structure OP1_2 can have a groove shape on the second interlayer insulating film ILD2, and the sidewalls and bottom surface of the trench structure OP1_2 can be formed from the second interlayer insulating film ILD2.

[0201] In this embodiment, the portion of the second electrode 155_2 of the capacitor Cst positioned or disposed in the trench structure OP1_2 may not directly contact the upper surface of the first interlayer insulating film ILD1. A portion of the second interlayer insulating film ILD2 and the first interlayer insulating film ILD1 may be positioned or disposed between the second electrode 155_2 of the capacitor Cst and the first gate electrode 121. However, even in this case, the thickness of the second interlayer insulating film ILD2 may be smaller or thinner than the thickness of the second interlayer insulating film ILD2 in another region, thereby reducing the gap between the second electrode 155_2 of the capacitor Cst and the first electrode of the capacitor Cst.

[0202] Figure 24 This is a schematic cross-sectional view of a display device according to an embodiment.

[0203] Reference Figure 24 According to the embodiment, the display device 1_3 and Figure 4 The difference in the embodiment of the display device 1 may be that the display device 1_3 may include an etch stop pattern 137_3 between the second electrode 155_3 of the capacitor Cst and the first interlayer insulating film ILD1, and the etch stop pattern 137_3 may be formed on the same layer as the oxide semiconductor layer 135.

[0204] The etch stop pattern 137_3 can be positioned in the silicon transistor region AR1 or disposed between the second electrode 155_3 of the capacitor Cst and the first interlayer insulating film ILD1, and stacked on the first interlayer insulating film ILD1. The bottom surface of the trench structure OP1 therein can be formed from the first interlayer insulating film ILD1. Figure 4Unlike other embodiments, the bottom surface of the trench structure OP1_3 according to this embodiment can be formed by an etch stop pattern 137_3. Therefore, the second electrode 155_3 of the capacitor Cst may not be in direct contact with the first interlayer insulating film ILD1, but rather may be in direct contact with the etch stop pattern 137_3 positioned or disposed on the first interlayer insulating film ILD1. The etch stop pattern 137_3 may have a width (or length) greater than the width (or length) of the trench structure OP1_3, and may protrude outwards at least from the sidewall of the trench structure OP1_3.

[0205] The etch stop pattern 137_3 can have a higher conductivity than the channel region 135c of the oxide semiconductor layer 135. The etch stop pattern 137_3 can have the same or similar conductivity as the first source / drain region 135a and the second source / drain region 135b of the oxide semiconductor layer 135. Therefore, the etch stop pattern 137_3 can be used as an electrode instead of as a dielectric of the capacitor Cst. For example, the etch stop pattern 137_3 and the second electrode 155_3 in contact with the upper part of the capacitor Cst can constitute a stacked second electrode of the capacitor Cst.

[0206] The second electrode 155_3 of the capacitor Cst can be superimposed on at least a portion of the etch stop pattern 137_3. In this case, the etch stop pattern 137_3 and the first interlayer insulating film ILD1 can be positioned or disposed between the second electrode 155_3 of the capacitor Cst and the first gate electrode 121.

[0207] The etch stop pattern 137_3 can be used as an etch stop when forming the trench structure OP1. Therefore, by making the dielectric thickness of the capacitor Cst uniform, the uniformity and stability of the capacitor Cst can be further improved.

[0208] In operation S03, which forms the oxide semiconductor layer 135, the etch stop pattern 137_3 and the oxide semiconductor layer 135 can be formed simultaneously using the same mask. Therefore, the material used to form the etch stop pattern 137_3 can be the same as the material used to form the oxide semiconductor layer 135, and the etch stop pattern 137_3 can be positioned or disposed on the same layer as the layer on which the oxide semiconductor layer 135 can be positioned or disposed. Since a separate mask for forming the etch stop pattern 137_3 is unnecessary, the number of masks required for the process is not increased.

[0209] Even in this case, a separate conductive layer may not be necessary for forming the first gate electrode 121 and the capacitor Cst, and the mask used to form the separate conductive layer may also be unnecessary, thus reducing the number of masks required for the process.

[0210] Figure 25 This is a schematic cross-sectional view of a display device according to an embodiment.

[0211] Reference Figure 25 According to the embodiment, the display device 1_4 and Figure 24 The difference in the display device 1_3 in the embodiment is that the second electrode 155_4 of the capacitor Cst can be completely superimposed with the etch stop pattern 137_4.

[0212] In the silicon transistor region AR1, the etch stop pattern 137_4 can be positioned or disposed between the second electrode 155_4 of the capacitor Cst and the first interlayer insulating film ILD1. The etch stop pattern 137_4 can be stacked on the first interlayer insulating film ILD1, and the second electrode 155_4 of the capacitor Cst can be completely stacked with the etch stop pattern 137_4. Therefore, the uniformity and stability of the capacitor Cst formed by the second electrode 155_4 of the capacitor Cst and the etch stop pattern 137_4 and the first gate electrode 121 can be further improved.

[0213] Even in this case, a separate conductive layer may not be necessary for forming the first gate electrode 121 and the capacitor Cst, and the mask used to form the separate conductive layer may also be unnecessary, thus reducing the number of masks required for the process.

[0214] Figure 26 This is a schematic cross-sectional view of a display device according to an embodiment.

[0215] Reference Figure 26 According to the embodiment, the display device 1_5 and Figure 4 The difference in the embodiment of the display device 1 is that the display device 1_5 may not include the second via layer VIA2 and the fourth conductive layer 160, but may include a curved via layer VIA0 in the non-display area NDA.

[0216] For example, in the non-display area NDA, the bent opening OP2_5 may be filled with a bent via layer VIA0 instead of the first via layer VIA1. The bent via layer VIA0 may comprise an inorganic insulating material or an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, BCB resin, or other materials. The bent via layer VIA0 may be a single film or a multilayer film formed as stacked films of different materials. The bent via layer VIA0 may be made of the same or similar material as the first via layer VIA1, but the disclosure is not limited thereto.

[0217] The non-display area line 156_5 can be positioned or disposed on the curved via layer VIA0. The non-display area line 156_5 can be formed by the third conductive layer 150. The non-display area line 156_5 can be formed together with the first source / drain electrode 151 and the second source / drain electrode 151 and 152 of the transistor positioned or disposed in the silicon transistor region AR1, the first source / drain electrode 153 and the second source / drain electrode 154 of the transistor positioned or disposed in the oxide transistor region AR2, and the second electrode 155 of the capacitor Cst, and can be made of the same or similar material as the material forming the above-described components 151, 152, 153, 154 and 155.

[0218] The first via layer VIA1 can be positioned or set on the non-display area line 156_5. The first via layer VIA1 can be formed simultaneously with the first via layer VIA1 of the display area DA, so that it has a height that is substantially the same as the height of the first via layer VIA1 of the display area DA.

[0219] In the display area DA, the anode electrode ANO and the pixel defining film PDL can be formed on the first via layer VIA1, and the anode electrode ANO can be stacked in the fifth contact hole CNT5_5.

[0220] Even in this case, a separate conductive layer may not be necessary for forming the first gate electrode 121 and the capacitor Cst, and the mask used to form the separate conductive layer may also be unnecessary, thus reducing the number of masks required for the process.

[0221] The manufacturing process will be described below. Figure 26 The method of the display device in the embodiment of the present invention.

[0222] Figure 27 It shows the manufacturing basis. Figure 26 A flowchart of a method for displaying a device according to an embodiment. Figures 28 to 30 It shows the manufacturing basis. Figure 26 A schematic cross-sectional view of the process operation of the method of the display device in an embodiment.

[0223] Reference Figure 27 and Figure 28As described above, the bent opening OP2_5 can be formed by operations S05 and S06, which form the first contact holes CNT1 to the fourth contact holes CNT4, the trench structure OP1, and the bent opening OP2_5. After operations S05 and S06, a bent via layer VIA0 (S06_5) can be formed on the bent opening OP2_5. The bent opening OP2_5 can be filled with the bent via layer VIA0, which can contact the upper surface of the substrate 101 in the bent opening OP2_5, and contact the side surfaces of the barrier layer 102, the buffer layer 103, the first gate insulating film GI1, the first interlayer insulating film ILD1 and the second interlayer insulating film ILD2, and the upper surface of the second interlayer insulating film ILD2.

[0224] Reference Figure 29 and Figure 30 A third conductive layer 150 (S07) can be formed on the second interlayer insulating film ILD2 and the bent via layer VIA0. The third conductive layer 150 may include a first source / drain electrode 151 and a second source / drain electrode 152 of a transistor located or disposed in the silicon transistor region AR1, a first source / drain electrode 153 and a second source / drain electrode 154 of a transistor located or disposed in the oxide transistor region AR2, a second electrode 155 of a capacitor Cst, and a non-display area line 156_5 located or disposed on the bent via layer VIA0.

[0225] A first via layer VIA1 (S08) can be formed on the third conductive layer 150. The first via layer VIA1 can have the same height in the display area DA and the non-display area NDA.

[0226] Although the disclosed embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the spirit and scope of the disclosure. Therefore, the above embodiments should be considered in a descriptive sense only and not for limiting purposes.

Claims

1. A display device, the display device comprising: Base; A first semiconductor pattern is disposed on the substrate; A first gate insulating film is disposed on the first semiconductor pattern; A first conductive layer is disposed on the first gate insulating film and includes: a first gate electrode; and a first electrode of a capacitor connected to the first gate electrode; A first interlayer insulating film is disposed on the first conductive layer; The second semiconductor pattern and the third semiconductor pattern are disposed on the first interlayer insulating film; A second gate insulating film is disposed on the second semiconductor pattern; The second gate electrode is disposed on the second gate insulating film; A second interlayer insulating film is disposed on the second gate electrode and the third semiconductor pattern; and A second conductive layer is disposed on the second interlayer insulating film and includes: a first source / drain electrode; a second source / drain electrode; and a second electrode of the capacitor. The second electrode of the capacitor is disposed in the trench structure in which the second interlayer insulating film is at least partially removed. The second electrode of the capacitor is further disposed on the upper surface of the second interlayer insulating film outside the trench structure, and The bottom surface of the trench structure is formed by the third semiconductor pattern, and the third semiconductor pattern is in contact with the second electrode of the capacitor and is disposed between the second electrode of the capacitor and the first interlayer insulating film.

2. The display device according to claim 1, wherein, The first interlayer insulating film is disposed between the first electrode and the second electrode of the capacitor, but the second interlayer insulating film is not present.

3. The display device according to claim 2, wherein, The thickness of the first interlayer insulating film between the first electrode and the second electrode of the capacitor is less than the thickness of the first interlayer insulating film in the region where the first interlayer insulating film is not stacked with the second conductive layer.

4. The display device according to claim 1, wherein, The thickness of the second interlayer insulating film between the first electrode and the second electrode of the capacitor is less than the thickness of the second interlayer insulating film in the region where the second interlayer insulating film is not stacked with the second conductive layer.

5. The display device according to claim 1, wherein: The sidewalls of the trench structure are formed by the second interlayer insulating film.

6. The display device according to claim 1, the display device further comprising a light-shielding pattern, the light-shielding pattern being coplanar with the first gate electrode and superimposed on the second semiconductor pattern.

7. The display device according to claim 6, wherein, The light-shielding pattern is connected to the second gate electrode or to one of the first source / drain electrode and the second source / drain electrode.

8. The display device according to claim 1, wherein, The second semiconductor pattern includes: a channel region superimposed on the second gate electrode; and a source / drain region disposed on the outside of the second gate electrode. The source / drain region and the third semiconductor pattern have a higher conductivity than the channel region.

9. The display device according to claim 8, wherein, The third semiconductor pattern has the same conductivity as the source / drain region.

10. A display device, the display device comprising: The first transistor includes a non-oxide semiconductor; The second transistor includes an oxide semiconductor disposed on a different layer from the non-oxide semiconductor; Capacitor; The first conductive layer includes the first electrode of the capacitor and the gate electrode of the first transistor; The second conductive layer includes the gate electrode of the second transistor; as well as The third conductive layer includes the source / drain electrodes of the first transistor, the source / drain electrodes of the second transistor, and the second electrode of the capacitor; The second electrode of the capacitor is disposed in a trench structure formed by an insulating layer. The second electrode of the capacitor is further disposed on the upper surface of the insulating layer outside the trench structure, and The bottom surface of the trench structure is formed by a third semiconductor pattern, and the third semiconductor pattern is in contact with the second electrode of the capacitor and is disposed between the second electrode of the capacitor and the first conductive layer.

11. The display device according to claim 10, wherein, One of the first transistor and the second transistor is a p-type metal-oxide-semiconductor transistor, and The other of the first transistor and the second transistor is an n-type metal-oxide-semiconductor transistor.

12. The display device according to claim 10, wherein, The insulating layer includes: a first insulating layer; and a second insulating layer disposed on the first insulating layer, and The trench structure includes: a sidewall formed of the second insulating layer; and the bottom surface.

13. A method for manufacturing a display device, the method comprising the following steps: A first semiconductor pattern is formed on the substrate; A first gate insulating film is formed on the first semiconductor pattern; Forming a first conductive layer on the first gate insulating film includes: forming a first gate electrode; and forming a first electrode of a capacitor connected to the first gate electrode. A first interlayer insulating film is formed on the first gate electrode and the first electrode of the capacitor; A second semiconductor pattern and a third semiconductor pattern superimposed on the first electrode of the capacitor are formed on the first interlayer insulating film; An insulating layer is formed on the second semiconductor pattern to form a second gate insulating film; A second conductive layer is formed on the insulating layer of the second gate insulating film; The insulating layer of the second conductive layer and the second gate insulating film is etched using a first etch mask to form the second gate electrode and the second gate insulating film; A second interlayer insulating film is formed on the second gate electrode and the third semiconductor pattern; The second interlayer insulating film, the first interlayer insulating film, and the first gate insulating film are etched using a second etch mask, and contact holes are formed to expose the source / drain regions of the first semiconductor pattern. The second interlayer insulating film is etched using a third etch mask, and a trench structure overlapping with the first electrode of the capacitor and exposing the third semiconductor pattern, and contact holes exposing the source / drain regions of the second semiconductor pattern are formed; and Forming a third conductive layer on the second interlayer insulating film includes: forming a first source / drain electrode; forming a second source / drain electrode; and forming a second electrode of the capacitor disposed in the trench structure on the second interlayer insulating film. The second electrode of the capacitor is further disposed on the upper surface of the second interlayer insulating film outside the trench structure, and The bottom surface of the trench structure is formed by the third semiconductor pattern, and the third semiconductor pattern is in contact with the second electrode of the capacitor and is disposed between the second electrode of the capacitor and the first interlayer insulating film.

14. The method according to claim 13, wherein, The step of forming the first interlayer insulating film includes: forming the first interlayer insulating film between the first electrode and the second electrode of the capacitor without forming the second interlayer insulating film.

15. The method according to claim 14, wherein, The step of forming the first interlayer insulating film includes: forming the thickness of the first interlayer insulating film between the first electrode and the second electrode of the capacitor to be less than the thickness of the first interlayer insulating film in the region in which the first interlayer insulating film is not stacked with the third conductive layer.

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