Multi-photodiode pixel unit

Abstract

A device is provided. The device includes a semiconductor substrate, which includes a first photodiode for generating a first charge, a second photodiode for generating a second charge, and a blocking layer located between the first photodiode and the second photodiode. Among them, the first photodiode, the blocking layer, and the second photodiode form a stack. The device further includes a floating drain and one or more gates, and the one or more gates include: a first gate portion and a second gate portion. The first gate portion is on the semiconductor substrate, and the second gate portion extends from the front surface through the first photodiode and reaches the blocking layer. The first gate portion is configured to conduct a first signal to control the flow of charge from the first photodiode to the floating drain, and the second gate portion is configured to conduct a second signal for controlling the blocking layer to control the flow of the second charge.

Description

[0001] Related Applications

[0002] This patent application claims priority to U.S. Provisional Patent Application Ser. No. 62 / 669,160, filed on May 9, 2018, entitled "PIXEL STRUCTURE WITH VERTICALLY-STACKED PINNED PHOTODIODES AND DEEP-GATE-BASED BARRIER SWITCHING", which is assigned to the assignee of the present invention and which is hereby incorporated by reference in its entirety for all purposes.

[0003] Background

[0004] The present disclosure generally relates to image sensors, and more particularly, to pixel cells including a plurality of photodiodes.

[0005] Typical pixels in an image sensor include a photodiode that senses incident light by converting photons into charge (e.g., electrons or holes). During exposure, the charge can be temporarily stored in the photodiode. To improve noise and dark current performance, a pinned photodiode can be included in the pixel to convert photons into charge. The pixel can further include a capacitor (e.g., a floating diffusion) to collect the charge from the photodiode and convert the charge into a voltage. An image of a scene can be derived from the voltages generated on the capacitors of the pixel array.

[0006] Summary

[0007] The present disclosure relates to image sensors. More specifically and without limitation, the present disclosure relates to an image sensor having an array of pixel cells.

[0008] In some examples, a device is provided. The device includes a semiconductor substrate that includes a front surface, a first photodiode, a second photodiode, a barrier layer, and a floating drain. The first photodiode is configured to generate a first charge, and the second photodiode is configured to generate a second charge. The barrier layer is between the first photodiode and the second photodiode and is configured to control the flow of the second charge from the second photodiode to the first photodiode. The floating drain is used to store the first charge or the second charge. The first photodiode, the barrier layer, and the second photodiode form a stack along an axis perpendicular to the front surface. The device further includes one or more gates that include: a first gate portion on the front surface above a channel region between the first photodiode and the floating drain; and a second gate portion that extends from the front surface through the first photodiode and reaches the barrier layer. The first gate portion is configured to conduct a first signal to control the flow of charge from the first photodiode via the channel region to the floating drain. The second gate portion is configured to conduct a second signal for controlling the barrier layer to control the flow of the second charge.

[0009] In some aspects, the device further includes a controller configured to: transmit a first signal via the first gate portion to transfer the first charge from the first photodiode to the floating drain via the channel region for readout; transmit a second signal via the second gate portion to transfer the second charge from the second photodiode to the first photodiode via the barrier layer; and transmit a first signal via the first gate portion to transfer the second charge from the second photodiode to the floating drain via the channel region for readout.

[0010] In some aspects, the semiconductor substrate is a first semiconductor substrate. The device further includes a second semiconductor substrate. The controller is part of the second semiconductor substrate.

[0011] In some aspects, the semiconductor substrate includes a back surface opposite the front surface, and the back surface is configured as a light-receiving surface. The first photodiode is configured to convert a first component of light in the infrared light wavelength range into the first charge. The second photodiode is configured to convert a second component of light in the visible light wavelength range into the second charge.

[0012] In some aspects, the front surface is configured as a light-receiving surface; the first photodiode is configured to convert a first component of light in the visible light wavelength range into the first charge; and the second photodiode is configured to convert a second component of light in the infrared light wavelength range into the second charge.

[0013] In some aspects, the semiconductor substrate includes a P-well that forms sidewalls on four sides of a stack of a first photodiode, a blocking layer, and a second photodiode. A second portion extends along a centerline passing through the first photodiode, and the centerline is equidistant from at least two of the sidewalls formed by the P-well.

[0014] In some aspects, the device further includes an oxide layer between the second gate portion and the first photodiode; and an interface passivation region (IPR) between the oxide layer and the first photodiode.

[0015] In some aspects, the IPR and the blocking layer are configured to provide an electric potential gradient from the second photodiode to the first photodiode.

[0016] In some aspects, the IPR and the blocking layer have different doping profiles to provide the electric potential gradient.

[0017] In some aspects, the second gate portion is doped with a dopant that has a doping concentration gradient along an axis to introduce an electric potential gradient.

[0018] In some aspects, the second photodiode is biased at a first voltage; the blocking layer is biased at a second voltage by a signal at the second gate portion; the first photodiode is biased at a third voltage; the channel region is biased at a fourth voltage by a signal at the first gate portion; and the first voltage, the second voltage, the third voltage, and the fourth voltage form an electric potential gradient from the second photodiode to the channel region to enable a second charge to flow following the electric potential gradient.

[0019] In some aspects, the device further includes a guard ring structure that shields an end of the second gate portion from the blocking layer.

[0020] In some aspects, the second gate portion has a non-uniform cross-sectional area.

[0021] In some aspects, the second gate portion has a wedge shape and includes inclined sidewalls that are inclined towards the light receiving surface.

[0022] In some aspects, the semiconductor substrate further includes a deep trench isolation (DTI) structure that extends along an axis. At least a portion of the first photodiode is located between the DTI structure and the inclined sidewalls of the second gate portion. The inclined sidewalls also incline towards the DTI structure and are configured to reflect a first light component towards the DTI structure and through the at least a portion of the first photodiode. The DTI structure is configured to reflect the first light component towards the inclined sidewalls and through the at least a portion of the first photodiode.

[0023] In some aspects, one or more gates include a first gate including a first gate portion and a second gate including a second gate portion. The first gate and the second gate are electrically insulated from each other.

[0024] In some aspects, one or more gates include a merged gate including a first gate portion and a second gate portion that are electrically connected to each other.

[0025] In some aspects, a first signal is transmitted via the first gate portion to transfer a first charge from a first photodiode to a floating drain via a channel region for readout; a second signal is transmitted via the second gate portion to: transfer a second charge from a second photodiode to the first photodiode via a blocking layer; and transfer the second charge from the second photodiode to the floating drain via the channel region for readout. The first signal is not sufficient to cause the second charge to flow from the second photodiode to the first photodiode via the blocking layer.

[0026] In some examples, a method is provided. The method includes: transmitting a first signal via a first gate portion of one or more gates to transfer a first charge from a first photodiode to a floating drain via a channel region between the first photodiode and the floating drain for readout, wherein the first gate portion is formed on a front side surface of a semiconductor substrate that further includes a floating drain, a first photodiode for generating the first charge, a second photodiode for generating a second charge, a blocking layer located between the first photodiode and the second photodiode, and the first photodiode, the blocking layer, and the second photodiode are formed in a stack along an axis perpendicular to the front side surface; quantifying the first charge in the floating drain to measure an intensity of light in a first wavelength range; transmitting a second signal via a second gate portion of one or more gates to transfer the second charge from the second photodiode to the first photodiode via the blocking layer, wherein the second gate portion extends along the axis from the front side surface through the first photodiode and reaches the blocking layer; transmitting the first signal via the first gate portion to transfer the second charge from the first photodiode to the floating drain via the channel region; and quantifying the second charge in the floating drain to measure an intensity of light in a second wavelength range.

[0027] In some aspects, the first wavelength range corresponds to a wavelength range of infrared light. The second wavelength range corresponds to a wavelength range of visible light. Brief Description of the Drawings

[0029] Exemplary embodiments are described with reference to the following drawings:

[0030] Figure 1A and Figure 1B are schematic diagrams of embodiments of a near-eye display.

[0031] Figure 2 is an embodiment of a cross-section of a near-eye display.

[0032] Figure 3 An isometric view of an embodiment of a waveguide display is shown.

[0033] Figure 4 A cross-section of an embodiment of a waveguide display is shown.

[0034] Figure 5 is a block diagram of an embodiment of a system including a near-eye display.

[0035] Figure 6 An example of an image sensor including multi-photodiode pixel units is shown.

[0036] Figure 7A and Figure 7B shows Figure 6 an example of the operation of the image sensor.

[0037] Figure 8 shows what can be Figure 6 an example of an array of pixel units that can be part of the image sensor.

[0038] Figure 9A and Figure 9B shows Figure 8 an example of the internal components of the pixel unit.

[0039] Figure 10 shows an example of the potential distribution for reading out charge from the Figure 8 array of pixel units.

[0040] Figure 11A and Figure 11B shows Figure 8 an example of the internal components of the pixel unit.

[0041] Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 12D 、 Figure 12E and Figure 12F shows Figure 8 an example of the internal components of the pixel unit.

[0042] Figure 13A and Figure 13B shows Figure 8 an example of the operation of the pixel unit.

[0043] Figure 14A and Figure 14B shows Figure 8 an example of the operation of the pixel unit.

[0044] Figure 15 shows an example of the internal components of the pixel unit of Figure 8 .

[0045] Figure 16 shows an example of the internal components of the pixel unit of Figure 8 .

[0046] Figure 17A , Figure 17B and Figure 17C show an example of the internal components and control signals of the pixel unit of Figure 8 .

[0047] Figure 18 shows an example of the operation of the pixel unit of Figure 8 .

[0048] Figure 19 shows an example of the internal components of the pixel unit of Figure 8 .

[0049] Figure 20 shows a flowchart of an example method for measuring light intensity.

[0050] The accompanying drawings depict embodiments of the present disclosure for illustrative purposes only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods shown can be employed without departing from the principles of the present disclosure and the advantages to be promoted.

[0051] In the accompanying drawings, similar components and / or features may have the same reference numerals. Additionally, each component of the same type can be distinguished by using a dash after the reference numeral and a second mark that differentiates between similar components. If only the first reference numeral is used in the specification, the description applies to any one of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0052] Detailed Description

[0053] In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain inventive embodiments. However, it is apparent that the various embodiments can be practiced without these specific details. The drawings and the description are not intended to be restrictive.

[0054] A typical image sensor generally includes a pixel unit array. Each pixel unit may have a photodiode to sense incident light by converting photons into charges (e.g., electrons or holes). To improve noise and dark current performance, a pinned photodiode may be included in the pixel to convert photons into charges. During exposure, the charges may be temporarily stored in the photodiode. Each pixel unit may also include a floating diffusion node to convert the charges into a voltage. A pixel value may be generated based on the voltage. The pixel value may represent the intensity of the light received by the pixel unit. An image including the pixel array may be derived from the digital output of the voltages output by the pixel unit array.

[0055] The image sensor can be used to perform imaging in different modes, such as 2D and 3D sensing. 2D and 3D sensing can be performed based on light in different wavelength ranges. For example, visible light can be used for 2D sensing, while invisible light (e.g., infrared light) can be used for 3D sensing. The image sensor may include a filter array to allow visible light in different optical wavelength ranges and colors (e.g., red, green, and blue) to reach a first set of pixel units assigned for 2D sensing, and to allow invisible light to reach a second set of pixel units assigned for 3D sensing.

[0056] To perform 2D sensing, the photodiode at the pixel unit may generate charges at a rate proportional to the intensity of the visible light incident on the pixel unit, and the amount of charge accumulated during the exposure period may be used to represent the intensity of the visible light (or a specific color component of the visible light). The charges may be temporarily stored at the photodiode and then transferred to a capacitor (e.g., floating diffusion) to generate a voltage. The voltage may be sampled and quantified by an analog-to-digital converter (ADC) to generate an output corresponding to the intensity of the visible light. The image pixel value may be generated based on the outputs of multiple pixel units configured to sense different color components (e.g., red, green, and blue) of the visible light.

[0057] In addition, to perform 3D sensing, light in different wavelength ranges (e.g., infrared light) may be projected onto an object, and the reflected light may be detected by the pixel units. The light may include structured light, light pulses, etc. The pixel unit outputs can be used to perform depth sensing operations based on, for example, detecting the pattern of the reflected structured light, measuring the time of flight of the light pulses, etc. To detect the pattern of the reflected structured light, the distribution of the amount of charge generated by the pixel units during the exposure time may be determined, and a pixel value may be generated based on the voltage corresponding to the amount of charge. For time-of-flight measurement, the timing of generating charges at the photodiode of the pixel unit may be determined to represent the time when the reflected light pulse is received at the pixel unit. The time difference between when the light pulse is projected onto the object and when the reflected light pulse is received at the pixel unit may be used to provide the time-of-flight measurement.

[0058] The pixel unit array can be used to generate scene information. In some examples, a subset of pixel units within the array (e.g., a first set) can be used to perform 2D sensing of the scene, and another subset of pixel units within the array (e.g., a second set) can be used to perform 3D sensing of the scene. The fusion of 2D and 3D imaging data is very useful for many applications that provide virtual reality (VR), augmented reality (AR), and / or mixed reality (MR) experiences. For example, a wearable VR / AR / MR system can perform scene reconstruction of the environment in which the system's user is located. Based on the reconstructed scene, VR / AR / MR can generate a display effect to provide an interactive experience. To reconstruct the scene, a subset of pixel units within the pixel unit array can perform 3D sensing to, for example, identify a set of physical objects in the environment and determine the distance between the physical objects and the user. Another subset of pixel units within the pixel unit array can perform 2D sensing to, for example, capture visual attributes including the texture, color, and reflectivity of these physical objects. The 2D and 3D image data of the scene can then be combined to create, for example, a 3D model of the scene that includes the visual attributes of the objects. As another example, a wearable VR / AR / MR system can also perform head tracking operations based on the fusion of 2D and 3D image data. For example, based on the 2D image data, the VR / AR / AR system can extract certain image features to identify an object. Based on the 3D image data, the VR / AR / AR system can track the position of the identified object relative to the wearable device worn by the user. The VR / AR / AR system can track head movement based on, for example, the change in the position of the identified object relative to the wearable device when the user's head moves.

[0059] However, using different sets of pixels for 2D and 3D imaging presents many challenges. First, since only a subset of the pixel units of the array is used to perform 2D imaging or 3D imaging, the spatial resolution of both the 2D image and the 3D image is lower than the maximum spatial resolution available at the pixel unit array. Although the resolution can be increased by including more pixel units, this approach results in an increase in the form factor of the image sensor as well as power consumption, both of which are particularly undesirable for wearable devices.

[0060] In addition, since the pixel units assigned to measure light in different wavelength ranges (for 2D and 3D imaging) are not collocated, different pixel units may capture information about different points of a scene, which complicates the mapping between 2D and 3D images. For example, a pixel unit that receives a specific color component of visible light (for 2D imaging) and a pixel unit that receives invisible light (for 3D imaging) may also capture information about different points of the scene. The outputs of these pixel units cannot be simply combined to generate 2D and 3D images. When a pixel unit array captures 2D and 3D images of a moving object, the lack of correspondence between the outputs of the pixel units due to their different positions deteriorates. Although there are processing techniques available for associating the outputs of different pixel units to generate a 2D image and for associating (e.g., interpolating) between 2D and 3D images, these techniques are typically computationally intensive and also increase power consumption.

[0061] The present disclosure relates to an image sensor having a pixel unit array. In some embodiments, each pixel unit includes a semiconductor substrate. The semiconductor substrate includes a first photodiode, a blocking layer, and a second photodiode that are formed in a stack along a propagation path of light within the semiconductor substrate. The first photodiode may convert a first component of light into a first charge, while the second photodiode may convert a second component of light into a second charge. In some examples, both the first photodiode and the second photodiode may be pinned photodiodes. The semiconductor substrate further includes a floating drain. The first photodiode may transfer the first charge to the floating drain for readout. The second photodiode may also transfer the second charge to the floating drain via the first photodiode for readout. A barrier carrier is sandwiched between the first photodiode and the second photodiode and may control the transfer of the second charge from the second photodiode to the first photodiode.

[0062] The pixel unit further includes one or more gates. The one or more gates include a first gate portion and a second gate portion. The first gate portion may be formed on the front surface of the first semiconductor substrate and may extend over the channel region between the first photodiode and the floating diffusion node. The second gate portion may extend from the front surface into the semiconductor substrate, intersect the first photodiode, and reach the blocking layer. The first gate portion may transmit a first signal for adjusting the electric potential of the channel region to control the transfer of the first charge or the second charge from the first photodiode to the floating diffusion node. The second gate portion may transmit a second signal for adjusting the electric potential of the blocking layer to control the transfer of the second charge from the second photodiode to the first photodiode. In some embodiments, the one or more gates may include a first gate including the first gate portion and a second gate including the second gate portion, and the first gate and the second gate are electrically isolated from each other. In some embodiments, to reduce the footprint of the pixel unit, the one or more gates may include a merged gate, in which the first gate portion and the second gate portion are electrically connected to each other.

[0063] Various techniques have been proposed to improve the flow of the second charge under the control of the second gate. For example, the second gate may extend along the centerline of the stack of the first photodiode, the blocking layer, and the second photodiode, where most of the charge is located because incident light is typically concentrated on the centerline of the pixel unit as it propagates within the stack. With this arrangement, the propagation path of most of the second charge through the blocking layer can be shortened, which can facilitate the flow of the second charge via the blocking layer. As another example, the semiconductor substrate may include an interface passivation region (IPR) around the interface between the second gate and the first photodiode to reduce dark current. A potential gradient may also be introduced between the blocking layer and the IPR to facilitate the flow of the second charge from the second photodiode into the first photodiode and prevent the charge from flowing back from the first photodiode to the second photodiode. As yet another example, considering the case where the second gate penetrates the blocking layer and reaches the second photodiode (e.g., by design, due to process control limitations, etc.), the semiconductor substrate may include a guard ring for isolating the second gate from the second photodiode to prevent the second charge from being trapped where the second gate intersects / reaches the second photodiode.

[0064] The pixel unit further includes a controller and a processing circuit, which can be part of a semiconductor substrate or can be formed in a separate semiconductor substrate. The controller can transmit a first signal to the first gate to enable a first charge to be transferred from the first photodiode to the floating diffusion node. The processing circuit can read out and quantify the first charge in the floating drain node to generate a first digital representation of a first component of light. The controller can reset the floating drain node after the measurement is completed. The controller can then transmit a second signal for controlling the blocking layer to allow a second charge to flow from the second photodiode to the first photodiode. The controller can also transmit the first signal to the first gate to enable the second charge to be transferred from the first photodiode to the floating diffusion node. The processing circuit can read out and quantify the second charge in the floating drain node to generate a second digital representation of a second component of light. In the case where the second gate and the first gate are electrically shorted together to form a combined gate, the combined gate can transmit the first signal and the second signal at different times. The first signal and the second signal can also have different signal levels to ensure that, in response to the first signal and the second signal, the transfer of charge (the first charge or the second charge) from the first photodiode to the floating drain and the transfer of the second charge via the blocking layer also occur at different times.

[0065] Using examples of the present disclosure, the pixel unit can use pinned photodiodes to perform photon-charge conversion for 2D and 3D imaging operations. Since pinned photodiodes can provide excellent performance in terms of dark current and noise, the pixel unit can more accurately measure low-intensity light, which can improve the sensitivity and performance of the image sensor in low-light intensity environments. In addition, performing 2D and 3D sensing with the same set of pixel units can facilitate the correspondence between the 2D image and the 3D image generated by the pixel units, especially in the case where the pinned photodiodes of each pixel unit simultaneously detect and measure light of different wavelengths within the same exposure period. Further, assuming that each pixel unit of the pixel unit array can be used to generate a 2D or 3D image, the full spatial resolution of the pixel unit array can be utilized. Therefore, the spatial resolution of the image can also be improved while the form factor and power consumption of the image sensor can be reduced.

[0066] The proposed pixel structure uses a gate to control the potential of the blocking layer to regulate the flow of charge from the second photodiode to the first photodiode, and this pixel structure can also provide additional advantages. For example, compared with the case of using conductive deep trench isolation (C-DTI) to control the potential of the blocking layer, the gate can have a much larger aspect ratio than this DTI structure and can be fabricated using a standard and relatively inexpensive process. In addition, as explained above, the gate can be strategically positioned (e.g., positioned on the center line of the photodiode stack) to facilitate the flow of most of the charge via the blocking layer.

[0067] Examples of the present disclosure may include or be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been adjusted in some manner before being presented to a user, and may include, for example, virtual reality (VR), augmented reality (AR), mixed reality (MR), hybrid reality, or some combination and / or derivative thereof. Artificial reality content may include fully generated content or content generated in combination with captured (e.g., real-world) content. Artificial reality content may include video, audio, haptic feedback, or some combination thereof, any of which may be presented in a single channel or multiple channels (e.g., stereoscopic video that produces a three-dimensional effect for a viewer). Additionally, in some embodiments, artificial reality may also be associated with an application, product, accessory, service, or some combination thereof that is used, for example, to create content in artificial reality and / or otherwise be used in artificial reality (e.g., perform an activity in artificial reality). An artificial reality system that provides artificial reality content may be implemented on various platforms, including a head-mounted display (HMD) connected to a host computer system, a stand-alone HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers.

[0068] Figure 1A is a schematic diagram of an example of a near-eye display 100. The near-eye display 100 presents media to a user. Examples of media presented by the near-eye display 100 include one or more images, videos, and / or audio. In some embodiments, the audio is presented via an external device (e.g., speakers and / or headphones) that receives audio information from the near-eye display 100, a console, or both, and presents audio data based on the audio information. The near-eye display 100 is generally configured to operate as a virtual reality (VR) display. In some embodiments, the near-eye display 100 is modified to operate as an augmented reality (AR) display and / or a mixed reality (MR) display.

[0069] The near-eye display 100 includes a frame 105 and a display 110. The frame 105 is coupled to one or more optical elements. The display 110 is configured to allow a user to view content presented by the near-eye display 100. In some embodiments, the display 110 includes a waveguide display assembly for directing light from one or more images toward the user's eyes.

[0070] The near-eye display 100 further includes image sensors 120a, 120b, 120c, and 120d. Each of the image sensors 120a, 120b, 120c, and 120d may include a pixel unit array that includes an array of pixel units and is configured to generate image data representing different fields of view along different directions. For example, sensors 120a and 120b may be configured to provide image data representing two fields of view along the Z-axis towards direction A, while sensor 120c may be configured to provide image data representing a field of view along the X-axis towards direction B, and sensor 120d may be configured to provide image data representing a field of view along the X-axis towards direction C.

[0071] In some embodiments, sensors 120a-120d may be configured as input devices to control or affect the display content of the near-eye display 100, thereby providing an interactive VR / AR / MR experience to a user wearing the near-eye display 100. For example, sensors 120a-120d may generate physical image data of the physical environment in which the user is located. The physical image data may be provided to a positioning and tracking system to track the positioning and / or movement path of the user in the physical environment. Then, the system may update the image data provided to the display 110 based on, for example, the positioning and orientation of the user to provide an interactive experience. In some embodiments, when the user moves within the physical environment, the positioning and tracking system may run a SLAM algorithm to track a set of objects in the physical environment and within the user's field of view. The positioning and tracking system may construct and update a map of the physical environment based on the set of objects and track the positioning of the user within the map. By providing image data corresponding to multiple fields of view, sensors 120a-120d may provide a more comprehensive view of the physical environment to the positioning and tracking system, which may result in more objects being included in the construction and update of the map. With this arrangement, the accuracy and robustness of tracking the user's positioning within the physical environment can be improved.

[0072] In some embodiments, the near-eye display 100 may further include one or more active illuminators 130 to project light into the physical environment. The projected light may be associated with different spectra (e.g., visible light, infrared light, ultraviolet light, etc.) and may be used for various purposes. For example, the illuminator 130 may project light and / or light patterns in a dark environment (or in an environment with low-intensity infrared light, ultraviolet light, etc.) to assist the sensors 120a - 120d in capturing 3D images of different objects within the dark environment. The 3D images may include, for example, pixel data representing the distance between the object and the near-eye display 100. The distance information may be used, for example, to construct a 3D model of the scene, track the user's head movement, track the user's location, etc. As discussed in more detail below, the sensors 120a - 120d may operate in a first mode for 2D sensing and a second mode for 3D sensing at different times. The 2D and 3D image data may be combined and provided to the system to provide more robust tracking of, for example, the user's location, the user's head movement, etc.

[0073] Figure 1B is a schematic diagram of another embodiment of the near-eye display 100. Figure 1B shows a side of the near-eye display 100 facing the eyeball 135 of a user wearing the near-eye display 100. As Figure 1B shown, the near-eye display 100 may further include a plurality of illuminators 140a, 140b, 140c, 140d, 140e, and 140f. The near-eye display 100 further includes a plurality of image sensors 150a and 150b. The illuminators 140a, 140b, and 140c may emit light in a specific optical frequency range (e.g., NIR) in the direction D (opposite to the Figure 1A direction A). The emitted light may be associated with a certain pattern and may be reflected by the user's left eyeball. The sensor 150a may include an array of pixel units to receive the reflected light and generate an image of the reflected pattern. Similarly, the illuminators 140d, 140e, and 140f may emit NIR light carrying a pattern. The NIR light may be reflected by the user's right eyeball and received by the sensor 150b. The sensor 150b may also include an array of pixel units to generate an image of the reflected pattern. Based on the images of the reflected patterns from the sensors 150a and 150b, the system may determine the user's gaze point and update the image data provided to the display 100 based on the determined gaze point to provide an interactive experience to the user. In some examples, the image sensors 150a and 150b may include the same pixel units as the sensors 120a - 120d.

[0074] Figure 2 is Figure 1A and Figure 1BAn example of a cross-section 200 of a near-eye display 100 as shown. The display 110 includes at least one waveguide display component 210. The exit pupil 230 is the positioning of a user's single eyeball 220 in the eyebox region when the user wears the near-eye display 100. For illustrative purposes, Figure 2 A cross-section 200 associated with the eyeball 220 and a single waveguide display component 210 is shown, but a second waveguide display is for the user's second eye.

[0075] The waveguide display component 210 is configured to direct image light to the eyebox located at the exit pupil 230 and to the eyeball 220. The waveguide display component 210 may be composed of one or more materials having one or more refractive indices (e.g., plastic, glass, etc.). In some embodiments, the near-eye display 100 includes one or more optical elements between the waveguide display component 210 and the eyeball 220.

[0076] In some embodiments, the waveguide display component 210 includes a stack of one or more waveguide displays, including but not limited to stacked waveguide displays, zoom waveguide displays, etc. A stacked waveguide display is a multi-color display created by stacking waveguide displays (e.g., a red-green-blue (RGB) display), and the corresponding monochromatic sources of the waveguide displays have different colors. A stacked waveguide display is also a multi-color display that can be projected on multiple planes (e.g., a multi-plane color display). In some configurations, a stacked waveguide display is a monochromatic display that can be projected on multiple planes (e.g., a multi-plane monochromatic display). A zoom waveguide display is a display that can adjust the focal position of the image light emitted from the waveguide display. In alternative embodiments, the waveguide display component 210 may include a stacked waveguide display and a zoom waveguide display.

[0077] Figure 3 An isometric view of an example of a waveguide display 300 is shown. In some embodiments, the waveguide display 300 is a component of the near-eye display 100 (e.g., the waveguide display component 210). In some embodiments, the waveguide display 300 is part of some other near-eye display or other system that directs image light to a specific location.

[0078] The waveguide display 300 includes a source component 310, an output waveguide 320, an illuminator 325, and a controller 330. The illuminator 325 may include Figure 1A the illuminator 130. For illustrative purposes, Figure 3 A waveguide display 300 associated with a single eyeball 220 is shown, but in some embodiments, another waveguide display separated or partially separated from the waveguide display 300 provides image light to the user's other eye.

[0079] The source component 310 generates image light 355. The source component 310 generates the image light 355 and outputs it to the coupling element 350 located on the first side 370-1 of the output waveguide 320. The output waveguide 320 is an optical waveguide that outputs the expanded image light 340 to the user's eyeball 220. The output waveguide 320 receives the image light 355 at one or more coupling elements 350 located on the first side 370-1, and guides the received input image light 355 to the guiding element 360. In some embodiments, the coupling element 350 couples the image light 355 from the source component 310 into the output waveguide 320. The coupling element 350 can be, for example, a diffraction grating, a holographic grating, one or more cascaded reflectors, one or more prismatic surface elements, and / or a holographic reflector array.

[0080] The guiding element 360 redirects the received input image light 355 to the decoupling element 365, such that the received input image light 355 is decoupled from the output waveguide 320 via the decoupling element 365. The guiding element 360 is part of the first side 370-1 of the output waveguide 320, or is fixed to the first side 370-1 of the output waveguide 320. The decoupling element 365 is part of the second side 370-2 of the output waveguide 320, or is fixed to the second side 370-2 of the output waveguide 320, such that the guiding element 360 is opposite to the decoupling element 365. The guiding element 360 and / or the decoupling element 365 can be, for example, a diffraction grating, a holographic grating, one or more cascaded reflectors, one or more prismatic surface elements, and / or a holographic reflector array.

[0081] The second side 370-2 represents a plane along the x dimension and the y dimension. The output waveguide 320 can be composed of one or more materials that facilitate total internal reflection of the image light 355. The output waveguide 320 can be composed of, for example, silicon, plastic, glass, and / or polymer. The output waveguide 320 has a relatively small form factor. For example, the output waveguide 320 can be about 50 mm wide along the x dimension, about 30 mm long along the y dimension, and about 0.5 mm - 1 mm thick along the z dimension.

[0082] The controller 330 controls the scanning operation of the source component 310. The controller 330 determines the scanning instruction of the source component 310. In some embodiments, the output waveguide 320 outputs the expanded image light 340 to the user's eyeball 220 with a large field of view (FOV). For example, the expanded image light 340 is provided to the user's eyeball 220 with a diagonal FOV of 60 degrees and / or greater and / or 150 degrees and / or less in (x and y). The output waveguide 320 is configured to provide a window having a length of 20 mm or greater and / or equal to or less than 50 mm; and / or a width of 10 mm or greater and / or equal to or less than 50 mm.

[0083] In addition, the controller 330 also controls the image light 355 generated by the source component 310 based on the image data provided by the image sensor 370. The image sensor 370 may be located on the first side 370-1 and may include, for example Figure 1A image sensors 120a-120d. The image sensors 120a-120d may be operated to perform 2D sensing and 3D sensing of an object 372 in front of the user (e.g., facing the first side 370-1). For 2D sensing, each pixel unit of the image sensors 120a-120d may be operated to generate pixel data representing the intensity of the light 374 generated by the light source 376 and reflected from the object 372. For 3D sensing, each pixel unit of the image sensors 120a-120d may be operated to generate pixel data representing the time-of-flight measurement of the light 378 generated by the illuminator 325. For example, each pixel unit of the image sensors 120a-120d may determine a first time when the illuminator 325 is enabled to project the light 378 and a second time when the pixel unit detects the light 378 reflected from the object 372. The difference between the first time and the second time may indicate the time of flight of the light 378 between the image sensors 120a-120d and the object 372, and the time-of-flight information may be used to determine the distance between the image sensors 120a-120d and the object 372. The image sensors 120a-120d may be operated to perform 2D and 3D sensing at different times and provide the 2D and 3D image data to the remote console 390, which may (or may not) be located within the waveguide display 300. The remote console may combine the 2D and 3D images to, for example, generate a 3D model of the user's environment to track the user's positioning and / or orientation, etc. The remote console may determine the content of the image to be displayed to the user based on the information derived from the 2D and 3D images. The remote console may transmit an instruction related to the determined content to the controller 330. Based on the instruction, the controller 330 may control the source component 310 to generate and output the image light 355 to provide an interactive experience to the user.

[0084] Figure 4An embodiment of a cross-section 400 of a waveguide display 300 is shown. The cross-section 400 includes a source assembly 310, an output waveguide 320, and an image sensor 370. In Figure 4 the example of, the image sensor 370 may include a set of pixel units 402 located on a first side 370-1 to generate an image of the physical environment in front of the user. In some embodiments, a mechanical shutter 404 and a filter array 406 may be inserted between the set of pixel units 402 and the physical environment. The mechanical shutter 404 may control the exposure of the set of pixel units 402. In some embodiments, as will be discussed below, the mechanical shutter 404 may be replaced by an electronic shutter gate. As will be discussed below, the filter array 406 may control the optical wavelength range of the light to which the set of pixel units 402 is exposed. Each pixel unit 402 may correspond to a pixel of the image. Although Figure 4 not shown in, it should be understood that each pixel unit 402 may also be covered with a filter to control the optical wavelength range of the light to be sensed by the pixel unit.

[0085] After receiving an instruction from a remote console, the mechanical shutter 404 may open and expose the set of pixel units 402 during an exposure period. During the exposure period, the image sensor 370 may obtain a light sample incident on the set of pixel units 402 and generate image data based on the intensity distribution of the incident light sample detected by the set of pixel units 402. The image sensor 370 may then provide the image data to the remote console, which determines the display content and provides display content information to the controller 330. The controller 330 may then determine the image light 355 based on the display content information.

[0086] The source assembly 310 generates the image light 355 according to an instruction from the controller 330. The source assembly 310 includes a source 410 and an optical system 415. The source 410 is a light source that generates coherent light or partially coherent light. The source 410 may be, for example, a laser diode, a vertical cavity surface emitting laser, and / or a light emitting diode.

[0087] The optical system 415 includes one or more optical components that condition the light from the source 410. Conditioning the light from the source 410 may include, for example, expanding, collimating, and / or adjusting the orientation according to an instruction from the controller 330. The one or more optical components may include one or more lenses, liquid lenses, mirrors, apertures, and / or gratings. In some embodiments, the optical system 415 includes a liquid lens having a plurality of electrodes that allows the beam to be scanned with a threshold scan angle to move the beam to an area outside the liquid lens. The light emitted from the optical system 415 (and also the source assembly 310) is referred to as the image light 355.

[0088] The output waveguide 320 receives the image light 355. The coupling element 350 couples the image light 355 from the source assembly 310 into the output waveguide 320. In an embodiment where the coupling element 350 is a diffraction grating, the grating pitch of the diffraction grating is selected such that total internal reflection occurs in the output waveguide 320, and the image light 355 propagates internally in the output waveguide 320 (e.g., by total internal reflection) towards the decoupling element 365.

[0089] The guiding element 360 redirects the image light 355 to the decoupling element 365 for decoupling from the output waveguide 320. In an embodiment where the guiding element 360 is a diffraction grating, the grating pitch of the diffraction grating is selected such that the incident image light 355 exits the output waveguide 320 at an angle inclined with respect to the surface of the decoupling element 365.

[0090] In some embodiments, the guiding element 360 and / or the decoupling element 365 are structurally similar. The expanded image light 340 exiting the output waveguide 320 is expanded along one or more dimensions (e.g., can be elongated along the x dimension). In some embodiments, the waveguide display 300 includes a plurality of source assemblies 310 and a plurality of output waveguides 320. Each source assembly 310 emits monochromatic image light corresponding to a specific wavelength band of a primary color (e.g., red, green, or blue). Each output waveguide 320 can be stacked at a certain interval distance to output multi-color expanded image light 340.

[0091] Figure 5 Is a block diagram of an embodiment of a system 500 including a near-eye display 100. The system 500 includes a near-eye display 100, an imaging device 535, an input / output interface 540, and image sensors 120a - 120d and 150a - 150b, each coupled to a control circuit 510. The system 500 can be configured as a head-mounted device, a wearable device, etc.

[0092] The near-eye display 100 is a display that presents media to a user. Examples of media presented by the near-eye display 100 include one or more images, videos, and / or audio. In some embodiments, the audio is presented via an external device (e.g., speakers and / or headphones), which receives audio information from the near-eye display 100 and / or the control circuit 510 and presents audio data to the user based on the audio information. In some embodiments, the near-eye display 100 can also act as AR glasses. In some embodiments, the near-eye display 100 uses computer-generated elements (e.g., images, videos, sounds, etc.) to enhance the view of the physical, real-world environment.

[0093] The near-eye display 100 includes a waveguide display assembly 210, one or more position sensors 525, and / or an inertial measurement unit (IMU) 530. The waveguide display assembly 210 includes a source assembly 310, an output waveguide 320, and a controller 330.

[0094] The IMU 530 is an electronic device that generates fast calibration data based on measurement signals received from one or more position sensors 525, the fast calibration data indicating an estimated position of the near-eye display 100 relative to an initial position of the near-eye display 100.

[0095] The imaging device 535 can generate image data for various applications. For example, the imaging device 535 can generate image data to provide slow calibration data according to calibration parameters received from the control circuit 510. The imaging device 535 can include, for example Figure 1A image sensors 120a - 120d for generating 2D image data and 3D image data of the physical environment in which the user is located to track the user's positioning and head movement. The imaging device 535 can further include, for example Figure 1B image sensors 150a - 150b for generating image data (e.g., 2D image data) to determine the user's gaze point, thereby identifying an object of interest to the user.

[0096] The input / output interface 540 is a device that allows a user to send action requests to the control circuit 510. An action request is a request to perform a specific action. For example, an action request can be to start or end an application, or to perform a specific action within an application.

[0097] The control circuit 510 provides media to the near-eye display 100 for presentation to the user based on information received from one or more of the imaging device 535, the near-eye display 100, and the input / output interface 540. In some examples, the control circuit 510 can be housed within a system 500 configured as a head-mounted device. In some examples, the control circuit 510 can be an independent console device communicatively coupled to other components of the system 500. In Figure 5 the example shown, the control circuit 510 includes an application storage 545, a tracking module 550, and an engine 555.

[0098] The application storage 545 stores one or more applications for execution by the control circuit 510. An application is a set of instructions that, when executed by a processor, generates content for presentation to the user. Examples of applications include: game applications, conference applications, video playback applications, or other suitable applications.

[0099] The tracking module 550 calibrates the system 500 using one or more calibration parameters and may adjust one or more calibration parameters to reduce errors in the position determination of the near-eye display 100.

[0100] The tracking module 550 uses slow calibration information from the imaging device 535 to track the movement of the near-eye display 100. The tracking module 550 also uses position information from the fast calibration information to determine the position of the reference point of the near-eye display 100.

[0101] The engine 555 executes applications within the system 500 and receives position information, acceleration information, velocity information, and / or predicted future positions of the near-eye display 100 from the tracking module 550. In some embodiments, the information received by the engine 555 can be used to generate a signal (e.g., a display instruction) to the waveguide display assembly 210 that determines the type of content presented to the user. For example, to provide an interactive experience, the engine 555 can determine the content to be presented to the user based on the user's location (e.g., provided by the tracking module 550), the user's gaze point (e.g., based on image data provided by the imaging device 535), and the distance between the object and the user (e.g., based on image data provided by the imaging device 535).

[0102] Figure 6 An example of an image sensor 600 is shown. The image sensor 600 can use the same pixel units for 2D sensing and 3D sensing. For example, the same pixel units can be configured to detect color components of visible light (e.g., red, green, or blue) for 2D sensing and detect infrared light for 3D sensing. The image sensor 600 can be a part of the near-eye display 100 and can provide 2D and 3D image data to Figure 5 the control circuit 510 to control the display content of the near-eye display 100. In Figure 6 the example, the image sensor 600 can include an illuminator 602, a filter array 604, a pixel unit array 606 including pixel units 606a, and a digitization module 608.

[0103] The illuminator 602 can be an infrared illuminator capable of projecting infrared light for 3D sensing, such as a laser, a light-emitting diode, etc. The projected light can include, for example, structured light, light pulses, etc. The filter array 604 can include an array of filter elements, where each filter element corresponds to a pixel unit of the pixel unit array 606 (e.g., pixel unit 606a). Each filter element can be configured to absorb incident light in a specific wavelength range and transmit the remaining light to the corresponding pixel unit. The incident light can include ambient visible light as well as infrared light projected by the illuminator 602 and reflected by an object. For example, one filter element can transmit the green component of visible light as well as infrared light to the pixel unit, while another filter element can transmit the blue component of visible light as well as infrared light to another pixel unit. In some examples, the filter array 604 can be configurable to select the color components of visible light to be transmitted together with the infrared light, such that the pixel unit 606a can be used to detect different color components of visible light as well as infrared light.

[0104] In addition, the pixel unit 606a can include a plurality of photodiodes to detect different color components of visible light and infrared light in the incident light. For example, as Figure 6 shown, the pixel unit 606a can include a photodiode 612 and a photodiode 614. The photodiode 612 and the photodiode 614 can be pinned photodiodes. The photodiode 612 can detect a first component of incident light in a first wavelength range (e.g., one of red, blue, or green of visible light) during an exposure period, convert the detected photons into charges, and store the charges. In addition, the photodiode 614 can detect a second component of incident light in a second wavelength range (e.g., infrared light) during the same or a different exposure period, convert the detected photons into charges, and store the charges. The pixel unit 606a can also include a charge storage device 616, and the charge storage device 616 can include a floating drain node, a metal capacitor, or a combination of both. At the end of the exposure period, the charges stored at the photodiodes 612 and 614 can be transferred to the charge storage device 616 to generate voltages for 2D and 3D sensing.

[0105] The image sensor 600 further includes a measurement module 608. The measurement module 608 may further include a 2D measurement module 622 for performing 2D imaging operations based on the charges generated by the photodiodes 612. The 2D imaging operations may include, for example, generating pixel values based on the magnitude of the voltage generated at the charge storage device 616, where the pixel values reflect the total amount of charge stored at the photodiodes 612 during the exposure period. The measurement module 608 may include a 3D measurement module 624 to perform 3D imaging operations based on the charges generated by the photodiodes 614. The 3D imaging operations may include, for example, detecting the pattern of structured light reflected by the surface of an object and comparing the detected pattern with the pattern of structured light projected by the illuminator 602 to determine the depth of different points on the surface relative to the pixel unit array. To detect the pattern of the reflected light, the 3D measurement module 624 may generate pixel values based on the magnitude of the voltage generated at the charge storage device 616, where the pixel values reflect the total amount of charge stored at the photodiodes 614 during the exposure. As another example, the 3D measurement module 624 may generate pixel values representing the time-of-flight measurements of light pulses emitted by the illuminator 602 and reflected by the object.

[0106] The image sensor 600 further includes a sensing controller 610 to control different components of the image sensor 600 to perform 2D and 3D imaging of an object. Now refer to Figure 7A and Figure 7B , which illustrate operation examples of the image sensor 600 for 2D and 3D imaging. Figure 7A An operation example of 2D imaging is illustrated. For 2D imaging, the pixel unit array 606 may detect visible light in the environment (including visible light reflected from an object). For example, refer to Figure 7A, a visible light source 700 (e.g., a light bulb, the sun, or other ambient visible light source) can project visible light 702 onto an object 704. Visible light 706 can be reflected by a point 708 of the object 704. The visible light 706 can be filtered by the filter array 604 to pass a predetermined wavelength range w0 of the reflected visible light 706, thereby generating filtered light 710a. The wavelength range w0 can correspond to a first color component of the visible light 706 reflected from the point 708 (e.g., a red component with a wavelength range of 620 - 750 nanometers (nm)). The filtered light 710a can be captured by the first photodiode 612 of the pixel unit 606a during an exposure period to generate and accumulate a first charge. At the end of the exposure period, the sensing controller 610 can direct the first charge to the charge storage device 616 to generate a voltage representing the intensity of the first color component and provide the first voltage to the 2D measurement module 622. The 2D measurement module 622 can include an analog-to-digital converter (ADC) and can be controlled by the sensing controller 610 to sample and quantify the first voltage to generate a digital value representing the intensity of the first color component of the visible light 706.

[0107] In addition, the image sensor 600 can also perform 3D imaging of the object 704. Referring to Figure 7B , the sensing controller 610 can control the illuminator 602 to project infrared light 728 onto the object 704, and the infrared light 728 can include light pulses, structured light, etc. The infrared light 728 can have a wavelength range of 700 nanometers (nm) to 1 millimeter (mm). Infrared photons 730 can be reflected from the object 704, propagate toward the pixel unit array 606, and pass through the filter 604. In some examples, the second photodiode 614 of the pixel unit 606a can convert the infrared photons 730 into a second charge. The detection and conversion of the infrared photons 730 by the second photodiode 614 can occur during the same exposure period as the detection and conversion of the visible light 706 by the first photodiode 612. This arrangement allows each pixel unit to perform 2D and 3D imaging of the same point of the object, which can improve the correspondence between the 2D and 3D images. The sensing controller 610 can direct the second charge to the charge storage device 616 to generate a voltage representing the intensity of the infrared light received at the pixel unit.

[0108] The 3D measurement module 624 can perform different types of depth sensing operations based on the type of light 728 projected onto the object 704. In the case where structured light 728 is projected onto the object 704, the 3D measurement module 624 can include an ADC and can be controlled by the sensing controller 610 to sample and quantify a second voltage to generate a digital value representing the intensity of the infrared light reflected by the point 708. A pattern of the intensity of the infrared light reflected by the object 704 can be obtained from the digital value. This pattern can be compared with the structured light pattern projected by the illuminator 602 to determine the depth of different points (including the point 708) on the surface of the object 704 relative to the pixel unit array 606. In the case where the infrared light 728 includes light pulses, the 3D measurement module 624 can detect a change in the charge stored at the second photodiode 614. The time-of-flight of the infrared light pulse can be determined based on the time difference between when the light pulse leaves the illuminator 602 and when the change in the charge stored at the second photodiode 614 is detected. Based on the information provided by each pixel unit, a 3D image of the object 704 can be generated.

[0109] Figure 8 An example of an array of pixel units 800 (e.g., pixel units 800a, 800b, 800c, and 800d) is shown, which can perform juxtaposed 2D and 3D image sensing and can be part of the image sensor 600. Figure 8 A cross-sectional view of the array of pixel units 800 (e.g., viewed from the x / y axis) is shown. As Figure 8 shown, each pixel unit in the pixel unit 800 can include a first semiconductor substrate 802, a second semiconductor substrate 804, and a metal layer 805 sandwiched between these substrates. The first semiconductor substrate 802 can include a light receiving surface 806, a first photodiode 808, a second photodiode 810, and a charge storage device 616, while the second semiconductor substrate 804 can include an interface circuit 850. In Figure 8 this case, the first semiconductor substrate 802, the metal layer 805, and the second semiconductor substrate 804 can form a stack along the z-axis. In some examples, the first semiconductor substrate 802 and the second semiconductor substrate 804 can be the same substrate, or the two substrates can be arranged laterally along the x / y axis.

[0110] Within the first semiconductor substrate 802, the first photodiode 808 and the second photodiode 810 may be formed in a stack along the propagation path of the light 820 perpendicular to the light receiving surface 806 (e.g., along the z-axis). The second photodiode 810 may be configured as a visible light sensing photodiode ("VIS PD"), while the first photodiode 808 may be configured as an infrared light sensing photodiode ("IR PD"). Specifically, the second photodiode 810 may be closer to the light receiving surface 806 than the first photodiode 808. When the light 820 enters the first semiconductor substrate 802 via the light receiving surface 806 and propagates, a first light component 822 of the light 820 having a relatively long infrared light wavelength range may propagate through the second photodiode 810, reach the first photodiode 808, and may be absorbed by the first photodiode 808. In addition, a second light component 824 of the light 820 having a relatively short visible light wavelength range stops at the second photodiode 810 and may be absorbed by the second photodiode 810.

[0111] Each pixel unit 800 further includes optical components to control the properties of the first light component 822 and the second light component 824 of the light 820. For example, each pixel unit 800 includes a microlens 832 for focusing the light 820 and a filter 834 for selecting the wavelength range of the second light component 824 (e.g., one of red, green, or blue) that will be absorbed / measured by the second photodiode 810. As Figure 8 shown, based on the configuration of the color filter 834, each of the pixel units 800a, 800b, 800c, and 800d may receive infrared light as the first light component 822, but receive visible light in different wavelength ranges as the second light component 824. In Figure 8 the example, the pixel unit 800a may receive red light as the second light component 824, the pixel units 800b and 800d may receive green light as the second light component 824, and the pixel unit 800c may receive blue light as the second light component 824.

[0112] Each of the first photodiode 808 and the second photodiode 810 may generate charges in response to the first light component 822 and the second light component 824, respectively. The charge generation rate of each photodiode may represent the intensities of the first light component 822 and the second light component 824. The charges generated by the first photodiode 808 and the second photodiode 810 may be stored in the charge storage device 616, in Figure 8In the example, the charge storage device 616 may include a floating drain 818 in the first semiconductor substrate 802. The amount of charge accumulated in the charge storage device 616 and the charge accumulation rate in the charge storage device 616 may be measured by the interface circuit 850. The interface circuit 850 may include a controller for controlling the flow of charge from the first photodiode 808 and the second photodiode 810 to the floating drain 818 for reading out. The interface circuit 850 further includes Figure 6 a measurement module 608 for reading out and quantifying the charge from the first photodiode 808 and the second photodiode 810 to determine the intensities of, for example, the first light component 822 and the second light component 824. The metal layer 805 further includes metal interconnects 830, which may couple the floating drain node 818 to the measurement module 608 of the second semiconductor substrate 804. The metal interconnects 830 may also couple the controller to the circuit in the first semiconductor substrate 802 that regulates the flow of charge. The metal interconnects 830 may transfer the voltage generated at the charge storage device 616, corresponding to the charge generated by the first photodiode 808 and the second photodiode 810, to the measurement module 608 to perform the measurements for the 2D and 3D image sensing operations as described above.

[0113] Now refer to Figure 9A and Figure 9B , which provide examples of additional components of the pixel unit 800. Figure 9A and Figure 9B show a cross-sectional view of an array of pixel units 800 (e.g., viewed from the x / y axes). In Figure 9A and Figure 9B , the semiconductor substrate 802 may be a P-type substrate and have a front surface 902 and a back surface 904. The front surface 902 is where additional semiconductor processes are performed, such as forming a polysilicon gate 918, doping and / or ion implanting to form the first photodiode 808, the second photodiode 810, the floating drain node 818, the pinning layers 905 and 915, etc. In Figure 9A , the pixel unit 800 may be configured as a backside-illuminated device, where the back surface 904 is configured as the light receiving surface 806, and the microlens 832 and the filter 834 may be placed on the back surface 904 to control the properties of the first light component 822 and the second light component 824 of the light 820. In Figure 9BIn [description], the pixel unit 800 can be configured as a front-side illumination device, where the front-side surface 902 is configured as the light-receiving surface 806. The insulating layer 952 can be placed above the polysilicon gate 918 and the oxide layer 916 on the front-side surface 902, and the microlens 832 and the filter 834 can be placed on the insulating layer 952 to control the properties of the first light component 822 and the second light component 824 of the light 820.

[0114] In Figure 9A and Figure 9B example, the first photodiode 808 and the second photodiode 810 can be configured as pinned photodiodes. In Figure 9A [description], the second pinned photodiode 810 can be formed by including an N-type region 906 and a P-type pinning layer 915 embedded in the P-type semiconductor substrate 802. The pixel unit 800 also includes a P-well 908 and an N-type region 912 and a P-type pinning layer 905 embedded in the P-well 908 for forming the first pinned photodiode 808. In Figure 9A [description], the N-type region 912 is farther from the back-side surface 904 (configured as the light-receiving surface 806) than the N-type region 906, which allows the first pinned photodiode 808 to mainly detect the infrared component (e.g., the first light component 822) of the light 820, and the second pinned photodiode 810 to mainly detect the visible light component (e.g., the second light component 824) of the light 824. In Figure 9B [description], the positions of the first pinned photodiode 808 and the second pinned photodiode 810 can be reversed, where the first pinned photodiode 808 is formed by the N-type region 906 and the second pinned photodiode 810 is formed by the N-type region 912. In Figure 9B [description], the N-type region 912 is closer to the front-side surface 902 (configured as the light-receiving surface 806) than the N-type region 906, which allows the first pinned photodiode 808 and the second pinned photodiode 810 to detect components of different wavelengths as in Figure 9A [description]. The first pinned photodiode 808 and the second pinned photodiode 810 can have the same or different pinning voltages (e.g., the maximum voltage difference across the photodiode). In the first pinned photodiode 808 and the second pinned photodiode 810, the complete isolation of the N-type regions 906 and 912 in the P-type substrate 901 and the P-well 908 can provide better dark current and noise performance.

[0115] In Figure 9A and Figure 9BIn [the figure], a blocking layer 914 is also formed between the first pinned photodiode 808 and the second pinned photodiode 810, and the first pinned photodiode 808, the blocking layer 914, and the second pinned photodiode 810 can be formed in a stack along the propagation direction of light within the P-type semiconductor substrate 802 (e.g., along the z-axis). The photodiode 808, the photodiode 810, and the blocking layer 914 can be formed by, for example, ion implantation from the front surface 902. As described in more detail below, the blocking layer 914 can prevent the charge stored in the first pinned photodiode 808 from entering the second pinned photodiode 810. The blocking layer 914 can also regulate the flow of charge from the second pinned photodiode 810 to the first pinned photodiode 808 for readout and quantization. In some examples, the blocking layer 914 can be a P-type layer and be part of the P-well 908 (or the P-type semiconductor substrate 802), or can be part of a P+ region with a higher P-type doping concentration. In some examples, the blocking layer 914 can also be an N-type layer (e.g., having an N-type doping concentration lower than both the N-type region 906 and the N-type region 912).

[0116] As described above, the pixel unit 800 further includes pinned layers 905 and 915, an oxide layer 916, a polysilicon gate 918, and a floating drain 818. The pinned layer 915 can be configured to separate the N-type region 912 so that it does not directly interface with the oxide layer 916, to reduce the dark current caused by surface-hole combination at the interface between the oxide layer 916 and the substrate, which can reduce the generation of dark signal at the first photodiode 808. In addition, the pinned layer 905 can separate the N-type region 906 so that it does not directly interface with the back surface 904 (the back surface 904 can interface with another oxide layer, a filter 834, etc.), to reduce the generation of dark signal at the second photodiode 810. The pinned layer 915 and the pinned layer 905 can also form the P-type regions of the first photodiode 808 and the second photodiode 810, respectively. The polysilicon gate 918 can receive a voltage via the oxide layer 916 and apply an electric field to create a channel at the channel region 922 between the N-type region 912 and the floating drain 818. The channel can be created to read out the charge generated by one of the first photodiode 808 or the second photodiode 810.

[0117] Figure 10 An example of the potential distribution within the first semiconductor substrate 802 for reading out charge from the first photodiode 808 or the second photodiode 810 is shown. Refer to Figure 10 , the potential of the blocking layer 914 can be modulated with respect to time to perform readout. As Figure 10As shown, at time 1000, the N-type regions 912 and 906 store negative charges generated in response to the first light component 822 and the second light component 824, and each can have a potential P 电荷 . The potential P 电荷 can be defined based on the amount of charge, the capacity of the quantum wells in the N-type regions 912 and 906, and the potential P 空 when the quantum wells are empty. At the same time, the channel region 922 can be in an off state, and no channel has been created at the channel region 922. The potential at the channel region 922 can be a potential lower than P 电荷 . In addition, the blocking layer 914 can be in an off state and can be set to a potential that prevents charge from flowing between the N-type regions 912 and 906, and the potential at the N-type region 912 can also be at a potential lower than P 电荷 . In Figure 10 , the potentials at the channel region 922 and the blocking layer 914 can be similar to P sub .

[0118] At time 1000, the storage capacities of the N-type regions 912 and 906 can be maximum. The maximum amount of charge that can be stored in the N-type region 912 can be defined based on the quantum well capacity of the N-type region 912 and the potential when both the channel region 912 and the blocking substrate 914 are in an off state. With this arrangement, when the maximum amount of charge is stored in the N-type region 912, P 电荷 can be maintained higher than the potentials of the blocking substrate 914 and the channel region 912 to trap the charge in the N-type region 912. As will be described in detail below, the potential at the channel region 922 can be configured to set the storage capacity of the N-type region 912. In addition, the maximum amount of charge that can be stored in the N-type region 906 can be defined based on the quantum well capacity of the N-type region 906, the potential P sub of the first semiconductor substrate 802, the potential of the blocking substrate 914 in an off state, and P 空 such that when the maximum amount of charge is stored in the N-type region 906, P 电荷 is maintained higher than the potentials of the first semiconductor substrate 802 and the blocking layer 914 to trap the charge in the N-type region 906.

[0119] At time 1002, the charge stored in the N-type region 912 can be read out. To read out the charge, by applying a voltage at the polysilicon gate 918 to form a channel in the channel region 922, the potential in the channel region 922 can be increased to P 沟道-导通 . The negative charge stored in the N-type region 912 can flow to the channel region 922 and then to the floating drain 818. At the same time, the potential of the blocking portion 914 is maintained at P sub, a potential P lower than the charge stored in the N-type region 906 电荷 . Therefore, the charge stored in the N-type region 906 remains trapped in that region.

[0120] At time 1004, the potential of the blocking layer 914 can be increased to be equal to or higher than P 电荷 . The charge stored in the N-type region 906 can flow to the N-type region 912. In Figure 10 the example of, the potential in the channel region 922 can be maintained at P 沟道-导通 , and all the charge from the N-type region 906 can be transferred to the floating drain 818. In some examples, as described below, the charge stored at the N-type region 906 can be transferred to the floating drain 818 in multiple steps for measurement operations of different light intensities.

[0121] Figure 11A and Figure 11B show a cross-sectional view of the pixel unit 800, which includes additional components for adjusting the potential of the blocking layer 914. Figure 11A shows the pixel unit 800 configured as a backside illumination device, while Figure 11B shows the pixel unit 800 configured as a frontside illumination device. As Figure 11A and Figure 11B shown, in addition to the polysilicon gate 918 (hereinafter referred to as the "first gate"), the pixel unit 800 may further include a polysilicon gate 1102 (hereinafter referred to as the "second gate") extending from the front surface 902 into the first semiconductor substrate 802. The second gate 1102 can be used to adjust the potential of the blocking layer 914. Specifically, the second gate 1102 can extend along an axis parallel to the propagation of light within the stack of the first photodiode 808, the blocking layer 914, and the second photodiode 810 (e.g., along the z-axis), and can penetrate the first photodiode 808 to reach the blocking layer 914. The pixel unit 800 may include an oxide layer 1106 for insulating the second gate 1102 from the first photodiode 808 and the blocking layer 914. The N-type regions 906 and 912, the P-well 908, and the blocking layer 914 are all connected to the first semiconductor substrate 802 and can be biased at a bias voltage (e.g., 0v). The second gate 1102 can receive a signal 1104, and a potential P1 can be generated at one end of the portion 1108 of the second gate 1102 closest to the blocking layer 914 from the signal 1104. According to the relationship between the potential P1 and the bias voltage of the blocking layer 914, positive or negative charges can accumulate at the portion 1108, and a potential P2 can be generated at the portion 1108. Refer to Figure 10In an example, the signal 1104 may include a negative voltage to generate a negative electric potential P1, which may attract positive charges and increase the electric potential P2 at the portion 1108 of the blocking layer 914. As the electric potential P2 increases, charges may flow from the N region 906 ( Figure 11A the N region 906 of the second photodiode 810 in Figure 11B the N region 906 of the first photodiode 808 in Figure 11A the N region 912 of the first photodiode 808 in Figure 11B the N region 912 of the second photodiode 810 in

[0122] Figure 12A - Figure 12F to the N region 912 ( Figure 12A for readout. FIG. Figure 12B shows a top view (e.g., viewed from the z-axis) of the pixel unit 800 having a backside illumination configuration, while Figure 12C and Figure 12D each show a cross-sectional view of the pixel unit 800. Figure 12B and Figure 12C show a cross-sectional view along an imaginary cut line A-A' that intersects the second gate 1102, while Figure 12C shows a cross-sectional view along an imaginary cut line B-B' that intersects the second gate 1102, the first gate 918, and the floating drain 818.

[0123] Referring to Figure 12A and Figure 12B , the second gate 1102 may be positioned on or near the centerline 1202 of the stack of the first photodiode 808, the blocking layer 914, and the second photodiode 810. In the case where the P-well 908 surrounds the stack and forms sidewalls on each of the four sides of the pixel unit 800, the centerline 1202 may be equidistant from two or more sidewalls. Such an arrangement may facilitate the flow of charges from the second photodiode 810 through the blocking layer 914 to the first photodiode 808 (or in a frontside illumination configuration, charges from the first photodiode 808 through the blocking layer 914 to the second photodiode 810). Specifically, due to the focusing effect of the microlens 832, when the first light component 822 and the second light component 824 propagate within the stack, the intensities of these two light components are generally highest at the centerline 1202. The concentration of charges generated by the photon conversion of the first light component 822 and the second light component 824 is also generally highest at the centerline 1202. Therefore, positioning the second gate 1102 on the centerline 1202 of the stack allows the electric potential of the blocking layer 914 to be adjusted also at the centerline, where most of the charges in each of the first photodiode 808 and the second photodiode 810 are closest. AsFigure 12C As shown, with this arrangement, a short propagation path (represented by the dashed line labeled C-C') across the blocking layer 914 can be provided for most of the charge in the second photodiode 810, which can facilitate the flow of charge from the second photodiode 810 to the first photodiode 808 via the blocking layer 914.

[0124] Reference Figure 12B and Figure 12C , the pixel unit 800 may include an interface passivation region (IPR) 1204 that surrounds the interface between the oxide layer 1106 and the first photodiode 808. The IPR 1204 can accumulate charge to reduce dark current. Specifically, crystal defects may exist at the interface between the oxide layer 1106 and the N-type region 912 of the first photodiode 808, and these crystal defects can generate dark current. The IPR 1204 can be created by accumulating charge to fill the crystal defects, thereby reducing dark current. The polarity of the charge accumulated at the IPR 1204 is opposite to the polarity of the charge converted from photons by the photodiode. For example, in the case where the first light component 822 and the second light component 824 generate negative charge by the photodiode, and this negative charge is transferred to the floating drain 818 for readout, positive charge can be accumulated at the interface to form a P-type IPR 1204. As Figure 12C shown, the IPR 1204 and the blocking layer 914 can form a P-type conduction path (represented by the dashed line labeled C'-D), which is part of the path (represented by the dashed line labeled E-E') of the charge from the second photodiode 810 to the first photodiode 808. Since the dark signal can be generated by the dark current and can be read out as a noise component at the floating drain 818, the formation of the IPR 1204 can reduce the noise component and improve the accuracy of the light intensity measurement.

[0125] There are various ways to form the IPR 1204. In one example, the IPR 1204 can be manifested as part of the manufacturing process of the second gate 1102. Specifically, the second gate 1102 can be formed by etching a hole in the first semiconductor substrate 802 along the center line 1202 from the front surface 902. The etching time can be determined based on the depth of the second gate 1102 into the first semiconductor substrate 802, which in turn can be determined based on the depth of the blocking layer 914 relative to the front surface 902. After the etching of the hole is completed (e.g., when the hole reaches the target depth), a P-type dopant can be introduced through the hole into the region of the first semiconductor substrate 802 surrounding the hole to form the P-type IPR 1204. The dopant can be introduced by, for example, diffusion, ion implantation, etc. After the IPR 1204 is formed, an oxide layer 1106 can be formed as a lining to cover the sidewalls of the hole. The oxide layer 1106 can be formed by, for example, thermal oxidation. Then the hole lined with the oxide layer 1106 can be filled with polysilicon to form the second gate 1102. In another example, the IPR 1204 can be formed based on applying a bias voltage at the second gate 1102. For example, in order to accumulate positive charges at the IPR 1204, a negative bias voltage can be applied at the second gate 1102.

[0126] As described above, the IPR 1204 and the blocking layer 914 can form a P-type conduction path. When a signal 1104 including a positive voltage is applied to the second gate 1102, charges can flow through the IPR 1204 and the blocking layer 914. The positive voltage can push the positive charge carriers away from the IPR 1204 and the blocking layer 914, thereby forming a channel of negative charges between the N region of the second photodiode 810 and the N region of the first photodiode 808. To ensure that negative charges flow through this channel, the IPR 1204 and the blocking layer 914 can be configured to maintain an electric potential gradient along the flow direction of the negative charges. For example, referring to Figure 12E , the IPR 1204 can be configured to maintain an electric potential P BA higher than that of the blocking layer 914 IPR , such that the negative charges from the second photodiode 810 can flow from a relatively lower electric potential (at the blocking layer 914) to a relatively higher electric potential (at the IPR 1204).

[0127] Various techniques can be employed to set the relative electric potential between the IPR 1204 and the blocking layer 914. In some examples, the IPR 1204 and the blocking layer 914 can have different doping profiles. For example, the IPR 1204 can have a higher P-type dopant concentration than the blocking layer 914. As another example, the IPR 1204 can be doped with P-type dopants while the blocking layer 914 can be doped with N-type dopants. In these examples, due to the different dopant concentrations, opposite charges can diffuse between the IPR 1204 and the blocking layer 914. The displacement of the charges creates a built-in electric field to pull back the charges. When an equilibrium is reached between the diffusion of the charges and the pulling back of the charges by the electric field, a built-in potential difference may be generated between the IPR 1204 and the blocking layer 914.

[0128] In addition, the second gate 1102 can also have a doping profile that is configured to create a potential difference between the IPR 1204 and the blocking layer 914. Specifically, the second gate 1102 can be doped with charge carrier impurities (P-type or N-type) to increase conductivity and reduce response time. Referring Figure 12F , the dopant concentration at the bottom 1230 of the second gate 1102 closest to the blocking layer 914 can be made lower than the dopant concentration at the top 1232 of the second gate 1102. The dopant concentration gradient within the second gate 1102 can also cause opposite charges to flow between the bottom 1230 and the top 1232, and can create a built-in potential difference ΔV between these two portions. Due to the built-in potential difference, the voltage V1 at the bottom 1230 of the second gate 1102 can be reduced by ΔV relative to the voltage V2 of the signal 1104 applied at the top 1232 of the second gate 1102. Since the voltage applied to the blocking layer 914 is reduced relative to the IPR 1204, fewer positive charges are attracted by the second gate 1102 and accumulated in the blocking layer 914 compared to the IPR 1204, which can also result in the blocking layer 914 having a lower electric potential than the IPR 1204.

[0129] Return to reference Figure 12B - Figure 12D, the P-well 908 of the pixel unit 800 may include an optional deep trench isolation (DTI) structure 1240. The DTI structure may act as an insulator to reduce the coupling between adjacent pixel unit devices (e.g., pixel units placed adjacent to each other along the x-axis and y-axis), and further improve the isolation of the N-type regions within the substrate. Each DTI structure may include one or more sidewalls made of silicon oxide and filled with a filling material. In some examples, the filling material may include metal or doped polysilicon and may be conductive to form a conductive DTI structure to support active quench, where the DTI structure 1240 may conduct a voltage to accumulate charge to fill the crystal defects between the P-well 908 and the silicon oxide sidewalls, thereby suppressing the dark current caused by the crystal defects. In Figure 12B - Figure 12D , the DTI structure 1240 may be a backside DTI structure formed from the backside surface 904, but it should be understood that the DTI structure 1240 may also be formed from the frontside surface 902. In some examples, the DTI structure 1240 may also penetrate the pixel unit 800 from the frontside surface 902 to the backside surface 904 along the z-axis to form a full-depth DTI structure.

[0130] Figure 13A and Figure 13B illustrates an example operation of the pixel unit 800 to read out charge from the second photodiode 810. Figure 13A illustrates the change in electric potential with respect to time along the charge conduction path from the N-type region 906 of the second photodiode 810 to the pinned layer 915, while Figure 13B illustrates the corresponding control signals at the first gate 918 and the second gate 1102.

[0131] Reference Figure 13A and Figure 13B , at time 1300, the N-type region 912 of the first photodiode 808 may be without charge after the stored charge has been transferred to the floating drain 818, while the N-type region 912 of the second photodiode 810 stores negative charge. The second gate 1102 may be biased at zero or a negative voltage by the signal 1104. As a result, both the blocking layer 914 and the IPR 1204 have a low electric potential and may prevent negative charge from flowing from the N-type region 906 into the N-type region 912.

[0132] At time 1302, the second gate 1102 may be biased at a positive voltage V by the signal 1104 onThe negative charges in the blocking layer 914 and the IPR 1204 can be pulled by a positive voltage while the positive charges are retained, which can raise the electric potential of the blocking layer 914 and the IPR 1204 to be higher than that of the N-type region 906. Then, the negative charges can flow from the N-type region 906 to the blocking layer 914 and then to the IPR 1204 following the electric potential gradient from the N-type region 906 to the IPR 1204.

[0133] At time 1304, the second gate 1102 can be biased back to zero or a negative voltage by the signal 1104, which causes the electric potential of the IPR 1204 and the blocking layer 914 to drop. The negative charges stored in the IPR 1204 can flow to the N-type region 912 of the second photodiode 810 following the electric potential gradient from the IPR 1204 to the N-type region 912. At time 1304, the signal 1310 can bias the first gate 918 at a positive voltage, which can increase the electric potential of the pinning layer 915 and generate a channel for transferring charges to the floating drain 818. As Figure 13B shown, the transition time of the falling edge of the signal 1104 within time 1304 can be extended (e.g., using a current-starved inverter) to more slowly reduce the electric potential of the IPR 1204 and the blocking layer 914, which can reduce the possibility that the charges stored in the IPR 1204 move (against the electric potential gradient) back to the blocking layer 914 and then back to the N-type region 906.

[0134] Figure 14A and Figure 14B shows another example operation of the pixel unit 800 for reading out charges from the second photodiode 810. Figure 14A shows the variation of the electric potential with respect to time along the charge conduction path from the N-type region 906 of the second photodiode 810 to the pinning layer 915, while Figure 14B shows the corresponding control signals at the first gate 918 and the second gate 1102.

[0135] Referring to Figure 14A , at time 1400, the N-type region 912 of the first photodiode 808 can be without charges after the stored charges are transferred to the floating drain 818, while the N-type region 912 of the second photodiode 810 stores negative charges. The second gate 1102 can be biased at zero or a negative voltage by the signal 1104. As a result, both the blocking layer 914 and the IPR 1204 have a low electric potential and can prevent negative charges from flowing from the N-type region 906 into the N-type region 912.

[0136] In addition, at time 1400 (and at other times), the N-type region 912 (of the first photodiode 808) is biased at the electric potential E 912, the electric potential E 912 is higher than the electric potential E of the N-type region 906 (of the second photodiode 810). 906 . When the second gate 1102 can be biased at a positive voltage V during a subsequent readout on , this arrangement allows negative charges to flow from the N-type region 906 to the N-type region 912, and does not require the bias of the second gate 1102 to return to zero or a negative voltage state to start the flow (as shown by the time 1304 in Figure 13A ). As a result, the time required to subsequently read out the charge from the second photodiode 810 can be reduced.

[0137] Specifically, at time 1402, the second gate 1102 can be biased at a positive voltage V by the signal 1104 on . The negative charges in the blocking layer 914 and the IPR 1204 can be pulled by the positive voltage, while the positive charges are retained, which can raise the electric potential of the blocking layer 914 and the IPR 1204 to be higher than the electric potential of the N-type region 906. At the same time, the electric potential (E 912 ) of the N-type region 912 can be maintained higher than the electric potential of the blocking layer 914 and the IPR 1204. As a result, an electric potential gradient can be formed from the N-type region 906 via the blocking layer 914 and the IPR 1204 to the N-type region 912, and the negative charges can follow the electric potential gradient from the N-type region 906 to the N-type region 912 to flow. Then, within the time 1402, the negative charges can follow the electric potential gradient from the N-type region 906 to the IPR 1204, flow from the N-type region 906 to the blocking layer 914, and then flow to the IPR 1204. This is different from the arrangement in Figure 13A - the bias of the second gate 1102 returns to zero or a negative voltage state to generate an electric potential gradient from the IPR 1204 to the N-type region 912 to start the flow of negative charges. Using this arrangement, the signal 1310 can also be configured to bias the first gate 918 at a positive voltage at time 1402 to transfer the charge from the N-type region 912 to the floating drain 818. In addition, since the second charge directly moves from the N-type region 906 to the N-type region 912 instead of being stored in the IPR 1204 and then transferred to the N-type region 912, when the bias of the second gate 1102 moves back to zero or a negative voltage, the risk of the charge flowing back from the IPR 1204 to the N-type region 906 is very small. Therefore, different from the examples in Figure 13A and Figure 13B , the transition time of the falling edge of the signal 1104 does not need to be extended. All of these can reduce the readout time of the charge stored in the second photodiode 810 and allow the readout to be performed at a higher frequency, which can further improve the operating speed of the pixel unit 800.

[0138] In the example of Figure 14A , E912 can be configured such that when the N-type region 912 is full of charge (after the charge in the N-type region 906 has been emptied), the electric potential at the N-type region 912 (after decreasing from E 912 ) remains higher than the electric potential at the N-type region 906 (and the electric potential of the IPR 1204 and the blocking layer 914 when conducting), to prevent charge from flowing back to the N-type region 906 at time 1402. Between E 912 and E 906 , a voltage headroom needs to be allocated to ensure a high enough E 912 . The same voltage headroom also needs to be allocated between E 912 and the floating drain 818 to ensure that charge can flow from E 912 to the floating drain 818. However, the maximum achievable voltage headroom may be limited by the supply voltage.

[0139] Figure 15 shows additional features that can be part of the pixel unit 800. As Figure 15 shown, in the case where the second gate 1102 penetrates the blocking layer 914 and reaches the N-type region 906 due to manufacturing uncertainties (such as uncertainties in the thickness of the blocking layer 914, uncertainties in the implantation depth of the blocking layer 914, etc.), the pixel unit 800 can include a shield 1502 for shielding the N-type region 906 from the second gate 1102. In Figure 15 , without the shield 1502, the positive voltage at the end 1506 of the second gate 1102 can capture the negative charge in the N-type region 906 and prevent the negative charge from flowing through the blocking layer 914 during readout.

[0140] To mitigate the impact of the second gate 1102 reaching the N-type region 906, a shield 1502 can be provided to shield the negative charge in the N-type region 906 from the end 1506 of the second gate 1102. In some examples, the shield 1502 can be configured as a P-type guard ring, which can cover the lateral sides (e.g., the sides parallel to the z-axis) and the horizontal sides (parallel to the x / y axes) of the end 1506. The P-type guard ring can provide negative charge for the positive voltage at the end 1506 to capture and allow the negative charge in the N-type region 906 to flow through the blocking layer 914 and the IPR 1204 under the positive voltage of the second gate 1102. In some examples, the P-type guard ring of the shield 1502 can be formed by ion implantation after the hole of the second gate 1102 is etched to reach the end 1506 and after the oxide layer 1106 is formed, but before filling the hole with polysilicon material to form the second gate 1102. A relatively low implantation energy can be used to facilitate the correct positioning of the shield 1502 relative to the end 1506.

[0141] In Figure 12A - Figure 15 it, an example of the second gate 1102 having a square cross-sectional shape and a uniform cross-sectional area (e.g., the shape of a rectangular rod) is shown. However, it should be understood that the second gate 1102 may have other cross-sectional shapes and may have a non-uniform cross-sectional area. For example, if the manufacturing process permits, the second gate 1102 may have a circular shape, an octagonal shape, etc. In addition, the second gate 1102 may also have a non-uniform cross-sectional area to further enhance the performance of the pixel unit 800.

[0142] Figure 16 An example of the second gate 1102 having a wedge shape to enhance the absorption of the first light component 822 (or the second light component 824) in the N-type region 912 of the first photodiode 808 is shown. As Figure 16 shown, the second gate 1102 may have a wedge shape having sidewalls 1602 (on which the oxide layer 1106 is formed), the sidewalls 1602 forming an angle with the center line 1202 and being inclined towards the DTI 1240 and the backside surface 904, the backside surface 904 being configured as a light-receiving surface. Both the oxide layer 1106 and the DTI 1240 oxide sidewalls may have refractive indices different from those of the P-well 908 and the N-type region 912. The sidewalls 1602 may reflect the first light component 822 of the incident light 820 towards the DTI 1240 at a predetermined angle and through the N-type region 912. Based on the angle and the different refractive indices, total internal reflection of the first light component 822 may occur at the interface between the P-well 908 and the DTI 1240. The first light component 822 may be reflected back from the interface to the sidewalls 1602 of the second gate 1102 and pass through the N-type region 912 again. When the first light component 822 undergoes repeated reflections between the sidewalls 1602 and the DTI 1240, the first light component 822 travels a longer distance within the N-type region 912, which allows the N-type region 912 to convert more photons of the first light component 822 into charges. With this arrangement, the photon-charge conversion rate of the N-type region 912 for the first light component 822 can be increased, which can enhance the intensity measurement of the first light component 822.

[0143] In some examples, the first gate 918 and the second gate 1102 of the pixel unit 800 may be combined to form a single gate. This arrangement can avoid the clearance distance (e.g., the clearance distance along the x-axis and the y-axis) between the first gate 918 and the second gate 1102 and simplify the structure of the pixel unit 800, both of which allow further reduction of the pitch and the coverage area of the pixel unit 800. Figure 17A - Figure 17BAn example of a pixel unit 800 with a polysilicon merged gate 1700 is shown, which provides the functions of both a first gate 918 and a second gate 1102. Figure 17A A top view (e.g., viewed from the z-axis) of the pixel unit 800 with a backside illumination configuration is shown, while Figure 17B A cross-sectional view of the pixel unit 800 along an imaginary cut line F-F' across the polysilicon merged gate 1700 and the floating drain 818 is shown. As Figure 17B shown, the polysilicon merged gate 1700 may include two parts that are electrically shorted together. Part 1700a may be formed on the front surface 902 and above a lightly doped channel region 1702 (e.g., doped with P-type dopant), while part 1700b may at least penetrate the N-type region 912 of the first photodiode 808 and reach the blocking layer 914. Part 1700a may receive one of the signals 1104 or 1310 and transmit the signal to part 1700b. If part 1700a transmits the signal 1104, part 1700b may perform the function of the second gate 1102 by transmitting the signal 1104 to increase the potential of the blocking layer 914 and the IPR 1204, thereby transferring charge from the N-type region 906 to the N-type region 912. If part 1700a receives the signal 1310, part 1700a may adjust the potential of the channel region 1702 to form a channel for transferring negative charge from the N-type region 912 to the floating drain 818.

[0144] To distinguish between the signal 1104 (for transferring charge through the blocking layer 914 and the IPR 1204) and the signal 1310 (for forming a channel to the floating drain 818 in the channel region 1702), the bias voltages and / or doping profiles of the channel region 1702, the blocking layer 914, the IPR 1204, the N-type regions, etc. of the photodiode may be configured such that a different input signal level is required at the polysilicon merged gate 1700 to form a channel in the channel region 1702 compared to transferring charge through the blocking layer 914. Specifically, referring back to Figure 12E , the IPR 1204 and the blocking layer 914 may have potentials P IPR and P BA with respect to the N-type region 906. P IPR and P BA may be configured based on the bias voltages and doping profiles of the blocking layer 914, the IPR 1204, and the N-type region 906. To allow negative charge to flow from the N-type region 906 into the blocking layer 914 and then into the IPR 1204, the signal 1104 needs to have at least the same signal level as P BA to raise the potential of the blocking layer 914 by P BA, making its potential higher than that of the N-type region 906. Meanwhile, the bias voltage and doping profile of the channel region 1702 can determine the threshold voltage for forming a channel in the channel region 1702, and the threshold voltage can set the signal level of the signal 1310 required to form the channel.

[0145] In some examples, as Figure 17C shown, the signal 1310 can be configured to have a smaller signal level (e.g., a smaller voltage) than the signal 1104, such that the signal 1310 is high enough to form a channel in the channel region 1702 for transferring the charge generated at the N-type region 912 of the first photodiode 808, but not high enough (e.g., less than P BA ), to pull the potential of the blocking layer 914 higher than that of the N-type region 906 for transferring charge via the blocking layer 914. Meanwhile, the signal 1104 is high enough (e.g., higher than or equal to P BA ), to allow charge to be transferred via the blocking layer 914 to the N-type region 912, and to form a channel in the channel region 1702 to transfer the charge received from the N-type region 912 to the floating drain 818. In the previous two-step readout scheme, the charge from the N-type region 906 needs to be first stored in the N-type region 912 before readout. The single-gate arrangement is different from this two-step readout scheme in that it allows for faster readout of charge from the N-type region 912.

[0146] Figure 18 shows Figure 17A and Figure 17B an example operation of the pixel unit 800. Figure 18 shows the potential variation along the cut line G-G' from the N-type region 906 (of the second photodiode 810) to the floating drain 818, and the potential variation along the cut line H-G' from the N-type region 912 (of the first photodiode 808) to the floating drain 818.

[0147] At time 1800, the polysilicon combined gate 1700 can receive a signal with zero or negative voltage. Along the cut line G-G', the IPR 1204 and the blocking layer 914 have a lower potential than that of the N-type region 906, and can prevent the negative charge in the N-type region 906 from flowing to the N-type region 912. Additionally, along the cut line H-G', both the P-well 908 and the IPR 1204 have a lower potential than that of the N-type region 912, and as a result, the negative charge generated by the N-type region 912 (from the conversion of the first light component 822) can be stored in the N-type region 912.

[0148] At time 1802, the polysilicon combined gate 1700 can receive a signal as Figure 17CThe signal 1310 as shown. The signal level of the signal 1310 is high enough to raise the electric potential of the IPR 1204 and the channel region 1702 to form a channel to the floating drain 818. The negative charges stored in the N-type region 912 can flow to the floating drain 818 via the IPR 1204 and the channel region 1702 for reading out. At the same time, the electric potential of the IPR 1204, the blocking layer 914, and the channel region 1702 can be raised by the signal 1310 by the potential difference E 1310 , but at least the electric potential of the blocking layer 914 remains lower than the electric potential of the N-type region 906. As a result, the negative charges remain trapped by the blocking layer 914 in the N-type region 906.

[0149] At time 1804, the polysilicon merged gate 1700 can receive the signal 1104 as Figure 17C shown. The signal 1104 can have a higher signal level than the signal 1310. Along the cut line G-G', the electric potential of the IPR 1204, the blocking layer 914, and the channel region 702 can be raised by the signal 1310 by the potential difference E 1104 , and these electric potentials are now higher than the electric potential of the N-type region 906. An electric potential gradient can be formed from the N-type region 906 to the floating drain 818. A channel is also formed in the channel region 702. Then, the negative charges can flow from the N-type region 906 to the floating drain following the electric potential gradient.

[0150] Figure 19 Shows an example schematic representation of various circuits of the pixel unit 800. As Figure 19 shown, the pixel unit 800 includes a set of switches M0, M1, M2, a first photodiode 808, a second photodiode 810, a charge storage device 616, a voltage buffer 1902, an analog-to-digital converter (ADC) 1904, and a controller 1906. The first photodiode 808, the second photodiode 810, the charge storage device 616, and the voltage buffer 1902 can be implemented in the first semiconductor substrate 802, while the ADC 1904 and the controller 1906 can be implemented in the second semiconductor substrate 804. The first photodiode 808 and the second photodiode 810 can be configured to mainly convert different components of the incident light 820 into charges. The charges can be read out and stored in the charge storage device 616 to generate a voltage (labeled "V OF "), and this voltage can be buffered by the voltage buffer 1902 to become the pixel output voltage (labeled "V 像素输出 "). The pixel output voltage can be quantized by the ADC 1904 to generate a digital output. The controller 1906 can control the switches and the ADC 1904 to perform the readout and quantization processes.

[0151] The first photodiode 808 and the second photodiode 810 can be configured to convert different components of the incident light 820 into charges mainly based on the configuration of the pixel unit 800. For example, in the case where the pixel unit 800 is a backside illumination (FSI) device, in which the second photodiode 810 is closer to the light receiving surface 806 than the first photodiode 808, the first photodiode 808 can be configured to detect infrared light as the first light component 822, while the second photodiode 810 can be configured to detect visible light (e.g., one of red, green, or blue) as the second light component 824. In the case where the pixel unit 800 is a frontside illumination (BSI) device, in which the first photodiode 808 is closer to the light receiving surface 806 than the second photodiode 810, the first photodiode 808 can be configured to detect visible light (e.g., one of red, green, or blue) as the first light component 822, while the second photodiode 810 can be configured to detect visible light (e.g., one of red, green, or blue) as the second light component 824. Each of the first photodiode 808 and the second photodiode 810 has quantum wells to store the charges generated in response to the first light component 822 and the second light component 824 respectively.

[0152] In addition, the charge storage device 616 can provide storage for reading out the charges stored in the first photodiode 808 and the second photodiode 810. Before a new measurement, the charge storage device 616 can be reset by the M2 reset switch, which can be enabled by the RST signal to connect the charge storage device 616 to a charge sink, thereby removing the charges stored in the charge storage device 616. Then, the charges can be read out from the first photodiode 808 or the second photodiode 810 via the transfer switch M1 and stored in the charge storage device 616 for subsequent quantization processing. The charge storage device 616 can generate a V OF voltage, which can be buffered by the voltage buffer 1902 to become the pixel output voltage V 像素输出 . The pixel output voltage V 像素输出 can be quantized by the ADC 1904 to generate a digital output.

[0153] Switches M0, M1, and MB can control the generation of charge and the transfer of charge from the first photodiode 808 and the second photodiode 810 to the charge storage device 616 for readout and quantization operations. The blocking switch MB can control the flow of charge from the second photodiode 810 to the first photodiode 808 for readout. The blocking switch MB can represent the blocking layer 914 and can be controlled by the barrier_switch signal, which can be signal 1104. The barrier_switch signal can represent the potential difference between the blocking layer 914 and the first semiconductor substrate 802 and can be configured based on, for example, applying signal 1104 via the second gate 1102 or the combined gate 1700.

[0154] Additionally, switch M0 can be a shutter switch. The shutter switch M0 controlled by the AB signal can control the start and end of the exposure period during which the first photodiode 808 is allowed to accumulate charge generated in response to the incident light 820. The disabling of the shutter switch M0 can start the exposure period of the first photodiode 808 and the second photodiode 810, while the enabling of the shutter switch M0 can reset the first photodiode 808 and end the exposure period. If the blocking switch MB is also enabled, the second photodiode 810 can also be reset. The shutter switch M0 can also be configured to provide an anti-blooming function to prevent the charge generated by the first photodiode 808 (and / or the second photodiode 810) from leaking into other pixel units of the image sensor, especially when the image sensor operates in an environment of strong ambient light.

[0155] Furthermore, the transfer switch M1 can be controlled by the TG signal to set the potential of the channel region 922, the TG signal can correspond to signal 1310, and the potential of the channel region 922 can control the flow of charge to the charge storage device 616. The transfer switch M1 can be represented by, for example, the first gate 918, the combined gate 1700, etc. For example, the TG signal that configures the transfer switch M1 to a partially conducting state allows the charge accumulated at the first photodiode 808 to be the remaining charge until the amount of charge stored at the first photodiode 808 exceeds the threshold. The transfer switch M1 allows the additional charge generated by the first photodiode 808 to flow as overflow charge to the charge storage device 616. Additionally, the TG signal can also configure the transfer switch M1 to a fully conducting state to transfer the remaining charge stored in the first photodiode 808 to the charge storage device 616 for readout and quantization.

[0156] Transfer switches M1 and blocking switch MB can control the readout and quantization of charges from the first photodiode 808 and the second photodiode 810. In the first readout, the blocking switch MB can be disabled. The transfer switch M1 can be configured in a fully-conductive state to transfer the charge from the first photodiode 808 (“first charge”) to the charge storage device 616. The transferred first charge can be stored in the charge storage device 616 and quantized by the ADC 1904 to generate a first digital output. Then, after the quantization is completed, both the first photodiode 808 and the charge storage device 616 can be reset. A second readout can then be performed, in which the blocking switch MB can be enabled. Then, the charge stored in the photodiode 810 (“second charge”) can be transferred to the photodiode 808 via the blocking switch MB. The transfer switch M1 can also be configured in a fully-on state to transfer the second charge from the photodiode 808 to the charge storage device 616 for subsequent quantization by the ADC 1904 to generate a second digital output. The controller 1906 generates control signals (e.g., signal 1310 and signal 1104) for the transfer switch M1 and the blocking switch MB based on, for example Figure 13A , Figure 13B and Figure 18 the sequences described therein to perform the readout of the first charge and the second charge.

[0157] Figure 20 FIG. shows a flowchart of an example method 2000 for measuring light intensity. The method 2000 can be performed by the controller 1906 and the photodiodes 808 and 810. The photodiodes 808 and 810 can be Figure 8 - Figure 17B part of the pixel unit 800.

[0158] The method 2000 starts at step 2002, in which the controller 1906 transmits a first signal via a first gate portion of one or more gates to transfer the first charge from the first photodiode to the floating drain via a channel region located between the first photodiode and the floating drain for readout. In some examples, the first gate portion can be a polysilicon gate 918 formed on the front surface 902 of the semiconductor substrate 802. In some examples, the first gate portion can be part 1700a of the merged gate 1700.

[0159] As discussed above, the semiconductor substrate further includes a floating drain (e.g., floating drain 818), a first photodiode for generating a first charge (e.g., formed by N-type region 912), a second photodiode for generating a second charge (formed by N-type region 906), and a blocking layer (e.g., blocking layer 914) located between the first photodiode and the second photodiode. The first photodiode, the blocking layer, and the second photodiode form a stack along an axis perpendicular to the front surface. A first signal can cause a channel to be formed in the channel region under the first gate portion to transfer the first charge out of the first photodiode. In some examples, the first photodiode is farther from the light receiving surface than the second photodiode and is configured to convert photons of infrared light into the first charge. In some examples, the first photodiode is closer to the light receiving surface than the second photodiode and is configured to convert photons of visible light into the first charge.

[0160] In step 2004, the first charge can be read out from the floating drain and quantified to measure the intensity of light in a first wavelength range (e.g., infrared light or visible light). The quantification can be performed by ADC 1904.

[0161] In step 2006, the controller 1906 transmits a second signal via a second gate portion of one or more gates to transfer the second charge from the second photodiode to the first photodiode via the blocking layer, where the second gate portion extends from the front surface through the first photodiode and reaches the blocking layer. In some examples, the second gate portion can be a polysilicon gate 1102. In some examples, the second gate portion can be part 1700b of the merged gate 1700. Based on the above techniques, the second signal can change the potential of the blocking layer and the IPR (e.g., IPR 1204) to allow the second charge to move from the second photodiode to the first photodiode. Depending on the position of the second photodiode relative to the light receiving surface, the second charge can be generated from photons of visible light or infrared light.

[0162] In step 2008, the controller 1906 transmits a first signal via the first gate portion to transfer the second charge from the first photodiode to the floating drain via the channel region.

[0163] In step 2010, the ADC 1904 can read out and quantify the second charge from the floating drain to measure the intensity of light in a second wavelength range (e.g., visible light or infrared light).

[0164] The foregoing description of embodiments of the present disclosure has been presented for purposes of illustration; it is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Those skilled in the relevant art can recognize that many modifications and variations are possible in light of the above disclosure.

[0165] Some portions of this description describe embodiments of the present disclosure in terms of algorithms and symbolic representations of operations on information. Those skilled in the data processing art typically use these algorithmic descriptions and representations to effectively convey the substance of their work to other technicians in the field. These operations, while described functionally, computationally, or logically, are to be understood as being implemented by a computer program, equivalent circuitry, microcode, or the like. Additionally, it has sometimes proven convenient and without loss of generality to refer to these arrangements of operations as modules. The described operations and their associated modules can be embodied in software, firmware, and / or hardware.

[0166] One or more hardware or software modules can be utilized, either alone or in combination with other devices, to perform or implement the described steps, operations, or processes. In some embodiments, a software module is implemented using a computer program product that includes a computer-readable medium containing computer program code that can be executed by a computer processor to perform any or all of the described steps, operations, or processes.

[0167] Embodiments of the present disclosure can also relate to apparatus for performing the described operations. The apparatus can be specially constructed for the required purposes, and / or it can include a general-purpose computing device selectively activated or reconfigured by a computer program stored in a computer. Such a computer program can be stored in a non-transitory, tangible computer-readable storage medium, or any type of medium suitable for storing electronic instructions, which can be coupled to a computer system bus. Additionally, any computing system mentioned in the specification can include a single processor, or it can be an architecture that employs a multi-processor design to enhance computing power.

[0168] Embodiments of the present disclosure can also relate to products produced by the computing processes described herein. Such products can include information produced by the computing process, where the information is stored on a non-transitory, tangible computer-readable storage medium and can include any embodiment of a computer program product or other data combinations described herein.

[0169] The language used in the specification has been chosen primarily for readability and guidance, and it may not have been chosen to depict or limit the subject matter of the invention. Thus, it is intended that the scope of the present disclosure not be limited by this detailed description, but rather by any claims issued on an application based thereon. Accordingly, the disclosure of embodiments is intended to be illustrative of the scope of the present disclosure and not limiting, with the scope of the present disclosure set forth in the appended claims.

Claims

1. A multi-photoelectric pixel unit device, comprising: a semiconductor substrate, which includes: a front surface; a first photodiode configured to generate a first charge; a second photodiode configured to generate a second charge; a blocking layer located between the first photodiode and the second photodiode and configured to control the flow of the second charge from the second photodiode to the first photodiode, wherein the first photodiode, the blocking layer, and the second photodiode form a stack along an axis perpendicular to the front surface; and a floating drain for storing the first charge or the second charge; one or more gates, which include: a first gate portion on the front surface above a channel region between the first photodiode and the floating drain; and a second gate portion extending from the front surface through the first photodiode and having an end terminating inside or below the blocking layer along the axis, wherein the first gate portion is configured to conduct a first signal to control the flow of the first charge from the first photodiode via the channel region to the floating drain, and wherein the second gate portion is configured to conduct a second signal for controlling the blocking layer to control the flow of the second charge.

2. The device according to claim 1, further comprising a controller configured to: transmit the first signal via the first gate portion to transfer the first charge from the first photodiode to the floating drain via the channel region for reading out; transmit the second signal via the second gate portion to transfer the second charge from the second photodiode to the first photodiode via the blocking layer; and transmit the first signal via the first gate portion to transfer the second charge from the second photodiode to the floating drain via the channel region for reading out.

3. The device according to claim 2, wherein, the semiconductor substrate is a first semiconductor substrate; and wherein the device further comprises a second semiconductor substrate; and wherein the controller is part of the second semiconductor substrate.

4. The device according to claim 1, wherein: the semiconductor substrate includes a back surface opposite to the front surface, and the back surface is configured as a light receiving surface; the first photodiode is configured to convert a first component of light in the infrared light wavelength range into the first charge; and the second photodiode is configured to convert a second component of light in the visible light wavelength range into the second charge.

5. The device according to claim 1, wherein: the front surface is configured as a light receiving surface; the first photodiode is configured to convert a first component of light in the visible light wavelength range into the first charge; and the second photodiode is configured to convert a second component of light in the infrared light wavelength range into the second charge.

6. The device according to claim 1, wherein, The semiconductor substrate includes a P-well that forms sidewalls on four sides of the stack of the first photodiode, the blocking layer, and the second photodiode; and wherein, the second gate portion extends along a centerline passing through the first photodiode, and the centerline is equidistant from at least two of the sidewalls formed by the P-well.

7. The device according to claim 1, further comprising: an oxide layer between the second gate portion and the first photodiode; and an interface passivation region (IPR) between the oxide layer and the first photodiode.

8. The device according to claim 7, wherein, the interface passivation region and the blocking layer are configured to provide a potential gradient from the second photodiode to the first photodiode.

9. The device according to claim 8, wherein, the interface passivation region and the blocking layer have different doping profiles to provide the potential gradient.

10. The device according to claim 8, wherein, the second gate portion is doped with a dopant that has a doping concentration gradient along the axis to introduce the potential gradient.

11. The device according to claim 1, wherein: the second photodiode is biased at a first voltage; the blocking layer is biased at a second voltage by a signal at the second gate portion; the first photodiode is biased at a third voltage; the channel region is biased at a fourth voltage by a signal at the first gate portion; and the first voltage, the second voltage, the third voltage, and the fourth voltage form a potential gradient from the second photodiode to the channel region to enable the second charge to flow following the potential gradient.

12. The device according to claim 1, further includes a guard ring structure that shields the end of the second gate portion from the blocking layer.

13. The device according to claim 1, wherein, the second gate portion has a non-uniform cross-sectional area.

14. The device according to claim 13, wherein, the second gate portion has a wedge shape and includes inclined sidewalls that are inclined towards the light receiving surface.

15. The device according to claim 14, wherein, the semiconductor substrate further includes a deep trench isolation structure extending along the axis; wherein at least a portion of the first photodiode is located between the deep trench isolation structure and the inclined sidewalls of the second gate portion; wherein the inclined sidewalls are also inclined towards the deep trench isolation structure and are configured to reflect a first light component towards the deep trench isolation structure and through the at least a portion of the first photodiode; and wherein the deep trench isolation structure is configured to reflect the first light component towards the inclined sidewalls and through the at least a portion of the first photodiode.

16. The device according to claim 1, wherein, the one or more gates include a first gate including the first gate portion and a second gate including the second gate portion; and Wherein, the first gate and the second gate are electrically insulated from each other.

17. The device according to claim 1, wherein, the one or more gates include a merged gate, and the merged gate includes the first gate portion and the second gate portion that are electrically connected to each other.

18. The device according to claim 17, further comprising a controller configured to: transmit the first signal via the first gate portion to transfer the first charge from the first photodiode to the floating drain via the channel region for reading out; transmit the second signal via the second gate portion to: transfer the second charge from the second photodiode to the first photodiode via the blocking layer; and transfer the second charge from the second photodiode to the floating drain via the channel region for reading out, wherein, the first signal is not sufficient to cause the second charge to flow from the second photodiode to the first photodiode via the blocking layer.

19. A method for measuring light intensity, comprising: transmitting a first signal via a first gate portion of one or more gates to transfer a first charge from a first photodiode to a floating drain via a channel region between the first photodiode and the floating drain for reading out, wherein the first gate portion is formed on a front surface of a semiconductor substrate, and the semiconductor substrate further includes the floating drain, the first photodiode for generating the first charge, a second photodiode for generating a second charge, and a blocking layer located between the first photodiode and the second photodiode, and the first photodiode, the blocking layer, and the second photodiode are formed in a stack along an axis perpendicular to the front surface; quantifying the first charge in the floating drain to measure the intensity of light in a first wavelength range; transmitting a second signal via a second gate portion of the one or more gates to transfer the second charge from the second photodiode to the first photodiode via the blocking layer, wherein the second gate portion extends from the front surface through the first photodiode and has an end that terminates inside or below the blocking layer along the axis; transmitting the first signal via the first gate portion to transfer the second charge from the first photodiode to the floating drain via the channel region; and quantifying the second charge in the floating drain to measure the intensity of light in a second wavelength range.

20. The method according to claim 19, wherein, the first wavelength range corresponds to the wavelength range of infrared light, and the second wavelength range corresponds to the wavelength range of visible light.

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