Semiconductor device

Abstract

Embodiments of the invention disclose semiconductor devices and methods of forming the same. An exemplary semiconductor device includes a nanostructure disposed over a substrate, where the nanostructure includes a plurality of semiconductor layers vertically spaced apart from one another and a dummy pattern layer including a dielectric material disposed over and vertically spaced apart from a top semiconductor layer of the plurality of semiconductor layers. The exemplary semiconductor device also includes a gate structure disposed over a channel region, where the gate structure surrounds each of the plurality of semiconductor layers of the nanostructure and the dummy pattern layer.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly to semiconductor devices and methods of forming the same. Background Technology

[0002] Multi-gate devices have been introduced to improve gate control by increasing gate channel coupling and reducing off-state current. One type of multi-gate device is the gate-all-around (GAA) device. A GAA device generally refers to any device having a gate structure or a portion of a gate structure formed on more than one side of a channel region (e.g., surrounding a portion of the channel region). GAA transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) fabrication processes and allow for significant miniaturization of transistors. However, fabricating GAA devices is challenging. For example, it has been observed that the formation of a dummy gate structure in a GAA device can lead to top channel damage, and work function metal (WFM) filling and patterning can lead to damage to the gate dielectric layer and barrier layer. Different layer configurations (including layer materials, thicknesses, etc.) between the top channel and adjacent channels in a GAA device can result in inconsistent threshold voltages (Vt) and thus reduce the performance of the GAA device. Summary of the Invention

[0003] In some embodiments, a semiconductor device is provided, the semiconductor device including a nanostructure disposed over a substrate, wherein the nanostructure includes a plurality of semiconductor layers perpendicularly spaced from each other and a dummy pattern layer disposed over and perpendicularly spaced from a top semiconductor layer of the plurality of semiconductor layers, the dummy pattern layer including a dielectric material; and a gate structure disposed over a channel region, wherein the gate structure surrounds each of the plurality of semiconductor layers of the nanostructure and the dummy pattern layer.

[0004] In some other embodiments, a semiconductor device is provided, the semiconductor device including a first nanostructure disposed over a substrate in a first type device region, wherein the first nanostructure includes a first semiconductor layer and a first dielectric pattern layer disposed over and perpendicularly spaced from the first semiconductor layer; a second nanostructure disposed over a substrate in a second type device region, wherein the second nanostructure includes a second semiconductor layer and a second dielectric pattern layer disposed over and perpendicularly spaced from the second semiconductor layer; and a gate structure disposed over a channel region of the first nanostructure and the second nanostructure, wherein the gate structure surrounds the first semiconductor layer and the first dielectric pattern layer of the first nanostructure and the second semiconductor layer and the second dielectric pattern layer of the second nanostructure.

[0005] In other embodiments, a method of forming a semiconductor device is provided, the method comprising forming a fin over a substrate, the fin including a semiconductor layer stack and a dummy pattern layer, wherein the semiconductor layer stack includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer and the second semiconductor layer comprising different semiconductor materials, and the dummy pattern layer comprising a dielectric material and disposed over the top layer of the semiconductor layer stack; forming a dummy gate structure over a channel region of the fin and across a source / drain region of the fin, wherein the dummy gate structure surrounds the fin including the dummy pattern layer and the semiconductor layer stack in the channel region; and replacing the dummy gate structure with a metal gate structure. Attached Figure Description

[0006] The embodiments of the present invention can be better understood from the following detailed description and the accompanying drawings. It should be noted that, according to industry standard practice, the various features shown in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity.

[0007] Figure 1 A flowchart showing an exemplary method for forming a semiconductor device according to some embodiments of the present invention is displayed.

[0008] Figure 2 Based on Figure 1 A perspective view of a portion of a semiconductor device at an intermediate stage of manufacturing, according to an embodiment of the method.

[0009] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A and Figure 16A Showing some embodiments according to the present invention Figure 1 The intermediate stage of the method, along Figure 2 A schematic cross-sectional view of a semiconductor device taken by line AA.

[0010] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B and Figure 16B Showing some embodiments according to the present invention Figure 1 The intermediate stage of the method, along Figure 2 A schematic cross-sectional view of a semiconductor device taken by line BB.

[0011] Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C and Figure 16C Showing some embodiments according to the present invention Figure 1 The intermediate stage of the method, along Figure 2 A schematic cross-sectional view of a semiconductor device taken by line CC.

[0012] The annotations in the attached figures are explained as follows: 100: Method 105, 110, 115, 120, 125, 130, 135, 140, 145, 150: Operation 200: Semiconductor devices 202: Base 202A: p-type doped region 202B: n-type doped region 203: Isolation Structure 204: Fins 204A, 204B: Semiconductor layers 204C: Passage Area 204S / D: Source / Drain Region 206: Virtual Pattern Layer 210: Dummy gate stack 212: Dummy gate electrode 214: Dielectric Etching Stop Layer 215: Gate spacer wall 215': Spacer layer 216: Hard mask layer 220: Trench 250: Epitaxial source / drain components 260,260': Contact etch stop layer 270, 270': Interlayer dielectric layer 280A, 280B: Metal gate 282: Gate dielectric layer 284: Barrier Layer 286: First work function metal layer 288: Second work function metal layer 290: Metal filler layer 296: Source / Drain Via 298: Gate via 1300: Photoresist MG: Distance Detailed Implementation

[0013] It is important to understand that the following disclosure provides many different embodiments or examples for implementing different components of the provided subject. Specific examples of the various components and their arrangements are described below to simplify the description of the disclosure. Of course, these are merely examples and are not intended to limit the invention. For example, the following disclosure describes forming a first component on or above a second component, indicating that it includes embodiments where the formed first component and the second component are in direct contact, as well as embodiments where additional components may be formed between the first component and the second component, so that the first component and the second component may not be in direct contact.

[0014] Furthermore, different examples in the disclosure may use repeated reference numerals and / or words. These repeated numerals or words are for simplification and clarity purposes and are not intended to limit the relationships between the various embodiments and / or the described appearance structures. Moreover, the following description of a component formed on, connected to, and / or coupled to another component may include embodiments where the components are in direct contact with each other, or embodiments where other components may be formed between these components such that these components are not in direct contact with each other. Furthermore, to facilitate the description of the relationship between one component and another in embodiments of the invention, spatially related terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “top,” “bottom,” etc., and their derivative terms (e.g., “horizontally,” “downward,” “upward,” etc.) are used. Spatially related terms are used to cover different orientations of the device including the component. Furthermore, when numbers or ranges of numbers are described using terms such as “approximately,” “about,” and similar terms, these terms are intended to cover a reasonable range of the described numbers, such as within + / - 10% of the described numbers or other values ​​that should be understood by those skilled in the art to which this invention pertains. For example, the term "about 5nm" covers a size range of 4.5nm to 5.5nm.

[0015] The embodiments of the present invention are generally related to semiconductor devices and methods of forming them, and particularly to methods of forming field-effect transistors (FETs), such as gate-around field-effect transistors (GAAFETs).

[0016] In a gate-around-the-loop device, the channel region of a single device may include multiple layers of semiconductor materials physically separated from each other. In some examples, the gate of the device is disposed above, beside, or even between the semiconductor layers of the device. Embodiments of the present invention provide a gate-around-the-loop device in which the fins of the gate-around-the-loop device include a dielectric dummy pattern layer disposed above the top layer of the multiple semiconductor layers. This dielectric dummy pattern layer protects the top semiconductor layer from damage during the formation of the dummy gate structure and / or protects the gate dielectric layer and the barrier layer / work function metal (WFM) layer from removal during the patterning of the work function metal. The protection provided by the dielectric dummy pattern layer enables a uniform layer configuration (including the number of layers, material per layer, and thickness per layer) between adjacent semiconductor layers and between the top semiconductor layer and the dummy pattern layer, thereby achieving a consistent threshold voltage (Vt) and improving the performance of the gate-around-the-loop device. Furthermore, since the dummy pattern layer is disposed above the top semiconductor layer of the fin, the distance between the top channel and the source / drain junction is increased, reducing the capacitance between the metal gate and the source / drain (S / D) junction. These advantages are merely illustrative and no particular advantage is required for any specific embodiment.

[0017] Figure 1 A flowchart illustrating an exemplary method 100 for forming a semiconductor device 200 (sometimes simply referred to as a device) according to some embodiments of the present invention is shown. Method 100 is merely exemplary and is not intended to limit the embodiments of the invention beyond the scope expressly described in the claims. Additional operations may be performed before, during, and after method 100, and some of the described operations may be substituted, eliminated, or moved for other embodiments of the method. Method 100 is described below in conjunction with other accompanying drawings showing three-dimensional views and cross-sectional schematic diagrams of a portion or the entire semiconductor device 200 during intermediate steps of method 100. In particular, Figure 2 Displays a three-dimensional view of the semiconductor device 200. Figures 3A-16A For along Figure 2 A schematic cross-sectional view of the semiconductor device 200 taken along plane AA (i.e., along the X direction). Figures 3B-16B For along Figure 2 A schematic cross-sectional view of the semiconductor device 200 taken along plane BB (i.e., along the X direction), and Figures 3C-16C For along Figure 2 A schematic cross-sectional view of the semiconductor device 200 taken from the plane CC (i.e., along the Y direction).

[0018] Semiconductor device 200 may be an intermediate device during the fabrication of an integrated circuit (IC) or a portion thereof. Semiconductor device 200 may include static random-access memory (SRAM) and / or other logic circuitry, passive components (e.g., resistors, capacitors, and inductors), and active components (e.g., p-type FETs (PFETs), n-type FETs (NFETs), fin-like FETs (FinFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells). Depending on the design requirements of semiconductor device 200, various transistors may be planar transistors or multi-gate transistors. Semiconductor device 200 may be part of a core region (also often referred to as a logic region), memory region (e.g., a static random access memory (SRAM) region), analog region, peripheral region (also often referred to as an input / output (I / O) region), dummy region, other suitable region, or a combination thereof. In some embodiments, semiconductor device 200 may be part of an integrated circuit chip, a system-on-a-chip (SoC), or a part of a SoC. Embodiments of the present invention are not limited to any particular number of devices or device regions or any particular device configuration. For example, although the shown semiconductor device 200 is a three-dimensional field-effect transistor device (e.g., a fin field-effect transistor or a gate-around field-effect transistor), this disclosure may also provide embodiments for manufacturing planar field-effect transistor devices.

[0019] Please refer to Figure 1 , 2 and Figures 3A-3CIn operation 105, a semiconductor device 200 is provided. The semiconductor device 200 includes a substrate 202, which is a bulk substrate comprising silicon. Alternatively or additionally, the bulk substrate includes other elemental semiconductors (e.g., germanium), compound semiconductors (e.g., silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, zinc oxide, zinc selenide, zinc sulfide, zinc telluride, cadmium selenide, cadmium sulfide, and / or cadmium telluride), alloy semiconductors (e.g., SiGe, SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), other Group III-V materials, other Group II-IV materials, or combinations thereof. Alternatively, substrate 202 may be a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The SOI substrate can be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. Substrate 202 may include various doped regions. In some embodiments, substrate 202 includes n-type doped regions (e.g., n-type wells) doped with n-type dopants, such as phosphorus (e.g., phosphorus). 31 P), arsenic, other n-type dopants, or combinations thereof. In some embodiments, the substrate 202 includes p-type doped regions (e.g., p-type wells) doped with p-type dopants, such as boron (e.g., arsenic, other n-type dopants, or combinations thereof). 11 B, BF2), indium, other p-type dopants, or combinations thereof. In some embodiments, substrate 202 includes doped regions formed by a combination of p-type and n-type dopants. For example, in the illustrated embodiment, substrate 202 includes a p-type doped region 202A doped with p-type dopants and an n-type doped region 202B doped with n-type dopants. Various doped regions may be formed directly on and / or in substrate 202, providing, for example, p-type well structures, n-type well structures, dual-well structures, bump structures, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes may be performed to form the various doped regions.

[0020] Semiconductor device 200 includes one or more fins 204 (also referred to as nanostructures or active fin regions) protruding from substrate 202. The fins 204 are oriented along the Y-direction and arranged side-by-side along the X-direction. Each fin 204 has a width defined in the X-direction, a length defined in the Y-direction, and a height defined in the Z-direction. The lower portions of the fins 204 are separated by an isolation structure 203. Each fin 204 includes a stack of semiconductor layers 204A and 204B, and a dummy pattern layer 206 is deposited on top of the stack of semiconductor layers 204A and 204B. Please refer to... Figure 2 The semiconductor device 200 includes two fins 204, and each fin 204 includes three semiconductor layers 204A and three semiconductor layers 204B. In various embodiments, the semiconductor device 200 may include any number of fins 204, and the fins 204 may include any number of alternately stacked semiconductor layers 204A and 204B. The total number of semiconductor layers in the fins 204 depends on the design of the semiconductor device 200. For example, the fins 204 may include 2-10 alternating semiconductor layers 204A and 204B. Each fin 204 has at least one channel region and at least one source region and one drain region defining its length in the Y direction, wherein at least one channel region 204C is disposed between the source region and the drain region (both referred to as source / drain (S / D) region 204S / D). Surface AA is cut along the source / drain region 204S / D of fin 204, surface BB is cut along the channel region 204C of fin 204, and surface CC is cut along the length of one of the fins 204.

[0021] Each fin 204 is adapted to provide an n-type field-effect transistor or a p-type field-effect transistor. In some embodiments, the fins 204 shown in this embodiment of the invention may be adapted to provide similar types of field-effect transistors, i.e., all n-type or all p-type. Alternatively, the fins 204 shown in this embodiment of the invention may be adapted to provide opposite types of field-effect transistors, i.e., n-type and p-type. In the shown embodiment, the fin 204 disposed in the p-type doped region 202A provides a p-type field-effect transistor, while the fin 204 disposed in the n-type doped region 202B provides an n-type field-effect transistor.

[0022] As described above, each fin 204 includes a semiconductor layer stack having various semiconductor layers disposed above the substrate 202. Figure 2 and Figures 3A-3CIn the illustrated embodiment, the semiconductor layer stack includes alternating semiconductor layers, such as semiconductor layer 204A comprising a first semiconductor material and semiconductor layer 204B comprising a second semiconductor material, the second semiconductor layer material being different from the first semiconductor layer material. Different semiconductor materials are provided for the alternating semiconductor layers 204A and 204B to have different oxidation rates and / or different etch selectivity. In some examples, semiconductor layer 204A comprises silicon (Si), and semiconductor layer 204B comprises silicon germanium (SiGe). Thus, the semiconductor layer stack has alternating Si / SiGe / Si / SiGe / ... layers arranged from bottom to top. In some embodiments, the bottom semiconductor layer 204A may be incorporated with a substrate 202 (which also comprises Si) and form part of the substrate 202. In some embodiments, the material of the top semiconductor layer in the semiconductor layer stack is the same as that of the bottom semiconductor layer. In some other embodiments, the material of the top semiconductor layer is different from that of the bottom semiconductor layer in the semiconductor layer stack. In some embodiments, for a semiconductor layer stack comprising alternating Si and SiGe layers, the bottom semiconductor layer comprises Si, and the top semiconductor layer may be either a Si or a SiGe layer. In some embodiments, the semiconductor layer stack comprises the same material but with alternating atomic percentages, such as a semiconductor layer 204A having a first atomic percentage and a semiconductor layer 204B having a second atomic percentage. In some examples, the semiconductor layer stack comprises SiGe layers with alternating atomic percentages of silicon and / or germanium (for example, from bottom to top, SiaGeb / SicGed / SiaGeb / SicGed…, where a and c are different atomic percentages of silicon, and b and d are different atomic percentages of germanium). In various embodiments, the alternating material layers in the semiconductor layer stack may comprise other materials (e.g., germanium), compound semiconductors (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (e.g., GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or combinations thereof. As discussed above, the materials of the alternating semiconductor layers may be selected based on the different oxidation rates and / or etch selectivity provided. In some embodiments, semiconductor layer 204A may be undoped or substantially doped (i.e., having an external dopant concentration of about 0 cm⁻³ to about 1 × 10¹⁷ cm⁻³). In some embodiments, doping is not intended when semiconductor layer 204A is formed. In some other embodiments, semiconductor layer 204A may be doped with p-type dopant, such as boron or boron compounds (B, I¹B, or BF₂), aluminum (Al), indium (In), gallium (Ga), or combinations thereof for p-type channels. Alternatively, semiconductor layer 204A may be doped with n-type dopant, such as phosphorus (P, ¹¹P), arsenic (As), antimony (Sb), or combinations thereof for n-type channels.In some embodiments, semiconductor layer 204A may include different compositions, and semiconductor layer 204B may include different compositions.

[0023] As discussed above, each fin 204 also includes a dummy pattern layer 206 disposed above the top layer of the semiconductor layer stack (alternating semiconductor layers 204A or 204B). In the illustrated embodiment, the dummy pattern layer 206 is disposed above the top semiconductor layer 204B, which includes SiGe. In some other embodiments, if the top layer of the alternating semiconductor layers is a semiconductor layer 204A including Si, the dummy pattern layer 206 is disposed above the top semiconductor layer 204A. The bottom surface of the dummy pattern layer 206 directly contacts the top surface of the top layer of the semiconductor layer stack and conformally patterns the top surface of the top layer of the semiconductor layer stack. The dummy pattern layer 206 includes a dielectric material having a different etch selectivity than the top layer of the semiconductor layer stack, thus protecting the semiconductor layer stack (semiconductor layers 204A or 204B) from damage during subsequent manufacturing processes (e.g., dummy gate structure formation and / or work function metallization). In some embodiments, the dummy pattern layer 206 includes a dielectric material, which includes oxygen, carbon, nitrogen, other suitable materials, or combinations thereof. For example, the dummy pattern layer 206 may include silicon nitride (SiN), silicon carbide nitride (SiCN), silicon carbide (SiOC), silicon carbide oxynitride (SiOCN), hafnium oxide (HfO), lanthanum oxide (LaO), aluminum oxide (AlO), other suitable dielectric materials, or combinations thereof.

[0024] In some embodiments, the different semiconductor layers (semiconductor layers 204A, 204B) of the fin 204 have the same thickness in the Z direction. In some other embodiments, the different semiconductor layers (semiconductor layers 204A, 204B) of the fin 204 have different thicknesses. In some embodiments, the bottom layer 204A of the semiconductor layer stack (embedded in the isolation structure 203) is thicker than the other layers of the semiconductor layer stack. In some embodiments, each semiconductor layer 204A and 204B extending over the isolation structure 203 has a thickness ranging from about 3 nm to about 30 nm. In some embodiments, the dummy pattern layer 206 has a thickness ranging from about 1 nm to about 30 nm, which is about 30% to 100% of the thickness of the semiconductor layers 204A and / or 204B extending over the isolation structure 203. For example, the thickness of the dummy pattern layer 206 is about 30% to about 100% of the thickness of the top semiconductor layer 204A. In some embodiments, the height of the fin 204 above the isolation structure 203 in the Z direction is about 50 nm to about 80 nm. Therefore, the ratio of the thickness of the dummy pattern layer 206 to the height of the fin 204 is approximately 5-25%. However, embodiments of the present invention are not limited to this configuration.

[0025] Fins 204 are formed over a substrate 202 using suitable processes. In some embodiments, a combination of deposition, epitaxy, photolithography, etching, and / or other suitable processes is performed to form fins 204 comprising alternating semiconductor layers 204A and 204B and a dummy pattern layer 206. For example, various semiconductor layers 204A and 204B comprising different semiconductor materials (e.g., semiconductor layer 204A comprising Si and semiconductor layer 204B comprising SiGe) are alternately deposited over the substrate 202. In some embodiments, semiconductor layers 204A and 204B can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (e.g., metal-organic chemical vapor deposition (MOCVD)), and / or other suitable epitaxial growth processes. Subsequently, a dummy pattern layer 206 is deposited over the alternating semiconductor layers 204A and 204B. The dummy pattern layer 206 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), other suitable methods, or combinations thereof. Next, a mask element is formed over semiconductor layers 204A and 204B and the dummy pattern layer 206 using a photolithography process. The photolithography process may include forming a photoresist (or resist) over semiconductor layers 204A and 204B and the dummy pattern layer 206, exposing the photoresist to a pattern defining various geometries, performing a post-exposure baking process, and developing the photoresist to form the mask element. Subsequently, the semiconductor layers 204A and 204B and the dummy pattern layer 206 are etched through the mask element to form trenches therein. The etching process may include one or more dry etching processes, wet etching processes, and other suitable etching techniques. For example, dry etching processes may use oxygen-containing gases, fluorine-containing gases (CF4, SF6, CH2F2, CHF3 and / or C2H6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. For example, wet etching processes may include etching in diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, solutions containing hydrofluoric acid (HF), nitric acid (HNO3), and / or acetic acid (CH3COOH), or other suitable wet etchants. The remaining portion of the layer forms fin 204.

[0026] In some other embodiments, the fin 204 may be formed in various steps. For example, a semiconductor stack including semiconductor layers 204A and 204B (excluding the dummy pattern layer 206) is formed by manufacturing steps including the deposition, epitaxy, photolithography, and etching processes described above. Subsequently, the dummy pattern layer 206 (e.g., by atomic layer deposition) is deposited over the top layer of the semiconductor stack, thereby forming the fin 204 including the dummy pattern layer 206 and the semiconductor layers 204A and 204B.

[0027] An isolation structure 203 is formed above and / or within a substrate 202 to separate active and / or passive device regions of the semiconductor device 200, such as the gate-around transistor of the semiconductor device 200. The isolation structure 203 further separates and isolates the fins 204 from each other. The isolation structure 203 can be configured in different structures, such as shallow trench isolation (STI), deep trench isolation (DTI), a local oxidation of silicon (LOCOS), or a combination thereof. The isolation structure 203 includes an isolation material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), other suitable isolation materials (e.g., including silicon, oxygen, nitrogen, carbon, and / or other suitable isolation components), or a combination thereof. In some embodiments, the shallow trench isolation component can be formed by etching trenches in the substrate (e.g., using dry etching and / or wet etching processes) and filling the trenches with an insulating material (e.g., using chemical vapor deposition (CVD) or spin-coating glass processes). Chemical mechanical polishing (CMP) processes can be performed to remove excess insulating material and / or planarize the top surface of the isolation structure 203. In some embodiments, the shallow trench isolation component can be formed by depositing an insulating material over the substrate 202 after forming the fins 204 (in some embodiments, such that the insulating material layer fills the gaps (trenches) between the fins 204) and etching back the insulating material layer to form the isolation structure 203. In some embodiments, the isolation structure 203 includes a multilayer structure filling the trenches, such as a bulk dielectric layer disposed over a pad dielectric layer, wherein the bulk dielectric layer and the pad dielectric layer comprise materials depending on design requirements, such as a bulk dielectric layer comprising silicon nitride disposed over a pad dielectric layer comprising thermal oxides. In some embodiments, the isolation structure 203 includes a dielectric layer disposed over a doped pad layer (e.g., comprising borosilicate glass (BSG) or phosphosilicate glass (PSG)).

[0028] Please refer to Figure 1 and Figures 4A-4C In operation 110, a dummy gate stack 210 is formed over fin 204. The dummy gate stack 210 serves as a placeholder for the subsequent formation of a metal gate structure. As will be discussed in detail below, after fabrication of other components of the semiconductor device 200 (e.g., epitaxial source / drain components 250), the dummy gate stack 210 is replaced with a metal gate structure during a gate replacement process. The dummy gate stack 210 extends along the X direction and spans the respective fin 204. In the illustrated embodiment, the dummy gate stack 210 is disposed over the channel region 204C of fin 204, and thus between the respective source / drain regions 204S / D of fin 204. The dummy gate stack 210 occupies the respective channel region 204C of fin 204, allowing current to flow between the respective source / drain regions 204S / D of fin 204 during operation. Figures 4A-4C In the illustrated embodiment, the dummy gate stack 210 includes a polysilicon dummy gate electrode 212 and various other layers, such as a dielectric etch stop layer 214 disposed above the dummy gate electrode 212 and / or a hard mask layer 216 disposed above the dielectric etch stop layer 214. The dummy gate stack 210 may also include an interface layer (not shown, e.g., silicon oxide) disposed above the fin 204 and the substrate 202 and below the dummy gate electrode 212. The dielectric etch stop layer 214 may include silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials. The hard mask layer 216 may include one or more layers of materials, such as silicon oxide (SiO), silicon nitride (SiN), and / or silicon carbide nitride (SiCN). The dummy gate electrode 212 may be a single or multiple dielectric layers. The material of the dummy gate electrode 212 can be selected from silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxynitride carbon (SiOCN), carbon oxides, nitrogen oxides, carbon nitrides, metal oxide dielectrics, hafnium oxide (HfO-) 2) Tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), yttrium oxide (Y2O3), any other suitable material or a combination thereof.

[0029] The dummy gate stack 210 can be formed by deposition, photolithography, etching, other suitable processes, or combinations thereof. For example, a deposition process can be performed to form the dummy gate electrode 212, dielectric etch stop layer 214, and hard mask layer 216 over the substrate 202, fin 204, and isolation structure 203. The deposition process can include chemical vapor deposition, physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition (HDPCVD), metal-organic chemical vapor deposition, remote plasma chemical vapor deposition (RPCVD), plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), plating, other suitable methods, or combinations thereof. Next, photolithographic patterning and etching processes are performed to pattern the dummy gate electrode 212, dielectric etch stop layer 214, and hard mask layer 216 to form a dummy gate stack 210, such that the dummy gate stack 210 surrounds the fin 204. The photolithographic patterning process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, other methods may be used to assist, perform, or replace the photolithographic exposure process, such as maskless lithography, electron beam writing, or ion beam writing. In other embodiments, the photolithographic patterning process uses nanoimprint lithography. The etching process may include dry etching, wet etching, other etching methods, or combinations thereof.

[0030] Please refer to Figure 1 , 5A -5C and Figures 6A-6C In operation 115, a gate spacer wall 215 is formed along the sidewall of the dummy gate stack 210. The formation of the gate spacer wall includes various steps. For example, such as... Figures 5A-5C As shown, spacer layer 215' is compliantly disposed over semiconductor device 200 including fin 204, dummy gate stack 210, and isolation structure 203. In various embodiments, spacer layer 215' may comprise a single layer or a multilayer structure. In some embodiments, spacer layer 215' may comprise one or more dielectric materials, such as silicon nitride (SiN), silicon oxide (SiO), silicon carbide (SiC), silicon carbide oxide (SiOC), silicon carbide nitride (SiCN), silicon carbide nitride oxide (SiOCN), other suitable materials, or combinations thereof. In conventional embodiments, spacer layer 215' has a thickness of several nanometers. Spacer layer 215' may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, physical vapor deposition, other suitable methods, or combinations thereof.

[0031] Please refer to Figures 6A-6C While still in operation 115, the spacer layer 215' is etched using an anisotropic etching process to remove portions of the spacer layer 215' on the top surface of the dummy gate stack 210 in the channel region 204C and on the top surface of the fin 204 in the source / drain regions 204S / D. A portion of the spacer layer 215' along the sidewalls of the dummy gate stack 210 is largely retained and becomes the gate spacer wall 215. In some embodiments, the anisotropic etching process is a dry (e.g., plasma) etching process. In some embodiments, the dry etching process may use an etchant comprising a bromine-containing gas (e.g., HBr and / or CHBr3), a fluorine-containing gas (CF4, SF6, CH2F2, CHF3 and / or C2H6), other suitable gases, or combinations thereof.

[0032] Please refer to Figure 1 and Figures 7A-7C In operation 120, a portion of the fin 204 in the source / drain region 204S / D is removed along the gate gap wall 215. Therefore, the alternating semiconductor layers 204A and 204B, as well as the sidewalls of the dummy pattern layer 206, are exposed to the source / drain region (see [reference]). Figure 7C In some embodiments, a portion of the fin 204 in the source / drain region 204S / D is removed by a suitable etching process, such as dry etching, wet etching, reactive ion etching (RIE), or a combination thereof. Figure 7C As shown, the portion of fin 204 (including dummy pattern layer 206 and semiconductor layers 204A and 204B) below gate spacer wall 215 is retained and substantially unchanged. In some embodiments, a portion of fin 204 is selectively removed along gate spacer wall 215 without etching or substantially etching a portion of dummy gate stack 210. In some embodiments, a portion of isolation structure 203 in source / drain region 204S / D may also be selectively etched (see reference). Figure 7A This exposes the top of the bottom layer of semiconductor layer 204A. This is known as a fin recess process. Fin recess processes can include dry etching processes, wet etching processes, other etching processes, or combinations thereof.

[0033] Please refer to Figure 1 and 8A-8C, in operation 125, epitaxial source / drain components 250 are epitaxially grown in the source / drain regions of fin 204. In some other embodiments, the epitaxial source / drain components 250 are grown from at least a portion of the fin active region and surround at least a portion of the fin active region. In some embodiments, as shown in the embodiments of the present invention, the epitaxial source / drain components 250 are spaced apart from each other. In some other embodiments, the epitaxial source / drain components 250 extend laterally (grow) along the X direction (in some embodiments, generally perpendicular to the length of fin 204) such that the epitaxial source / drain components 250 are merged epitaxial source / drain components spanning more than one fin. In some other embodiments, the epitaxial source / drain components 250 include partially merged portions (having interruptions (or gaps) between epitaxial materials grown on adjacent fins 204) and / or fully merged portions (without interruptions (or gaps) between epitaxial materials grown on adjacent fins 204). In some embodiments, the epitaxial source / drain component 250 comprises the same material as the semiconductor layer 204A (e.g., both comprise silicon). In some other embodiments, the epitaxial source / drain component 250 and the semiconductor layer 204A comprise different materials or compositions. In various embodiments, the epitaxial source / drain component 250 may comprise a semiconductor material (e.g., silicon or germanium), a compound semiconductor (e.g., silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide), an alloy semiconductor (e.g., GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or a combination thereof. The epitaxial source / drain component 250 may be grown epitaxially using an epitaxial process. Epitaxial processes may include chemical vapor deposition techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure chemical vapor deposition and / or plasma-assisted chemical vapor deposition), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or combinations thereof. Gas and / or liquid precursors may be used in epitaxial processes.

[0034] In some embodiments, the epitaxial source / drain component 250 may be doped with n-type dopant and / or p-type dopant. In some embodiments, the epitaxial source / drain component 250 is doped with boron (e.g., 11 B or BF2), indium, carbon, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial source / drain devices or Si:Ge:C epitaxial source / drain devices). In some embodiments, the epitaxial source / drain device 250 is doped with phosphorus (P, BF2), indium, carbon, other p-type dopants, or combinations thereof (e.g., forming Si:Ge:B epitaxial source / drain devices). 31P), arsenic (As), other n-type dopants, or combinations thereof (e.g., forming Si:P epitaxial source / drain devices, Si:C epitaxial source / drain devices, or Si:C:P epitaxial source / drain devices). In some embodiments, the epitaxial source / drain device 250 comprises multiple epitaxial semiconductor layers, and the different epitaxial semiconductor layers include different amounts of dopants. In some embodiments, the epitaxial source / drain device 250 includes material and / or dopants to achieve desired tensile and / or compressive stresses in the channel region. In some embodiments, the epitaxial source / drain device 250 is doped during deposition by adding impurities to the source material of the epitaxial process. In some embodiments, the epitaxial source / drain device 250 is doped by an ion implantation process following the deposition process. In some embodiments, an annealing process is performed to activate the dopants in the epitaxial source / drain device 250 of the semiconductor device 200, such as heavily doped drain (HDD) regions and / or lightly doped drain (LDD) regions.

[0035] Please refer to Figure 1 and 9A-9C, in operation 130, a contact etch stop layer (CESL) 260 and an interlevel dielectric (ILD) layer 270 are deposited over a substrate 202. Specifically, the contact etch stop layer 260 and the interlevel dielectric layer 270 are disposed over the epitaxial source / drain components 250, the dummy gate stack 210, the gate spacer 215, and / or the isolation structure 203. In some embodiments, the interlevel dielectric layer 270 is a multilayer interconnect (MLI) component electrically coupling various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or source / drain components) of the semiconductor device, enabling the various devices and / or components to operate according to the design specifications of the semiconductor device 200. Interlayer dielectric layer 270 includes a dielectric layer comprising silicon oxide, silicon nitride, silicon oxynitride, an oxide formed of tetraethylorthosilicate (TEOS), phosphosilicate glass, borophosphosilicate glass (BPSG), a low-dielectric-constant dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-dielectric-constant dielectric materials include fluorine-doped silicate glass (FSG), carbon-doped silicon oxide, black diamond (registered by Applied Materials, Santa Clara, CAR), desiccant, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK (registered by Dow Chemical, Midland, Michigan), polyimide, other low-dielectric-constant dielectric materials, or combinations thereof. In some embodiments, interlayer dielectric layer 270 has a multilayer structure having multiple dielectric materials. In some embodiments, a contact etch stop layer 260 is disposed between the interlayer dielectric layer 270 and the epitaxial source / drain component 250, the isolation structure 203, the dummy gate stack 210, and / or the gate spacer 215. The contact etch stop layer 260 comprises a material different from that of the interlayer dielectric layer 270; for example, the contact etch stop layer 260 comprises a dielectric material different from that of the interlayer dielectric layer 270. In the illustrated embodiment, the interlayer dielectric layer 270 comprises a low dielectric constant dielectric material, and the contact etch stop layer 260 comprises silicon and nitrogen (e.g., silicon nitride or silicon oxynitride).The contact etch stop layer 260 and / or the interlayer dielectric layer 270 are formed over the substrate 202, for example, by a deposition process, such as chemical vapor deposition, flowable chemical vapor deposition (FCVD), physical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, metal-organic chemical vapor deposition, distal plasma chemical vapor deposition, plasma-assisted chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer chemical vapor deposition, ambient pressure chemical vapor deposition, plating, other suitable methods, or combinations thereof. After depositing the contact etch stop layer 260 and / or the interlayer dielectric layer 270, a chemical mechanical polishing process is performed to planarize the top surface of the semiconductor device 200. The chemical mechanical polishing process also removes the hard mask layer 216 and the dielectric etch stop layer 214 (see reference). Figure 9B and 9C Therefore, the dummy gate electrode 212 is exposed on the top surface of the semiconductor device 200.

[0036] Please refer to Figure 1 and Figures 10A-10C In operation 135, the dummy gate electrode 212 is removed to form trench 220. For example... Figure 10B As shown, the sidewalls of the fin 204, including semiconductor layers 204A and 204B and the dummy pattern layer 206, are exposed in the trench 220. In some embodiments, the step of removing the dummy gate electrode 212 includes one or more etching processes, such as wet etching, dry etching, reactive ion etching, other etching techniques, or combinations thereof. Removing the dummy gate electrode 212 may also result in the removal of the top of the dummy pattern layer 206, which can damage the dummy pattern layer 206 due to a reduction in its overall thickness (also referred to as thinning). This effect may be unintentional and may be caused by insufficient etch selectivity between the dummy gate electrode 212 and the underlying layer. However, thinning the dummy pattern layer 206 does not adversely affect the manufacturing process described in the embodiments of the invention as much as in conventional manufacturing processes. In conventional manufacturing processes, the semiconductor fin does not include the dummy pattern layer 206. Therefore, the top semiconductor layer of the semiconductor fin (e.g., semiconductor layer 204A comprising Si) can be damaged (thinned) during the etching process for removing the dummy gate. Therefore, the top channel semiconductor layer (e.g., semiconductor layer 204A) of the semiconductor device is thinner than the other channel semiconductor layers of the semiconductor device. Consequently, the performance of the semiconductor device decreases. However, in this embodiment of the invention, the semiconductor fin includes a dummy pattern layer 206 disposed above the top layer of the semiconductor layer stack, thus protecting the top semiconductor layer (e.g., semiconductor layer 204A comprising Si) during the etching process that removes the dummy gate and preventing damage / loss of the top channel. Therefore, with the protection of the dummy pattern layer 206, all channel semiconductor layers of the semiconductor device have a uniform thickness to ensure the performance of the semiconductor device.

[0037] Please refer to Figure 1 and Figure 11A-11C In operation 140, the semiconductor layer 204B or a portion of the semiconductor layer 204B of the fin 204 is selectively removed to extend a trench 220 between the semiconductor layer 204A and the dummy pattern layer 206. Thus, the semiconductor layer 204A and the dummy pattern layer 206 are suspended in the channel region 204C of the fin 204. Depending on the design requirements of the semiconductor device 200, the semiconductor layer 204A and the dummy pattern layer 206 may be lightly etched or not etched. In some embodiments, the semiconductor layer 204A and the dummy pattern layer 206 are lightly etched to form various shapes of nanostructures, such as nanowires, nanosheets, or other shaped nanostructures. Because the semiconductor layer 204B comprises a material with a different etch selectivity than the material of the semiconductor layer 204A and the dielectric material of the dummy pattern layer 206, the semiconductor layer 204B is removed by a selective etching process, which is adjusted to remove only the semiconductor layer 204B while the semiconductor layer 204A and the dummy pattern layer 206 remain substantially unchanged. In some embodiments, the step of selectively removing the semiconductor layer 204B may include an oxidation process (e.g., to form a structure including SiGeO). x The semiconductor layer 204B is then selectively oxidized and removed (e.g., removing SiGeO). x Selective etching can be selective wet etching, selective dry etching, or a combination of the foregoing. In some embodiments, the selective wet etching process may include hydrofluoric acid (HF) or NH4OH etchant.

[0038] Please refer to Figure 1 , Figures 12A-12C to Figures 15A-15C In operation 145, metal gates 280A and 280B are formed in trench 220. Metal gates 280A and 280B are configured to include the same or different layers and / or materials, such that metal gates 280A and 280B can achieve the desired functionality according to the design of semiconductor device 200. In the illustrated embodiment, metal gate 280A is formed in p-type doped region 202A, and metal gate 280B is formed in n-type doped region 202B. The threshold voltage (Vt) of the p-type field-effect transistor in p-type doped region 202A is different from the threshold voltage of the n-type device in n-type doped region 202B; therefore, metal gate 280A is configured differently from metal gate 280B. For example, the number, material, and / or thickness of the layers in metal gate 280A may differ from the number, material, and / or thickness of the layers in metal gate 280B. In these embodiments, metal gates 280A and 280B may share one or more layers, such that some layers may extend continuously from metal gate 280A to metal gate 280B. In some embodiments, the one or more layers shared by metal gates 280A and 280B may be configured to achieve different characteristics.

[0039] First, please refer to Figures 12A-12C Each metal gate 280A and 280B includes a gate dielectric layer 282 surrounding each suspended semiconductor layer 204A and dummy pattern layer 206, a barrier layer 284 disposed above the gate dielectric layer 282, and a first work function metal (WFM) layer 286 disposed above the barrier layer 284. Figure 12B As shown, each first work function metal layer 286 surrounds the barrier layer 284, further surrounds the gate dielectric layer 282, and further surrounds the semiconductor layer 204A and the dummy pattern layer 206. The following... Figures 13A-13C to Figures 15A-15C This section will introduce some other layers / structures of metal gates 280A and 280B, enabling different metal gate configurations to provide different work functions and different threshold voltages (for example, the threshold voltage of a p-type field-effect transistor in p-type doped region 202A differs from the threshold voltage of an n-type field-effect transistor in n-type doped region 202B). Figure 12B and 12CAs shown, a gate dielectric layer 282 is compliantly deposited in trench 220 and surrounds the suspended semiconductor layer 204A and dummy pattern layer 206 of fin 204. In some embodiments, the thickness of the gate dielectric layer 282 is from about half a nanometer to several nanometers. In some embodiments, the thickness of the gate dielectric layer 282 of metal gate 280A is substantially the same as the thickness of the gate dielectric layer 282 of metal gate 280B. In some other embodiments, the thickness of the gate dielectric layer 282 of metal gate 280A is different from the thickness of the gate dielectric layer 282 of metal gate 280B. The gate dielectric layer 282 includes a dielectric material, such as silicon oxide, a high dielectric constant dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 282 includes one or more high dielectric constant dielectric layers, which include, for example, hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable components, or combinations thereof. In some embodiments, the one or more high-dielectric-constant dielectric layers include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, other suitable high-dielectric-constant dielectric materials, or combinations thereof. In some embodiments, the high-dielectric-constant dielectric material has a dielectric constant greater than or equal to about 5 (k≥5). In some embodiments, the gate dielectric layer 282 further includes an interface layer (including a dielectric material, such as silicon oxide) disposed between the high-dielectric-constant dielectric layer and the semiconductor layer 204A. In some embodiments, the gate dielectric layer 282 includes a nitrogen-doped oxygen-containing dielectric layer and a high-dielectric-constant dielectric layer disposed above the nitrogen-doped oxygen-containing dielectric layer. In some embodiments, the gate dielectric layer 282 is configured to adjust the work function of the p-type field-effect transistor in the p-type doped region 202A and the n-type field-effect transistor in the n-type doped region 202B according to the design requirements of the semiconductor device 200. The gate dielectric layer 282 is formed by various processes, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, other suitable processes, or combinations thereof.

[0040] Subsequently, a barrier layer 284 is compliantly deposited over the gate dielectric layer 282 in the trench 220 and surrounds the suspended semiconductor layer 204A and dummy pattern layer 206 of the fin 204. The barrier layer 284 may include materials that promote adhesion between adjacent layers and / or block and / or reduce diffusion between adjacent gate layers, such as gate dielectric layers and work function layers. In some embodiments, the barrier layer 284 includes a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals, or combinations thereof), a metal oxide, a metal nitride (e.g., TiN), or a combination thereof. In some embodiments, the barrier layer 284 may include a work function metal material. The barrier layer 284 is formed by various deposition processes, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, other suitable processes, or combinations thereof.

[0041] Subsequently, a first work function metal layer 286 is compliantly deposited over the barrier layer 284 and the gate dielectric layer 282 in the trench 220, and surrounds the suspended semiconductor layer 204A and the dummy pattern layer 206 of the fin 204. The first work function metal layer 286 may include a conductive material adjusted to have a desired work function (e.g., n-type work function or p-type work function), such as an n-type work function material and / or a p-type work function material. p-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials, or combinations thereof. n-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof. The first work function metal layer 286 is formed by various deposition processes, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, other suitable processes, or combinations thereof.

[0042] Please refer to Figures 13A-13CIn operation 145, the first work function metal layer 286 of a type of metal gate (e.g., an n-type metal gate 280B) is removed by a multi-critical voltage (multi-Vt) work function metal patterning process. In the illustrated embodiment, the first work function metal layer 286 of the n-type metal gate 280B used to form the n-type field-effect transistor in the n-type doped region 202B is removed by an N / P patterning process. For example, an N / P patterning process can be performed to protect the p-type field-effect transistor in the p-type doped region 202A with photoresist 1300. The photolithography process may include spin coating, soft baking, exposure, post-baking, development, cleaning, drying, and other suitable processes. Alternatively, N / P patterning may be performed by immersion lithography, electron beam lithography, or other suitable processes. Subsequently, the first work function metal layer 286 of the metal gate 280B used to form the n-type field-effect transistor in the n-type doped region 202B may be removed by dry etching, wet etching, or a combination of dry etching and wet etching processes. Next, after removing the first work function metal layer 286 of the metal gate 280B, the photoresist 1300 is removed. The first work function metal layer 286 of the metal gate 280A used to form the p-type field-effect transistor in the p-type doped region 202A is retained.

[0043] Removal of the first work function metal layer 286 of the metal gate 280B (e.g., in a multi-critical voltage work function metal patterning process) also removes or damages a portion of the underlying layer (e.g., a portion of the barrier layer 284 and / or the gate dielectric layer 282) above the dummy patterned layer 206 in the n-type doped region 202B. Figure 13B As shown, a portion of the barrier layer 284 and gate dielectric layer 282 above the dummy pattern layer 206 is removed, with the remaining portions of the barrier layer 284 and gate dielectric layer 282 only surrounding (contacting) the side and bottom surfaces of the dummy pattern layer 206. In some other embodiments, the portion of the barrier layer 284 above the dummy pattern layer 206 is removed, while the portion of the gate dielectric layer 282 above the dummy pattern layer 206 is retained. Thus, the gate dielectric layer 282 covers the top surface of the dummy pattern layer 206, and the barrier layer 284 and gate dielectric layer 282 surround (cover) the side and bottom surfaces of the dummy pattern layer 206. In some other embodiments, after the work function metal patterning process, the portions of the barrier layer 284 and gate dielectric layer 282 above the dummy pattern layer 206 are retained (although a portion of the barrier layer above the dummy pattern layer 206 may be slightly removed), so that both the gate dielectric layer 282 and the barrier layer 284 surround the dummy pattern layer 206.

[0044] Damage to the barrier layer and / or gate dielectric layer does not adversely affect the manufacturing process described in this embodiment of the invention as in conventional manufacturing processes. In conventional manufacturing processes, the top layer of fin 204 is a top channel semiconductor layer (e.g., top channel layer 204A comprises Si). In this case, the work function metal patterning process can cause damage or disappearance of the top of the gate dielectric layer and / or barrier layer surrounding the top channel semiconductor layer, thereby affecting the critical voltage consistency of the semiconductor device. However, in this embodiment of the invention, the top layer of fin 204 is a dummy patterned layer 206. The dummy patterned layer 206 protects the top channel semiconductor layer 204A during the work function metal patterning process. Therefore, although the work function metal patterning process can remove / damage the gate dielectric layer 282 and barrier layer 284 above the dummy patterned layer 206, the gate dielectric layer 282 and barrier layer 284 surrounding the top channel semiconductor layer 204A are protected and remain unchanged (undamaged or disappeared). In addition, a dummy pattern layer 206 is formed above the top channel semiconductor layer 204A, which can reduce the capacitance between the metal gate and the source / drain junction (formed later).

[0045] Please refer to Figures 14A-14C A second work function metal layer 288 is compliantly deposited over the semiconductor device 200, particularly over the barrier layer 284 and gate dielectric layer 282 of the metal gate 280B, and over the first work function metal layer 286, barrier layer 284, and gate dielectric layer 282 of the metal gate 280A. The second work function metal layer 288 surrounds the suspended semiconductor layer 204A and dummy pattern layer 206 of the fin 204. The second work function metal layers 288 are not connected to each other, and various gaps are formed between the second work function metal layers 288 surrounding each semiconductor layer 204A and dummy pattern layer 206. The second work function metal layer 288 may include a conductive material adjusted to have a desired work function (e.g., n-type work function or p-type work function), such as an n-type work function material and / or a p-type work function material similar to the first work function metal layer 286. However, the work function material of the second work function metal layer 288 differs from the work function material of the first work function metal layer 286. The second work function metal layer 288 is formed by various processes, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition and / or other suitable processes, such as the processes described in the embodiments of the present invention.

[0046] Please refer to Figures 15A-15CA metal filler layer 290 is formed above the channel region 204C of the fin 204 and fills the gaps formed between the second work function metal layers 288. The metal filler layer 290 may include a suitable conductive material, such as aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), other suitable conductive materials, or combinations thereof. The metal filler layer 290 is formed by various deposition processes, such as atomic layer deposition, chemical vapor deposition, physical vapor deposition, and / or other suitable processes, such as those described in the embodiments of the present invention.

[0047] In conventional manufacturing processes, without the protection of a dummy pattern layer above the channel semiconductor layer, the layer configuration above the top channel semiconductor layer (e.g., layer type, number of layers, layer material, layer thickness, etc., including barrier layers, work function metal layers, or other gate layers) differs from the layer configuration between adjacent channel semiconductor layers, which can lead to inconsistent critical voltages in the semiconductor device. However, as Figure 15B As shown, with the protection of the dummy pattern layer 206, the metal gate layer configuration (e.g., distance MG) between adjacent channel semiconductor layers 204A is the same as the metal gate layer configuration (e.g., distance MG) between the top channel semiconductor layer 204 and the dummy pattern layer 206. Therefore, the consistency of the critical voltage of various types of field-effect transistors is improved. Furthermore, as described above, the capacitance between the metal gate and the source / drain junction can be reduced.

[0048] Metal gates 280A and 280B may include other material layers, such as adhesive layers, hard mask layers, and / or capping layers. The various layers of metal gates 280A and 280B can be formed by any suitable method, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, plating, chemical oxidation, thermal oxidation, other suitable methods, or combinations thereof. A chemical mechanical polishing process can be performed to remove any excess material from metal gates 280A and 280B to planarize the top surface of the semiconductor device 200.

[0049] Please refer to Figure 1 and Figures 16A-16C In operation 150, method 100 performs further processing to complete the fabrication of semiconductor device 200. For example, various contacts / vias (e.g., source / drain vias 296 and gate vias 298), wires, and multilayer interconnect components (e.g., metal layers, other etch stop layers (e.g., etch stop layer 260'), other interlayer dielectric layers (e.g., interlayer dielectric layer 270')) may be formed over substrate 202. These components are configured to connect various components to form a functional circuit that may include one or more multi-gate devices.

[0050] While not intended to be limiting, one or more embodiments of the present invention can provide numerous advantages for semiconductor devices and their fabrication processes. For example, a semiconductor device according to an embodiment of the present invention includes a dielectric dummy pattern layer above a semiconductor layer suspended in a channel region of the semiconductor device. The dummy pattern layer can protect the top semiconductor layer from damage (thinning) during the formation of the dummy gate structure. The dummy pattern layer also prevents the gate dielectric layer, barrier layer, and other layers surrounding the top channel layer from being removed / damaged during multi-critical voltage work function metal patterning processes. Furthermore, having a dummy pattern layer can reduce the capacitance between the metal gate and the source / drain junction.

[0051] This disclosure provides numerous different embodiments. Embodiments of the invention disclose a semiconductor device having a dummy patterned layer disposed above a top semiconductor channel layer and a method for forming the same. An exemplary semiconductor device includes a nanostructure disposed above a substrate, wherein the nanostructure includes a plurality of semiconductor layers perpendicularly spaced from each other and a dummy patterned layer disposed above and perpendicularly spaced from a top semiconductor layer of the plurality of semiconductor layers, the dummy patterned layer comprising a dielectric material. An exemplary semiconductor device also includes a gate structure disposed above a channel region, wherein the gate structure surrounds each of the plurality of semiconductor layers of the nanostructure and the dummy patterned layer.

[0052] In some embodiments, the gate structure of an exemplary semiconductor device includes a dielectric layer surrounding each of a plurality of semiconductor layers and contacting at least one bottom surface of a dummy patterned layer of a nanostructure; a first work function metal (WFM) layer surrounding the dielectric layer, each of the plurality of semiconductor layers of the nanostructure, and the dummy patterned layer; and a metal fill layer surrounding the first work function metal layer. The gate structure may also include a second work function metal (WFM) layer disposed between the first work function metal layer and the dielectric layer. In some embodiments, the dielectric layer surrounds the entire surface of the dummy patterned layer. In some other embodiments, the dielectric layer does not cover the top surface of the dummy patterned layer. The thicknesses of the dielectric layer, work function metal layer, and metal fill layer between the dummy patterned layer and the top semiconductor layer are respectively equal to the thicknesses of the dielectric layer, work function metal layer, and metal fill layer between the top semiconductor layer and the next semiconductor layer below the top semiconductor layer of the plurality of semiconductor layers. In some embodiments, the thickness of the dummy patterned layer is about 30% to about 100% of the thickness of the top semiconductor layer of the plurality of semiconductor layers of the nanostructure.

[0053] Another exemplary semiconductor device includes a first nanostructure disposed over a substrate in a first type of device region, wherein the first nanostructure includes a first semiconductor layer and a first dielectric pattern layer disposed over and perpendicularly spaced from the first semiconductor layer; and a second nanostructure disposed over a substrate in a second type of device region, wherein the second nanostructure includes a second semiconductor layer and a second dielectric pattern layer disposed over and perpendicularly spaced from the second semiconductor layer. This exemplary semiconductor device further includes a gate structure disposed over a channel region of the first and second nanostructures, wherein the gate structure surrounds the first semiconductor layer and the first dielectric pattern layer of the first nanostructure, and the second semiconductor layer and the second dielectric pattern layer of the second nanostructure.

[0054] In some embodiments, the materials of the first dielectric patterned layer and the second dielectric patterned layer are selected from SiN, SiCN, SiOC, SiOCN, HfO, LaO, AlO, or combinations thereof. In some embodiments, the gate structure includes a gate dielectric layer surrounding a first semiconductor layer and a first dielectric patterned layer of a first nanostructure; a first work function metal (WFM) layer surrounding the gate dielectric layer; a second work function metal layer surrounding the first work function metal layer; and a metal-filled layer surrounding the second work function metal layer. In some other embodiments, the gate dielectric layer also surrounds a second semiconductor layer of a second nanostructure and contacts the bottom surface of the second dielectric patterned layer of the second nanostructure, but not the top surface; the second work function metal layer surrounds the gate dielectric layer and the second semiconductor layer and the second dielectric patterned layer of the second nanostructure. In some embodiments, the gate structure further includes a gate spacer disposed along the sidewall of the gate dielectric layer, and a portion of the first dielectric patterned layer and a portion of the second dielectric patterned layer are below the gate spacer.

[0055] An exemplary method of forming a semiconductor device includes forming a fin over a substrate, the fin comprising a semiconductor layer stack and a dummy pattern layer, wherein the semiconductor layer stack includes a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the dummy pattern layer comprising a dielectric material and disposed above the top layer of the semiconductor layer stack. The method also includes forming a dummy gate structure over a channel region of the fin and across a source / drain region of the fin, wherein the dummy gate structure surrounds the fin comprising the dummy pattern layer and the semiconductor layer stack in the channel region; and replacing the dummy gate structure with a metal gate structure.

[0056] In some embodiments, the step of replacing the dummy gate structure with a metal gate structure includes removing the dummy gate structure to expose a dummy patterned layer and a first semiconductor layer and a second semiconductor layer in the channel region; selectively removing the second semiconductor layer such that the first semiconductor layer and the dummy patterned layer are suspended in the channel region; and depositing a metal gate stack to surround the suspended first semiconductor layer and dummy patterned layer. In some embodiments, the step of removing the dummy gate structure also removes the top of the dummy patterned layer. In some embodiments, the step of depositing the metal gate stack includes depositing a dielectric layer around the suspended first semiconductor layer and dummy patterned layer; and depositing a conductive metal layer over the dielectric layer such that the conductive metal layer surrounds the dielectric layer, the first semiconductor layer, and the dummy patterned layer. In some embodiments, the step of depositing the conductive metal layer includes depositing a first work function metal (WFM) layer over the dielectric layer such that the first work function metal layer surrounds the dielectric layer. In some other embodiments, the step of depositing the conductive metal layer further includes depositing a second work function metal layer over the first work function metal layer; and depositing a metal fill layer over the second work function metal layer. In some other embodiments, the step of depositing the conductive metal layer further includes removing the first work function metal layer; depositing a second work function metal layer over the dielectric layer; and depositing a metal fill layer over the second work function metal layer. In some embodiments, the step of removing the first work function metal layer also removes a portion of the dielectric layer over the dummy pattern layer.

[0057] The foregoing outlines the features of numerous embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various perspectives. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: A nanostructure disposed on a substrate, wherein the nanostructure includes a plurality of semiconductor layers perpendicularly spaced from each other and a dummy pattern layer disposed above and perpendicularly spaced from a top semiconductor layer of the plurality of semiconductor layers, the dummy pattern layer including a dielectric material; and A gate structure is disposed above a channel region, wherein the gate structure surrounds each of the plurality of semiconductor layers of the nanostructure and the dummy pattern layer.

2. The semiconductor device as claimed in claim 1, wherein, The gate structure includes: Multiple gate dielectric layers surround each of the multiple semiconductor layers and contact at least one bottom surface of the dummy pattern layer of the nanostructure; Multiple first work function metal layers surround each of the multiple gate dielectric layers, each of the multiple semiconductor layers of the nanostructure, and the dummy pattern layer; and A metal filler layer surrounds the plurality of first work function metal layers.

3. The semiconductor device as claimed in claim 2, wherein, The gate structure also includes: Multiple second work function metal layers are disposed between the multiple first work function metal layers and the multiple gate dielectric layers.

4. The semiconductor device as claimed in claim 2, wherein, The multiple gate dielectric layers surround the entire surface of the dummy pattern layer.

5. The semiconductor device as claimed in claim 2, wherein, The multiple gate dielectric layers do not cover the top surface of the dummy pattern layer.

6. The semiconductor device of claim 3, wherein, The thicknesses of the plurality of gate dielectric layers, the plurality of first work function metal layers, the plurality of second work function metal layers, and the metal fill layer between the dummy pattern layer and the top semiconductor layer are respectively the same as the thicknesses of the plurality of gate dielectric layers, the plurality of first work function metal layers, the plurality of second work function metal layers, and the metal fill layer between the top semiconductor layer and the next semiconductor layer below the top semiconductor layer of the plurality of semiconductor layers.

7. The semiconductor device of claim 1, wherein, The thickness of the dummy pattern layer is in the range of approximately 30% to approximately 100% of the thickness of the top semiconductor layer of the plurality of semiconductor layers of the nanostructure.

8. A semiconductor device, comprising: A first nanostructure is disposed above a substrate in a first type of device region, wherein the first nanostructure includes a first semiconductor layer and a first dielectric pattern layer disposed above the first semiconductor layer and vertically spaced from the first semiconductor layer, wherein the first dielectric pattern layer is disposed at a higher horizontal height than any semiconductor layer of the first nanostructure. A second nanostructure is disposed above the substrate of a second type of device region, wherein the second nanostructure includes a second semiconductor layer and a second dielectric pattern layer disposed above and perpendicularly spaced from the second semiconductor layer; and A gate structure is disposed above a plurality of channel regions of the first nanostructure and the second nanostructure, wherein the gate structure surrounds the first semiconductor layer and the first dielectric pattern layer of the first nanostructure and the second semiconductor layer and the second dielectric pattern layer of the second nanostructure.

9. The semiconductor device of claim 8, wherein, The materials of the first dielectric pattern layer and the second dielectric pattern layer are selected from SiN, SiCN, SiOC, SiOCN, HfO, LaO, AlO, or combinations thereof.

10. The semiconductor device of claim 8, wherein, The gate structure includes: A gate dielectric layer surrounds the first semiconductor layer and the first dielectric pattern layer of the first nanostructure; A first work function metal layer surrounds the gate dielectric layer; A second work function metal layer, surrounding the first work function metal layer; and A metal-filled layer surrounds the second work function metal layer.

11. The semiconductor device of claim 10, wherein: The gate dielectric layer surrounds the second semiconductor layer of the second nanostructure and contacts the bottom surface of the second dielectric pattern layer of the second nanostructure, but not the top surface. The second work function metal layer surrounds the gate dielectric layer, the second semiconductor layer of the second nanostructure, and the second dielectric pattern layer.

12. The semiconductor device of claim 10, wherein, The gate structure also includes a gate gap wall disposed along the sidewall of the gate dielectric layer, and a portion of the first dielectric pattern layer and a portion of the second dielectric pattern layer are below the gate gap wall.

13. A semiconductor device, comprising: A first stack of a plurality of first semiconductor layers is disposed on a substrate, wherein the first stack of the plurality of first semiconductor layers is spaced apart from each other; A second stack of multiple second semiconductor layers is disposed on the substrate, wherein the second stack of the multiple second semiconductor layers is spaced apart from each other; A first dielectric pattern layer is disposed directly above the topmost first semiconductor layer of the first stack of the plurality of first semiconductor layers; A first gate dielectric layer is disposed on the sidewalls and directly above the bottom surface of the first dielectric pattern layer; and A first gate electrode is disposed directly above the top surface of the first dielectric pattern layer.

14. The semiconductor device of claim 13, wherein the first gate electrode includes a work function material layer.

15. The semiconductor device of claim 13, wherein the first gate dielectric layer comprises an interface layer and a high dielectric constant dielectric layer.

16. The semiconductor device of claim 13, further comprising: A second dielectric pattern layer is disposed directly above the topmost second semiconductor layer of the second stack of the plurality of second semiconductor layers; A second gate dielectric layer is disposed on the sidewalls and directly above the bottom surface of the second dielectric pattern layer; and A second gate electrode is disposed around the second gate dielectric layer, such that the second gate electrode is prevented from being connected to the second dielectric pattern layer through the second gate dielectric layer.

17. The semiconductor device of claim 13, wherein, The first gate dielectric layer is in contact with the top surface of the first dielectric pattern layer.

18. The semiconductor device of claim 13, further comprising a dielectric sidewall spacer disposed along the first gate electrode such that the dielectric sidewall spacer is in contact with the first dielectric pattern layer.

19. The semiconductor device of claim 13, wherein, The first gate electrode extends between the topmost first semiconductor layer of the first stack of the plurality of first semiconductor layers and another first semiconductor layer of the first stack of the plurality of first semiconductor layers.

20. The semiconductor device of claim 13, further comprising a source / drain component disposed on the substrate, wherein the first dielectric pattern layer is connected to the source / drain component.

21. A method for forming a semiconductor device, comprising: A fin is formed on a substrate. The fin includes a semiconductor layer stack and a dummy pattern layer. The semiconductor layer stack includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer include different semiconductor materials. The dummy pattern layer includes a dielectric material and is disposed on a top layer of the semiconductor layer stack. A dummy gate structure is formed above a channel region of the fin and across a source / drain region of the fin, wherein the dummy gate structure surrounds the fin, including the dummy pattern layer and the semiconductor layer stack, within the channel region; and The dummy gate structure is replaced with a metal gate structure.

22. The method of forming a semiconductor device as claimed in claim 21, wherein, The steps of replacing the dummy gate structure with the metal gate structure include: Remove the dummy gate structure to expose the dummy pattern layer, the first semiconductor layer, and the second semiconductor layer in the channel region; Selectively remove the second semiconductor layer, such that the first semiconductor layer and the dummy pattern layer are suspended in the channel region; and The metal gate stack is deposited to surround the suspended first semiconductor layer and the dummy pattern layer.

23. The method of forming a semiconductor device as claimed in claim 22, wherein, The step of removing the dummy gate structure also removes one top of the dummy pattern layer.

24. The method of forming a semiconductor device as claimed in claim 22, wherein, The steps for depositing this metal gate structure include: Deposit a dielectric layer surrounding the suspended first semiconductor layer and the dummy pattern layer; and A conductive metal layer is deposited above the dielectric layer, such that the conductive metal layer surrounds the dielectric layer, the first semiconductor layer, and the dummy pattern layer.

25. The method of forming a semiconductor device as claimed in claim 24, wherein, The steps for depositing the conductive metal layer include: A first work function metal layer is deposited above the dielectric layer, such that the first work function metal layer surrounds the dielectric layer.

26. The method of forming a semiconductor device as claimed in claim 25, wherein, The step of depositing the conductive metal layer further includes: A second work function metal layer is deposited above the first work function metal layer; and A metal filler layer is deposited on top of the second work function metal layer.

27. The method for forming a semiconductor device as claimed in claim 25, wherein the step of depositing the conductive metal layer further comprises: Remove the metal layer with the first work function; A second work function metal layer is deposited above the dielectric layer; as well as A metal filler layer is deposited on top of the second work function metal layer.

28. The method of forming a semiconductor device as claimed in claim 27, wherein, The step of removing the first work function metal layer also removes a portion of the dielectric layer above the dummy pattern layer.

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