Static random access memory cell

Abstract

The present disclosure provides static random access memory (SRAM) cells and memory structures. An SRAM cell according to the present disclosure includes a first pull-up gate all around (GAA) transistor and a first pull-down GAA transistor coupled together to form a first inverter, a second pull-up GAA transistor and a second pull-down GAA transistor coupled together to form a second inverter, a first pass gate GAA transistor coupled to an output of the first inverter and an input of the second inverter, a second pass gate GAA transistor coupled to an output of the second inverter and an input of the first inverter, a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor, and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

Description

Technical Field

[0001] This disclosure relates to memory devices, and more particularly to memory devices having SRAM cells. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuitry than the previous generation. In the development of ICs, functional density (e.g., the number of interconnects per unit chip area) typically increases, while geometric dimensions (e.g., the smallest components (or lines) that can be produced using manufacturing processes) shrink. This miniaturization process usually provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of IC processes and manufacturing.

[0003] For example, as integrated circuit (IC) technology has evolved towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating the short-channel effect (SCE). Multi-gate devices typically refer to devices where the gate structure, or a portion thereof, is located on more than one side of the channel region. Fin-like field-effect transistors (FinFETs) and gate-all-around transistors (GAAs) (both also known as non-planar transistors) are examples of multi-gate devices and have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have an elevated channel with gates surrounding more than one side of the channel (for example, the top and sidewalls of a semiconductor material "fin" extending from the substrate are surrounded by gates). Compared to planar transistors, this configuration provides better control over the channel and significantly reduces SCE (specifically, by reducing subcritical leakage current (i.e., the coupling between the source and drain of a FinFET in the "off" state)). The gate structure of a GAA transistor can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. In some embodiments, such a channel region comprises multiple vertically stacked nanostructures (extending horizontally, thus providing a horizontally oriented channel). Such a GAA transistor may be referred to as a vertically stacked horizontal GAA (VGAA) transistor.

[0004] Static random access memory (SRAM) cells have become popular storage units in high-speed communications, high-density storage, image processing, and system-on-chip (SoC) products. While existing SRAM cells are generally sufficient for their intended purpose, they are not entirely satisfactory in every aspect. Summary of the Invention

[0005] This disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a first pull-up gate full-loop (GAA) transistor and a first pull-down GAA transistor coupled together to form a first inverter; a second pull-up GAA transistor and a second pull-down GAA transistor coupled together to form a second inverter; a first transmission gate GAA transistor coupled to the output of the first inverter and the input of the second inverter; a second transmission gate GAA transistor coupled to the output of the second inverter and the input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor; and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

[0006] This disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a first fin-shaped vertical stack located on a first p-type well, a second fin-shaped vertical stack located on an n-type well adjacent to the first p-type well, a third fin-shaped vertical stack located on an n-type well, a fourth fin-shaped vertical stack located on a second p-type well adjacent to the n-type well, a first dielectric fin located between the first and second fin-shaped vertical stacks, a second dielectric fin located between the second and third fin-shaped vertical stacks, and a third dielectric fin located between the third and fourth fin-shaped vertical stacks.

[0007] This disclosure provides a memory structure. The memory structure includes a first SRAM cell comprising a plurality of first gate-all-around (GAA) transistors, a second SRAM cell comprising a plurality of second GAA transistors, and dielectric fins located between the first SRAM cell and the second SRAM cell. In this embodiment, the first SRAM cell is a mirror image of the second SRAM cell partitioned by the dielectric fins. Attached Figure Description

[0008] The embodiments of this disclosure will be better understood from the following embodiments and the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of illustration. It should also be emphasized that the accompanying drawings only illustrate typical embodiments of the invention and should not be considered as limiting the scope, as the invention can also be applied to other embodiments.

[0009] Figure 1 This shows a circuit diagram of an SRAM cell.

[0010] Figure 2 This is a layout of SRAM cells according to some embodiments of the present disclosure.

[0011] Figure 3As shown in some embodiments of this disclosure, Figure 2 The layout is along the cross-sectional view of line segment A-A'.

[0012] Figure 4 As shown in some embodiments of this disclosure, Figure 2 The layout is along the cross-sectional view of line segment B-B'.

[0013] Figure 5 As shown in some embodiments of this disclosure, Figure 2 The layout is along the cross-sectional view of line segment C-C'.

[0014] Figure 6 As shown in some embodiments of this disclosure, Figure 2 The layout is along the cross-sectional view of line segment D-D'.

[0015] Figures 7A to 7C This is a schematic cross-sectional view of a dielectric fin as shown in some embodiments of the present disclosure.

[0016] Figure 8 This is a simplified partial layout of SRAM macrocode as shown in some embodiments of this disclosure.

[0017] Explanation of reference numerals in the attached figures:

[0018] 100: SRAM cell

[0019] 102: First transmission gate transistor

[0020] 104: Second transfer gate transistor

[0021] 106: First pull-up transistor

[0022] 108: Second pull-up transistor

[0023] 110: First pull-down transistor

[0024] 112: Second pull-down transistor

[0025] 114: First storage node

[0026] 116: Second storage node

[0027] 118: First inverter

[0028] 120: Second inverter

[0029] BL: Bitline

[0030] BLB: Bitline

[0031] WL: Character Line

[0032] CVdd: Voltage Bus

[0033] CVss: Grounding potential

[0034] 200: SRAM cell

[0035] 202: First transmission gate transistor

[0036] 204: Second transfer gate transistor

[0037] 206: First pull-up transistor

[0038] 208: Second pull-up transistor

[0039] 210: First pull-down transistor

[0040] 212: Second pull-down transistor

[0041] 222: First fin-shaped vertical stacking

[0042] 224: Second fin-shaped vertical stacking

[0043] 226: Third fin-shaped vertical stacking

[0044] 228: Fourth fin-shaped vertical stacking

[0045] 231: First dielectric fin

[0046] 232: Second dielectric fin

[0047] 233: Third dielectric fin

[0048] 234: Fourth dielectric fin

[0049] 235: Fifth dielectric fin

[0050] 2001: n-type well

[0051] 2002: P-type well

[0052] 2004: P-type well

[0053] 2010: First Interface

[0054] 2020: Second Interface

[0055] W1: First width

[0056] W2: Second width

[0057] AA',BB',CC',DD': line segments

[0058] 22: First fin structure

[0059] 24: Second fin structure

[0060] 26: Third fin structure

[0061] 28: Fourth fin structure

[0062] 201: Substrate

[0063] 203: Isolation Features

[0064] 242: First channel component

[0065] 244: Gate dielectric layer

[0066] 246: Second channel component

[0067] 231': Dielectric fin

[0068] 252: First gate cutoff dielectric characteristics

[0069] 254: Second gate cutoff dielectric characteristics

[0070] 256: Third gate cutoff dielectric characteristics

[0071] 262: First gate stack segment

[0072] 264: Second gate stack segment

[0073] 266: Third gate stack segment

[0074] T1: First thickness

[0075] T2: Second thickness

[0076] H1: First Height

[0077] H2: Second Altitude

[0078] 272: n-type epitaxial source / drain characteristics

[0079] 274: p-type epitaxial source / drain characteristics

[0080] 282: First source / drain contact

[0081] 284: Second source / drain contact

[0082] 280: Silicification layer

[0083] 290: Gate spacer

[0084] 292: Internal spacers

[0085] 286: Third source / drain contact

[0086] 288: Fourth source / drain contact

[0087] 300: Capping layer

[0088] 310: Dielectric layer

[0089] 32: First thin layer

[0090] 34: Second thin layer

[0091] 36: Capping layer

[0092] 230: Dielectric fins

[0093] 400: SRAM macro code

[0094] 200X: SRAM cell

[0095] 200Y: SRAM cell

[0096] 200XY: SRAM cell Detailed Implementation

[0097] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of the components and arrangements of this disclosure are described below for simplification. Naturally, these examples are not intended to limit this disclosure. For example, if the description states that a first feature is formed on or above a second feature, it may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition is for simplification and clarity and does not inherently define the relationships between the various embodiments and / or configurations discussed.

[0098] Furthermore, this disclosure may use spatial relative terms such as “below,” “below,” “lower than,” “above,” “higher than,” and similar words to describe the relationship between one element or feature and other elements or features in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are also intended to cover the different orientations of the device in use or operation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatial relative terms used herein will be interpreted accordingly.

[0099] Furthermore, when a number or range of numbers is described using terms such as "about," "approximately," or similar, the term is intended to encompass reasonable figures that include the stated number, such as + / - 10% of the stated number or other values ​​understood by one of skill in the art. For example, the term "about 5 nanometers (nm)" covers a size range from about 4.5 nm to about 5.5 nm.

[0100] This disclosure relates to memory devices, and more particularly to SRAM cells and memory structures. An SRAM cell and memory structure according to embodiments of this disclosure includes GAA transistors separated by dielectric fins. In one embodiment, the SRAM cell includes a first pass-gate GAA transistor and a first pull-down GAA transistor formed on a first fin-shaped vertical stack of a channel member, a first pull-up GAA transistor formed on a second fin-shaped vertical stack of the channel member, a second pull-up GAA transistor formed on a third fin-shaped vertical stack of the channel member, and a second pull-down GAA transistor and a second pass-gate GAA transistor formed on a fourth fin-shaped vertical stack of the channel member. The first, second, third, and fourth fin-shaped vertical stacks of the channel member are interposed by five dielectric fins. The epitaxial source / drain features of all GAA transistors in the SRAM cell are confined by the dielectric fins. In this respect, the epitaxial source / drain features of all GAA transistors in the SRAM can contact the dielectric fins. Although this disclosure is described with respect to embodiments in SRAM cells formed by GAA transistors, it should be understood that embodiments of this disclosure are applicable to a variety of semiconductor devices.

[0101] Static Random Access Memory (SRAM) is a type of volatile semiconductor memory that uses bistable latching circuitry to store each bit. Each bit in an SRAM is stored in four transistors (a first pull-up transistor (PU-1), a second pull-up transistor (PU-2), a first pull-down transistor (PD-1), and a second pull-down transistor (PD-2), forming two cross-coupled inverters. This memory cell has two stable states, used to represent 0 and 1. Two additional access transistors (a first transmission gate transistor (PG-1) and a second transmission gate transistor (PG-2)) are used to control access to the memory cell during read and write operations. A typical SRAM cell includes six transistors (6T) for storing each memory bit. Figure 1 This is a circuit diagram of SRAM cell 100 shown according to some embodiments of this disclosure. In some cases, Figure 1 The SRAM cell 100 includes six (6) transistors and may be referred to as a single-port SRAM cell 100 or a 6T SRAM cell 100. It should be noted that although embodiments of this disclosure are described in conjunction with a 6T SRAM cell, this disclosure is not limited thereto. This disclosure can be applied to SRAM cells including more transistors, such as 7T, 8T, 9T, or 10T, which may be single-port, dual-port, or multi-port.

[0102] SRAM cell 100 includes a first transfer gate transistor (PG-1) 102, a second transfer gate transistor (PG-2) 104, a first pull-up transistor (PU-1) 106, a second pull-up transistor (PU-2) 108, a first pull-down transistor (PD-1) 110, and a second pull-down transistor (PD-2) 112. In SRAM cell 100, each transfer gate transistor, pull-up transistor, and pull-down transistor may be a multi-gate transistor, such as a GAA transistor. The gates of the first transfer gate transistor 102 and the second transfer gate transistor 104 are electrically coupled to a word line (WL), which determines whether SRAM cell 100 is selected. In SRAM cell 100, memory bits (e.g., latches or flip-flops) are formed by the first and second pull-up transistors 106 and 108 and the first and second pull-down transistors 110 and 112 to store one bit of data. The complementary values ​​of the bits are stored in the first storage node 114 and the second storage node 116. The stored bits can be written to or read from the SRAM cell 100 via bit lines (BL) and bit lines (BLB). In this arrangement, bit lines BL and BLB can carry complementary bit line signals. The SRAM cell 100 is powered via a voltage bus CVdd, which has a positive power supply voltage, and the SRAM cell 100 is also connected to ground potential CVss.

[0103] SRAM cell 100 includes a first inverter 118 formed by a first pull-up transistor (PU-1) 106 and a first pull-down transistor (PD-1) 110, and a second inverter 120 formed by a second pull-up transistor (PU-2) 108 and a second pull-down transistor (PD-2) 112. The first inverter 118 and the second inverter 120 are coupled between a voltage bus CVdd and a ground potential CVss. Figure 1 As shown, the first inverter 118 and the second inverter 120 are cross-coupled. That is, the input of the first inverter 118 is coupled to the output of the second inverter 120. Similarly, the input of the second inverter 120 is coupled to the output of the first inverter 118. The output of the first inverter 118 is referred to as the first memory node 114. Similarly, the output of the second inverter 120 is referred to as the second memory node 116. In normal operating mode, the first memory node 114 is in the opposite logic state to the second memory node 116. By using two cross-coupled inverters, the SRAM cell 100 can use a latching structure to retain data, so that the stored data will not be lost as long as it is powered by Vdd without a refresh cycle.

[0104] In an SRAM array formed by multiple SRAM cells 100, the SRAM cells 100 are arranged in rows and columns. A row of the SRAM array is formed by bit line pairs, namely bit lines BL and BLB. Cells of the SRAM array are positioned between their respective bit line pairs. Figure 1 As shown, SRAM cell 100 is positioned between bit line BL and bit line BLB. Figure 1 As shown, the SRAM cell 100 also includes a first transfer gate transistor (PG-1) 102 connecting the bit line BL to the output 114 (also referred to as the first memory node 114) of the first inverter 118. The SRAM cell 100 also includes a second transfer gate transistor (PG-2) 104 connecting the bit line BLB to the output 116 (also referred to as the second memory node 116) of the second inverter 120. The gates of the first transfer gate transistor (PG-1) 102 and the second transfer gate transistor (PG-2) 104 are connected to the word line (WL), which is connected to a column of SRAM cells in the SRAM array.

[0105] In operation, if the first transfer gate transistor (PG-1) 102 and the second transfer gate transistor (PG-2) 104 are inactive, the SRAM cell 100 will maintain complementary values ​​at the first and second memory nodes 114 and 116 indefinitely while powered by the voltage bus CVdd. This is because each inverter in the pair of cross-coupled inverters drives the input of the other, thereby maintaining the voltages at the first and second memory nodes 114 and 116. This situation will remain stable until power is removed from the SRAM cell 100 or a write cycle is performed to change the data stored in the first and second memory nodes 114 and 116.

[0106] During a write operation, bit lines BL and BLB are set to opposite logic values ​​according to the new data to be written to SRAM cell 100. For example, in an SRAM write operation, the logic state "1" stored in the data latch of SRAM cell 100 can be reset by setting bit line BL to "0" and bit line BLB to "1". In response to the binary code from the column decoder (not shown), word lines coupled to the first and second transmission gate transistors (PG-1) 102 and (PG-2) 104 of SRAM cell 100 are asserted to select memory cells and turn on the first and second transmission gate transistors (PG-1) 102 and (PG-2) 104. In this way, the first memory node 114 and the second memory node 116 are connected to bit lines BL and BLB, respectively. Furthermore, the first storage node 114 of the data latch is discharged to "0" via bit line BL, while the second storage node 116 of the data latch is charged to "1" via bit line BLB. In this way, the new data logic "0" is latched into the SRAM cell 100.

[0107] During a read operation, the bit lines BL and BLB of SRAM cell 100 are precharged to a voltage approximately equal to the operating voltage of the memory bank where SRAM cell 100 is located. In response to the binary code from the column decoder, the word lines coupled to the first transmission gate transistor (PG-1) 102 and the second transmission gate transistor (PG-2) 104 of SRAM cell 100 are declared to select the data latch for a read operation.

[0108] During a read operation, a bit line coupled to the memory node storing logic "0" is discharged to a lower voltage via the turned-on first and second transmission gate transistors (PG-1) 102 and (PG-2) 104. Simultaneously, the other bit line retains its pre-charge voltage because there is no discharge path between the other bit line and the memory node storing logic "1". The differential voltage between bit line BL and bit line BLB is detected by a sense amplifier (not shown). Furthermore, the sense amplifier amplifies the differential voltage and reports the logic state of the memory cell via a data buffer.

[0109] Reference Figure 2 , Figure 2 The image below shows the layout of the SRAM cell 200 according to some embodiments of this disclosure. Figure 1Similar to the SRAM cell 100 shown in the circuit diagram, the SRAM cell 200 includes six (6) transistors, serving as a first transmission gate transistor 202, a second transmission gate transistor 204, a first pull-up transistor 206, a second pull-up transistor 208, a first pull-down transistor 210, and a second pull-down transistor 212. At least in some embodiments, Figure 1 The SRAM cell 100 in the middle can be implemented as Figure 2 SRAM cell 200 in the middle.

[0110] exist Figure 2 In some embodiments shown, SRAM cells 200 are formed on an n-type well 2001 (or n-type region 2001, N-well 2001) sandwiched between two p-type wells 2002 and 2004 (or p-type regions 2002 and 2004, P-wells 2002 and 2004). The N-well 2001 and the P-wells 2002 and 2004 are formed on a substrate (…). Figure 2 Not shown in China Figure 3 The image is shown on substrate 201. In some embodiments, such as Figure 2 As shown, the first transmission gate transistor 202, the first pull-down transistor 210, the second pull-down transistor 212, and the second transmission gate transistor 204 can be formed in P-wells 2002 and 2004, while the first pull-up transistor 206 and the second pull-up transistor 208 are formed in N-well 2001. In these embodiments, the first transmission gate transistor 202, the first pull-down transistor 210, the second pull-down transistor 212, and the second transmission gate transistor 204 are n-type GAA transistors, while the first pull-up transistor 206 and the second pull-up transistor 208 are p-type GAA transistors.

[0111] exist Figure 2 In some alternative embodiments not shown, the SRAM cell 200 is formed on a P-well sandwiched between two N-wells. In those embodiments, first and second transmission gate transistors and first and second pull-down transistors are formed in the N-wells, and first and second pull-up transistors are formed in the P-well between the two N-wells. In those embodiments, the first and second transmission gate transistors and first and second pull-down transistors are p-type GAA transistors, while the first and second pull-up transistors are n-type nanowire GAA transistors.

[0112] In some embodiments, the SRAM cell 200 includes four fin-shaped vertical stacks: a first fin-shaped vertical stack 222, a second fin-shaped vertical stack 224, a third fin-shaped vertical stack 226, and a fourth fin-shaped vertical stack 228. The first fin-shaped vertical stack 222 is formed on a P-well 2002 and forms the channel regions for the first transmission gate transistor 202 and the first pull-down transistor 210. The second fin-shaped vertical stack 224 and the third fin-shaped vertical stack 226 are formed on an N-well 2001 and form the channel regions for the first pull-up transistor 206 and the second pull-up transistor 208, respectively. The fourth fin-shaped vertical stack 228 is formed on a P-well 2004 and forms the channel regions for the second pull-down transistor 212 and the second transmission gate transistor 204. In some embodiments, each of the first fin-shaped vertical stack 222, the second fin-shaped vertical stack 224, the third fin-shaped vertical stack 226, and the fourth fin-shaped vertical stack 228 may include about two to about ten channel members.

[0113] In some cases, fin-like vertical stacks can be formed by depositing or epitaxially growing alternating layers of two different semiconductor materials, resolving the alternating layers to form a fin structure, and selectively removing thin layers formed from one of the two semiconductor materials. For example, alternating layers of silicon (Si) and silicon germanium (SiGe) can be epitaxially grown on a substrate. The alternating layers can then be resolved to form a fin structure comprising a stack of staggered Si strips and SiGe strips. In the process of forming the channel regions of transistors in an SRAM cell, depending on the conductivity type of the transistor, the channel regions of the fin structure can undergo different etching processes to selectively remove Si strips or SiGe strips, thereby releasing the Si channel components or SiGe channel components extending between the source / drain regions. The channel components can take different shapes and sizes and can be referred to as nanostructures, nanowires, or nanosheets. In some embodiments, the channel components can be in-situ doped during epitaxial growth or doped by implantation. These fin-like structures are separated by isolation features, such as shallow trench isolation (STI) features. In some embodiments, each fin-like vertical stack may include a top portion formed of alternating layers and a base portion formed of a substrate. The base portion of the fin-like vertical stack has a fin shape and may be referred to as a fin structure. The base portion of the fin-like vertical stack may be substantially embedded in the isolation feature, and the top end of the base portion of the fin-like vertical stack may be flush with the top surface of the isolation feature. The top portion of the fin-like vertical stack extends from the isolation feature and rises above the isolation feature.

[0114] exist Figure 2In some embodiments shown, the first fin vertical stack 222, the second fin vertical stack 224, the third fin vertical stack 226, and the fourth fin vertical stack 228 are interleaved with dielectric fins. In these embodiments, the first fin vertical stack 222 is disposed between the first dielectric fin 231 and the second dielectric fin 232, the second fin vertical stack 224 is disposed between the second dielectric fin 232 and the third dielectric fin 233, the third fin vertical stack 226 is disposed between the third dielectric fin 233 and the fourth dielectric fin 234, and the fourth fin vertical stack 228 is disposed between the fourth dielectric fin 234 and the fifth dielectric fin 235. The first dielectric fin 231 and the fifth dielectric fin 235 can be used as boundaries or ends of the SRAM cell 200. In other words, one side of the first dielectric fin 231 along the Y direction is adjacent to the SRAM cell 200, and the other side of the first dielectric fin 231 along the Y direction is adjacent to another SRAM cell adjacent to the SRAM cell 200. Similarly, one side of the fifth dielectric fin 235 along the Y direction is adjacent to the SRAM cell 200, and the other side of the fifth dielectric fin 235 along the Y direction is adjacent to another SRAM cell adjacent to the SRAM cell 200.

[0115] Still refer to Figure 2 The channel components in the first finned vertical stack 222 form the channel regions of the first transmission gate transistor (PG-1) 202 and the first pull-down transistor (PD-1) 210. The channel components in the second finned vertical stack 224 form the channel region of the first pull-up transistor (PU-1) 206. The channel components in the third finned vertical stack 226 form the channel region of the second pull-up transistor (PU-2) 208. The channel components in the fourth finned vertical stack 228 form the channel regions of the second pull-down transistor (PD-2) 212 and the second transmission gate transistor (PG-2) 204. Figure 2 In some embodiments shown, a second dielectric fin 232 is disposed between a first pull-down transistor (PD-1) 210 and a first pull-up transistor (PU-1) 206. P-well 2002 and N-well 2001 are bonded at a first interface 2010. The second dielectric fin 232 is disposed on the first interface 2010. Similarly, a fourth dielectric fin 234 is disposed between a second pull-up transistor (PU-2) 208 and a second pull-down transistor (PD-2) 212. P-well 2004 and N-well 2001 are bonded at a second interface 2020. The fourth dielectric fin 234 is disposed on the second interface 2020.

[0116] Still refer to Figure 2A first fin-shaped vertical stack 222 is disposed on P-well 2002. A second fin-shaped vertical stack 224 and a third fin-shaped vertical stack 226 are disposed on N-well 2001. A fourth fin-shaped vertical stack 228 is disposed on P-well 2004. Therefore, the first transmission gate transistor (PG-1) 202, the first pull-down transistor (PD-1) 210, the second transmission gate transistor (PG-2) 204, and the second pull-down transistor (PD-1) 212 can be n-type GAA transistors. The first pull-up transistor (PU-1) 206 and the second pull-up transistor (PU-2) 208 can be p-type GAA transistors. In some embodiments, the n-type GAA transistor requires a wider channel width than the p-type GAA transistor to increase the switching speed. In those embodiments, each of the first fin vertical stack 222 and the fourth fin vertical stack 228 has a first width W1 along the X direction, while each of the second fin vertical stack 224 and the third fin vertical stack 226 has a second width W2 along the X direction. In some cases, the ratio of the first width W1 to the second width W2 (W1 / W2) is between about 1 and about 5, including between about 1.1 and about 3.0. In some embodiments, the first width W1 and the second width W2 may be in the range of about 4 nm to about 60 nm.

[0117] Different cross-sectional views of the SRAM cell 200 are provided to show the structural details of the SRAM cell 200. For example, Figure 3 show Figure 2 A cross-sectional view of SRAM cell 200 along line segment A-A'. Figure 4 show Figure 2 A cross-sectional view of SRAM cell 200 along line segment B-B'. Figure 5 show Figure 2 A cross-sectional view of SRAM cell 200 along line segment C-C'. Figure 6 show Figure 2 A cross-sectional view of SRAM cell 200 along line segment D-D'.

[0118] Now refer to Figure 3 , Figure 3 show Figure 2 A cross-sectional view of SRAM cell 200 along line segment A-A'. Figure 2Line segment A-A' extends through the first dielectric fin 231, the channel region of the first pull-down transistor (PD-1) 210 (formed on the first fin vertical stack 222), the second dielectric fin 232, the first pull-up transistor (PU-1) 206, the third dielectric fin 233, the third fin vertical stack 226, the fourth dielectric fin 234, the second transmission gate transistor (PG-2) 204 (formed on the fourth fin vertical stack 228), and the fifth dielectric fin 235. (As shown) Figure 3 As shown, the first pull-down transistor (PD-1) 210 includes a first channel member 242 disposed on the first fin structure 22. The first pull-up transistor (PU-1) 206 includes a second channel member 246 disposed on the second fin structure 24. The third fin vertical stack 226 includes a second channel member 246 disposed on the third fin structure 26. The second transmission gate transistor (PG-2) 204 includes a second channel member 242 disposed on the fourth fin structure 28. The first channel member 242 is a channel member formed from the first fin vertical stack 222 on P-well 2002 and the fourth fin vertical stack 228 on P-well 2004. The first channel member 242 has a first width W1 and a first thickness T1. The second channel member 246 is a channel member formed from the second fin vertical stack 224 and the third fin vertical stack 226 on N-well 2001. The second channel member 246 has a second width W2 and a second thickness T2. In some cases, the ratio (W1 / W2) of the first width W1 to the second width W2 is between about 1 and about 5, including between about 1.1 and about 3.0. The first thickness T1 and the second thickness T2 are the same or substantially the same. In some embodiments, the first thickness T1 and the second thickness T2 may be in the range of about 3 nm to about 10 nm, and the first width W1 and the second width W2 may be in the range of about 6 nm to about 60 nm.

[0119] An isolation feature 203 is disposed between the first fin structure 22, the second fin structure 24, the third fin structure 26, and the fourth fin structure 28. The isolation feature 203 is disposed between adjacent fin structures. In some embodiments, the top surface of the isolation feature 203 is substantially flush with each of the first fin structure 22, the second fin structure 24, the third fin structure 26, and the fourth fin structure 28. The isolation feature 203 may be referred to as a shallow trench isolation (STI) feature 203 and may include silicon oxide. Figure 3Each dielectric fin shown, such as the first dielectric fin 231, the second dielectric fin 232, the third dielectric fin 233, the fourth dielectric fin 234, and the fifth dielectric fin 235, is partially embedded in the isolation feature 203. That is, each dielectric fin has a lower portion disposed or embedded in the isolation feature 203, and an upper portion rising above the top surface of the isolation feature 203. Each dielectric fin can have a single-layer structure or a multi-layer structure. Taking the third dielectric fin 233 as an example, in... Figure 7A , Figure 7B ,as well as Figure 7C Different embodiments of dielectric fins are shown in the figure. Figure 7A In some embodiments shown, the third dielectric fin 233 has a single-layer structure and may be formed of silicon oxycarbonate, silicon oxynitride, silicon carbonitride, silicon nitride, aluminum oxide, yttrium oxide, tantalum oxide, titanium oxide, hafnium oxide, or zirconium oxide. In some alternative embodiments, the third dielectric fin 233 has a multilayer structure. Figure 7B In the middle, the third dielectric fin 233 includes two thin layers: a first thin layer 32 and a second thin layer 34. Figure 7B In the illustrated embodiment, the second thin layer 34 is encapsulated by or disposed within the first thin layer 32. In some embodiments, the first thin layer 32 may be formed of silicon nitride, while the second thin layer 34 may be formed of a high-k dielectric material, such as aluminum oxide, yttrium oxide, tantalum oxide, titanium oxide, hafnium oxide, or zirconium oxide. As used herein, the high-k dielectric material has a dielectric constant greater than 3.9, where 3.9 is the dielectric constant of silicon oxide, while the low-k dielectric material has a dielectric constant equal to or less than 3.9. Figure 7C In some alternative embodiments shown, the third dielectric fin 233 may include a cap layer 36. The cap layer 36 may be formed of silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon carbide. It should be noted that in most embodiments, the dielectric fins are primarily formed of high-k dielectric materials because they tend to have lower etch rates. The third dielectric fin 233 is only used as… Figure 7A , Figure 7B ,as well as Figure 7C Examples are provided to illustrate the exemplary structure of the dielectric fins of this disclosure. This disclosure fully envisions... Figures 7A to 7C The embodiments described herein are implementations of other dielectric fins.

[0120] Regarding metal gate stacking Figure 2 Line segment A-A' passes through several gate stack segments. For example... Figure 3As shown, line segment A-A' passes through the first gate stack segment 262, the second gate stack segment 264, and the third gate stack segment 266. In some embodiments, the first gate stack segment 262, the second gate stack segment 264, and the third gate stack segment 266 have a uniform structure and composition, although these gate stack segments are disposed across both n-type and p-type GAA transistor regions. In these embodiments, each of the first gate stack segment 262, the second gate stack segment 264, and the third gate stack segment 266 includes a gate dielectric layer 244, a work function metal layer, and a fill metal layer. The work function metal layer and the fill metal layer may be collectively referred to as the gate electrode. The gate electrode may include materials selected from the following: titanium nitride, tantalum nitride, titanium aluminide, titanium aluminum nitride, tantalum aluminum nitride, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, aluminum, tungsten, copper, cobalt, nickel, platinum, or combinations thereof. The gate dielectric layer 244 may include an interface layer and at least one high-k dielectric layer. In some alternative embodiments, there are first gate stack segments 262 and 266, and second gate stack segment 264, which have different structures and compositions. In these alternative embodiments, the first gate stack segment 262 and 266, as gate stacks of an n-type GAA transistor, may have an n-type work function metal layer. Similarly, the second gate stack segment 264, as gate stacks of a p-type GAA transistor, may have a p-type work function metal layer. The formation of metal layers with different work functions may require multiple repetitions of material deposition and etching-back processes. In these alternative embodiments, dielectric fins can be used as lateral spacers and etch-stop features. They are used as lateral spacers when material is selectively deposited in the corresponding p-type or n-type device regions. They are used as lateral etch-stop features when etch-back is required. In some embodiments, different combinations of high-k dielectric layers can be implemented for the n-type and p-type device regions to introduce different threshold voltages. In those embodiments, dielectric fins can also be used as lateral spacers and etch-stop features for similar reasons.

[0121] In some embodiments, the gate stack segment may undergo a metal gate cut process, wherein a gate cutout is formed to distinguish the gate stack segment, and a reverse material is filled in the gate cutout to form a gate cutout dielectric feature (or gate end feature). Figure 3 The first gate-cut dielectric feature 252, the second gate-cut dielectric feature 254, and the third gate-cut dielectric feature 256 are shown. As described above, the first gate-cut dielectric feature 252, the second gate-cut dielectric feature 254, and the third gate-cut dielectric feature 256 are formed by a metal gate cutoff process and may be formed of a high-k dielectric material, such as silicon nitride, aluminum oxide, yttrium oxide, tantalum oxide, titanium oxide, hafnium oxide, or zirconium oxide. In some embodiments, the gate cutoff opening may overlap with the dielectric fin, such that the dielectric fin can be used as an etch stop layer for the metal gate cutoff process. In those embodiments, the gate-cut dielectric feature may overlap with the dielectric fin and may fall directly above the dielectric fin. For example, a first gate-cutoff dielectric feature 252 is disposed on a first dielectric fin 231, a second gate-cutoff dielectric feature 254 is disposed on a fourth dielectric fin 234, and a third gate-cutoff dielectric feature 256 is disposed on a dielectric fin 231' in an adjacent SRAM cell. Figure 3 In this configuration, a second dielectric fin 232 is disposed on a first interface 2010, while a fourth dielectric fin 234 is disposed on a second interface 2020. A second gate-cutoff dielectric feature 254 is disposed on the fourth dielectric fin 234, and therefore also on the second interface 2020. Because the gate-cutoff opening reduces the height of the dielectric fin, the dielectric fin can have a reduced height whenever a gate-cutoff dielectric feature is formed on it. For example, a third dielectric fin 233 has a first height H1, while a fourth dielectric fin 234 has a second height H2, which is smaller than the first height H1. In some cases, the difference between the first height H1 and the second height H2 can be between approximately 5 nm and approximately 15 nm.

[0122] A cross-sectional view along the line segment passing through the first dielectric fin 231, the first transmission gate transistor (PG-1) 202, the second dielectric fin 232, the second fin vertical stack 224, the third dielectric fin 233, the second pull-up transistor (PU-2) 208, the fourth dielectric fin 234, the second pull-down transistor (PD-2) 212, and the fifth dielectric fin 235 of the SRAM cell 200 is similar to the cross-sectional view along the line segment A-A', and will not be described again here.

[0123] Now refer to Figure 4 , Figure 4 show Figure 2The SRAM cell 200 is shown in a cross-sectional view along line segment B-B'. Line segment B-B' passes through dielectric fins 231-235 and the epitaxial source / drain features of the first pull-down transistor (PD-1) 210, the first pull-up transistor (PU-1) 206, the second pull-up transistor (PU-2) 208, and the second transmission gate transistor (PG-2) 204. These epitaxial source / drain features include n-type epitaxial source / drain features 272 and p-type epitaxial source / drain features 274, each of which is formed by a fin structure. The n-type epitaxial source / drain feature 272 may differ from the p-type epitaxial source / drain feature 274. In some cases, the former may comprise phosphorus-doped silicon or other suitable materials, while the latter may comprise boron-doped silicon germanium or other suitable materials. For example, the n-type epitaxial source / drain feature 272 is formed by a first fin structure 22 and a fourth fin structure 28. The p-type epitaxial source / drain feature 274 is formed by the second fin structure 24 and the third fin structure 26. Figure 4 In the illustrated embodiment, the first dielectric fin 231, the second dielectric fin 232, the third dielectric fin 233, and the fourth dielectric fin 234 are used to separate the epitaxial source / drain features and prevent them from contacting each other. That is, using the dielectric fins as boundaries to prevent bridging of adjacent epitaxial source / drain features allows the epitaxial source / drain features to grow to their maximum size until they contact and are confined by the dielectric fins. In some embodiments, each of the n-type epitaxial source / drain features 272 and the p-type epitaxial source / drain features 274 contacts an adjacent dielectric fin. For example, the n-type epitaxial source / drain feature 272 on the first fin structure 22 may directly contact the first dielectric fin 231 and the second dielectric fin 232. The same applies to other n-type epitaxial source / drain features 272 or p-type epitaxial source / drain features 274.

[0124] In some embodiments, the SRAM cell 200 may include a source / drain contact electrically coupled to more than one epitaxial source / drain feature. Figure 4In the illustrated embodiment, the SRAM cell 200 includes a first source / drain contact 282 and a second source / drain contact 284. The first source / drain contact 282 is electrically coupled to an n-type epitaxial source / drain feature 272 on a first fin structure 22 and a p-type epitaxial source / drain feature 274 on a second fin structure 24. The first source / drain contact 282 also spans over a second dielectric fin 232 and can directly contact the second dielectric fin 232. Similarly, the second source / drain contact 284 is electrically coupled to a p-type epitaxial source / drain feature 274 on a third fin structure 26 and an n-type epitaxial source / drain feature 272 on a fourth fin structure 28. The second source / drain contact 284 spans over a fourth dielectric fin 234 and can directly contact the fourth dielectric fin 234. According to this disclosure, source / drain contacts such as the first source / drain contact 282 and the second source / drain contact 284 may be formed of titanium, titanium nitride, cobalt, ruthenium, platinum, tungsten, aluminum, copper, or combinations thereof.

[0125] like Figure 5 As shown, line segment C-C' passes through the first pull-down transistor (PD-1) 210, the first transfer gate transistor (PG-1) 202, and their n-type epitaxial source / drain features 272. The first gate stack segment 262 may be padded on its sidewalls by gate spacers 290. The gate spacers 290 may be oxide, nitrogen-doped silicon oxide, porous oxide, or a combination thereof. Furthermore, in Figure 5 In some embodiments shown, the first gate stack segment 262 may be covered and protected by a capping layer 300. The material for the capping layer 300 may be selected from the group consisting of silicon oxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, aluminum oxide, yttrium oxide, other suitable nitride dielectrics, or other suitable metal oxides. The n-type epitaxial source / drain features 272 may be electrically coupled to source / drain contacts, including a third source / drain contact 286, a first source / drain contact 282, and a fourth source / drain contact 288. In some embodiments, the n-type epitaxial source / drain features 272 may be electrically coupled to the source / drain contacts via a silicide layer 280. In some embodiments, the source / drain contacts (third source / drain contact 286, first source / drain contact 282, and fourth source / drain contact 288) and the top surface of the capping layer 300 can be planarized, for example by etching, grinding, or chemical mechanical polishing (CMP). A dielectric layer 310 can be formed on the planarized source / drain contacts and the capping layer 300. Figure 5As shown, the first channel member 242 of the first pull-down transistor (PD-1) 210 and the first transmission gate transistor (PG-1) 202 is also coupled to the n-type epitaxial source / drain feature 272. In some embodiments, internal spacers 292 are partially formed in the space between adjacent first channel members 242 to reduce capacitance and prevent leakage.

[0126] Now refer to Figure 6 , Figure 6 show Figure 2 A cross-sectional view of SRAM cell 200 along line segment D-D'. (See diagram below.) Figure 6 As shown, line segment D-D' passes through the first pull-up transistor (PU-1) 206 and its p-type epitaxial source / drain features 274. The second gate stack segment 264 may be padded on its sidewalls by gate spacers 290. Furthermore, in Figure 6 In some embodiments shown, the second gate stack segment 264 may be covered and protected by a capping layer 300. p-type epitaxial source / drain features 274 may be electrically coupled to source / drain contacts, including a fifth source / drain contact 285 and a first source / drain contact 282. In some embodiments, the p-type epitaxial source / drain features 274 may be electrically coupled to the respective source / drain contacts via a silicide layer 280. In some embodiments, the source / drain contacts (the fifth source / drain contact 285 and the first source / drain contact 282) and the top surface of the capping layer 300 may be planarized, for example by etching, polishing, or chemical mechanical polishing (CMP). A dielectric layer 310 may be formed on the planarized source / drain contacts and the capping layer 300. Figure 6 As shown, the second channel member 246 of the first pull-up transistor (PU-1) 206 is also coupled to the p-type epitaxial source / drain feature 274. In some embodiments, internal spacers 292 are partially formed in the space between adjacent second channel members 246 to reduce capacitance and prevent leakage.

[0127] In some cases, multiple SRAM cells can be connected together to form an SRAM macro. For example, a 32x32 SRAM cell array can form a 1K-bit SRAM macro, while a 256x32 SRAM cell array can form an 8K-bit SRAM macro. When SRAM cells are arranged together to form an array, the SRAM cell layout can be flipped or rotated to achieve higher package density. Flipping and rotating allow adjacent SRAM cells to share common connections, common P-wells, or common N-wells. Now refer to Figure 8 . Figure 8 This displays a partially simplified layout of SRAM macrocode 400, which includes features similar to... Figure 2 SRAM cell 100 or Figures 3 to 6 SRAM cells 200. For ease of explanation, in Figure 8 Only four SRAM cells of SRAM macro code 400 are shown, and each of the four SRAM cells is in the same order as... Figures 3 to 6 The configuration / orientation of SRAM cell 200 is shown. Specifically, SRAM cell 200X is a mirror image of SRAM cell 200 opposite the X-axis, SRAM cell 200Y is a mirror image of SRAM cell 200 opposite the Y-axis, and SRAM cell 200XY is a mirror image of SRAM cell 200X opposite the Y-axis or a mirror image of SRAM cell 200Y opposite the X-axis. Most notably, because SRAM cell 200 and SRAM cell 200Y share dielectric fin 230, SRAM cell 200 is a mirror image of SRAM cell 200Y opposite the dielectric fin 230, and vice versa. The dielectric fin 230 has self-isolation features (and...). Figures 3 to 6 Similar to isolation feature 203 in the image, it extends and rises above the isolation feature, which is positioned between SRAM cell 200 and SRAM cell 200Y. Similarly, because SRAM cell 200X and SRAM cell 200XY share dielectric fin 230, SRAM cell 200X is a mirror image of SRAM cell 200XY opposite the dielectric fin 230, and vice versa. Dielectric fin 230 self-isolation feature (similar to...) Figures 3 to 6 The isolation feature (similar to the isolation feature 203) extends and rises above the isolation feature, which is located between SRAM cell 200X and SRAM cell 200XY.

[0128] Based on the foregoing discussion, it can be seen that this disclosure provides advantages over conventional SRAM cells and SRAM macrocode. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor are all embodiments required to have specific advantages. This disclosure provides an embodiment of a 6T SRAM cell formed by GAA transistors. The 6T SRAM cell of this disclosure comprises four fin-shaped vertical stacks with five dielectric fins interleaved. The dielectric fins are used to prevent bridging of adjacent epitaxial source / drain features, facilitate different work function metal arrangements in different device regions, and control the metal gate cutoff process.

[0129] This disclosure provides embodiments of SRAM cells and memory structures. In one embodiment, an SRAM cell is provided. The SRAM cell includes a first pull-up gate full-loop (GAA) transistor and a first pull-down GAA transistor coupled together to form a first inverter; a second pull-up GAA transistor and a second pull-down GAA transistor coupled together to form a second inverter; a first transmission gate GAA transistor coupled to the output of the first inverter and the input of the second inverter; a second transmission gate GAA transistor coupled to the output of the second inverter and the input of the first inverter; a first dielectric fin disposed between the first pull-up GAA transistor and the first pull-down GAA transistor; and a second dielectric fin disposed between the second pull-up GAA transistor and the second pull-down GAA transistor.

[0130] In some embodiments, the first dielectric fin and the second dielectric fin include silicon oxycarbonate, silicon oxynitride, silicon carbonitride, silicon nitride, aluminum oxide, yttrium oxide, tantalum oxide, titanium oxide, hafnium oxide, or zirconium oxide. In some embodiments, each of the first dielectric fin and the second dielectric fin includes a first thin layer and a second thin layer disposed within the first thin layer, the first thin layer including silicon nitride, and the second thin layer including aluminum oxide, yttrium oxide, tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, or combinations thereof. In some embodiments, the first pull-up GAA transistor includes a first source / drain feature disposed on the first fin structure, the first pull-down GAA transistor includes a second source / drain feature disposed on the second fin structure, and the first dielectric fin is disposed between the first source / drain feature and the second source / drain feature. In some embodiments, an isolation feature is disposed between the first fin structure and the second fin structure, and the first dielectric fin includes a lower portion and an upper portion above the lower portion. In those embodiments, the lower portion of the first dielectric fin is disposed within an isolation feature, and the upper portion of the first dielectric fin extends over the isolation feature. In some embodiments, the first dielectric fin contacts a first source / drain feature and a second source / drain feature. In some embodiments, a first transmission gate GAA transistor and a first pull-down GAA transistor are disposed on a first p-type well, a first pull-up GAA transistor and a second pull-up GAA transistor are disposed on an n-type well, a second transmission gate GAA transistor and a second pull-down GAA transistor are disposed on a second p-type well, the first dielectric fin is disposed on a first interface located between the first p-type well and the n-type well, and the second dielectric fin is disposed on a second interface located between the second p-type well and the n-type well. In some embodiments, the SRAM cell further includes a gate cutoff dielectric feature located on the second dielectric fin. In some embodiments, the gate cutoff dielectric feature is formed of a dielectric material having a dielectric constant greater than 3.9.

[0131] In another embodiment, an SRAM cell is provided. The SRAM cell includes a first fin-shaped vertical stack on a first p-type well, a second fin-shaped vertical stack on an n-type well adjacent to the first p-type well, a third fin-shaped vertical stack on an n-type well, a fourth fin-shaped vertical stack on a second p-type well adjacent to the n-type well, a first dielectric fin located between the first and second fin-shaped vertical stacks, a second dielectric fin located between the second and third fin-shaped vertical stacks, and a third dielectric fin located between the third and fourth fin-shaped vertical stacks.

[0132] In some embodiments, the first fin vertical stack includes a first transfer gate-gate full-loop (GAA) transistor and a first pull-down GAA transistor; the second fin vertical stack includes a first pull-up GAA transistor; the third fin vertical stack includes a second pull-up GAA transistor; and the fourth fin vertical stack includes a second transfer gate GAA transistor and a second pull-down GAA transistor. In some embodiments, the SRAM cell further includes a fourth dielectric fin adjacent to the first fin vertical stack, and a fifth dielectric fin adjacent to the fourth fin vertical stack. In some embodiments, the fourth and fifth dielectric fins define two ends of the SRAM cell. In some embodiments, the SRAM cell further includes an isolation feature located within the first, second, third, and fourth fin vertical stacks. In those embodiments, each of the first, second, and third dielectric fins is disposed on the isolation feature. In some embodiments, each of the first and fourth vertical fin stacks includes a first width (W1), each of the second and third vertical fin stacks includes a second width (W2), and the ratio of the first width to the second width (W1 / W2) is between about 1.1 and about 3.0. In some embodiments, each of the first, second, and third dielectric fins includes one or more dielectric materials selected from a group consisting of: silicon oxycarbonate, silicon oxynitride, silicon carbonitride, silicon nitride, aluminum oxide, yttrium oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide.

[0133] In a further embodiment, a memory structure is provided. This memory structure includes a first SRAM cell comprising a plurality of first gate-all-around (GAA) transistors, a second SRAM cell comprising a plurality of second GAA transistors, and dielectric fins located between the first SRAM cell and the second SRAM cell. In this embodiment, the first SRAM cell is a mirror image of the second SRAM cell partitioned by the dielectric fins.

[0134] In some embodiments, dielectric fins are disposed on an isolation feature located between a first SRAM cell and a second SRAM cell. In some embodiments, dielectric fins are disposed on a p-type well. In some embodiments, the first SRAM cell and the second SRAM cell share a p-type well.

[0135] The foregoing outlines the features of various embodiments or examples to enable those skilled in the art to better understand this disclosure. Those skilled in the art should understand that they can readily design or modify other processes and structures based on this disclosure to achieve the same purpose and / or obtain the same advantages as the embodiments or examples described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the concept and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this disclosure without departing from its concept and scope. For example, by implementing different thicknesses for bit line conductors and word line conductors, those skilled in the art can achieve different resistances for the conductors. However, other techniques for changing the resistance of metallic conductors can also be used.

Claims

1. A static random access memory (SRAM) cell, comprising: A first pull-up gate full-loop transistor and a first pull-down gate full-loop transistor are coupled together to form a first inverter; A second pull-up gate full-loop transistor and a second pull-down gate full-loop transistor are coupled together to form a second inverter; A first transmission gate full-loop transistor is coupled to the output of the first inverter and the input of the second inverter; A second transmission gate full-loop transistor is coupled to the output of the second inverter and the input of the first inverter. A first dielectric fin is disposed between the first pull-up gate full-ring transistor and the first pull-down gate full-ring transistor; and A second dielectric fin is disposed between the second pull-up gate full-ring transistor and the second pull-down gate full-ring transistor; Each of the aforementioned first pull-up gate full-ring transistor, first pull-down gate full-ring transistor, second pull-up gate full-ring transistor, second pull-down gate full-ring transistor, first transmission gate full-ring transistor, and second transmission gate full-ring transistor includes a plurality of channel components, which are vertically stacked above a substrate and spaced apart from the substrate. The first pull-down gate full-ring transistor includes a first source / drain feature disposed on a first fin structure, the first pull-up gate full-ring transistor includes a second source / drain feature disposed on a second fin structure, and the first dielectric fin is disposed between the first source / drain feature and the second source / drain feature.

2. The static random access memory unit as described in claim 1, wherein: The aforementioned first dielectric fin and the aforementioned second dielectric fin include silicon oxycarbonate, silicon oxynitride, silicon oxycarbonitrile, silicon nitride, aluminum oxide, yttrium oxide, tantalum oxide, titanium oxide, hafnium oxide, or zirconium oxide; and Each of the first dielectric fin and the second dielectric fin is partially disposed in an isolation feature and spaced apart from the substrate by the isolation feature.

3. The static random access memory unit as described in claim 1, wherein: Each of the first dielectric fin and the second dielectric fin is partially disposed in an isolation feature; Each of the first dielectric fin and the second dielectric fin includes a first thin layer and a second thin layer disposed in the first thin layer; The second thin layer is separated from the isolation feature by the first thin layer; The first thin layer mentioned above includes silicon nitride; and The aforementioned second thin layer includes aluminum oxide, yttrium oxide, tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, or a combination thereof.

4. The static random access memory unit as claimed in claim 1, wherein: An isolation feature is disposed between the first fin structure and the second fin structure. The first dielectric fin includes a lower portion and an upper portion above the lower portion; and The lower portion of the first dielectric fin is disposed within the isolation feature, and the upper portion of the first dielectric fin extends over the isolation feature.

5. The static random access memory cell of claim 1, wherein the first dielectric fin is in contact with the first source / drain feature and the second source / drain feature.

6. The static random access memory unit as claimed in claim 1, wherein: The aforementioned first transmission gate full-loop transistor and the aforementioned first pull-down gate full-loop transistor are disposed on a first p-type well; The first pull-up gate full-ring transistor and the second pull-up gate full-ring transistor are disposed on an n-type well; The aforementioned second transmission gate full-loop transistor and the aforementioned second pull-down gate full-loop transistor are disposed on a second p-type well; The first dielectric fin is disposed on a first interface, the first interface being located between the first p-type well and the n-type well; and The second dielectric fin is disposed on a second interface, which is located between the second p-type well and the n-type well.

7. The static random access memory unit as claimed in claim 1, further comprising: A gate-cut-off dielectric feature is located on the aforementioned second dielectric fin.

8. The static random access memory cell of claim 7, wherein the gate cutoff dielectric feature is formed of a dielectric material having a dielectric constant greater than 3.

9.

9. A static random access memory (SRAM) cell, comprising: A first pull-up transistor and a first pull-down transistor are coupled together to form a first inverter; A second pull-up transistor and a second pull-down transistor are coupled together to form a second inverter; A first transmission gate transistor is coupled to the output of the first inverter and the input of the second inverter; A second transmission gate transistor is coupled to the output of the second inverter and the input of the first inverter. A first dielectric fin is disposed between the first pull-up transistor and the first pull-down transistor; and A second dielectric fin is disposed between the second pull-up transistor and the second pull-down transistor; The first pull-down transistor includes a plurality of first channel components vertically stacked on and spaced apart from a first fin structure; the first transmission gate transistor includes a plurality of second channel components vertically stacked on and spaced apart from the first fin structure; the first pull-up transistor includes a plurality of third channel components vertically stacked on and spaced apart from a second fin structure; the second pull-up transistor includes a plurality of fourth channel components vertically stacked on and spaced apart from a third fin structure; the second pull-down transistor includes a plurality of fifth channel components vertically stacked on and spaced apart from a fourth fin structure; and the second transmission gate transistor includes a plurality of sixth channel components vertically stacked on and spaced apart from the fourth fin structure. The first pull-down transistor includes a first source / drain feature disposed above the first fin structure, and the first pull-up transistor includes a second source / drain feature disposed above the second fin structure, and the first source / drain feature and the second source / drain feature are in contact with the first dielectric fin.

10. The static random access memory unit as claimed in claim 9, wherein: The aforementioned first fin structure is disposed on a first P-well; The aforementioned second fin structure and the aforementioned third fin structure are disposed on a well N; The aforementioned fourth fin structure is disposed on a second P-well; and The aforementioned well N is sandwiched between the aforementioned first well P and the aforementioned second well P.

11. The static random access memory cell of claim 10, further comprising: An isolation feature is disposed between the first fin structure and the second fin structure, wherein: The first dielectric fin mentioned above includes a lower portion and an upper portion above the lower portion; The lower portion of the first dielectric fin is disposed within the isolation feature, and the upper portion of the first dielectric fin rises above the isolation feature; and The lower portion is separated from the first P well and the N well by the aforementioned isolation features.

12. The static random access memory cell of claim 9, wherein: The aforementioned first source / drain characteristics include phosphorus-doped silicon; and The aforementioned second source / drain characteristics include boron-doped silicon germanium.

13. The static random access memory unit as claimed in claim 9, further comprising: A source / drain contact is disposed on the first source / drain feature and the second source / drain feature, and is electrically coupled to the first source / drain feature and the second source / drain feature.

14. The static random access memory cell as claimed in claim 13, wherein the source / drain contacts are also directly disposed on the first dielectric fin.

15. A static random access memory device, comprising: A first pull-down transistor and a first transmission gate transistor are disposed on a first P-well on a substrate; A first pull-up transistor and a second pull-up transistor are disposed on an N-well on the aforementioned substrate; A second pull-down transistor and a second transmission gate transistor are disposed on a second P-well on the aforementioned substrate; A first dielectric fin is disposed between the first pull-up transistor and the first pull-down transistor; and A second dielectric fin is disposed between the second pull-up transistor and the second pull-down transistor, wherein: The first pull-down transistor includes a plurality of first channel components and a first gate structure. The first channel components are located above the substrate and spaced apart from the substrate. The first gate structure encloses each of the first channel components. The first transmission gate transistor includes a plurality of second channel components and a second gate structure. The second channel components are located above the substrate and spaced apart from the substrate. The second gate structure surrounds each of the second channel components. The first pull-up transistor includes a plurality of third channel components and a third gate structure. The third channel components are located above the substrate and spaced apart from the substrate. The third gate structure surrounds each of the third channel components. The second pull-up transistor mentioned above includes a plurality of fourth channel components and a fourth gate structure. The fourth channel components are located above the substrate and spaced apart from the substrate. The fourth gate structure surrounds each of the fourth channel components. The second pull-down transistor includes a plurality of fifth channel components and a fifth gate structure, wherein the fifth channel components are located above and spaced from the substrate, and the fifth gate structure surrounds each of the fifth channel components; and The second transmission gate transistor includes a plurality of sixth channel components and a sixth gate structure. The sixth channel components are located above and spaced from the substrate, and the sixth gate structure surrounds each of the sixth channel components.

16. The static random access memory device of claim 15, wherein the first gate structure and the second gate structure have the same composition.

17. The static random access memory device of claim 15, wherein the composition of the first gate structure is different from the composition of the second gate structure.

18. The static random access memory device of claim 15, further comprising: A gate-cut-off dielectric feature is located on the aforementioned second dielectric fin; The aforementioned gate cutoff dielectric feature separates the aforementioned third gate structure from the aforementioned sixth gate structure.

19. A static random access memory (SRAM) cell, comprising: A first fin-shaped vertical stack is located on a first p-type well, including a first fin structure and a plurality of first channel components above the first fin structure, wherein the first fin-shaped vertical stack forms a first transmission gate transistor and a first pull-down transistor. A second fin-shaped vertical stack is located on an n-type well adjacent to the first p-type well, including a second fin structure and a plurality of second channel components above the second fin structure, wherein the second fin-shaped vertical stack forms a first pull-up transistor; A third fin-shaped vertical stack is located on the above-mentioned n-type well, including a third fin structure and a plurality of third channel components above the above-mentioned third fin structure, wherein the above-mentioned third fin-shaped vertical stack forms a second pull-up transistor. A fourth fin-shaped vertical stack is located on a second p-shaped well adjacent to the aforementioned n-shaped well, including a fourth fin structure and a plurality of fourth channel components above the aforementioned fourth fin structure, wherein the aforementioned fourth fin-shaped vertical stack forms a second transmission gate transistor and a second pull-down transistor; A first dielectric fin is located between the first vertical stack of fins and the second vertical stack of fins. A second dielectric fin is located between the second vertical stack of fins and the third vertical stack of fins; and A third dielectric fin is located between the aforementioned third fin-shaped vertical stack and the aforementioned fourth fin-shaped vertical stack. The first pull-down transistor includes a first source / drain feature disposed above the first fin structure, and the first pull-up transistor includes a second source / drain feature disposed above the second fin structure, and the first source / drain feature and the second source / drain feature are in contact with the first dielectric fin.

20. The static random access memory unit of claim 19, further comprising: A fourth dielectric fin is vertically stacked adjacent to the aforementioned first fin; as well as A fifth dielectric fin is vertically stacked adjacent to the aforementioned fourth fin.

21. The static random access memory cell of claim 20, wherein the fourth dielectric fin and the fifth dielectric fin define the two ends of the static random access memory cell.

22. The static random access memory unit of claim 20, further comprising: A first gate-cut-off dielectric feature is disposed on the aforementioned fourth dielectric fin; A second gate-cut-off dielectric feature is disposed on the fifth dielectric fin.

23. The static random access memory unit of claim 19, further comprising: An isolation feature is located among the first fin-shaped vertical stack, the second fin-shaped vertical stack, the third fin-shaped vertical stack, and the fourth fin-shaped vertical stack. Each of the first dielectric fin, the second dielectric fin, and the third dielectric fin is disposed on the isolation feature.

24. The static random access memory cell of claim 19, wherein: Each of the first fin-shaped vertical stack and the fourth fin-shaped vertical stack mentioned above includes a first width (W1); Each of the aforementioned second fin-shaped vertical stack and the aforementioned third fin-shaped vertical stack includes a second width (W2); and The ratio of the first width to the second width (W1 / W2) is between 1.1 and 3.

0.

25. The static random access memory cell of claim 19, wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin comprises one or more dielectric materials selected from a group consisting of the following materials: Silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon nitride, aluminum oxide, yttrium oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide.

26. The static random access memory cell of claim 19, wherein the first dielectric fin is directly disposed above an interface, the interface being located between the first p-type well and the n-type well.

27. The static random access memory cell of claim 19, wherein the third dielectric fin is disposed directly above an interface located between the n-type well and the second p-type well.

28. A memory structure, comprising: A first static random access memory cell, comprising: A first fin-shaped vertical stack is located on a first p-type well, including a first fin structure and a plurality of first channel components above the first fin structure, wherein the first fin-shaped vertical stack forms a first transmission gate transistor and a first pull-down transistor. A second fin-shaped vertical stack is located on an n-type well adjacent to the first p-type well, including a second fin structure and a plurality of second channel components above the second fin structure, wherein the second fin-shaped vertical stack forms a first pull-up transistor; A third fin-shaped vertical stack is located on the above-mentioned n-type well, including a third fin structure and a plurality of third channel components above the above-mentioned third fin structure, wherein the above-mentioned third fin-shaped vertical stack forms a second pull-up transistor. A fourth fin-shaped vertical stack is located on a second p-shaped well adjacent to the aforementioned n-shaped well, including a fourth fin structure and a plurality of fourth channel components above the aforementioned fourth fin structure, wherein the aforementioned fourth fin-shaped vertical stack forms a second transmission gate transistor and a second pull-down transistor; A first dielectric fin is located between the aforementioned first fin-shaped vertical stack and the aforementioned second fin-shaped vertical stack; A second dielectric fin, located between the aforementioned second fin-shaped vertical stack and the aforementioned third fin-shaped vertical stack; and A third dielectric fin is located between the aforementioned third vertical stack of fins and the aforementioned fourth vertical stack of fins. The first pull-down transistor includes a first source / drain feature disposed above the first fin structure, and the first pull-up transistor includes a second source / drain feature disposed above the second fin structure, and the first source / drain feature and the second source / drain feature are in contact with the first dielectric fin.

29. The memory structure as described in claim 28, wherein: The first dielectric fin is directly disposed above a first interface, which is located between the first p-type well and the n-type well; and The aforementioned third dielectric fin is directly disposed above a second interface, which is located between the aforementioned n-type well and the aforementioned second p-type well.

30. The memory structure of claim 28, further comprising: A fourth dielectric fin is vertically stacked adjacent to the aforementioned fourth fin-shaped fin; The aforementioned fourth dielectric fin is disposed on the aforementioned second p-type well.

31. The memory structure of claim 30, wherein each of the first dielectric fin, the second dielectric fin, the third dielectric fin, and the fourth dielectric fin comprises one or more dielectric materials selected from a group consisting of the following materials: Silicon oxide, silicon oxynitride, silicon carbon oxynitride, silicon nitride, aluminum oxide, yttrium oxide, titanium oxide, tantalum oxide, hafnium oxide, and zirconium oxide.

32. The memory structure of claim 30, further comprising: A second static random access memory unit; The second static random access memory unit is a mirror image of the first static random access memory unit relative to the fourth dielectric fin.

33. The memory structure of claim 32, wherein the first static random access memory unit and the second static random access memory unit share the second p-type well.

34. A memory cell, comprising: A first nanostructure is vertically stacked above a first fin structure on a first p-type well, wherein the vertically stacked first nanostructure forms a first transmission gate transistor and a first pull-down transistor. A second nanostructure is vertically stacked above a second fin structure on an n-type well adjacent to the first p-type well, wherein the vertically stacked second nanostructure forms a first pull-up transistor. A third nanostructure is vertically stacked above a third fin structure on the aforementioned n-type well, wherein the vertically stacked third nanostructure forms a second pull-up transistor. A fourth nanostructure is vertically stacked above a fourth fin structure on a second p-type well adjacent to the above-mentioned n-type well, wherein the vertically stacked fourth nanostructure forms a second transmission gate transistor and a second pull-down transistor; A first dielectric fin is located between the vertical stacking of the first nanostructure and the vertical stacking of the second nanostructure; A second dielectric fin, situated between the vertically stacked second nanostructure and the vertically stacked third nanostructure; and A third dielectric fin is positioned between the vertically stacked third nanostructure and the vertically stacked fourth nanostructure. The first pull-down transistor includes a first source / drain feature disposed above the first fin structure, and the first pull-up transistor includes a second source / drain feature disposed above the second fin structure, and the first source / drain feature and the second source / drain feature are in contact with the first dielectric fin.

35. The memory cell of claim 34, further comprising: A gate structure is disposed on the vertical stack of the first nanostructure and the vertical stack of the second nanostructure; The gate structure described above encloses and surrounds each of the first nanostructures vertically stacked to form the first pull-down transistor and each of the second nanostructures vertically stacked to form the first pull-up transistor.

36. The memory cell of claim 34, wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin comprises: A first thin layer; and A second thin layer is disposed within the aforementioned first thin layer; The composition of the first thin layer is different from that of the second thin layer.

37. The memory cell of claim 36, wherein each of the first dielectric fin, the second dielectric fin, and the third dielectric fin further comprises a capping layer disposed on the first thin layer and the second thin layer.

38. A memory structure, comprising: A first static random access memory cell includes a plurality of first gate full-ring transistors; A second static random access memory cell, comprising a plurality of second gate full-ring transistors; and A dielectric fin is located between the first static random access memory unit and the second static random access memory unit. The first static random access memory cell is a mirror image of the second static random access memory cell, which is divided by the dielectric fins.

39. The memory structure of claim 38, wherein the dielectric fins are disposed on an isolation feature located between the first static random access memory cell and the second static random access memory cell.

40. The memory structure of claim 38, wherein the dielectric fins are disposed on a p-shaped well.

41. The memory structure of claim 40, wherein the first static random access memory unit and the second static random access memory unit share the p-type well.

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