Signal processing circuit, signal processing device and signal processing method

Abstract

A signal processing circuit (12) outputs a first output signal at a first timing and outputs a second output signal at a second timing when a first input signal changes at a first timing earlier than or the same as a second input signal changes at a second timing; and outputs the first output signal and the second output signal at the second timing when the first timing is later than the second timing.

Description

Technical Field

[0001] The present disclosure relates to a signal processing circuit, a signal processing device and a signal processing method. Background Art

[0002] Patent document 1 describes a multiplication-accumulation operation device that represents operation result information by using a time difference between two signals. The multiplication-accumulation operation device described in Patent document 1 can be applied to a neural network circuit. The neural network circuit has a multi-layer configuration including multiple layers connected to each other, each layer including a plurality of multiplication-accumulation operation circuits. In addition, a signal processing circuit that performs various types of signal processing is arranged between one layer and another layer. Examples of various types of signal processing include activation function arithmetic processing and maximum pooling processing (maximum pooling).

[0003] The above-mentioned various types of signal processing are performed by a digital signal processing circuit. Therefore, before performing the above-mentioned various types of signal processing, it is necessary to use a time-to-digital converter circuit that converts two signals representing information with a time difference into digital signals. The time-to-digital converter circuit corresponds to an analog-to-digital (A / D) converter circuit. Further, after performing the above-mentioned various types of signal processing, it is necessary to use a digital-to-time converter circuit that converts the digital signal into two signals representing information with a time difference. The digital-to-time converter circuit corresponds to a digital-to-analog (D / A) converter circuit.

[0004] Reference List

[0005] Patent Literature

[0006] Patent Document 1: WO 2018 / 034163 A Summary of the invention

[0007] Technical issues

[0008] Unfortunately, however, time-to-digital converter circuits and digital-to-time converter circuits consume a large amount of power.

[0009] In view of this, the present disclosure proposes a signal processing circuit, a signal processing device, and a signal processing method capable of suppressing power consumption.

[0010] Solution to the problem

[0011] According to the present disclosure, a signal processing circuit is provided: when a first timing at which a first input signal changes is earlier than or the same as a second timing at which a second input signal changes, a first output signal is output at the first timing and a second output signal is output at the second timing; and when the first timing is later than the second timing, the first output signal and the second output signal are output at the second timing.

[0012] Moreover, according to the present disclosure, a signal processing device is provided, including: a multiplication-addition operation circuit, which performs a first multiplication-addition operation of multiplying and adding a plurality of signals with coefficients of a first group respectively and outputs a first signal, and performs a second multiplication-addition operation of multiplying and adding a plurality of signals with coefficients of a second group respectively and outputs a second signal; and a signal processing circuit, which outputs a first output signal at a first timing and outputs a second output signal at a second timing when a first timing at which the first signal changes is earlier than or the same as a second timing at which the second signal changes, and outputs the first output signal and the second output signal at the second timing when the first timing is later than the second timing.

[0013] Advantageous Effects of the Invention

[0014] According to the present disclosure, power consumption can be suppressed. It should be noted that the effects described here do not necessarily have to be limited and may be any effects described in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a diagram showing a configuration of a neural network device according to a first embodiment of the present disclosure.

[0016] Figure 2 : is a diagram showing the configuration of a multiply-and-accumulate operation circuit of the neural network device according to the first embodiment of the present disclosure.

[0017] Figure 3 is a diagram showing input / output characteristics of ReLU.

[0018] Figure 4 : is a diagram showing the configuration of an activation function circuit of the neural network device according to the first embodiment of the present disclosure.

[0019] Figure 5 : is a timing chart showing the operation timing of the activation function circuit of the neural network device according to the first embodiment of the present disclosure.

[0020] Figure 6 : is a timing chart showing the operation timing of the activation function circuit of the neural network device according to the first embodiment of the present disclosure.

[0021] Figure 7 is a diagram showing the relationship between the input timing and the output timing of the activation function circuit of the neural network device according to the first embodiment of the present disclosure.

[0022] Figure 8 : is a diagram showing the configuration of a maximum pooling circuit (MaxPooling circuit) of the neural network device according to the first embodiment of the present disclosure.

[0023] Fig. 9 : is a timing chart showing the operation timing of the maximum pooling circuit of the neural network device according to the first embodiment of the present disclosure.

[0024] Fig.10 is a diagram showing a configuration of an activation function circuit according to a second embodiment of the present disclosure.

[0025] Fig.11 is a diagram showing a configuration of an activation function circuit according to a third embodiment of the present disclosure.

[0026] Fig.12 is a diagram showing a configuration of an activation function circuit according to a fourth embodiment of the present disclosure.

[0027] Fig.13 is a diagram showing a configuration of a maximum pooling circuit according to a fifth embodiment of the present disclosure.

[0028] Fig.14 is a diagram showing a configuration of a maximum pooling circuit according to a sixth embodiment of the present disclosure.

[0029] Fig.15 is a diagram showing a configuration of a comparator of a maximum pooling circuit according to a seventh embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the following embodiments, the same components are represented by the same reference symbols, and their repeated descriptions will be omitted.

[0031] (First Embodiment)

[0032] [Configuration of Neural Network Device According to First Embodiment]

[0033] Figure 1 1 is a diagram showing a configuration of a neural network device according to a first embodiment of the present disclosure. The neural network device 1 includes a first layer circuit 2 , a first inter-layer circuit 3 , a second layer circuit 4 , and a second inter-layer circuit 5 .

[0034] The neural network device 1 is an example of a signal processing device of the present disclosure.

[0035] In the first embodiment, the neural network device 1 includes two layers, namely, a first layer circuit 2 and a second layer circuit 4. However, the present disclosure is not limited to this configuration. The neural network device 1 may include three or more layers. Further, the neural network device 1 may be formed on a semiconductor chip (bare die).

[0036] The first layer circuit 2 is used for multiple input signals xi (i is a natural number from 1 to N; N is a natural number of 2 or more) performs a multiplication-addition operation and outputs a signal indicating the operation result to the first interlayer circuit 3. The first interlayer circuit 3 performs the following processing on the output signal from the first interlayer circuit 2 and outputs a signal indicating the processing result to the second interlayer circuit 4. The second interlayer circuit 4 performs a multiplication-addition operation on the output signal from the first interlayer circuit 3 and outputs a signal indicating the processing result to the second interlayer circuit 5. The second interlayer circuit 5 performs the following processing on the output signal from the second interlayer circuit 4 and outputs a signal indicating the processing result to the subsequent circuit.

[0037] The first layer circuit 2 includes a plurality of multiplication-accumulation circuits 11. The first inter-layer circuit 3 includes a plurality of activation function circuits 12 and a plurality of maximum pooling circuits 13. The second layer circuit 4 includes a plurality of multiplication-accumulation circuits 11. The second inter-layer circuit 5 includes a plurality of activation function circuits 12 and a plurality of maximum pooling circuits 13.

[0038] The activation function circuit 12 is an example of a signal processing circuit of the present disclosure. The maximum pooling circuit 13 is an example of a second signal processing circuit of the present disclosure. The multiply-accumulate operation circuit 11 is an example of a multiply-accumulate operation circuit of the present disclosure.

[0039] [Configuration and operation of multiplication and accumulation circuit]

[0040] Figure 2 : is a diagram showing a configuration of a multiply-and-accumulate operation circuit of a neural network device according to a first embodiment of the present disclosure. The multiply-and-accumulate operation circuit 11 includes a first multiply-and-accumulate operation circuit 11p and a second multiply-and-accumulate operation circuit 11m.

[0041] The multiplication and accumulation circuit 11 is a circuit that generates a positive absolute value signal t vin + (ie, the output signal from the first product-addition operation circuit 11p) and the negative absolute value signal t vin - The time difference between the output signals from the second multiply-add operation circuit 11m and the output signals from the second multiply-add operation circuit 11m represents the time axis of the operation result information.

[0042] The first product-add operation circuit 11p includes a capacitor Cp having one end electrically connected to a standard potential. An example of the standard potential is a ground potential, but the present disclosure is not limited thereto. Further, the capacitor Cp may be a gate capacitance of another storage device (eg, a MOS transistor).

[0043] The first product-addition operation circuit 11p includes a resistor Rp 0The first product-addition operation circuit 11p further includes a diode D for preventing backflow, and the anode of the diode D is electrically connected to the resistor Rp. 0 The bias voltage BTp is input to the resistor Rp. 0 Accordingly, the bias voltage BTp and the resistor Rp 0 A current corresponding to the resistance value is supplied to the capacitor Cp.

[0044] The first product-addition operation circuit 11p includes a plurality of resistors Rp i (i is a natural number from 1 to N; N is a natural number of 2 or more). In addition, the first product-addition operation circuit 11p includes a plurality of diodes D for preventing backflow, wherein the anodes are electrically connected to the resistor Rp i The cathode is electrically connected to the other end of the capacitor Cp. i Input to resistor Rp i The other end of the i The voltage and resistor Rp i The current corresponding to the resistance value is supplied to the capacitor Cp to increase the voltage of the capacitor Cp. i It can be a pulse width modulated signal.

[0045] Therefore, the first multiplication-addition operation circuit 11p performs the multiplication-addition operation of the following equation (1). In equation (1), w i is the weighting factor and is represented by the resistor Rp i In the first product-addition operation circuit 11p, w i is the coefficient representing the positive load.

[0046]

[0047] Resistor Rp i The resistance value may be switchable or changeable.

[0048] The first product-addition operation circuit 11p includes a comparator CMPp. When the voltage of the capacitor Cp is lower than the threshold voltage Vth, the comparator CMPp outputs a low-level signal t vin + When the voltage of capacitor Cp is the threshold voltage Vth or greater, comparator CMPp outputs a high level signal t vin + .

[0049] The larger the product-accumulation operation result is, the faster the voltage of the capacitor Cp rises, causing the first product-accumulation operation circuit 11p to output a high-level signal tvin + The smaller the result of the multiplication and addition operation, the slower the voltage rise of the capacitor Cp, causing the first multiplication and addition operation circuit 11p to output a high-level signal t vin + timing delay.

[0050] The second product-addition operation circuit 11m includes a capacitor Cm having one end electrically connected to a standard potential. The capacitor Cm may be a gate capacitance of another storage device (eg, a MOS transistor).

[0051] The second product-addition operation circuit 11m includes a resistor Rm 0 The second product-addition operation circuit 11m further includes a diode D for preventing backflow, wherein the anode is electrically connected to the resistor Rm. 0 The bias voltage BTm is input to the resistor Rm. 0 The other end of the resistor Rm is connected to the bias voltage BTm. 0 A current corresponding to the resistance value is supplied to the capacitor Cm.

[0052] The second product-addition operation circuit 11m includes a plurality of resistors Rm i (i is a natural number from 1 to N; N is a natural number of 2 or more). In addition, the second product-addition operation circuit 11m includes a plurality of diodes D for preventing backflow, wherein the anodes are electrically connected to the resistor Rm i The cathode is electrically connected to the other end of the capacitor Cm. i Input to resistor Rm i The other end of the i Voltage and resistor Rm i A current corresponding to the resistance value is supplied to the capacitor Cm to increase the voltage of the capacitor Cm.

[0053] Therefore, the second multiplication-addition operation circuit 11m performs the multiplication-addition operation of the above equation (1). In the second multiplication-addition operation circuit 11m, w i is a coefficient that expresses the absolute value of the negative load.

[0054] Resistor Rm i The resistance value may be switchable or changeable.

[0055] The second product-addition operation circuit 11m includes a comparator CMPm. When the voltage of the capacitor Cm is lower than the threshold voltage Vth, the comparator CMPm outputs a low-level signal t vin -When the voltage of the capacitor Cm is the threshold voltage Vth or greater, the comparator CMPm outputs a high level signal t vin - .

[0056] The larger the multiplication-accumulation operation result is, the faster the voltage of the capacitor Cm rises, causing the second multiplication-accumulation operation circuit 11m to output a high-level signal t vin - The smaller the multiplication and addition operation result is, the slower the voltage rise of the capacitor Cm is, causing the second multiplication and addition operation circuit 11m to output a high level signal t vin - timing delay.

[0057] The multiplication and accumulation circuit 11 uses the signal t vin + With signal t vin - The time difference between them indicates the operation result information.

[0058] [Configuration and operation of activation function circuit]

[0059] The activation function circuit 12 is a circuit for t vin + and t vin - (ie, the output signal from the multiplication and addition operation circuit 11) A circuit that performs nonlinear function operation. In the first embodiment, the nonlinear function used is a modified linear unit (ReLU). ReLU is expressed by the following equation (2). ReLU is sometimes called a ramp function.

[0060]

[0061] Figure 3 is a diagram showing the input / output characteristics of ReLU. Figure 3 As shown in the graph 101 of , when the input value is less than 0, the output value is 0. When the input value is 0 or greater, the output value is equal to the input value.

[0062] Figure 4 1 is a diagram showing a configuration of an activation function circuit of the neural network device according to the first embodiment of the present disclosure. The activation function circuit 12 includes a logic circuit.

[0063] Logic circuits are roughly classified into combinational circuits and sequential circuits. A combinational circuit is a circuit in which the current output signal depends only on the current input signal and does not depend on the previous input signal. Examples of combinational circuits include a logic OR circuit (OR gate circuit) and a logic AND circuit (AND gate circuit). A sequential circuit is a circuit in which the current output signal depends on both the current input signal and the previous input signal. Examples of sequential circuits include D-type flip-flops and RS-type flip-flops.

[0064] like Figure 4 As shown in FIG. 1 , the activation function circuit 12 includes a logic OR circuit (OR gate circuit) 21 , which is a combinational circuit.

[0065] The logical OR circuit 21 is an example of a first logical circuit of the present disclosure.

[0066] The logic OR circuit 21 is used to generate the signal t vin + and signal t vin - Perform a logical OR operation, and then, output signal t vout + , which is the result of a logical OR operation.

[0067] The activation function circuit 12 converts the signal t vin - Output intact as signal t vout - .

[0068] Figure 5 is a timing diagram showing the operation timing of the activation function circuit of the neural network device according to the first embodiment of the present disclosure. Specifically, Figure 5 It shows that when the signal t vin + The rising timing is earlier than the signal t vin - 1 is a diagram showing the operation timing of the activation function circuit 12 at the rising timing of .

[0069] Signal vin + At the timing t 1 From low level to high level. Timing t 1 The time 102 between the predetermined timing T and the operation result of the first product-addition operation circuit 11p (reference Figure 2 ) corresponds to the positive absolute value of .

[0070] Signal vin - At the timing t 1 After the timing t 2 From low level to high level. Timing t2 The time 103 between the predetermined timing T and the operation result of the second product-addition operation circuit 11m (reference Figure 2 ) corresponds to the negative absolute value of .

[0071] In addition, the multiplication and accumulation circuit 11 is configured to generate a multiplication and accumulation circuit 11 by timing t 1 With timing t 2 The time difference 104 (positive time difference) between them represents the multiplication-addition operation result information.

[0072] Because the signal t vin + At the timing t 1 rises to a high level, so the logic OR circuit 21 outputs a high level signal t vout + .

[0073] Because the signal t vin - At the timing t 2 rises to a high level, so the activation function circuit 12 outputs a high level signal t vout - .

[0074] Therefore, the signal t vout + and signal t vout - The time difference between 105 and the signal t vin + and signal t vin - The time difference 104 between them is the same.

[0075] Figure 6 is a timing diagram showing the operation timing of the activation function circuit of the neural network device according to the first embodiment of the present disclosure. Specifically, Figure 6 It shows that when the signal t vin + The rising timing is later than the signal t vin - 1 is a diagram showing the operation timing of the activation function circuit 12 at the rising timing of .

[0076] Signal vin - At the timing t 11 From low level to high level. Timing t 11 The time 107 between the predetermined timing T corresponds to the calculation result of the second product-addition calculation circuit 11m.

[0077] Signal vin + At the timing t 11 After the timing t12 From low level to high level. Timing t 12 The time 106 between the predetermined timing T corresponds to the calculation result of the first product-addition calculation circuit 11p.

[0078] In addition, the multiplication and accumulation circuit 11 is configured to generate a multiplication and accumulation circuit 11 by timing t 11 With timing t 12 The time difference 108 (negative time difference) between them represents the multiplication-addition operation result information.

[0079] Because the signal t vin - At the timing t 11 rises to a high level, so the logic OR circuit 21 outputs a high level signal t vout + .

[0080] Because the signal t vin - At the timing t 11 rises to a high level, so the activation function circuit 12 outputs a high level signal t vout - .

[0081] Therefore, at the same timing, the output signal t vout + and signal t vout - .

[0082] Figure 7 is a diagram showing the relationship between the input timing and the output timing of the activation function circuit of the neural network device according to the first embodiment of the present disclosure.

[0083] In the signal t vin + The rising timing is earlier than or equal to the signal t vin - When the rising timing is the same as that of signal t vin + Compared with the rising timing of the signal t vout + The rising timing of the signal t is delayed by a delay time α. Here, the delay time α is the propagation delay time of the activation function circuit 12. Further, vin - Compared with the rising timing of the signal t vin - The rising timing is delayed by a delay time α.

[0084] In which the signal t vin + The rising timing is later than the signal t vin -In the case of rising timing, with signal t vin - Compared with the rising timing of the signal t vout + The rising timing of the signal is delayed by a delay time α. Similarly, with the signal t vin - Compared with the rising timing of the signal t vout - The rising timing is delayed by a delay time α.

[0085] As described above, the activation function circuit 12 can perform the activation function processing without using the time-to-digital converter circuit. Further, the activation function circuit 12 can output the signal generated by the activation function operation to the timing circuit without using the digital-to-time converter circuit. In this way, the activation function circuit 12 can eliminate the need for the time-to-digital converter circuit and the digital-to-time converter circuit. Accordingly, the activation function circuit 12 can suppress the power consumption of the time-to-digital converter circuit and the digital-to-time converter circuit.

[0086] Furthermore, the activation function circuit 12 can eliminate the need for a time-to-digital converter circuit and a digital-to-time converter circuit. Accordingly, the activation function circuit 12 can reduce the area of ​​the circuit of the neural network device 1 occupied by the time-to-digital converter circuit and the digital-to-time converter circuit.

[0087] Furthermore, the activation function circuit 12 can be obtained by combining the circuit (the logic or circuit 21 in the first embodiment). Accordingly, compared with the case where nonlinear function processing is implemented by a digital signal processing circuit after time-to-digital conversion, the activation function circuit 12 can reduce the circuit size and suppress power consumption.

[0088] Furthermore, the activation function circuit 12 can suppress power consumption and enable the circuit to be reduced in size. Accordingly, the activation function circuit 12 can enable the number of layers of the neural network device 1 to be increased.

[0089] [Configuration and operation of the max pooling circuit]

[0090] The maximum pooling circuit 13 is a circuit that performs a maximum pooling process of extracting and outputting a larger signal of the output signals of the two activation function circuits 12 .

[0091] Figure 8 is a diagram showing a configuration of a maximum pooling circuit of a neural network device according to a first embodiment of the present disclosure.

[0092] The maximum pooling circuit 13 includes two first circuits 41 - 1 and 41 - 2 and a second circuit 42 .

[0093] One circuit, namely, the first circuit 41-1 includes an output signal S 4 The first time length signal output circuit 51, signal S 4 is a signal S representing the first input signal 2 The first timing of the change is related to the signal S as the second input signal 3 Change the time length between the first time length and the second timing signal.

[0094] Furthermore, the first circuit 41-1 includes a second time length signal output circuit 52. The second time length signal output circuit 52 generates a second time length signal based on the signal S as the enable control signal. 1 The timing output signal S 4 As the second time length signal S 6 .

[0095] Signal S 2 and S 3 and respectively as a signal t of the output signal of an activation function circuit 12 vout + and t vout - correspond.

[0096] The first time length signal output circuit 51 is an exclusive OR circuit (XOR gate circuit), which is a circuit for outputting the signal S 2 and signal S 3 A combinational circuit that performs an XOR operation.

[0097] The second time length signal output circuit 52 includes a circuit based on the signal S 4 The capacitor 62 is charged and based on the signal S as the enable control signal 1 The charging / discharging circuit 53 discharges the capacitor 62 .

[0098] The charge / discharge circuit 53 includes a first constant voltage source 61 outputting a reference potential Vref. Further, the charge / discharge circuit 53 includes a capacitor 62 having one end electrically connected to the first constant voltage source 61 and the other end electrically connected to the node N.

[0099] Further, the charging / discharging circuit 53 includes a first constant current source 64 having one end electrically connected to the power supply potential VDD on the high potential side. Further, the charging / discharging circuit 53 includes a first switch 65, wherein the input / output path is connected between the other end of the first constant current source 64 and the node N, and the signal S 4 is supplied to the control terminal.

[0100] Furthermore, the charging / discharging circuit 53 further includes a second constant current source 66, one end of which is connected to the standard potential. Further, the charging / discharging circuit 53 includes a second switch 67, wherein the input / output path is connected between the node N and the other end of the second constant current source 66, and the signal S 1 is supplied to the control terminal.

[0101] Further, the charging / discharging circuit 53 includes a third switch 63, wherein the input / output path is connected to both ends of the capacitor 62, and the signal S as a reset signal 0 is supplied to the control terminal.

[0102] The second time length signal output circuit 52 includes a comparator 69 in which an inverting input terminal is electrically connected to a second constant voltage source 68 outputting a reference potential Vref, and a non-inverting input terminal is electrically connected to a node N.

[0103] The comparator 69 converts the signal S 5 The signal S is compared with the reference potential Vref and 5 The high level signal S is output during the period when the reference potential Vref or greater 6 .

[0104] Another circuit, namely, the first circuit 41-2 includes an output signal S 9 The first time length signal output circuit 51, signal S 9 is a signal S representing the first input signal 7 The first timing of the change is related to the signal S as the second input signal 8 Change the time length between the first time length and the second timing signal.

[0105] Furthermore, the first circuit 41-2 includes a second time length signal output circuit 52. The second time length signal output circuit 52 generates a second time length signal based on the signal S 1 The timing output signal S 9 As signal S 11 (It is the second time length signal).

[0106] Signal S 7 and S 8 and the signal t as the output signal of another activation function circuit 12 vout + and t vout - correspond.

[0107] Since the circuit configuration of the first circuit 41 - 2 is similar to that of the first circuit 41 - 1 , a description thereof will be omitted.

[0108] The second circuit 42 includes a logic OR circuit (OR gate circuit) 71, which is a circuit for generating a signal S 6 and signal S 11 A combinational circuit that performs a logical OR operation.

[0109] Furthermore, the second circuit 42 includes a D-type first flip-flop 72, which is a first flip-flop 72 that generates a signal S as an output signal of the logic OR circuit 71. 12 The rising edge of the signal remains high (power supply potential VDD) and the output signal S 13 timing circuit.

[0110] Furthermore, the second circuit 42 includes an inverting circuit (NOT gate circuit) 73, which is used to make the signal S 12 Further, the second circuit 42 includes a D-type second flip-flop 74, which maintains a high level at the rising edge of the output signal of the inverting circuit 73 and outputs a signal S 14 timing circuit.

[0111] In the first embodiment, the second circuit 42 extracts and outputs the larger signal of the output signals of the two first circuits 41-1 and 41-2. However, the present disclosure is not limited to this. The second circuit 42 can extract and output the maximum signal among the output signals of three or more first circuits. For example, the logic or circuit 71 can be a 3-input logic or circuit, and the three first circuits can be electrically connected to the three input parts of the logic or circuit 71.

[0112] Fig. 9 : is a timing chart showing the operation timing of the maximum pooling circuit of the neural network device according to the first embodiment of the present disclosure.

[0113] The time period from timing 0 to the predetermined timing T is the reset time period. 11 To timing t 12 During the time period, the signal S as a reset signal 0 rises to a high level.

[0114] When the signal S 0 At the timing t 11 When the signal S having the potential of the node N rises to a high level, the third switch 63 in the first circuit 41-1 is turned on, thereby short-circuiting both ends of the capacitor 62. 5 Indicates the reference potential Vref.

[0115] Similarly, the third switch 63 in the first circuit 41-2 is turned on, thereby short-circuiting both ends of the capacitor 62. Accordingly, the signal S as the potential of the node N is 10 Indicates the reference potential Vref.

[0116] The time period from the timing T to the predetermined timing 2T corresponds to the charging cycle.

[0117] At the timing t 13 , a signal S as a first input signal of the first circuit 41 - 2 7 rises to a high level. Because the signal S 7 rises to a high level, so the first time length signal output circuit 51 as an XOR circuit outputs a high level signal S 9 When the signal S 9 When the signal S is raised to a high level, the first switch 65 is turned on. Since the first switch 65 is turned on, the first constant current source 64 charges the capacitor 62. Accordingly, the signal S as the potential of the node N is 10 Linear increase.

[0118] At the timing t 14 , a signal S as a first input signal of the first circuit 41 - 1 2 rises to a high level. Because the signal S 2 rises to a high level, so the first time length signal output circuit 51 as an XOR circuit outputs a high level signal S 4 When the signal S 4 When the signal S is raised to a high level, the first switch 65 is turned on. Since the first switch 65 is turned on, the first constant current source 64 charges the capacitor 62. Accordingly, the signal S as the potential of the node N is 5 (Linear increase.

[0119] At the timing t 15 , as the signal S of the second input signal of the first circuit 41 - 1 3 rises to a high level. Because the signal S 3 rises to a high level, so the first time length signal output circuit 51 as an XOR circuit outputs a low level signal S 4 When the signal S 4 When the voltage drops to a low level, the first switch 65 is turned off. Since the first switch 65 is turned off, the capacitor 62 is not charged. Accordingly, the signal S as the potential of the node N is 5 Stop rising and remain at a constant level.

[0120] Here, when the current value of the first constant current source 64 is Icharge, the capacitance value of the capacitor 62 is C, and from the timing t 14 To timing t 15 The length of time is ΔTcharge, and the voltage Vc of the capacitor 62 is expressed by the following equation (3):

[0121] Vc=(Icharge / C)*ΔTcharge+Vref (3)

[0122] At the timing t 16 , a signal S as a second input signal of the first circuit 41 - 2 8 rises to a high level. Because the signal S 8 rises to a high level, so the first time length signal output circuit 51 as an XOR circuit outputs a low level signal S 9 Because the signal S 9 The first switch 65 is turned off because the first switch 65 is turned off, so the capacitor 62 is not charged. Therefore, the signal S as the potential of the node N is 10 Stop rising to a constant level.

[0123] At this time, the voltage Vc of the capacitor 62 of the first circuit 41 - 2 is expressed by the above equation (3).

[0124] A period from the timing 2T to the predetermined timing 3T is defined as an output period.

[0125] At timing 2T, the signal S serving as the enable control signal 1 rises to a high level.

[0126] In the first circuit 41-1, the signal S 1 is at a high level, and thus, the second switch 67 is turned on. Since the second switch 67 is turned on, the second constant current source 66 discharges the capacitor 62. Accordingly, the signal S having the potential of the node N is 5 According to the above formula (3), at the timing 2T, the signal S 5 The potential of is higher than the reference potential Vref. Accordingly, the comparator 69 outputs a high level signal S 6 .

[0127] Similarly, in the first circuit 41-2, the signal S 1 is at a high level, and thus, the second switch 67 is turned on. Since the second switch 67 is turned on, the second constant current source 66 discharges the capacitor 62. Therefore, the signal S as the potential of the node N 10 According to the above formula (3), at the timing 2T, the signal S 10 The potential of is higher than the reference potential Vref. Therefore, the comparator 69 outputs a high level signal S 11 .

[0128] In the second circuit 42, because the signal S 6 and signal S 11 rises to a high level, so the logic OR circuit 71 outputs a high level signal S 12 Because the signal S 12rises to a high level, so the first flip-flop 72 remains at the high level of a predetermined potential (here, the power supply potential VDD) and outputs a high-level signal S 13 .

[0129] At timing t 17 , the signal S of the potential of the node N having the first circuit 41-1 5 drops below the reference potential Vref. Accordingly, the comparator 69 outputs a low-level signal S 6 .

[0130] Here, when the current value of the second constant current source 66 is Idischarge, the time length ΔTdischarge from timing 2T to timing t is expressed by the following formula (4) 17 .

[0131] ΔTdischarge

[0132] =(Vc - Vref) / (Idischarge / C)

[0133] =(Icharge / Idischarge)*ΔTcharge (4)

[0134] Therefore, the time length ΔTdischarge is directly proportional to the time length ΔTcharge. That is, the discharge time is directly proportional to the charge time.

[0135] When Idischrage = Icharge, the charge / discharge circuit 53 can set the time length ΔTdischarge to be equal to the time length ΔTcharge. That is, the charge / discharge circuit 53 can set the discharge time to be equal to the charge time.

[0136] When Idischrage < Icharge, the charge / discharge circuit 53 can set the time length ΔTdischarge to be longer than the time length ΔTcharge. That is, the charge / discharge circuit 53 can set the discharge time to be longer than the charge time. With this setting, the charge / discharge circuit 53 can also obtain an amplification function for the input time information.

[0137] At timing t 18 , the signal S of the potential of the node N having the first circuit 41-2 10 drops below the reference potential Vref. Accordingly, the comparator 69 outputs a low-level signal S 11 .

[0138] At this time, the time length ΔTdischarge from timing 2T to timing t is expressed by the above formula (4) 18 .

[0139] In the second circuit 42, because the signal S 6 and signal S 11 drops to a low level, so the logic OR circuit 71 outputs a low level signal S 12 .

[0140] Because the signal S 6 The rising edge of the signal S 11 The timing of the rising edge of the signal S 6 With signal S 11 The logic OR circuit 71 can output the signal S 11 Signals S with the same time length 12 .

[0141] Because the signal S 12 The second flip-flop 74 maintains a high level at a predetermined potential (here, the power supply potential VDD) and outputs a high level signal S 14 .

[0142] In the pulse signal (signal S 12 ), rather than a differential signal (signal S 13 and signal S 14 ) is sufficient as a signal for the next layer, the second circuit 42 can omit the first trigger 24, the inverting circuit 73, and the second trigger 25.

[0143] As described above, when the signal S is used as the output signal of the activation function circuit 12 2 and S 3 and the signal S as the output signal of another activation function circuit 12 7 and S 8 When comparing, the maximum pooling circuit 13 extracts the signal S as the larger signal. 7 and signal S 8 Then, the maximum pooling circuit 13 outputs the time difference and the extracted signal S 7 and signal S 8 The time difference between the same signal S 13 and signal S 14 With this configuration, the maximum pooling circuit 13 can implement maximum pooling processing.

[0144] The max pooling circuit 13 can perform max pooling processing without the need to use a time-to-digital converter circuit. Further, the max pooling circuit 13 can output the max pooling result signal to the timing circuit without the need to use a digital-to-time converter circuit. Similarly, the max pooling circuit 13 can eliminate the need for a time-to-digital converter circuit and a digital-to-time converter circuit. Accordingly, the max pooling circuit 13 can suppress the power consumption of the time-to-digital converter circuit and the digital-to-time converter circuit.

[0145] In addition, the max pooling circuit 13 can eliminate the need for a time-to-digital converter circuit and a digital-to-time converter circuit. Accordingly, the max pooling circuit 13 can enable the circuit of the neural network device 1 to reduce the area occupied by the time-to-digital converter circuit and the digital-to-time converter circuit.

[0146] Further, the max pooling circuit 13 can suppress power consumption and reduce the circuit size. Accordingly, the max pooling circuit 13 can enable an increase in the number of layers of the neural network device 1.

[0147] Further, when the max pooling circuit 13 is adjusted to achieve Idischrage < Icharge, the time length ΔTdischarge can be set to be longer than the time length ΔTcharge. That is, the max pooling circuit 13 can set the discharge time to be longer than the charging time. With this setting, the max pooling circuit 13 can also amplify the input time information.

[0148] [Summary]

[0149] As described above, the activation function circuit 12 can perform activation function processing without the need to use a time-to-digital converter circuit. Further, the activation function circuit 12 can output the signal generated by the activation function operation to the timing circuit without the need to use a digital-to-time converter circuit. In this way, the activation function circuit 12 can eliminate the need for a time-to-digital converter circuit and a digital-to-time converter circuit. Accordingly, the activation function circuit 12 can suppress the power consumption of the time-to-digital converter circuit and the digital-to-time converter circuit.

[0150] Further, the activation function circuit 12 can eliminate the need for a time-to-digital converter circuit and a digital-to-time converter circuit. Accordingly, the activation function circuit 12 can enable the circuit of the neural network device 1 to reduce the area occupied by the time-to-digital converter circuit and the digital-to-time converter circuit.

[0151] Further, the activation function circuit 12 can be obtained by combining the circuit (the logic or circuit 21 in the first embodiment). Accordingly, the activation function circuit 12 can reduce the circuit size and suppress power consumption compared to the case where nonlinear function processing is implemented by digital signal processing after time-to-digital conversion.

[0152] Furthermore, the activation function circuit 12 can suppress power consumption and reduce the circuit size. Accordingly, the activation function circuit 12 can increase the number of layers of the neural network device 1.

[0153] (Second Embodiment)

[0154] Fig.10 is a diagram showing a configuration of an activation function circuit according to a second embodiment of the present disclosure.

[0155] The activation function circuit 12 of the first embodiment (refer to Figure 4 ), the activation function circuit 12A further includes a logic OR circuit (OR gate circuit) 22.

[0156] The logical OR circuit 22 is an example of a second logical circuit of the present disclosure.

[0157] The logic OR circuit 22 performs the operation on the signal t vin - and signal t vin - Performs a logical OR operation and outputs a signal t as a result of the logical OR operation vout - Signal t vin - With signal t vin - The logical sum (or) and signal t vin - same.

[0158] In the activation function circuit 12A, the signal t vout + The delay time is the delay time of the logic OR circuit 21, and the signal t vout - The delay time of is the delay time of the logic OR circuit 22. Here, the delay time of the logic OR circuit 21 is the same as the delay time of the logic OR circuit 22.

[0159] Therefore, the activation function circuit 12A can suppress the signal t vout + The delay time and signal t vout - The difference between the delay times.

[0160] It should be noted that the activation function circuit 12A may include another combinational circuit, for example, a buffer circuit, instead of the logic OR circuit 22. However, from the viewpoint of suppressing the difference in delay time from the logic OR circuit 21, the activation function circuit 12A preferably includes the logic OR circuit 22 having the same delay time as that of the logic OR circuit 21.

[0161] (Third Embodiment)

[0162] Fig.11 is a diagram showing a configuration of an activation function circuit according to a third embodiment of the present disclosure.

[0163] The activation function circuit 12 of the first embodiment (refer to Figure 4 ), the activation function circuit 12B further includes a combinational circuit 23, a first trigger 24, and a second trigger 25.

[0164] The combinational circuit 23 is an example of a third logic circuit of the present disclosure. The first flip-flop 24 is an example of a first sequential circuit of the present disclosure. The second flip-flop 25 is an example of a second sequential circuit of the present disclosure.

[0165] The combinational circuit 23 includes a first buffer circuit group 26 having a plurality of buffer circuits (delay circuits) connected in multiple stages, a second buffer circuit group 27 having a plurality of buffer circuits (delay circuits) connected in multiple stages, and an exclusive OR circuit 28 .

[0166] The first buffer circuit group 26 delays the output signal of the logical OR circuit 21 and outputs the signal to one input terminal of the exclusive OR circuit 28. The second buffer circuit group 27 delays the output signal of the logical OR circuit 21 and outputs the signal to one input terminal of the exclusive OR circuit 28. vin - The signal is delayed and output to the other input terminal of the exclusive OR circuit 28 .

[0167] The D-type first flip-flop 24 holds the output signal of the logic OR circuit 21 at the rising edge and falling edge of the output signal S of the combinational circuit 23, and outputs the signal t vout + .

[0168] The D-type second flip-flop 25 holds the signal t vin - At the rising edge and falling edge of the output signal S of the combinational circuit 23, and the output signal t vout - .

[0169] The combinational circuit 23 includes a first buffer circuit group 26 and a second buffer circuit group 27 to ensure the setup time of the first flip-flop 24 and the second flip-flop 25 .

[0170] The first buffer circuit group 26 delays the output signal of the logic OR circuit 21, and the second buffer circuit group 27 delays the output signal of the logic OR circuit 21. vin - Accordingly, the output signal of the logic OR circuit 21 and the signal t vin - The output signal S of the XOR circuit 28 is input to the first flip-flop 24 and the second flip-flop 25 at the timing.

[0171] This ensures the setup time of the first flip-flop 24 so that the output signal of the logic OR circuit 21 can be reliably maintained. Similarly, the setup time of the second flip-flop 25 is ensured so that the signal t vin - .

[0172] It should be noted that the signal t vin + Through the logic OR circuit 21, the signal t is input to the first trigger 24, and without passing through the logic circuit, the signal t vin - is input to the second flip-flop 25. Therefore, it is preferable to set the number of buffer circuits in the second buffer circuit group 27 to be greater than the number of buffer circuits in the first buffer circuit group 26. As shown in the example, the first buffer circuit group 26 includes three buffer circuits, and the second buffer circuit group 27 includes four buffer circuits.

[0173] In the activation function circuit 12B, the first flip-flop 24 holds the output signal of the logic OR circuit 21 and outputs a signal t vout + Furthermore, the second flip-flop 25 holds the signal t vin - And the output signal t vout - Therefore, the first flip-flop 24 holds the output signal of the logic OR circuit 21 and the second flip-flop 25 holds the signal t vin - After that, the multiplication and accumulation circuit 11 (reference Figure 2 ) can stop signal t vin + and signal t vin - With this configuration, the multiply-accumulate operation circuit 11 in the previous stage can start the subsequent multiply-accumulate operation.

[0174] This enables the activation function circuit 12B to achieve high-speed neural operations.

[0175] (Fourth Embodiment)

[0176] Fig.12 is a diagram showing a configuration of an activation function circuit according to a fourth embodiment of the present disclosure.

[0177] The activation function circuit 12B of the third embodiment (refer to Fig.11 ) compared to the activation function circuit 12C further includes a logic OR circuit 22 (refer to the second embodiment of the present invention Fig.10 ). Compared with the activation function circuit 12B of the third embodiment, the activation function circuit 12C includes a combinational circuit 23A instead of the combinational circuit 23.

[0178] The combined circuit 23 of the third embodiment (see Fig.11 ) Compared with the combinational circuit 23A, the combinational circuit 23A includes the second buffer circuit group 27A instead of the second buffer circuit group 27.

[0179] In the activation function circuit 12C, the signal t vin + Through the logic OR circuit 21, it is input to the first flip-flop 24, and the signal t vin - The signal is input to the second flip-flop 25 through the logic OR circuit 22 .

[0180] Therefore, it is preferable to set the number of buffer circuits in the second buffer circuit group 27A equal to the number of buffer circuits in the first buffer circuit group 26. As shown in the example, the first buffer circuit group 26 includes three buffer circuits, and the second buffer circuit group 27A includes three buffer circuits.

[0181] Activation function circuit 12C is similar in operation to activation function circuit 12B.

[0182] In the fourth embodiment, the combinational circuit 23A includes the first buffer circuit group 26 and the second buffer circuit group 27A located on the input terminal side of the exclusive OR circuit 28. However, the present disclosure is not limited thereto. The combinational circuit 23A may include one buffer circuit group located on the output terminal side of the exclusive OR circuit 28 instead of the first buffer circuit group 26 and the second buffer circuit group 27A. This makes it possible to suppress the number of buffer circuits.

[0183] (Fifth Embodiment)

[0184] Fig.13 is a diagram showing a configuration of a maximum pooling circuit according to a fifth embodiment of the present disclosure.

[0185] The maximum pooling circuit 13 of the first embodiment (see Figure 8) Compared with the first circuit 41-1 and the second circuit 41-2, the maximum pooling circuit 13A includes the first circuits 41-1A and 41-2A instead of the first circuits 41-1 and 41-2.

[0186] With the first circuit 41-1 (reference Figure 8 ) Compared with the first circuit 41-1A, the first circuit 41-1A includes the second time length signal output circuit 52A instead of the second time length signal output circuit 52.

[0187] The second time length signal output circuit 52 (reference Figure 8 ) Compared with the second time length signal output circuit 52A, the second time length signal output circuit 52A includes a charging / discharging circuit 53A instead of the charging / discharging circuit 53.

[0188] With the charge / discharge circuit 53 (reference Figure 8 ), the charge / discharge circuit 53A includes a resistor 64A instead of the first constant current source 64. Compared with the charge / discharge circuit 53, the charge / discharge circuit 53A includes a resistor 66A instead of the second constant current source 66.

[0189] Since the circuit configuration of the first circuit 41 - 2A is similar to that of the first circuit 41 - 1A, a description thereof will be omitted.

[0190] When the first switch 65 is turned on, the capacitor 62 is charged from the power supply potential VDD via the resistor 64A. Further, when the second switch 67 is turned on, the capacitor 62 is discharged via the resistor 66A.

[0191] Here, the resistance value of the resistor 64A is Rcharge, the resistance value of the resistor 66A is Rdischarge, and the capacitance value of the capacitor 62 is C. The time constant of the RC series circuit formed by the resistor 64A and the capacitor 62 is (Rcharge*C). The time constant of the RC series circuit formed by the resistor 66A and the capacitor 62 is (Rdischarge*C). When the charging time is sufficiently shorter than the time constant (Rcharge*C) and the discharging time is sufficiently shorter than the time constant (Rdischarge*C), the following equations (5) and (6) hold as approximate equations.

[0192] Vc≈((VDD / Rcharge) / C)*ΔTcharge+Vref (5)

[0193] ΔTdischarge

[0194] ≈(Vc-Vref) / (VDD / Rdischarge / C)

[0195] = (Rdischarge / Rcharge) * ΔTcharge (6)

[0196] In this way, the max-pooling circuit 13A can perform operations similar to those of the max-pooling circuit 13.

[0197] Furthermore, when adjusted such that Rcharge < Rdischarge, the max-pooling circuit 13A can set the time length ΔTdischarge to be longer than the time length ΔTcharge. That is, the max-pooling circuit 13A can set the discharge time to be longer than the charge time. With this setting, the max-pooling circuit 13A can also amplify the input time information.

[0198] (Sixth Embodiment)

[0199] Fig.14 FIG. is a diagram showing the configuration of the max-pooling circuit according to the sixth embodiment of the present disclosure.

[0200] Compared with the max-pooling circuit 13 of the first embodiment (refer to Figure 8 ), the max-pooling circuit 13B includes first circuits 41-1B and 41-2B instead of the first circuits 41-1 and 41-2.

[0201] Compared with the first circuit 41-1 (refer to Figure 8 ), the first circuit 41-1B includes a second time length signal output circuit 52B instead of the second time length signal output circuit 52.

[0202] Compared with the second time length signal output circuit 52 (refer to Figure 8 ), the second time length signal output circuit 52B includes a charge / discharge circuit 53B instead of the charge / discharge circuit 53.

[0203] Compared with the charge / discharge circuit 53 (refer to Figure 8 ), the charge / discharge circuit 53B does not include the first constant voltage source 61 or the second constant voltage source 68.

[0204] In both the first circuit 41-1B and the first circuit 41-2B, a reference potential Vref is supplied from one first constant voltage source 61 to one end of the capacitor 62 of the charge / discharge circuit 53B and the inverting terminal of the comparator 69.

[0205] Therefore, compared with the max-pooling circuit 13, the max-pooling circuit 13B can reduce the number of constant voltage sources.

[0206] (Seventh Embodiment)

[0207] Fig.15is a diagram showing a configuration of a comparator of a maximum pooling circuit according to a seventh embodiment of the present disclosure.

[0208] In the above-mentioned embodiments, in the case where the time length error due to the deviation of the comparator 69 can be tolerated, the comparator 69 does not need to have the deviation removal function. Fig.15 As shown in FIG. 1 , when the time length error due to the deviation of the comparator 69 cannot be tolerated, it is preferable that the comparator 69 has a deviation removal function.

[0209] The comparator 69 includes a first circuit 91 , a second circuit 92 , and a third circuit 93 .

[0210] The first circuit 91, which is a differential pair circuit, includes a capacitor 121. The first circuit 91 further includes N-channel transistors 122, 123, and 125. The first circuit 91 further includes P-channel transistors 124 and 126.

[0211] The source of the transistor 122 is connected to a standard potential. A predetermined bias potential Vbias is input to the gate of the transistor 122. The drain of the transistor 122 is electrically connected to the source of the transistor 123 and the source of the transistor 125.

[0212] The signal S is converted to 5 Input to the gate of transistor 123. The drain of transistor 123 is electrically connected to the drain and gate of transistor 124.

[0213] The source of the transistor 124 is electrically connected to the power supply potential VDD.

[0214] The reference potential Vref is input to the gate of the transistor 125. The drain of the transistor 125 is electrically connected to the node N 1 .

[0215] The drain of transistor 126 is electrically connected to node N 1 The gate of the transistor 126 is electrically connected to the gate and drain of the transistor 124. The source of the transistor 126 is electrically connected to the power supply potential VDD.

[0216] The second circuit 92 includes an N-channel transistor 127 , a P-channel transistor 129 , and a capacitor 128 .

[0217] The source of the transistor 127 is electrically connected to the standard potential. The bias potential Vbias is input to the gate of the transistor 127. The drain of the transistor 127 is electrically connected to the node N 2 .

[0218] The drain of transistor 129 is electrically connected to node N 2The gate of transistor 129 is electrically connected to node N 1 The source of the transistor 129 is electrically connected to the power supply potential VDD.

[0219] One end of the capacitor 128 is electrically connected to the node N 2 The other end of capacitor 128 is electrically connected to node N via switch 137. 1 The signal S will be used as the reset signal 0 Input to the control terminal of switch 137.

[0220] The switch 136 is electrically connected between the gate of the transistor 123 and the node N 2 The signal S that will be used as the reset signal 0 Input to the control terminal of switch 136.

[0221] The third circuit 93 includes switches 130 , 133 , and 135 , an N-channel transistor 131 , a P-channel transistor 132 , and an inverter circuit (inverter circuit) 134 .

[0222] The source of the transistor 131 is electrically connected to the standard potential via the switch 130. The signal S as the enable control signal 1 The gate of transistor 131 is electrically connected to node N 2 The drain of transistor 131 is electrically connected to node N 3 .

[0223] The drain of transistor 132 is connected to node N 3 The gate of transistor 132 is electrically connected to node N 2 The source of the transistor 132 is electrically connected to the power supply potential VDD via the switch 133. 1 Input to the control terminal of the switch 133.

[0224] The inverting circuit 134 makes the signal S 1 Invert and invert the signal S 1 The output is to the control terminal of the switch 135. The switch 135 is electrically connected to the node N 3 Between the standard potential.

[0225] The third circuit 93 is connected from the node N 3 Output signal S 6 .

[0226] In the signal S 5 When the potential of the node N is lower than the reference potential Vref, the first circuit 91 as the differential pair circuit is connected to the node N 1 Output low level signal. Further, when the signal S 5When the potential of the node N is higher than the reference potential Vref, the first circuit 91 1 Output high level signal.

[0227] At the node N from the second circuit 92 1 When a low level signal is input, transistor 129 is turned on and the 2 Output a high level signal. Further, at the node N of the second circuit 92 1 When a high level signal is input, transistor 129 is turned off and the 2 Outputs a low level signal.

[0228] In the third circuit 93, when the signal S serving as the enable control signal 1 At high level and from node N 2 When a high level signal is input, transistor 131 is turned on and the 3 Output low level signal S 6 .

[0229] In the third circuit 93, when the signal S serving as the enable control signal 1 At high level and from node N 2 When a low level signal is input, transistor 132 is turned on and the 3 Output high level signal S 6 .

[0230] When the signal S is used as the enable control signal 1 When it drops to a low level, transistors 131 and 132 are turned off, switch 135 is turned on, and node N 3 Therefore, the third circuit 93 is connected from the node N 3 Output low level signal S 6 .

[0231] Furthermore, the comparator 69 uses the signal S as a reset signal. 0 As the deviation information acquisition signal. When the signal S 0 When it rises to a high level, node N 1 and node N 2 The node N is electrically connected via the capacitor 128. 2 The gates of transistors 123 are electrically connected to each other.

[0232] Thus, the comparator 69 first stores the charge representing the deviation information of the comparator 69 in the capacitor 121. Then, the comparator 69 performs the signal S 5 The comparison operation with the reference potential Vref realizes the comparator function without deviation.

[0233] The effects described in this specification are merely examples, and thus, there may be other effects without being limited to the exemplified effects.

[0234] It should be noted that the present technology can also have the following configurations.

[0235] (1) A signal processing circuit,

[0236] When the first timing of the change of the first input signal is earlier than or the same as the second timing of the change of the second input signal, the first output signal is output at the first timing and the second output signal is output at the second timing, and when the first timing is later than the second timing, the first output signal and the second output signal are output at the second timing.

[0237] (2) The signal processing circuit according to (1), comprising:

[0238] The first logic circuit performs a logic operation on a first input signal and a second input signal and outputs a first output signal.

[0239] (3) The signal processing circuit according to (2),

[0240] The first logic circuit is a logic OR circuit that performs a logic OR operation on a first input signal and a second input signal and outputs a first output signal.

[0241] (4) The signal processing circuit according to (2) or (3),

[0242] The second input signal is output as the second output signal.

[0243] (5) The signal processing circuit according to (2) or (3), further comprising:

[0244] The second logic circuit performs a logic operation on the second input signal and outputs a second output signal.

[0245] (6) The signal processing circuit according to (5),

[0246] The circuit delay time of the second logic circuit is the same as the circuit delay time of the first logic circuit.

[0247] (7) The signal processing circuit according to (5) or (6),

[0248] The second logic circuit is a logic OR circuit that performs a logic OR operation on the second input signal and the second input signal and outputs a second output signal.

[0249] (8) The signal processing circuit according to any one of (2) to (7), further comprising:

[0250] a third logic circuit that performs a logic operation on the first output signal and the second output signal and outputs a timing signal indicating a timing at which the first output signal and the second output signal are maintained;

[0251] a first sequential circuit that holds and outputs a first output signal based on a timing signal; and

[0252] The second sequential circuit holds and outputs a second output signal based on the timing signal.

[0253] (9) The signal processing circuit according to (8),

[0254] Wherein, each of the first sequential circuit and the second sequential circuit is a trigger.

[0255] (10) A signal processing device comprising:

[0256] a multiply-add operation circuit that performs a first multiply-add operation of multiplying and adding a plurality of signals by coefficients of a first group and outputs a first signal, and performs a second multiply-add operation of multiplying and adding a plurality of signals by coefficients of a second group and outputs a second signal; and

[0257] A signal processing circuit that outputs a first output signal at a first timing and a second output signal at a second timing when a first timing at which a first signal changes is earlier than or the same as a second timing at which a second signal changes, and that outputs a first output signal and a second output signal at a second timing when the first timing is later than the second timing.

[0258] (11) The signal processing circuit according to (10), further comprising:

[0259] A second signal processing circuit is electrically connected to the plurality of signal processing circuits and outputs a first output signal and a second output signal having a longest time length between a first timing at which the first output signal changes and a second timing at which the second output signal changes.

[0260] (12) The signal processing device according to (10) or (11),

[0261] Among them, the coefficients of the first group are coefficients representing positive loads respectively; and

[0262] The coefficients of the second group are coefficients respectively indicating the absolute values ​​of the negative loads.

[0263] (13) A signal processing method, comprising:

[0264] In a case where a first timing at which the first input signal changes is earlier than or the same as a second timing at which the second input signal changes, outputting a first output signal at the first timing and outputting a second output signal at the second timing; and

[0265] When the first timing is later than the second timing, the first output signal and the second output signal are output at the second timing.

[0266] Reference Numbers List

[0267] 1 Neural Network Equipment

[0268] 2 First layer circuit

[0269] 3 First layer circuit

[0270] 4 Layer 2 Circuit

[0271] 5 Second layer circuit

[0272] 11 Multiplication and accumulation circuit

[0273] 11p First multiplication and accumulation circuit

[0274] 11m Second multiplication and accumulation circuit

[0275] 12 Activation Function Circuit

[0276] 12A Activation Function Circuit

[0277] 12B activation function circuit

[0278] 12C activation function circuit

[0279] 13 Max Pooling Circuit

[0280] 13A Max Pooling Circuit

[0281] 13B Max Pooling Circuit

[0282] 21 Logic OR Circuit

[0283] 22 Logic OR Circuit

[0284] 23 Combinational Circuits

[0285] 23A Combination Circuit

[0286] 24 First Trigger

[0287] 25 Second trigger

[0288] 26. First buffer circuit group

[0289] 27 Second buffer circuit group

[0290] 27A Second buffer circuit group

[0291] 28 XOR circuit

[0292] 41-1 First Circuit

[0293] 41-1A First Circuit

[0294] 41-1B First Circuit

[0295] 41-2 First Circuit

[0296] 41-2A First Circuit

[0297] 41-2B First Circuit

[0298] 42 Second Circuit

[0299] 51 First time length signal output circuit

[0300] 52 Second time length signal output circuit

[0301] 52A Second time length signal output circuit

[0302] 52B Second time length signal output circuit

[0303] 53 Charging / amplifying circuit

[0304] 53A charging / amplifying circuit

[0305] 53B Charging / amplifying circuit

[0306] 69 Comparator

[0307] 91 First Circuit

[0308] 92 Second Circuit

[0309] 93 3rd Circuit.

Claims

1. An activation function circuit, comprising: A first input terminal configured to receive an input of a first input signal; A second input terminal configured to receive an input of a second input signal; A first output terminal, configured to output a first output signal; A second output terminal is configured to output a second output signal; The first logic circuit comprises: A first terminal connected to the first input terminal and configured to receive the first input signal from the first input terminal; a second terminal connected to the second input terminal and configured to receive the second input signal from the second input terminal; and a third terminal connected to the first output terminal and configured to output the first output signal to the first output terminal, wherein the first logic circuit is configured to perform a logic operation on the first input signal received from the first terminal and the second input signal received from the second terminal and output the first output signal from the third terminal, wherein, in a case where a first timing at which the first input signal changes is earlier than or the same as a second timing at which the second input signal changes, the first output signal is output at the first timing and the second output signal is output at the second timing, and in a case where the first timing is later than the second timing, the first output signal and the second output signal are output at the second timing, The activation function circuit further comprises: a second logic circuit that performs a logic operation on the second input signal and outputs the second output signal, The circuit delay time of the second logic circuit is the same as the circuit delay time of the first logic circuit.

2. The activation function circuit according to claim 1, in, The first logic circuit is a logic OR circuit that performs a logic OR operation on the first input signal and the second input signal and outputs the first output signal.

3. The activation function circuit according to claim 1, in, The second input signal is output as the second output signal.

4. The activation function circuit according to claim 1, in, The second logic circuit is a logical OR circuit that performs a logical OR operation on the second input signal and the second input signal and outputs the second output signal.

5. The activation function circuit according to claim 1 further comprises: a third logic circuit that performs a logic operation on the first output signal and the second output signal and outputs a timing signal indicating a timing at which the first output signal and the second output signal are maintained; a first sequential circuit, which maintains and outputs the first output signal based on the timing signal; as well as The second sequential circuit holds and outputs the second output signal based on the timing signal.

6. The activation function circuit according to claim 5, in, Each of the first sequential circuit and the second sequential circuit is a flip-flop.

7. A signal processing device, comprising: a multiply-add operation circuit that performs a first multiply-add operation of multiplying and adding a plurality of signals by coefficients of a first group and outputs a first signal, and performs a second multiply-add operation of multiplying and adding the plurality of signals by coefficients of a second group and outputs a second signal; and An activation function circuit according to any one of claims 1 to 6.

8. The signal processing device according to claim 7, further comprising: A maximum pooling circuit is electrically connected to the plurality of activation function circuits and outputs the first output signal and the second output signal, wherein the first output signal and the second output signal have a longest time length between a first timing at which the first output signal changes and a second timing at which the second output signal changes.

9. The signal processing device according to claim 7, in, The coefficients of the first group are coefficients respectively representing positive loads; and The coefficients of the second group are coefficients respectively indicating absolute values ​​of negative loads.

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