Vertical power transistor and method for manufacturing a vertical power transistor

Abstract

The invention relates to a vertical power transistor (1) having a semiconductor substrate (2), the semiconductor substrate comprising a first semiconductor material and having at least one epitaxial layer (3), wherein a trench structure extends from a surface of the semiconductor substrate (2) into the interior of the at least one epitaxial layer (3), characterized in that the trench structure has a first region (13), the first region extending from a trench bottom to a determined height of the respective trench, wherein the first region (13) comprises a first partial region, the first partial region having a first depth (t1) and a first width (w1), wherein the first partial region extends substantially perpendicular to the surface of the semiconductor substrate (2), wherein the first region (13) comprises a second partial region, the second partial region having a second depth and a second width (w2), wherein the second partial region has a first inclination angle relative to the surface of the semiconductor substrate (2), wherein the first region (13) comprises a third partial region, the third partial region having a third depth and a third width, wherein the third partial region has a second inclination angle relative to the surface of the semiconductor substrate (2), wherein the first region (13) is electrically conductively connected to a source junction.

Description

Technical Field

[0001] The present invention relates to a vertical power transistor having a specifically shaped trench structure and a method for manufacturing the vertical power transistor. Background Art

[0002] In vertical power transistors, shielding of the gate oxide against high field strengths when a high positive voltage is applied between drain and source in blocking operation and in the event of a short circuit is problematic. Furthermore, limiting the short-circuit current is difficult.

[0003] Different possibilities for shielding the gate oxide are known from the prior art. One possibility is to embed or dig out a p-doped region in the epitaxial layer below the trench structure of the power transistor. The p-doped region is electrically connected to the source region of the power transistor. Due to the position of the p-doped region below the MIS head, the p-doped region shields the high field strengths of the MIS head and significantly contributes to limiting the short-circuit current.

[0004] The disadvantage here is that an additional epitaxial step is required for producing the recessed p-region, which is associated with high costs and additional process risks.

[0005] Another possibility is to produce a deep-reaching p+ region by implantation at the side of the MIS head. Here, the implantation of this region is deeper than the implantation of the MIS head, so that the MIS head is shielded from high field strengths.

[0006] Disadvantages here are that high energies have to be used for deep implantation, which results in high costs, leads to severe damage to the semiconductor crystal, and lateral ion scattering changes the field dimensions (Pitchmaβ). Summary of the invention

[0007] The object of the present invention is to improve the effective power of a vertical power transistor.

[0008] A vertical power transistor has a semiconductor substrate comprising a first semiconductor material and having at least one epitaxial layer. A trench structure extends from the surface of the semiconductor substrate to the interior of the at least one epitaxial layer. According to the present invention, the trench structure has a first region, which extends from the bottom of the trench to a determined height of the corresponding trench. The first region includes a first partial region, which has a first depth and a first width. The first partial region extends substantially perpendicular to the surface of the semiconductor substrate. Here, the concept "substantially" indicates that manufacturing tolerances are included. The first region includes a second partial region, which has a second depth and a second width. The second partial region has a first inclination angle relative to the surface of the semiconductor substrate. The first region includes a third partial region, which has a third depth and a third width. The third partial region has a second inclination angle relative to the surface of the semiconductor substrate. The first region is electrically connected to the source joint.

[0009] The advantage here is that the first sub-region and the second sub-region have a small lateral distance with respect to one another, so that the space requirement is small.

[0010] In one embodiment, the first region has a fourth subregion which extends substantially perpendicularly to the surface of the semiconductor substrate. The fourth subregion has a fourth depth and a fourth width, wherein the fourth depth is greater than the first depth.

[0011] Advantageously, the side walls of the fourth partial region are arranged perpendicular to the surface of the semiconductor substrate, so that the channel length of the vertical power transistor is minimized, thereby minimizing the channel resistance.

[0012] In a further embodiment, a first layer having a first doping is arranged on the surface of the first region. The first doping has a first charge carrier type that is different from a second charge carrier type of a second doping of the epitaxial layer.

[0013] The advantage here is that only small leakage currents occur.

[0014] In one configuration, the first region is at least partially filled with a second semiconductor material, wherein the second semiconductor material has a third doping of at least 1E13 cm^-3.

[0015] Advantageously, the gate oxide is shielded from high electric field strengths in the blocking case, ie when a high voltage is applied to the vertical power transistor between drain and source, and the current flow in the event of a short circuit is effectively limited since the electric field is directed away from the gate oxide via the space charge region of the first region.

[0016] In other configurations, the second semiconductor material includes polysilicon or 3C-SiC.

[0017] The advantage here is that heterojunctions are formed between the epitaxial layer and the partial region filled with the second semiconductor material. These heterojunctions form an energy barrier, i.e. they are rectifying and thus limit the current in the case of a short circuit and keep the electric field away from the gate oxide in blocking operation. In addition, the breakdown voltage when the vertical power transistor is operated in the fourth quadrant of the transistor characteristic field is lower than the breakdown voltage in a component without heterojunctions.

[0018] In one embodiment, the first semiconductor material includes silicon carbide.

[0019] The method for manufacturing a vertical power transistor on a semiconductor substrate according to the present invention comprises generating a first partial region of a trench structure by means of etching, wherein the semiconductor substrate has a first semiconductor material and at least one epitaxial layer, wherein the first partial region of the trench structure extends substantially perpendicularly to the surface of the semiconductor substrate into the interior of the epitaxial layer, wherein each first partial region has a first depth and a first width. The method also comprises a rotation of the semiconductor substrate at a first tilt angle and comprises generating a second partial region of the trench structure by means of etching, wherein the second partial region of the trench structure has a first tilt angle relative to the surface of the semiconductor substrate, wherein each second partial region of the trench structure has a second depth and a second width, respectively. The method also comprises a rotation of the semiconductor substrate at a second tilt angle and comprises generating a third partial region of the trench structure by means of etching, wherein each third partial region of the trench structure has a third depth and a third width, respectively. The method also comprises generating an electrical connection of the second partial region and the third partial region to the source junction.

[0020] The advantage here is that the deep sub-regions are of strip-shaped configuration, tilted or tilted relative to the surface of the semiconductor substrate, and whose ends have a small distance relative to each other, so that in the blocking case high field strengths are kept away from the gate oxide and the current in the case of a short circuit is effectively limited.

[0021] In one configuration, a fourth partial region of the trench structure is produced by etching, wherein the fourth partial region has a fourth depth which is greater than the first depth.

[0022] Advantageously, the gate oxide has a high quality, since the trench surface is produced in the region of the gate oxide independently of the first subregion and the channel length can be selected to be shorter.

[0023] In a further configuration, a layer having a first doping is deposited on the surface of the trench structure, wherein the first doping has a first charge carrier type that is different from a second charge carrier type of the second doping of the epitaxial layer.

[0024] The advantage here is that the layer extends slightly into the monocrystalline epitaxial layer, so that no increase in blocking current occurs at the boundary surfaces of the epitaxial layer due to recombination.

[0025] In a further configuration, the first partial region and the second partial region are filled with a second semiconductor material.

[0026] Further advantages emerge from the following description of exemplary embodiments or from the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The present invention is explained below with reference to preferred embodiments and the accompanying drawings. The accompanying drawings show:

[0028] Figure 1 Example of a vertical power transistor,

[0029] Figure 2 Another example of a vertical power transistor,

[0030] Figure 3 Used to manufacture according to Figure 1 A method of vertical power transistor, and

[0031] Figure 4 Figure 3 Selected method steps for producing the trench structure. DETAILED DESCRIPTION

[0032] Figure 1 A vertical power transistor 1 is shown with a semiconductor substrate 2, on the front side of which at least one epitaxial layer 3 is arranged. The vertical power transistor 1 is, for example, a metal oxide semiconductor field effect transistor (MOSFET). The semiconductor substrate 2 comprises a first semiconductor material, for example silicon carbide, in particular 4H-SiC, wherein the epitaxial layer 3 is n-doped.

[0033] A second layer 7 is arranged on the epitaxial layer 3, which acts as a channel region or body region. A third layer is arranged on the second layer 7, which includes a body bonding region 8 and a source region 9. A second metal layer 15 is arranged on the rear side of the semiconductor substrate 2, which acts as a drain metallization. The vertical power transistor 1 has a trench structure, that is, a plurality of trenches. The trench has a depth of 0.5 μm to 14 μm and a spacing of 0.2 μm to 10 μm is measured at the respective outermost ends of the trench bottom. Each trench has a first region 13, which extends from the trench bottom to a certain height of the respective trench. Here, the first region 13 includes a first partial region, a second partial region and a third partial region, wherein the second partial region and the third partial region have an inclination relative to the surface of the semiconductor substrate 2. The shape of the first region 13 is essentially V-shaped, wherein the open side of the V-shape points in the direction of the second metal layer 15. This means that the trench does not have a side wall perpendicular to the substrate surface starting from the corresponding trench bottom. The trench bottom can be rounded about the corresponding side wall. The first region 13 is at least partially filled with a second semiconductor material. The second semiconductor material is, for example, polysilicon or 3C-SiC. The second semiconductor material has a third doping, which has a dopant concentration of at least 1E13 cm^-3. In the third doping, p carriers are used in the case of polysilicon, and either n carriers or p carriers are used in the case of 3C-SiC. The first region 13 is electrically connected to the source region 9. In each trench, a gate dielectric 5 made of SiO2, for example, and a gate electrode 6 made of polysilicon, for example, are arranged inside the trench structure above the first region 13. A structured insulating layer 16 is arranged on each trench, that is, above the trench structure, which electrically insulates the gate electrode 6 from the source region 9. A first metal layer 14 is arranged on the structured insulating layer 16.

[0034] Figure 2 Another example of a vertical power transistor 51 is shown. The vertical power transistor 51 includes Figure 1 1 , wherein functionally identical elements have the same reference numerals. The vertical power transistor 51 is, for example, a metal oxide semiconductor field effect transistor. Additionally, the vertical power transistor 51 has a first layer 4, which is arranged on the trench surface of the first region 13. The first layer 4 has a first doping. The first doping has a first carrier type, which is different from a second carrier type of the second doping of the epitaxial layer 3.

[0035] In an embodiment, the epitaxial layer 3 is doped with n-carriers, for example. The first layer 4 is doped with p-carriers. The first doping has a higher doping concentration than the second doping. The doping profile of the first doping is configured so that the electric field drops to zero inside the first layer 4 when receiving the blocking voltage. This means that the doping concentration of the first layer 4 is selected to be so high that the electric field when receiving the blocking voltage remains inside the highly doped thin first layer 4 and does not reach the first region 13 filled with polysilicon. The first region is produced before the trench is filled, for example, by means of ion implantation and a subsequent recovery step (Ausheilschritt). Alternatively, the epitaxial layer 3 may not be uniformly n-doped, but rather doped with a high concentration of n-carriers in the region at the bottom of the trench, so that the first layer 4 has the function of a "counter-doped" layer. As a result, the on-resistance (RDSon) of the vertical power transistor 1 is reduced.

[0036] Involving both Figure 1 The vertical power transistor 1 also involves Figure 2 In the configuration of the vertical power transistor 51, the trench structure includes a fourth partial region, which extends substantially perpendicularly to the surface of the semiconductor substrate 2. The fourth partial region has a fourth depth and a fourth width, wherein the fourth depth is greater than the first depth, so that the first region 13 is composed of the first partial region, the second partial region and the fourth partial region. This results in a region of the trench structure below the gate electrode, which also has side walls perpendicular to the surface of the semiconductor substrate 2. The fourth partial region is at least partially filled with a second semiconductor material. The fourth partial region ensures that the trench wall runs vertically in the region of the inverted channel. This minimizes the length of the inverted channel and thus minimizes the channel resistance.

[0037] Figure 3A method 300 for producing a vertical power transistor on a semiconductor substrate having at least one epitaxial layer is described. The method 300 starts with step 310, in which a first partial region of a trench structure is produced by etching, in particular by sputtering etching. The first partial region of the trench structure extends substantially perpendicularly to the surface of the semiconductor substrate into the interior of the epitaxial layer, wherein each first partial region has a first depth and a first width. In a subsequent step 320, the semiconductor substrate is rotated so that the surface of the semiconductor substrate has a first tilt angle relative to a first plane, which is arranged perpendicular to the surface of the semiconductor substrate in an initial state, i.e., when not rotated. In a subsequent step 330, a second partial region of the trench structure is produced by etching. The second partial region of the trench structure has a first tilt angle relative to the surface of the semiconductor substrate, i.e., the second partial region is arranged obliquely. Each second partial region has a second depth and a second width. In a subsequent step 340, the semiconductor substrate is rotated so that the surface of the semiconductor substrate has a second tilt angle relative to the first plane. In an embodiment, the value of the first tilt angle corresponds to the value of the second tilt angle, wherein the first tilt angle has a different sign from the second tilt angle. In a subsequent step 350, a third partial region of the trench structure is produced by etching. The third partial region has a second inclination angle relative to the surface of the semiconductor substrate. Each third partial region has a third depth and a third width, respectively. In an optional step 360, a first layer with a first doping is deposited on the surface of the trench structure, wherein the first doping has a first carrier type, which is different from the second carrier type of the second doping of the epitaxial layer. In a subsequent step 370, an electrical connection is generated between the second partial region and the third partial region via a source junction. In an optional step 380, a fourth partial region of the trench structure is produced by etching, wherein the fourth partial region has a fourth depth, which is greater than the first depth.

[0038] Figure 4 Show Figure 3 Selected method steps for producing a trench structure in the method of . The production of the trench structure comprises at least three etching steps, which are preferably carried out by means of sputter etching, ie a dry etching method. Figure 4 a shows method step 310 in which a first partial region of the trench structure is produced by etching. To this end, a hard mask having a certain thickness dM is arranged on the substrate surface so that a vertical trench having a first depth t1 and a first width w1 is produced by etching. Figure 4b shows a method step 330, in which a second partial region of the trench structure is produced by etching. To this end, the semiconductor substrate is tilted or flipped at a first tilt angle +PHI in a previous step. The first tilt angle is, for example, 15°. The second partial region produced in this way is tilted relative to the surface of the semiconductor substrate. The second partial regions each have a second width w2, which depends on the first depth t1, the first width w1, the determined thickness dM of the mask and the first tilt angle +PHI. The second width w2 can be determined by means of the following formula:

[0039] w2=(w1-dM*tan(PHI)*cos(PHI)).

[0040] Figure 4 c shows method step 350, in which a third partial region of the trench structure is produced by etching. For this purpose, the semiconductor substrate is tilted or turned at a second tilt angle -PHI in a previous step. The third partial region produced in this way is tilted relative to the surface of the semiconductor substrate in a direction different from that of the second partial region.

[0041] Furthermore, during production, it should be noted that the width w3 of the bottom of the planar trench remaining after the second etching process, i.e., the first oblique etching, or after step 330, satisfies the following condition: w3 ≥ (w1-dM*tan(PHI)) / 2. If this condition is not met, a different etching profile for the third partial region is obtained for geometric reasons. In other words, the second partial region and the third partial region are arranged symmetrically with respect to the perpendicular midline of the corresponding trench when the condition is met. The minimum inclination angle PHIMIN and the maximum inclination angle PHIMAX can be determined by means of the following formula:

[0042] PHIMIN=arctan(w1 / (2*(t1+dM))) and PHIMAX=arctan(w1 / (t1+dM)).

[0043] Figure 4 d shows method step 380, in which a fourth partial region of the trench structure is produced by etching. For this purpose, photolithography is carried out in advance in order to adjust the width w4 of the trench.

[0044] After the inclined trench structure is generated, the trench is filled with highly doped polysilicon, so that a heterojunction is generated between the polysilicon layer and the low-doped 4H-SiC layer.

[0045] Vertical power transistors with a suitable trench structure can be used in power electronics applications, such as inverters for electric or hybrid vehicles, but also in non-vehicle applications, such as photovoltaic or wind power inverters, train drives or high voltage rectifiers.

Claims

1. A vertical power transistor (1) comprising a semiconductor substrate (2) comprising a first semiconductor material and having at least one epitaxial layer (3), in, A trench structure extends from the surface of the semiconductor substrate (2) into the interior of the at least one epitaxial layer (3), characterized in that the trench structure has a first region (13), the first region respectively extending from the bottom of the trench to a certain height of the corresponding trench, wherein the first region (13) includes a first partial region, the first partial region respectively having a first depth (t1) and a first width (w1), wherein the first partial region extends substantially perpendicular to the surface of the semiconductor substrate (2), wherein the first region (13) includes a second partial region, the second partial region respectively having a second depth and a second width (w2), wherein the second partial region has The invention relates to a semiconductor substrate (2) having a first inclination angle relative to the surface of the semiconductor substrate (2), wherein the first region (13) includes a third partial region, the third partial region respectively having a third depth and a third width, wherein the third partial region has a second inclination angle relative to the surface of the semiconductor substrate (2), wherein the second partial region and the third partial region are arranged symmetrically about the perpendicular midline of the corresponding groove so that their shape is basically V-shaped, wherein the open side of the V-shape points in the direction of the second metal layer (15), the second metal layer (15) is arranged on the rear side of the semiconductor substrate (2), wherein the first region (13) is electrically conductively connected to the source joint.

2. The vertical power transistor (1) according to claim 1, It is characterized in that The first region (13) comprises a fourth partial region, which extends substantially perpendicularly to the surface of the semiconductor substrate (2), wherein the fourth partial region has a fourth depth and a fourth width, wherein the fourth depth is greater than the first depth (t1).

3. The vertical power transistor (1) according to claim 1 or 2, It is characterized in that A first layer (4) having a first doping is arranged on the surface of the first region (13), wherein the first doping has a first charge carrier type which is different from a second charge carrier type of a second doping of the epitaxial layer (3).

4. The vertical power transistor (1) according to claim 1 or 2, It is characterized in that The first region (13) is at least partially filled with a second semiconductor material having a third doping of at least 1E13 cm^-3.

5. The vertical power transistor (1) according to claim 4, It is characterized in that The second semiconductor material includes polysilicon or 3C-SiC.

6. The vertical power transistor (1) according to claim 1 or 2, It is characterized in that The first semiconductor material includes silicon carbide.

7. A method (300) for manufacturing a vertical power transistor on a semiconductor substrate, in, The semiconductor substrate comprises a first semiconductor material and has at least one epitaxial layer, and the method comprises the following steps: - generating (310) first partial regions of a trench structure by means of etching, wherein the first partial regions of the trench structure extend substantially perpendicularly to the surface of the semiconductor substrate into the interior of the epitaxial layer, wherein each first partial region of the trench structure has a first depth and a first width, - rotating the semiconductor substrate at a first tilt angle (320), - generating (330) second partial regions of the trench structure by means of etching, wherein the second partial regions of the trench structure have a first angle of inclination relative to the surface of the semiconductor substrate, wherein each second partial region of the trench structure has a second depth and a second width, - rotating the semiconductor substrate at a second tilt angle (340), wherein the value of the first tilt angle corresponds to the value of the second tilt angle, wherein the first tilt angle has a different sign than the second tilt angle, - generating (350) third partial regions of the trench structure by means of etching, wherein the third partial regions of the trench structure have a second inclination angle relative to the surface of the semiconductor substrate, wherein each third partial region of the trench structure has a third depth and a third width, - producing (370) an electrical connection of the second partial region and the third partial region to a source junction.

8. The method (300) according to claim 7, It is characterized in that A fourth partial region of the trench structure is produced by etching, wherein the fourth partial region has a fourth depth which is greater than the first depth.

9. The method (300) according to claim 7 or 8, It is characterized in that A first layer having a first doping is deposited at least on the surface of the first partial region and the second partial region, wherein the first doping has a first charge carrier type that is different from a second charge carrier type of a second doping of the epitaxial layer.

10. The method (300) according to claim 7 or 8, It is characterized in that The first partial region and the second partial region are filled with a second semiconductor material.

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