Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a manufacturing method thereof, the semiconductor memory device comprising: a first memory chip in which a first memory array is formed; a second memory chip in which a second memory array is formed; a back surface of the second memory chip is stacked on a surface of the first memory chip; a second conductive pillar is formed in the second memory chip, the second conductive pillar penetrating the second memory chip, and the second memory chip forms an electrical connection with the first memory chip through the second conductive pillar; a peripheral circuit is formed in the first memory chip, the peripheral circuit comprising a first circuit, at least part of a second circuit, and a common circuit, the first circuit being used to control the first memory array, the second circuit being used to control the second memory array, the first circuit being connected to the first memory array, the second circuit being connected to the second memory array, and the common circuit connecting the first circuit and the second circuit. The data transmission efficiency of the semiconductor memory device is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor memory device and its manufacturing method. Background Technology

[0002] Because volatile memory chips (such as DRAM) have faster read speeds, while non-volatile memory chips (such as NAND flash) have the advantage of retaining data even when power is off, most modern data processing systems need to include both volatile and non-volatile memory chips to take advantage of their respective strengths. Since volatile and non-volatile memory chips have different structures, they are typically manufactured using different process technologies, forming separate chips.

[0003] When a data processing system includes both volatile and non-volatile memory chips, the two types of chips typically exist independently and are connected to each other via transmission lines for data transmission. The disadvantages of this approach are the long transmission path between the volatile and non-volatile memory chips, bandwidth limitations in the chip interfaces and transmission lines, restricted data exchange speed, and a relatively large overall size, making it difficult to adapt to applications requiring high integration.

[0004] Therefore, improving the data transfer speed between volatile and non-volatile memory chips and increasing integration are urgent problems to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor memory device and a method for manufacturing the same, so as to improve the integration and data transmission speed of the semiconductor memory device.

[0006] To address the aforementioned problems, the present invention provides a semiconductor memory device, comprising: a first memory chip, wherein a first memory array and peripheral circuitry are formed within the first memory chip; the peripheral circuitry includes a first circuit, at least a portion of a second circuit, and a common circuit; the first circuit is used to control the first memory array, the second circuit is used to control the second memory array, the first circuit is connected to the first memory array, the second circuit is connected to the second memory array, and the common circuit connects the first circuit and the second circuit; a second memory chip, wherein a second memory array is formed within the second memory chip; the back side of the second memory chip is stacked on the surface of the first memory chip; a second conductive post is formed within the second memory chip, and the second memory chip is electrically connected to the first memory chip through the second conductive post.

[0007] Optionally, a second conductive bump is formed on the back of the second memory chip to connect to the second conductive post, and an electrical connection is formed between the second conductive bump and the first memory chip.

[0008] Optionally, it also includes a substrate on which an I / O interface circuit is formed; the peripheral circuit is electrically connected to the I / O interface circuit of the substrate.

[0009] Optionally, the peripheral circuit is formed in the edge region of the first memory chip and is electrically connected to the I / O interface circuit of the substrate via bonding leads.

[0010] Optionally, a first conductive post is formed within the first memory chip, and the second conductive post is electrically connected to the first conductive post.

[0011] Optionally, a first conductive bump is formed on the surface of the first memory chip away from the second memory chip, which is connected to the first conductive post; the first conductive bump is electrically connected to the I / O interface circuit of the substrate.

[0012] Optionally, a redistributed conductive layer is formed on the front and / or back of the first memory chip.

[0013] Optionally, the first storage array is a volatile storage array, and the second storage array is a non-volatile storage array.

[0014] The present invention also provides a method for manufacturing a semiconductor memory device, comprising: forming a first memory chip, wherein a first memory array and peripheral circuitry are formed within the first memory chip, the peripheral circuitry including a first circuit, at least a portion of a second circuitry, and a common circuit, wherein the first circuitry is used to control the first memory array, the second circuitry is used to control the second memory array, the first circuitry is connected to the first memory array, the second circuitry is connected to the second memory array, and the common circuitry connects the first circuitry and the second circuitry; forming a second memory chip, wherein a second memory array and a second conductive post penetrating the second memory chip are formed within the second memory chip; stacking the back side of the second memory chip onto the back side of the first memory chip, and forming an electrical connection between the second memory chip and the first memory chip through the second conductive post.

[0015] Optionally, it further includes forming a second conductive bump on the back of the second memory chip to connect to the second conductive post; and forming an electrical connection between the second conductive bump and the first memory chip.

[0016] Optionally, the system may also provide a substrate on which an I / O interface circuit is formed; and form an electrical connection between the peripheral circuitry within the first memory chip and the I / O interface circuitry of the substrate.

[0017] Optionally, the peripheral circuit is formed on the edge region of the first memory chip, and the I / O interface circuit of the substrate and the peripheral circuit are electrically connected by wire bonding process.

[0018] Optionally, it further includes forming a first conductive post that penetrates the first memory chip; and forming an electrical connection between the second conductive post and the first conductive post.

[0019] Optionally, a first conductive bump is formed on the surface of the first memory chip away from the second memory chip to connect to the first conductive post; an electrical connection is formed between the first conductive bump and the I / O interface circuit of the substrate.

[0020] Optionally, a redistributed conductive layer may also be formed on the front and / or back of the first memory chip.

[0021] Optionally, the first storage array is a volatile storage array, and the second storage array is a non-volatile storage array.

[0022] In this invention, the first and second memory chips of the semiconductor memory device are electrically connected by stacking them together. Vertical interconnection between the two chips is achieved by forming conductive pillars that penetrate the memory chips, which significantly reduces the I / O connection length for signal transmission between the two chips, greatly reduces power consumption of the connection circuit, and improves transmission efficiency. Furthermore, stacking the first and second memory chips together, compared to placing the two chips separately, greatly reduces the area of ​​the semiconductor memory device and improves integration.

[0023] Furthermore, since the first memory chip and the second memory chip are close to each other, the memory arrays of the first memory chip and the second memory chip can share some circuits, thereby saving circuit area and reducing power consumption. Attached Figure Description

[0024] Figures 1A to 1D This is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the module structure of a semiconductor memory device according to a specific embodiment of the present invention; Figure 3 This is a schematic diagram of the common circuit of a semiconductor memory device according to a specific embodiment of the present invention; Figures 4A to 4CThis is a schematic diagram illustrating the data input / output method of the first and second memory chips according to a specific embodiment of the present invention.

[0025] Figures 5A to 5C This is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention; Figures 6A to 6D This is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention; Figures 7A to 7D This is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention; Figure 8 This is a schematic flowchart of a method for manufacturing a semiconductor memory device according to a specific embodiment of the present invention; Figures 9A to 9B A schematic diagram of the formation process of a semiconductor memory device according to a specific embodiment of the present invention; Figures 10A to 10B A schematic diagram of the formation process of a semiconductor memory device according to a specific embodiment of the present invention; Figures 11A to 11B A schematic diagram of the formation process of a semiconductor memory device according to a specific embodiment of the present invention. Detailed Implementation

[0026] The following detailed description, in conjunction with the accompanying drawings, illustrates specific embodiments of a semiconductor memory device and its manufacturing method provided by the present invention.

[0027] Please refer to Figure 1, which is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention.

[0028] The semiconductor memory device of this specific embodiment includes: a first memory chip 101 and a second memory chip 102, wherein the first memory chip 101 and the second memory chip 102 are stacked and connected.

[0029] The first memory chip 101 and the second memory chip 102 can be different types of memory chips. In one specific embodiment, the first memory chip 101 is a volatile memory chip, and the second memory chip 102 is a non-volatile memory chip. In this specific embodiment, the first memory chip 101 is a DRAM chip, and the second memory chip 102 is a NAND chip. In other specific embodiments, the first memory chip 101 can also be an SRAM chip, and the second memory chip 102 can also be a non-volatile memory chip such as a PROM or EPROM.

[0030] The first memory chip 101 includes a first memory array, which is a DRAM memory array; the second memory chip 102 includes a second memory array, which is a NAND memory array. The first memory array and the second memory array can be two-dimensional or three-dimensional memory arrays, and the substrates of the first memory chip 101 and the second memory chip 102 can be polycrystalline silicon or monocrystalline silicon, that is, the first memory array and the second memory array are formed on a polycrystalline silicon or monocrystalline silicon substrate.

[0031] The first memory chip 101 and / or the second memory chip 102 may also have peripheral circuits for controlling the first memory array and controlling the second memory array.

[0032] The first memory chip 101 and the second memory chip 102 are stacked and connected to each other. The first memory chip 101 includes a front side 1012 and a back side 1011, and the second memory chip 102 includes a front side 1022 and a back side 1021, which are opposite to the front side. The front side refers to the device layer surface of the memory chip, and the back side refers to the other surface opposite to the front side.

[0033] Please refer to Figure 1A In this specific embodiment, the front side 1012 of the first memory chip 101 and the front side 1022 of the second memory chip 102 are stacked and connected opposite each other. In other specific embodiments, the back side 1021 of the second memory chip 102 and the front side 1012 of the first memory chip 101 are stacked and connected opposite each other (see reference). Figure 1B In other specific embodiments, the front side 1022 of the second memory chip 102 is stacked and connected opposite to the back side 1011 of the first memory chip 101 (see reference). Figure 1C In other specific embodiments, the back surface 1021 of the second memory chip 102 is stacked and connected opposite to the back surface 1011 of the first memory chip 101 (see reference). Figure 1D ).

[0034] Both the first memory chip 101 and the second memory chip 102 have interconnect structures such as interconnect lines and interconnect pillars. The first memory chip 101 and the second memory chip 102 can be electrically connected through the interconnect structures.

[0035] Please refer to Figure 1AIn this specific embodiment, the front side 1012 of the first memory chip 101 and the front side 1022 of the second memory chip 102 are stacked and connected. The second memory chip 102 and the interconnect structure exposed on the front side of the first memory chip 101 are bonded together with metal, and the dielectric layer on the front side of the second memory chip 102 and the first memory chip 101 are bonded together with adhesive. While realizing the stacking of the first memory chip 101 and the second memory chip 102, electrical connection is achieved through the metal bonding between the interconnect structures.

[0036] In another specific embodiment, the first memory chip 101 and the second memory chip 102 may both have passivation layers formed on their front sides. Through the bonding process between the two passivation layers, the first memory chip 101 and the second memory chip 102 are stacked and bonded. Furthermore, the corresponding connection between the first memory chip 101 and the second memory chip 102 is achieved through a deep through-hole connection structure that penetrates the first memory chip 101 and / or the second memory chip 102.

[0037] In other specific embodiments, the first memory chip 101 and the second memory chip 102 can also be stacked together using other bonding methods and interconnection structures. Those skilled in the art can make reasonable designs as needed.

[0038] Because the first memory chip 101 and the second memory chip 102 are stacked together and electrically connected directly through an interconnect structure, the I / O connection length for signal transmission between the two chips can be greatly reduced, significantly reducing the power consumption of the connection circuit and improving transmission efficiency. Furthermore, the stacking of the first memory chip 101 and the second memory chip 102, compared to placing the two chips separately, can greatly reduce the area of ​​the semiconductor memory device and improve integration.

[0039] Since the first memory chip 101 and the second memory chip 102 are close to each other, the memory arrays of the first memory chip 101 and the second memory chip 102 can share some circuits, thereby saving circuit area and reducing power consumption.

[0040] In this specific embodiment, since the first memory chip 101 is a DRAM memory chip, and the storage density of the DRAM memory array is relatively low, the first memory chip 101 can also form peripheral circuits in addition to the DRAM memory array 201. These peripheral circuits include a DRAM dedicated circuit 202, a NAND dedicated circuit 204, and a common circuit 203. The second memory chip 102 is a NAND memory chip, forming a NAND memory array 205. The DRAM memory array is connected to the DRAM dedicated circuit 202, and the NAND memory array 205 is connected to the NAND dedicated circuit 204.

[0041] The dedicated DRAM circuit 202 corresponds to the DRAM storage array 201. Specifically, the dedicated DRAM circuit 202 includes a serial-to-parallel converter, a double data transmission control circuit, etc., and is used to control the DRAM storage array.

[0042] The dedicated NAND circuit 204 corresponds to the NAND memory array. Specifically, the dedicated NAND circuit 204 includes control circuits related to programming / erase operations, as well as high-voltage generation circuits, etc., for controlling the NAND memory array 205.

[0043] The common circuit 203 connects the DRAM dedicated circuit 202 and the NAND dedicated circuit 204. Since only the NAND memory array 205 needs to be formed within the second memory chip 102, the process difficulty of forming the second memory chip 102 can be reduced, and the process cycle can be shortened.

[0044] Please refer to Figure 2 The first memory chip 101 and the second memory chip 102 are stacked on top of each other, and the NAND memory array 205 is electrically connected to the NAND dedicated circuit 204.

[0045] In other specific embodiments, all or part of the circuits in the NAND dedicated circuit 204, the common circuit 203, and the DRAM dedicated circuit 202 may also be formed within the second memory chip 102.

[0046] Please refer to Figure 3 This is a schematic diagram of the structure of the common circuit 203 according to a specific embodiment of the present invention.

[0047] The shared circuit 203 includes a power management unit 2031, a bandgap reference unit 2032, a time-division multiplexing unit 2033, and a calibration unit 2034. It may also include a control logic unit, a bias unit, etc., and can be used by the DRAM storage array 201 and the NAND storage array 205 for data transmission.

[0048] The DRAM dedicated circuit 202 and the NAND dedicated circuit 204 are respectively connected to the power management unit 2031, the bandgap reference unit 2032, and the time-division multiplexing unit 2033. The calibration unit 2034 is connected to the time-division multiplexing unit 2033.

[0049] Please refer to Figures 4A to 4C This is a schematic diagram of the data input / output method of the first memory chip 101 and the second memory chip 102, which is a specific embodiment of the present invention.

[0050] The semiconductor memory device further includes a substrate on which an I / O interface circuit is formed, the I / O interface circuit being used for signal transmission with the outside of the semiconductor memory device.

[0051] Please combine Figure 2 In one specific embodiment, the DRAM dedicated circuit 202 is connected to the I / O interface circuit. The NAND storage array 205 is connected to the I / O interface circuit through the NAND dedicated circuit 204, the common circuit 203, and the DRAM dedicated circuit 202. The DRAM storage array 201 is connected to the I / O interface circuit through the DRAM dedicated circuit 202. For details, please refer to... Figure 4A The NAND flash memory array 205 of the second memory chip and the DRAM memory array 201 of the first memory chip directly transmit data. When data needs to be read from the NAND flash memory array 205, the data in the NAND flash memory array 205 is first output to the DRAM memory array 201 of the first memory chip, and then the DRAM memory array 201 outputs the data outward, acting as a buffer. The I / O interface circuit can directly control the DRAM memory array through the dedicated DRAM circuit 202; the I / O interface circuit controls the NAND flash memory array 205 through the dedicated DRAM circuit 202, the shared circuit 203, and the dedicated NAND circuit 204.

[0052] In another specific embodiment, the NAND dedicated circuit 204 and the DRAM dedicated circuit 202 are respectively connected to the I / O interface circuit. The DRAM storage array 201 is connected to the I / O interface circuit through the DRAM dedicated circuit 202, and the NAND storage array 205 is connected to the I / O interface circuit through the NAND dedicated circuit 204. Please refer to... Figure 4B The NAND storage array 205 and the DRAM storage array 201 can respectively input and output data.

[0053] Please refer to Figure 4C In another specific embodiment, the shared circuit 203 includes an interface control unit 401. The DRAM dedicated circuit 202 and the NAND dedicated circuit 204 are respectively connected to the interface control unit 401. The interface control unit 401 is connected to the I / O interface circuit. The DRAM storage array 201 and the NAND storage array 205 are connected to the I / O interface circuit through the interface control unit 401. The interface control unit 401 can be part of the shared circuit of the NAND storage array 205 and the DRAM storage array 201, and is used for time-division multiplexing control, data protocol conversion, etc. The interface control unit 401 controls the data input and output between the NAND storage array 205 and the DRAM storage array 201.

[0054] In other specific implementations, appropriate NAND dedicated circuits, DRAM dedicated circuits, and shared circuits can be designed according to requirements to realize various forms of I / O methods.

[0055] In the above specific embodiments, since the first memory chip and the second memory chip are stacked and connected, the I / O transmission path is shortened, and the I / O transmission mode of the first memory chip and the second memory chip can be flexibly set.

[0056] Please refer to Figure 5A This is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention.

[0057] The semiconductor storage device includes a DRAM storage chip 510 and a NAND storage chip 520, with the back side 5201 of the NAND storage chip 520 stacked on the front side 5102 of the DRAM storage chip 510.

[0058] A conductive pillar 521 is formed within the NAND memory chip 520, penetrating the NAND memory chip 520. A redistributed conductive layer 522 is formed on the front side 5202 of the NAND memory chip 520, and the redistributed conductive layer 522 is connected to the NAND memory array and / or NAND circuitry within the NAND memory chip 520. One end of the conductive pillar 521 is connected to the redistributed conductive layer 522, and then to the NAND memory array and / or NAND circuitry.

[0059] The NAND memory chip 520 has a second conductive bump 523 formed on the back surface 5201 of the NAND memory chip 520, located on top of the conductive post 521; the DRAM memory chip 510 has a first conductive bump 511 formed on the front surface 5102 of the DRAM memory chip 510. The first conductive bump 511 and the second conductive bump 523 are electrically connected by metal bonding. The back surface 5201 of the NAND memory chip 520 and the front surface 5102 of the DRAM memory chip 510 are connected and fixed at other locations by an adhesive layer (not shown in the figure). In this specific embodiment, the conductive post 521 is connected to the... A redistributed conductive layer may also be formed on the front side 5102 of the DRAM memory chip 510, connecting the first conductive bump 511 to the peripheral circuitry inside the DRAM memory chip 510. A solder pad 513 is also formed on the front side 5102 of the DRAM memory chip 510 to connect to the peripheral circuitry inside the DRAM memory chip 510. The solder pad 513 is connected to the I / O interface circuitry of the semiconductor memory device via bonding leads 512, enabling signal transmission between the DRAM memory chip 510 and the I / O interface circuitry.

[0060] To facilitate wire bonding, when the NAND memory chip 520 is stacked on the surface of the DRAM memory chip 510, the area where the solder pad 513 is located is exposed.

[0061] Please refer to Figure 5B and Figure 5C The peripheral circuit region 514 within the DRAM memory chip 510 is located on one side edge of the DRAM memory chip 510. Figure 5C ) or the two side edge areas ( Figure 5B This allows for external connections via bonding wires.

[0062] In one specific embodiment, the NAND storage array in the NAND storage chip 520 is connected to the NAND dedicated circuit in the DRAM storage chip via conductive pillar 521, or the NAND dedicated circuit in the NAND storage chip 510 is connected to the common circuit in the DRAM storage chip 510 via the conductive pillar 521; the I / O interface circuit is connected to at least one of the NAND dedicated circuit, the common circuit, and the DRAM dedicated circuit in the DRAM storage chip 510.

[0063] Please refer to Figure 6A This is a schematic diagram of the structure of a semiconductor memory device according to another specific embodiment of the present invention.

[0064] In this specific embodiment, a second conductive post 621 is formed inside the NAND memory chip 620, penetrating the NAND memory chip 620. The second conductive post 621 is connected to a redistributed conductive layer 622 formed on the front side 6202 of the NAND memory chip 620, and a second conductive bump 623 formed on the back side 6201 of the NAND memory chip 620.

[0065] A first conductive post 612 is formed through the DRAM memory chip 610. A first conductive bump 611 and a redistributed conductive layer 614 are formed on the front side 6102 of the DRAM memory chip 610. A portion of the first conductive post 612 is connected to the first conductive bump 611 and the redistributed conductive layer 614. A third conductive bump 613 is formed on the back side 6101 of the DRAM memory chip 610, and the third conductive bump 613 is connected to the first conductive post 612. The third conductive bump 613 can be electrically connected to the I / O interface circuit through processes such as metal bonding or soldering.

[0066] The NAND memory array within the NAND memory chip 620 is electrically connected to the DRAM memory chip via a portion of the second conductive posts 621 and the second conductive bumps 623, which are bonded to the first conductive bumps 611. A portion of the second conductive posts 621 is further connected to the first conductive post 612 via the second conductive bumps 623 and the first conductive bumps 611, and is connected to the I / O chip via the third conductive bump 613.

[0067] In this specific embodiment, the direct connection between the NAND storage array and the I / O interface circuit can be achieved through the electrical connection of the first conductive post 612 and the second conductive post 621.

[0068] Please refer to Figures 6B-6DIn this specific embodiment, the peripheral circuit region 640 of the DRAM memory chip 610 may be located in the middle of the DRAM memory chip 610 (e.g., Figure 6B As shown), one side edge area (such as Figure 6C (as shown) or the two side edge areas (such as Figure 6D (As shown).

[0069] Please refer to Figure 7A This is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention.

[0070] In this specific embodiment, a second conductive post 721 is formed inside the NAND memory chip 720, penetrating the NAND memory chip 720. The second conductive post 721 is connected to a redistributed conductive layer 722 formed on the front side 7202 of the NAND memory chip 720, and a second conductive bump 723 formed on the back side 7201 of the NAND memory chip 720.

[0071] The back surface 7201 of the NAND flash memory chip 720 is stacked on the back surface 7101 of the DRAM memory chip. A first conductive post 712 is formed inside the DRAM memory chip 710, penetrating the DRAM memory chip 710. A first conductive bump 711 is formed on the back surface 7101 of the DRAM memory chip 710, and the first conductive post 712 is connected to the first conductive bump 711. A third conductive bump 713 and a redistributed conductive layer 714 are formed on the front surface 7102 of the DRAM memory chip 710. Part of the third conductive bump 713 is connected to the first conductive post 712, and part of the first conductive post 712 is connected to the redistributed conductive layer 714.

[0072] The second conductive post 721 is connected to the first conductive post 712 via the second conductive bump 723 and the first conductive bump 711. The second conductive bump 723 and the first conductive bump 711 are connected by metal bonding. The third conductive bump 713 can be connected to the I / O interface circuit through processes such as metal bonding or soldering.

[0073] The DRAM memory chip 710 includes a DRAM memory array, a DRAM dedicated circuit, and a NAND dedicated circuit. The redistribution conductive layer 714 can be connected to the NAND dedicated circuit. The NAND memory array in the NAND memory chip 720 is connected to the NAND dedicated circuit in the DRAM memory chip 710 through the second conductive post 721, the first conductive post 712, and the redistribution conductive layer 714.

[0074] Please refer to Figures 7B-7DIn this specific embodiment, the peripheral circuit region 740 of the DRAM memory chip 710 may be located in the middle of the DRAM memory chip 710 (e.g., Figure 7B As shown), one side edge area (such as Figure 7C (as shown) or the two side edge areas (such as Figure 7D (As shown).

[0075] A specific embodiment of the present invention also provides a method for manufacturing a semiconductor memory device.

[0076] Please refer to Figure 8 This is a schematic flowchart illustrating the formation process of a semiconductor memory device according to a specific embodiment of the present invention.

[0077] The method for manufacturing the semiconductor memory device includes: Step S101: Form a first memory chip, in which a first memory array is formed.

[0078] The first memory chip 101 can be a volatile memory chip. In this specific embodiment, the first memory chip 101 is a DRAM chip. The first memory chip 101 can also be an SRAM chip.

[0079] The first memory chip 101 includes a first memory array, which in this specific embodiment is a DRAM memory array. The first memory array can be a two-dimensional or three-dimensional memory array. The first memory chip 101 includes a polycrystalline silicon or monocrystalline silicon substrate, and the first memory array is formed on the polycrystalline silicon or monocrystalline silicon substrate.

[0080] Step S102: Form a second memory chip, in which a second memory array is formed and a second conductive post penetrates the second memory chip.

[0081] The second memory chip 102 can be a non-volatile memory chip. In this specific embodiment, the second memory chip 102 is a NAND chip. The second memory chip 102 can also be a non-volatile memory chip such as a PROM or EPROM.

[0082] The second memory chip 102 includes a second memory array, which in this specific embodiment is a NAND memory array. The second memory array can be a two-dimensional or three-dimensional memory array. The second memory chip 102 includes a polycrystalline silicon or monocrystalline silicon substrate, and the second memory array is formed on the polycrystalline silicon or monocrystalline silicon substrate.

[0083] Steps S101 and S102 further include forming peripheral circuits for controlling the first memory array and the second memory array within the first memory chip 101 and / or the second memory chip 102. These peripheral circuits include a first circuit, a second circuit, and a shared circuit. The first circuit controls the first memory array, and the second circuit controls the second memory array. The first circuit is connected to the first memory array, the second circuit is connected to the second memory array, and the shared circuit connects the first circuit and the second circuit.

[0084] In this specific embodiment, step S101 includes forming a DRAM dedicated circuit 202, a NAND dedicated circuit 204, and a common circuit 203 on the substrate of the first memory chip (please refer to...). Figure 2 The DRAM dedicated circuit 202 may include a serial-to-parallel converter, a double data transfer control circuit, etc., for controlling the DRAM memory array 201. The NAND dedicated circuit 204 may include control circuits related to programming / erase operations, as well as a high-voltage generation circuit, etc., for controlling the NAND memory array 205. The common circuit 203 connects the DRAM dedicated circuit 202 and the NAND dedicated circuit 204. The common circuit 203 may include: a control logic unit, a bandgap reference unit, a bias unit, a power management unit, a time-division multiplexing unit, and a calibration unit. In step S102 of this specific embodiment, only the second memory array needs to be formed, without the need to form other peripheral circuits, thereby reducing the process difficulty of forming the second memory chip and shortening the process cycle.

[0085] In other specific embodiments, all or part of the circuits in the NAND dedicated circuit 204, the common circuit 203, and the DRAM dedicated circuit 202 may also be formed within the second memory chip 102.

[0086] Step S103: Stack the back side of the second memory chip on the back side of the first memory chip, and form an electrical connection between the second memory chip and the first memory chip through the second conductive post.

[0087] Please refer to Figures 1A to 1D The front side 1012 of the first memory chip 101 and the front side 1022 of the second memory chip 102 can be stacked and connected opposite each other. In other specific embodiments, the back side 1021 of the second memory chip 102 and the front side 1012 of the first memory chip 101 can be stacked and connected opposite each other (see reference). Figure 1BIn other specific embodiments, the front side 1022 of the second memory chip 102 can be stacked opposite to the back side 1011 of the first memory chip 101 (see reference). Figure 1C In other specific embodiments, the back surface 1021 of the second memory chip 102 is stacked and connected opposite to the back surface 1011 of the first memory chip 101 (see reference). Figure 1D ).

[0088] Interconnection structures such as interconnect lines and interconnect pillars can be formed in the first memory chip 101 and the second memory chip 102 in steps S101 and S102. Then, after stacking the first memory chip 101 and the second memory chip 102, the electrical connection between the first memory chip 101 and the second memory chip 102 is realized through the interconnection structure.

[0089] Please refer to Figure 1A In this specific embodiment, the front side 1012 of the first memory chip 101 and the front side 1022 of the second memory chip 102 are connected by stacking. The second memory chip 102 and the interconnect structure exposed on the front side of the first memory chip 101 are bonded together by metal bonding, and the dielectric layer on the front side of the second memory chip 102 and the first memory chip 101 are bonded together by adhesive layer. While realizing the stacking of the first memory chip 101 and the second memory chip 102, electrical connection is achieved through the metal bonding between the interconnect structures.

[0090] In another specific embodiment, the first memory chip 101 and the second memory chip 102 may both have passivation layers formed on their front sides. Through the bonding process between the two passivation layers, the first memory chip 101 and the second memory chip 102 can be stacked and bonded. The corresponding connection between the first memory chip 101 and the second memory chip 102 can be achieved through a deep through-hole connection structure that penetrates the first memory chip 101 and / or the second memory chip 102.

[0091] In other specific embodiments, the first memory chip 101 and the second memory chip 102 can also be stacked together using other bonding methods and interconnection structures. Those skilled in the art can make reasonable designs as needed.

[0092] By directly connecting the first memory chip 101 and the second memory chip 102 through an interconnect structure by stacking the chips together, the I / O connection length for signal transmission can be greatly reduced, the power consumption of the connection circuit can be greatly reduced, and the transmission efficiency can be improved. Furthermore, stacking the first memory chip 101 and the second memory chip 102 together, compared to placing the two chips separately, can significantly reduce the area of ​​the semiconductor memory device and improve the integration density.

[0093] Since the first memory chip 101 and the second memory chip 102 are close to each other, the memory arrays of the first memory chip 101 and the second memory chip 102 can share some circuits, thereby saving circuit area and reducing power consumption.

[0094] The method for manufacturing the semiconductor memory device further includes: forming an I / O interface circuit on the first memory chip or the second memory chip for controlling the semiconductor memory device. In one specific embodiment, the first circuit can be connected to the I / O interface circuit of the semiconductor memory device, and the second memory array is connected to the I / O interface circuit via the second circuit, a common circuit, and the first circuit. The first memory array is connected to the I / O interface circuit via the first circuit. In another specific embodiment, the second circuit and the first circuit can be respectively connected to the I / O interface circuit of the semiconductor memory device, and the first memory array is connected to the I / O interface circuit via the first circuit. The second memory array is connected to the I / O interface circuit via the second circuit. In another specific embodiment, the common circuit includes an interface control unit, the first circuit and the second circuit are respectively connected to the interface control unit, the interface control unit is connected to the I / O interface circuit of the semiconductor memory device, and the first memory array and the second memory array are connected to the I / O interface circuit via the interface control unit.

[0095] In other specific implementations, appropriate NAND dedicated circuits, DRAM dedicated circuits, and shared circuits can be designed according to requirements to achieve various forms of I / O.

[0096] Please refer to Figure 9A , 9B And 5A, for example Figure 5A The diagram shows a structural schematic of the semiconductor memory device formation process.

[0097] Please refer to Figure 9A A NAND memory chip 520 is formed. A NAND memory array is formed on a monocrystalline silicon or polycrystalline silicon substrate. In other embodiments, some NAND-specific circuitry may also be formed.

[0098] Additionally, a redistributed conductive layer 522 is formed on the front side 5202 of the NAND memory chip 520, and a conductive pillar 521 is formed penetrating the NAND memory chip 520, the conductive pillar 521 being connected to the redistributed conductive layer 522; a second conductive bump 523 is formed on the back side 5201 of the NAND memory chip 520, connecting to the conductive pillar 521.

[0099] Please refer to Figure 9B A DRAM memory chip 510 is formed. A DRAM memory array and peripheral circuitry are formed on a monocrystalline silicon or polycrystalline silicon substrate. The peripheral circuitry includes DRAM-specific circuitry, common circuitry, and at least a portion of NAND-specific circuitry.

[0100] In addition, a first conductive bump 511 and a solder pad 513 for connecting peripheral circuits are formed on the front side 5102 of the DRAM memory chip 510.

[0101] Please refer to Figure 5A The NAND flash memory chip 520 and the DRAM memory chip 510 are stacked and connected. Specifically, the back side 5201 of the NAND flash memory chip 520 faces the front side 5102 of the DRAM memory chip 510. The second conductive bump 523 on the back side of the NAND flash memory chip 520 is connected to the first conductive bump 511 on the front side of the DRAM memory chip 510 by metal bonding, and other locations are bonded by adhesive layers. Furthermore, the NAND flash memory chip 520 does not cover the solder pads 513.

[0102] It also includes a substrate on which I / O interface circuitry is formed. A wire bonding process is used to connect the solder pads 513 to the I / O interface circuitry on the substrate via bonding wires 514.

[0103] Please refer to Figure 10A , 10B And 6A, for example Figure 5A The diagram shows a structural schematic of the semiconductor memory device formation process.

[0104] Please refer to Figure 10A A NAND memory chip 620 is formed, and a redistributed conductive layer 622 is formed on the front side 6202 of the NAND memory chip 620; a second conductive post 621 is formed through the NAND memory chip 620, and the second conductive post 621 is connected to the redistributed conductive layer 622; a second conductive bump 623 is formed on the back side of the NAND memory chip 620, which is connected to the second conductive post 621.

[0105] Please refer to Figure 10BA DRAM memory chip 610 is formed, and a redistributed conductive layer 614 and a first conductive bump 611 are formed on the front side 6102 of the DRAM memory chip 610. A first conductive post 612 is formed through the DRAM memory chip 610, and a third conductive bump 613 is formed on the back side 6101 of the DRAM memory chip 610. Part of the third conductive bump 613 is connected to the first conductive post 612, and part of the first conductive post 612 is connected to the redistributed conductive layer 614.

[0106] Please refer to Figure 6A The NAND flash memory chip 620 and the DRAM memory chip 610 are stacked and connected. Specifically, the back surface 6201 of the NAND flash memory chip 620 faces the front surface 6102 of the DRAM memory chip 610; the first conductive bump 611 and the second conductive bump 623 are electrically connected by metal bonding, and the back surface 6201 of the NAND flash memory chip 620 and the front surface 6102 of the DRAM memory chip 610 are bonded and fixed at other locations by an adhesive layer (not shown in the figure). The third conductive bump 613 can be electrically connected to the I / O interface circuit through processes such as metal bonding or soldering.

[0107] Please refer to Figure 11A , 11B And 7A, for example Figure 7A The diagram shows a structural schematic of the semiconductor memory device formation process.

[0108] Please refer to Figure 11A A NAND memory chip 720 is formed, a redistributed conductive layer 722 is formed on the front side 7202 of the NAND memory chip 720, and a second conductive post 721 is formed through the NAND memory chip 720, the conductive post 721 being connected to the redistributed conductive layer 722; a second conductive bump 723 is formed on the back side 7201 of the NAND memory chip 720, connecting to the second conductive post 721.

[0109] Please refer to Figure 11B A DRAM memory chip 710 is formed, and a first conductive bump 711 is formed on the back side 7101 of the DRAM memory chip 710; a first conductive post 712 is formed penetrating the DRAM memory chip 710, and the first conductive post 712 is connected to the first conductive bump 711; a third conductive bump 613 and a redistributed conductive layer 714 are formed on the front side 7102 of the DRAM memory chip 710, and a portion of the third conductive bump 713 is connected to the first conductive post 712, and a portion of the first conductive post 712 is connected to the redistributed conductive layer 714.

[0110] Please refer to Figure 7AThe NAND flash memory chip 720 and the DRAM memory chip 710 are stacked and connected. The back surface 7201 of the NAND flash memory chip 720 faces the back surface 7101 of the DRAM memory chip. The first conductive bump 711 and the second conductive bump 723 are connected by metal bonding. The third conductive bump 713 can be connected to the I / O interface circuit through processes such as metal bonding or soldering.

[0111] In other specific embodiments of the present invention, the connection method of conductive pillars and conductive bumps can be reasonably set according to the specific circuit positions within the DRAM memory chip and the NAND memory chip to realize the vertical interconnection between the DRAM memory chip and the NAND memory chip, as well as the electrical connection between the DRAM memory chip and the I / O interface circuit.

[0112] The above-mentioned semiconductor memory device manufacturing method stacks and connects two memory chips, which can improve the integration of the memory device; and, by stacking and connecting the two memory chips and forming conductive pillars that penetrate the memory chips, vertical interconnection between the two memory chips can be achieved, which can shorten the data transmission path and improve the transmission efficiency.

[0113] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized in that, include: A first memory chip, wherein a first memory array and peripheral circuitry are formed within the first memory chip, the peripheral circuitry including a first circuit, a second circuitry and a common circuitry; The second memory chip contains only a second memory array; the first memory array is a volatile memory array, and the second memory array is a non-volatile memory array. The first circuit and the shared circuit are used to control the first storage array, the second circuit and the shared circuit are used to control the second storage array, the first circuit is connected to the first storage array, the second circuit is connected to the second storage array, and the shared circuit is connected to the first circuit and the second circuit. The back side of the second memory chip is stacked on the surface of the first memory chip; The second memory chip has a second conductive post that penetrates through it, and the second memory chip is electrically connected to the first memory chip through the second conductive post.

2. The semiconductor memory device according to claim 1, characterized in that, The second memory chip has a second conductive bump on its back side that connects to the second conductive post, and an electrical connection is formed between the second conductive bump and the first memory chip.

3. The semiconductor memory device according to claim 1, characterized in that, It also includes a substrate on which an I / O interface circuit is formed; the peripheral circuit is electrically connected to the I / O interface circuit of the substrate.

4. The semiconductor memory device according to claim 3, characterized in that, The peripheral circuit is formed in the edge region of the first memory chip and is electrically connected to the I / O interface circuit of the substrate through bonding leads.

5. The semiconductor memory device according to claim 3, characterized in that, A first conductive post is formed inside the first memory chip, and a second conductive post is electrically connected to the first conductive post.

6. The semiconductor memory device according to claim 5, characterized in that, The surface of the first memory chip away from the second memory chip has a first conductive bump that connects to the first conductive post; the first conductive bump is electrically connected to the I / O interface circuit of the substrate.

7. The semiconductor memory device according to claim 1, characterized in that, A redistributed conductive layer is formed on the front and / or back of the first memory chip.

8. A method for manufacturing a semiconductor memory device, characterized in that, include: A first memory chip is formed, and a first memory array and peripheral circuits are formed within the first memory chip. The peripheral circuits include a first circuit, a second circuit, and a common circuit. A second memory chip is formed, which contains only a second memory array and a second conductive pillar penetrating the second memory chip; the first memory array is a volatile memory array, and the second memory array is a non-volatile memory array. The first circuit and the shared circuit are used to control the first storage array, the second circuit and the shared circuit are used to control the second storage array, the first circuit is connected to the first storage array, the second circuit is connected to the second storage array, and the shared circuit is connected to the first circuit and the second circuit. The back side of the second memory chip is stacked on the surface of the first memory chip, and the second memory chip is electrically connected to the first memory chip through the second conductive post.

9. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, It also includes forming a second conductive bump on the back of the second memory chip to connect to the second conductive post; and forming an electrical connection between the second conductive bump and the first memory chip.

10. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, It also includes providing a substrate on which an I / O interface circuit is formed; and forming an electrical connection between the peripheral circuits in the first memory chip and the I / O interface circuit of the substrate.

11. The method for manufacturing a semiconductor memory device according to claim 10, characterized in that, The peripheral circuit is formed on the edge region of the first memory chip, and the I / O interface circuit of the substrate is electrically connected to the peripheral circuit through wire bonding process.

12. The method for manufacturing a semiconductor memory device according to claim 10, characterized in that, It also includes forming a first conductive post that penetrates the first memory chip; and forming an electrical connection between the second conductive post and the first conductive post.

13. The method for manufacturing a semiconductor memory device according to claim 12, characterized in that, A first conductive bump is formed on the surface of the first memory chip away from the second memory chip to connect to the first conductive post; an electrical connection is formed between the first conductive bump and the I / O interface circuit of the substrate.

14. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, It also includes forming a redistributed conductive layer on the front and / or back of the first memory chip.

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