Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and its manufacturing method are disclosed. The semiconductor memory device includes: a first memory chip, in which a first memory array is formed; a second memory chip, in which a second memory array is formed; the first memory chip and the second memory chip are stacked to form an electrical connection; the first memory chip has a first circuit, at least a portion of a second circuit, and a common circuit formed therein; the first circuit controls the first memory array; the second circuit controls the second memory array; the first circuit is connected to the first memory array; the second circuit is connected to the second memory array; and the common circuit connects the first circuit and the second circuit. The semiconductor memory device improves integration and data transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a semiconductor memory device and its manufacturing method. Background Technology

[0002] Because volatile memory chips (such as DRAM) have faster read speeds, while non-volatile memory chips (such as NAND flash) have the advantage of retaining data even when power is off, most modern data processing systems need to include both volatile and non-volatile memory chips to take advantage of their respective strengths. Since volatile and non-volatile memory chips have different structures, they are typically manufactured using different process technologies, forming separate chips.

[0003] When a data processing system includes both volatile and non-volatile memory chips, the two types of chips typically exist independently and are connected to each other via transmission lines for data transmission. The disadvantages of this approach are the long transmission path between the volatile and non-volatile memory chips, bandwidth limitations in the chip interfaces and transmission lines, restricted data exchange speed, and a relatively large overall size, making it difficult to adapt to applications requiring high integration.

[0004] Therefore, improving the data transfer speed between volatile and non-volatile memory chips and increasing integration are urgent problems to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a semiconductor memory device and a method for manufacturing the same, so as to improve the integration and data transmission speed of the semiconductor memory device.

[0006] To address the aforementioned problems, the present invention provides a semiconductor memory device, comprising: a first memory chip, wherein a first memory array is formed within the first memory chip; a second memory chip, wherein a second memory array is formed within the second memory chip; the first memory chip and the second memory chip are stacked together to form an electrical connection; the first memory chip further comprises a first circuit, at least a portion of a second circuit, and a common circuit, wherein the first circuit is used to control the first memory array, the second circuit is used to control the second memory array, the first circuit is connected to the first memory array, the second circuit is connected to the second memory array, and the common circuit is connected to the first circuit and the second circuit.

[0007] Optionally, the first storage array is a volatile storage array, and the second storage array is a non-volatile storage array.

[0008] Optionally, the shared circuit includes one or more of the following: a control logic unit, a bandgap reference unit, a bias unit, a power management unit, a time-division multiplexing unit, or a calibration unit.

[0009] Optionally, the storage array is a two-dimensional or three-dimensional storage array.

[0010] Optionally, the first memory chip and the second memory chip use monocrystalline silicon or polycrystalline silicon substrates.

[0011] Optionally, the first circuit is connected to the I / O interface of the semiconductor memory device, and the second memory array is connected to the I / O interface through the second circuit, the common circuit, and the first circuit. The first memory array is connected to the I / O interface through the first circuit.

[0012] Optionally, the second circuit and the first circuit are respectively connected to the I / O interface of the semiconductor memory device, the first memory array is connected to the I / O interface through the first circuit, and the second memory array is connected to the I / O interface through the second circuit.

[0013] Optionally, the common circuit includes an interface control unit, the first circuit and the second circuit are respectively connected to the interface control unit, the interface control unit is connected to the I / O interface of the semiconductor memory device, and the first memory array and the second memory array are connected to the I / O interface through the interface control unit.

[0014] The present invention also provides a method for manufacturing a semiconductor memory device, comprising: forming a first memory chip, wherein the first memory chip has a first memory array, a first circuit, at least a portion of a second circuit, and a common circuit formed therein; forming a second memory chip, wherein the second memory chip has a second memory array formed therein; the first circuit is used to control the first memory array, the second circuit is used to control the second memory array, the first circuit is connected to the first memory array, the second circuit is connected to the second memory array, and the common circuit is connected to the first circuit and the second circuit; and stacking the first memory chip and the second memory chip to form an electrical connection.

[0015] Optionally, the first storage array is a volatile storage array, and the second storage array is a non-volatile storage array.

[0016] Optionally, the shared circuit includes one or more of the following: a control logic unit, a bandgap reference unit, a bias unit, a power management unit, a time-division multiplexing unit, or a calibration unit.

[0017] Optionally, the storage array is a two-dimensional or three-dimensional storage array.

[0018] Optionally, the first memory chip and the second memory chip use monocrystalline silicon or polycrystalline silicon substrates.

[0019] Optionally, it further includes forming an I / O interface on the first memory chip, the first circuit being connected to the I / O interface of the semiconductor memory device, the second memory array being connected to the I / O interface through the second circuit, the common circuit, and the first circuit, and the first memory array being connected to the I / O interface through the first circuit.

[0020] Optionally, it further includes forming an I / O interface on the first memory chip, with the second circuit and the first circuit respectively connected to the I / O interface of the semiconductor memory device, the first memory array connected to the I / O interface through the first circuit, and the second memory array connected to the I / O interface through the second circuit.

[0021] Optionally, it further includes forming an I / O interface on the first memory chip; the common circuit includes an interface control unit, the first circuit and the second circuit are respectively connected to the interface control unit, the interface control unit is connected to the I / O interface of the semiconductor memory device, and the first memory array and the second memory array are connected to the I / O interface through the interface control unit.

[0022] In this invention, the first and second memory chips of the semiconductor memory device are electrically connected by stacking them together. This significantly reduces the I / O connection length for signal transmission between the two chips, greatly reduces the power consumption of the connection circuit, and improves transmission efficiency. Furthermore, stacking the first and second memory chips together, compared to placing the two chips separately, greatly reduces the area of ​​the semiconductor memory device and improves integration.

[0023] Furthermore, since the first memory chip and the second memory chip are close to each other, the memory arrays of the first memory chip and the second memory chip can share some circuits, thereby saving circuit area and reducing power consumption. Attached Figure Description

[0024] Figures 1A to 1D This is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the module structure of a semiconductor memory device according to a specific embodiment of the present invention; Figure 3 This is a schematic diagram of the common circuit of a semiconductor memory device according to a specific embodiment of the present invention; Figures 4A to 4CThis is a schematic diagram illustrating the data input / output method of the first and second memory chips according to a specific embodiment of the present invention.

[0025] Figure 5 This is a schematic flowchart illustrating the manufacturing process of a semiconductor memory device according to a specific embodiment of the present invention. Detailed Implementation

[0026] The following detailed description, in conjunction with the accompanying drawings, illustrates specific embodiments of a semiconductor memory device and its manufacturing method provided by the present invention.

[0027] Please refer to Figure 1, which is a schematic diagram of the structure of a semiconductor memory device according to a specific embodiment of the present invention.

[0028] The semiconductor memory device of this specific embodiment includes: a first memory chip 101 and a second memory chip 102, wherein the first memory chip 101 and the second memory chip 102 are stacked and connected.

[0029] The first memory chip 101 and the second memory chip 102 can be different types of memory chips. In one specific embodiment, the first memory chip 101 is a volatile memory chip, and the second memory chip 102 is a non-volatile memory chip. In this specific embodiment, the first memory chip 101 is a DRAM chip, and the second memory chip 102 is a NAND chip. In other specific embodiments, the first memory chip 101 can also be an SRAM chip, and the second memory chip 102 can also be a non-volatile memory chip such as a PROM or EPROM.

[0030] The first memory chip 101 includes a first memory array, which is a DRAM memory array; the second memory chip 102 includes a second memory array, which is a NAND memory array. The first memory array and the second memory array can be two-dimensional or three-dimensional memory arrays, and the substrates of the first memory chip 101 and the second memory chip 102 can be polycrystalline silicon or monocrystalline silicon, that is, the first memory array and the second memory array are formed on a polycrystalline silicon or monocrystalline silicon substrate.

[0031] The first memory chip 101 and / or the second memory chip 102 may also have peripheral circuits for controlling the first memory array and controlling the second memory array.

[0032] The first memory chip 101 and the second memory chip 102 are stacked and connected to each other. The first memory chip 101 includes a front side 1012 and a back side 1011, and the second memory chip 102 includes a front side 1022 and a back side 1021, which are opposite to the front side. The front side refers to the device layer surface of the memory chip, and the back side refers to the other surface opposite to the front side.

[0033] Please refer to Figure 1A In this specific embodiment, the front side 1012 of the first memory chip 101 and the front side 1022 of the second memory chip 102 are stacked and connected opposite each other. In other specific embodiments, the back side 1021 of the second memory chip 102 and the front side 1012 of the first memory chip 101 are stacked and connected opposite each other (see reference). Figure 1B In other specific embodiments, the front side 1022 of the second memory chip 102 is stacked and connected opposite to the back side 1011 of the first memory chip 101 (see reference). Figure 1C In other specific embodiments, the back surface 1021 of the second memory chip 102 is stacked and connected opposite to the back surface 1011 of the first memory chip 101 (see reference). Figure 1D ).

[0034] Both the first memory chip 101 and the second memory chip 102 have interconnect structures such as interconnect lines and interconnect pillars. The first memory chip 101 and the second memory chip 102 can be electrically connected through the interconnect structures.

[0035] Please refer to Figure 1A In this specific embodiment, the front side 1012 of the first memory chip 101 and the front side 1022 of the second memory chip 102 are stacked and connected. The second memory chip 102 and the interconnect structure exposed on the front side of the first memory chip 101 are bonded together with metal, and the dielectric layer on the front side of the second memory chip 102 and the first memory chip 101 are bonded together with adhesive. While realizing the stacking of the first memory chip 101 and the second memory chip 102, electrical connection is achieved through the metal bonding between the interconnect structures.

[0036] In another specific embodiment, the first memory chip 101 and the second memory chip 102 may both have passivation layers formed on their front sides. Through the bonding process between the two passivation layers, the first memory chip 101 and the second memory chip 102 are stacked and bonded. Furthermore, the corresponding connection between the first memory chip 101 and the second memory chip 102 is achieved through a deep through-hole connection structure that penetrates the first memory chip 101 and / or the second memory chip 102.

[0037] In other specific embodiments, the first memory chip 101 and the second memory chip 102 can also be stacked together using other bonding methods and interconnection structures. Those skilled in the art can make reasonable designs as needed.

[0038] Because the first memory chip 101 and the second memory chip 102 are stacked together and electrically connected directly through an interconnect structure, the I / O connection length for signal transmission between the two chips can be greatly reduced, significantly reducing the power consumption of the connection circuit and improving transmission efficiency. Furthermore, the stacking of the first memory chip 101 and the second memory chip 102, compared to placing the two chips separately, can greatly reduce the area of ​​the semiconductor memory device and improve integration.

[0039] Since the first memory chip 101 and the second memory chip 102 are close to each other, the memory arrays of the first memory chip 101 and the second memory chip 102 can share some circuits, thereby saving circuit area and reducing power consumption.

[0040] Please refer to Figure 2 In this specific embodiment, since the first memory chip 101 is a DRAM memory chip, and the storage density of the DRAM memory array is relatively low, the first memory chip 101, in addition to the DRAM memory array 201, may also form a DRAM dedicated circuit 202, a NAND dedicated circuit 204, and a common circuit 203. The second memory chip 102 is a NAND memory chip, forming a NAND memory array 205. The DRAM memory array is connected to the DRAM dedicated circuit 202, and the NAND memory array 205 is connected to the NAND dedicated circuit 204.

[0041] The dedicated DRAM circuit 202 corresponds to the DRAM storage array 201. Specifically, the dedicated DRAM circuit 202 includes a serial-to-parallel converter, a double data transmission control circuit, etc., and is used to control the DRAM storage array.

[0042] The dedicated NAND circuit 204 corresponds to the NAND memory array. Specifically, the dedicated NAND circuit 204 includes control circuits related to programming / erase operations, as well as high-voltage generation circuits, etc., for controlling the NAND memory array 205.

[0043] The common circuit 203 connects the DRAM dedicated circuit 202 and the NAND dedicated circuit 204. Since only the NAND memory array 205 needs to be formed within the second memory chip 102, the process difficulty of forming the second memory chip 102 can be reduced, and the process cycle can be shortened.

[0044] Please refer to Figure 2 The first memory chip 101 and the second memory chip 102 are stacked on top of each other, and the NAND memory array 205 is electrically connected to the NAND dedicated circuit 204.

[0045] In other specific embodiments, all or part of the circuits in the NAND dedicated circuit 204, the common circuit 203, and the DRAM dedicated circuit 202 may also be formed within the second memory chip 102.

[0046] Please refer to Figure 3 This is a schematic diagram of the structure of the common circuit 203 according to a specific embodiment of the present invention.

[0047] The shared circuit 203 includes a power management unit 2031, a bandgap reference unit 2032, a time-division multiplexing unit 2033, and a calibration unit 2034. It may also include a control logic unit, a bias unit, etc., and can be used by the DRAM storage array 201 and the NAND storage array 205 for data transmission.

[0048] The DRAM dedicated circuit 202 and the NAND dedicated circuit 204 are respectively connected to the power management unit 2031, the bandgap reference unit 2032, and the time-division multiplexing unit 2033. The calibration unit 2034 is connected to the time-division multiplexing unit 2033.

[0049] Please refer to Figures 4A to 4C This is a schematic diagram of the data input / output method of the first memory chip 101 and the second memory chip 102, which is a specific embodiment of the present invention.

[0050] Please combine Figure 2 In one specific embodiment, the DRAM dedicated circuit 202 is connected to the I / O interface of the semiconductor memory device. The NAND memory array 205 is connected to the I / O interface through the NAND dedicated circuit 204, the common circuit 203, and the DRAM dedicated circuit 202. The DRAM memory array 201 is connected to the I / O interface through the DRAM dedicated circuit. For details, please refer to... Figure 4AThe NAND flash memory array 205 of the second memory chip directly transmits data with the DRAM memory array 201 of the first memory chip. When data needs to be read from the NAND flash memory array 205, the data in the NAND flash memory array 205 is first output to the DRAM memory array 201 of the first memory chip, and then the DRAM memory array 201 outputs the data outward, acting as a buffer. The I / O interface can directly control the DRAM memory array through the dedicated DRAM circuit 202; the I / O interface controls the NAND flash memory array 205 through the dedicated DRAM circuit 202, the common circuit 203, and the dedicated NAND circuit 204.

[0051] In another specific embodiment, the NAND dedicated circuit 204 and the DRAM dedicated circuit 202 are respectively connected to the I / O interface of the semiconductor memory device. The DRAM memory array 201 is connected to the I / O interface through the DRAM dedicated circuit 202, and the NAND memory array 205 is connected to the I / O interface through the NAND dedicated circuit 204. Please refer to... Figure 4B The NAND storage array 205 and the DRAM storage array 201 can respectively input and output data.

[0052] Please refer to Figure 4C In another specific embodiment, the shared circuit 203 includes an interface control unit 401. The DRAM dedicated circuit 202 and the NAND dedicated circuit 204 are respectively connected to the interface control unit 401. The interface control unit 401 is connected to the I / O interface of the semiconductor memory device. The DRAM memory array 201 and the NAND memory array 205 are connected to the I / O interface through the interface control unit 401. The interface control unit 401 can be part of the shared circuit of the NAND memory array 205 and the DRAM memory array 201, and is used for time-division multiplexing control, data protocol conversion, etc. The interface control unit 401 controls the data input and output between the NAND memory array 205 and the DRAM memory array 201.

[0053] In other specific implementations, appropriate NAND dedicated circuits, DRAM dedicated circuits, and shared circuits can be designed according to requirements to realize various forms of I / O methods.

[0054] In the above specific embodiments, since the first memory chip and the second memory chip are stacked and connected, the I / O transmission path is shortened, and the I / O transmission mode of the first memory chip and the second memory chip can be flexibly set.

[0055] A specific embodiment of the present invention also provides a method for manufacturing a semiconductor memory device.

[0056] Please refer to Figure 5 This is a schematic flowchart illustrating the formation process of a semiconductor memory device according to a specific embodiment of the present invention.

[0057] Please refer to this as well. Figures 1A to 1D The method for manufacturing the semiconductor memory device includes: Step S101: Form a first memory chip, in which a first memory array is formed.

[0058] The first memory chip 101 can be a volatile memory chip. In this specific embodiment, the first memory chip 101 is a DRAM chip. The first memory chip 101 can also be an SRAM chip.

[0059] The first memory chip 101 includes a first memory array, which in this specific embodiment is a DRAM memory array. The first memory array can be a two-dimensional or three-dimensional memory array. The first memory chip 101 includes a polycrystalline silicon or monocrystalline silicon substrate, and the first memory array is formed on the polycrystalline silicon or monocrystalline silicon substrate.

[0060] Step S102: Form a second memory chip, in which a second memory array is formed.

[0061] The second memory chip 102 can be a non-volatile memory chip. In this specific embodiment, the second memory chip 102 is a NAND chip. The second memory chip 102 can also be a non-volatile memory chip such as a PROM or EPROM.

[0062] The second memory chip 102 includes a second memory array, which in this specific embodiment is a NAND memory array. The second memory array can be a two-dimensional or three-dimensional memory array. The second memory chip 102 includes a polycrystalline silicon or monocrystalline silicon substrate, and the second memory array is formed on the polycrystalline silicon or monocrystalline silicon substrate.

[0063] Steps S101 and S102 further include forming peripheral circuits for controlling the first memory array and the second memory array within the first memory chip 101 and / or the second memory chip 102. These peripheral circuits include a first circuit, a second circuit, and a shared circuit. The first circuit controls the first memory array, and the second circuit controls the second memory array. The first circuit is connected to the first memory array, the second circuit is connected to the second memory array, and the shared circuit connects the first circuit and the second circuit.

[0064] In this specific embodiment, step S101 includes forming a DRAM dedicated circuit 202, a NAND dedicated circuit 204, and a common circuit 203 on the substrate of the first memory chip (please refer to...). Figure 2 The DRAM dedicated circuit 202 may include a serial-to-parallel converter, a double data transfer control circuit, etc., for controlling the DRAM memory array 201. The NAND dedicated circuit 204 may include control circuits related to programming / erase operations, as well as a high-voltage generation circuit, etc., for controlling the NAND memory array 205. The common circuit 203 connects the DRAM dedicated circuit 202 and the NAND dedicated circuit 204. The common circuit 203 may include: a control logic unit, a bandgap reference unit, a bias unit, a power management unit, a time-division multiplexing unit, and a calibration unit. In step S102 of this specific embodiment, only the second memory array needs to be formed, without the need to form other peripheral circuits, thereby reducing the process difficulty of forming the second memory chip and shortening the process cycle.

[0065] In other specific embodiments, all or part of the circuits in the NAND dedicated circuit 204, the common circuit 203, and the DRAM dedicated circuit 202 may also be formed within the second memory chip 102.

[0066] Step S103: Stack the first memory chip and the second memory chip to form an electrical connection.

[0067] Please refer to Figures 1A to 1C The front side 1012 of the first memory chip 101 and the front side 1022 of the second memory chip 102 can be stacked and connected opposite each other. In other specific embodiments, the back side 1021 of the second memory chip 102 and the front side 1012 of the first memory chip 101 can be stacked and connected opposite each other (see reference). Figure 1B In other specific embodiments, the front side 1022 of the second memory chip 102 can be stacked opposite to the back side 1011 of the first memory chip 101 (see reference). Figure 1C In other specific embodiments, the back surface 1021 of the second memory chip 102 is stacked and connected opposite to the back surface 1011 of the first memory chip 101 (see reference). Figure 1D ).

[0068] Interconnection structures such as interconnect lines and interconnect pillars can be formed in the first memory chip 101 and the second memory chip 102 in steps S101 and S102. Then, after stacking the first memory chip 101 and the second memory chip 102, the electrical connection between the first memory chip 101 and the second memory chip 102 is realized through the interconnection structure.

[0069] Please refer to Figure 1A In this specific embodiment, the front side 1012 of the first memory chip 101 and the front side 1022 of the second memory chip 102 are connected by stacking. The second memory chip 102 and the interconnect structure exposed on the front side of the first memory chip 101 are bonded together by metal bonding, and the dielectric layer on the front side of the second memory chip 102 and the first memory chip 101 are bonded together by adhesive layer. While realizing the stacking of the first memory chip 101 and the second memory chip 102, electrical connection is achieved through the metal bonding between the interconnect structures.

[0070] In another specific embodiment, the first memory chip 101 and the second memory chip 102 may both have passivation layers formed on their front sides. Through the bonding process between the two passivation layers, the first memory chip 101 and the second memory chip 102 can be stacked and bonded. The corresponding connection between the first memory chip 101 and the second memory chip 102 can be achieved through a deep through-hole connection structure that penetrates the first memory chip 101 and / or the second memory chip 102.

[0071] In other specific embodiments, the first memory chip 101 and the second memory chip 102 can also be stacked together using other bonding methods and interconnection structures. Those skilled in the art can make reasonable designs as needed.

[0072] By directly connecting the first memory chip 101 and the second memory chip 102 through an interconnect structure by stacking the chips together, the I / O connection length for signal transmission can be greatly reduced, the power consumption of the connection circuit can be greatly reduced, and the transmission efficiency can be improved. Furthermore, stacking the first memory chip 101 and the second memory chip 102 together, compared to placing the two chips separately, can significantly reduce the area of ​​the semiconductor memory device and improve the integration density.

[0073] Since the first memory chip 101 and the second memory chip 102 are close to each other, the memory arrays of the first memory chip 101 and the second memory chip 102 can share some circuits, thereby saving circuit area and reducing power consumption.

[0074] The method for manufacturing the semiconductor memory device further includes: forming an I / O interface on the first memory chip or the second memory chip for controlling the semiconductor memory device. In one specific embodiment, the first circuit can be connected to the I / O interface of the semiconductor memory device, and the second memory array is connected to the I / O interface through the second circuit, a common circuit, and the first circuit. The first memory array is connected to the I / O interface through the first circuit. In another specific embodiment, the second circuit and the first circuit can be respectively connected to the I / O interface of the semiconductor memory device, the first memory array is connected to the I / O interface through the first circuit, and the second memory array is connected to the I / O interface through the second circuit. In another specific embodiment, the common circuit includes an interface control unit, the first circuit and the second circuit are respectively connected to the interface control unit, the interface control unit is connected to the I / O interface of the semiconductor memory device, and the first memory array and the second memory array are connected to the I / O interface through the interface control unit.

[0075] In other specific implementations, appropriate NAND dedicated circuits, DRAM dedicated circuits, and shared circuits can be designed according to requirements to achieve various forms of I / O.

[0076] The above-mentioned semiconductor memory device manufacturing method stacks and connects two memory chips, which can improve the integration of the memory device; and the stacking and connection between the two memory chips can shorten the data transmission path and improve the transmission efficiency.

[0077] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor memory device, characterized by comprising: include: A first memory chip, wherein a first memory array is formed within the first memory chip; The second memory chip contains only a second memory array. The first memory chip and the second memory chip are stacked to form an electrical connection; the first memory array is a volatile memory array, and the second memory array is a non-volatile memory array. The first memory chip also includes a first circuit, a second circuit, and a common circuit. The first circuit and the common circuit are used to control the first memory array, the second circuit and the common circuit are used to control the second memory array, the first circuit is connected to the first memory array, the second circuit is connected to the second memory array, and the common circuit is connected to the first circuit and the second circuit.

2. The semiconductor storage device according to claim 1, wherein The shared circuit includes one or more of the following: a control logic unit, a bandgap reference unit, a bias unit, a power management unit, a time-division multiplexing unit, or a calibration unit.

3. The semiconductor memory device according to claim 1, characterized in that, The storage array is a two-dimensional or three-dimensional storage array.

4. The semiconductor memory device according to claim 1, characterized in that, The first memory chip and the second memory chip use monocrystalline silicon or polycrystalline silicon substrates.

5. The semiconductor memory device according to claim 1, characterized in that, The first circuit is connected to the I / O interface of the semiconductor memory device. The second memory array is connected to the I / O interface through the second circuit, the common circuit, and the first circuit. The first memory array is connected to the I / O interface through the first circuit.

6. The semiconductor memory device according to claim 1, characterized in that, The second circuit and the first circuit are respectively connected to the I / O interface of the semiconductor memory device. The first memory array is connected to the I / O interface through the first circuit, and the second memory array is connected to the I / O interface through the second circuit.

7. The semiconductor memory device according to claim 1, characterized in that, The common circuit includes an interface control unit. The first circuit and the second circuit are respectively connected to the interface control unit. The interface control unit is connected to the I / O interface of the semiconductor memory device. The first memory array and the second memory array are connected to the I / O interface through the interface control unit.

8. A method for manufacturing a semiconductor memory device, characterized in that, include: A first memory chip is formed, and a first memory array, a first circuit, at least a portion of a second circuit, and a common circuit are formed within the first memory chip; A second memory chip is formed, and only a second memory array is formed within the second memory chip; the first memory array is a volatile memory array, and the second memory array is a non-volatile memory array; The first circuit and the shared circuit are used to control the first storage array, the second circuit and the shared circuit are used to control the second storage array, the first circuit is connected to the first storage array, the second circuit is connected to the second storage array, and the shared circuit is connected to the first circuit and the second circuit. The first memory chip and the second memory chip are stacked to form an electrical connection.

9. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, The shared circuit includes one or more of the following: a control logic unit, a bandgap reference unit, a bias unit, a power management unit, a time-division multiplexing unit, or a calibration unit.

10. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, The storage array is a two-dimensional or three-dimensional storage array.

11. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, The first memory chip and the second memory chip use monocrystalline silicon or polycrystalline silicon substrates.

12. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, It also includes forming an I / O interface, wherein the first circuit is connected to the I / O interface of the semiconductor memory device, and the second memory array is connected to the I / O interface through the second circuit, the common circuit and the first circuit, and the first memory array is connected to the I / O interface through the first circuit.

13. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, It also includes forming an I / O interface, wherein the second circuit and the first circuit are respectively connected to the I / O interface of the semiconductor memory device, the first memory array is connected to the I / O interface through the first circuit, and the second memory array is connected to the I / O interface through the second circuit.

14. The method for manufacturing a semiconductor memory device according to claim 8, characterized in that, It also includes forming an I / O interface; the common circuit includes an interface control unit, the first circuit and the second circuit are respectively connected to the interface control unit, the interface control unit is connected to the I / O interface of the semiconductor memory device, and the first memory array and the second memory array are connected to the I / O interface through the interface control unit.

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