Memory array and method for forming a memory array including memory cell strings

Abstract

The present application relates to memory arrays and methods for forming memory arrays including strings of memory cells. A memory array including strings of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The active channel material strings of the memory cells extend through the insulating layers and the conductive layers. The active channel material strings in the laterally spaced memory blocks include a portion of a memory plane. A wall extending in height is in the memory plane laterally between laterally adjacent memory blocks, and it completely surrounds an island in the memory plane laterally between laterally adjacent memory blocks. Other embodiments including methods are disclosed.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and methods for forming memory arrays including strings of memory cells. Background Art

[0002] Memory is a type of integrated circuit system and is used in computer systems to store data. Memory can be manufactured in one or more arrays of individual memory cells. Memory cells can be written or read using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines can conductively interconnect memory cells along the columns of the array, and access lines can conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long time without power. Traditionally, non-volatile memory is specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and therefore needs to be refreshed / rewritten to maintain data storage. Volatile memory can have a retention time of several milliseconds or less. In any case, the memory cell is configured to hold or store memory in at least two different selectable states. In a binary system, the state is considered to be "0" or "1". In other systems, at least some individual memory cells can be configured to store information at more than two levels or states.

[0004] A field effect transistor is a type of electronic component that can be used in a memory cell. These transistors include a pair of conductive source / drain regions with a semiconductor channel region between them. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of an appropriate voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also contain additional structures, such as a reversibly programmable charge storage region, as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and has many uses in modern computers and devices. For example, a modern personal computer may store the BIOS on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid-state drives instead of traditional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be used as a basic architecture for integrated flash memory. A NAND cell includes at least one selection device that is coupled in series to a series combination of memory cells (the series combination is generally referred to as a NAND string). The NAND architecture can be configured in a three-dimensional arrangement including vertically stacked memory cells that each include a reversibly programmable vertical transistor. Control circuitry or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that each include a transistor.

[0007] The memory array may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks) and memory planes, for example, as shown and described in U.S. Patent Application Publication Nos. 2015 / 0228659, 2016 / 0267984, and 2017 / 0140833, which are hereby and fully incorporated herein by reference, and various aspects of which may be used in some embodiments of the invention disclosed herein. The memory block may at least partially define the longitudinal profile of each word line in each word line layer of the vertically stacked memory cells. The connection to these word lines may appear at the end or edge of the array of vertically stacked memory cells in a so-called "staircase structure". The staircase structure includes each "rung" (or also referred to as a "step" or "staircase") defining the contact area of ​​each word line, and a conductive through-hole contact extending in height above the contact area to provide electrical access to the word line. Summary of the invention

[0008] One aspect of the present disclosure provides a memory array including a string of memory cells, wherein the memory array includes: laterally spaced memory blocks, the memory blocks respectively including vertical stacks, the vertical stacks including alternating insulating layers and conductive layers, and effective channel material strings of memory cells extend through the insulating layers and the conductive layers in a memory array region; the insulating layers and the conductive layers of the laterally spaced memory blocks extend from the memory array region to a step region adjacent to the memory array region, the insulating layers and the conductive layers of the memory blocks in the step region include effective step structures, the effective step structures are laterally spaced relative to each other and are respectively horizontally extended longitudinally; each step structure includes a pair of walls extending in height, the walls are laterally spaced inwardly from the sides of the corresponding step structure, are laterally spaced relative to each other, and are respectively horizontally extended longitudinally; and each step structure has no effective TAV laterally between the pair of walls.

[0009] Another aspect of the present disclosure provides a memory array including a string of memory cells, wherein the memory array includes: laterally spaced memory blocks, the memory blocks respectively including vertical stacks, the vertical stacks including alternating insulating layers and conductive layers, and effective channel material strings of memory cells extend through the insulating layers and the conductive layers in a memory array region; the insulating layers and the conductive layers of the laterally spaced memory blocks extend from the memory array region to a step region adjacent to the memory array region, the insulating layers and the conductive layers of the memory blocks in the step region include effective step structures, the effective step structures are laterally spaced relative to each other and are respectively horizontally elongated longitudinally; and each step structure includes a pair of walls extending in height, the walls are laterally spaced inwardly from the sides of the corresponding step structure, are laterally spaced relative to each other, and are respectively horizontally elongated longitudinally; at least one of the walls is neither horizontally and longitudinally oriented parallel to the horizontal of its respective step structure, nor is it angled orthogonally relative to the horizontal longitudinal orientation.

[0010] Another aspect of the present disclosure provides a memory array including a string of memory cells, wherein the memory array includes: laterally spaced memory blocks, the memory blocks respectively including vertical stacks, the vertical stacks including alternating insulating layers and conductive layers, and effective channel material strings of memory cells extend through the insulating layers and the conductive layers in a memory array region; the insulating layers and the conductive layers of the laterally spaced memory blocks extend from the memory array region to a step region adjacent to the memory array region, the insulating layers and the conductive layers of the memory blocks in the step region include effective step structures, the effective step structures are laterally spaced relative to each other and are respectively horizontally extended longitudinally; each step structure includes a pair of walls extending in height, the walls are laterally spaced inwardly from the sides of the corresponding step structure, are laterally spaced relative to each other, and are respectively horizontally extended longitudinally; and each step structure does not have any interconnecting walls extending laterally between the pair of walls.

[0011] Another aspect of the present disclosure provides a memory array including a string of memory cells, wherein the memory array includes: laterally spaced memory blocks, the memory blocks respectively including a vertical stack, the vertical stack including alternating insulating layers and conductive layers, an effective channel material string of the memory cell extending through the insulating layer and the conductive layer, the effective channel material string in the laterally spaced memory blocks including a portion of a memory plane; and a wall extending in height, the wall being in the memory plane laterally between the laterally adjacent memory blocks, and which completely surrounds an island, the island being laterally between the laterally adjacent memory blocks in the memory plane.

[0012] Another aspect of the present disclosure provides a memory array including a string of memory cells, wherein the memory array includes: laterally spaced memory blocks, the memory blocks respectively including a vertical stack, the vertical stack including alternating insulating layers and conductive layers, an effective channel material string of the memory cell extending through the insulating layers and the conductive layers, the effective channel material string in the laterally spaced memory blocks including a portion of a memory plane; and a pair of height-extending walls, the walls being laterally spaced relative to each other in the memory plane laterally between the laterally adjacent memory blocks and being respectively horizontally elongated longitudinally; at least one of the walls is not horizontally longitudinally oriented parallel to the horizontal direction of the laterally adjacent memory block between which at least one of the walls is laterally interposed.

[0013] Another aspect of the present disclosure provides a memory array including a string of memory cells, wherein the memory array includes: laterally spaced memory blocks, the memory blocks respectively including vertical stacks, the vertical stacks including alternating insulating layers and conductive layers, effective channel material strings of memory cells extending through the insulating layers and the conductive layers, the effective channel material strings in the laterally spaced memory blocks including a portion of a memory plane; and a pair of height-extending walls, the walls being laterally spaced relative to each other and respectively extending longitudinally horizontally, the pair of walls being edges of a plane.

[0014] Another aspect of the present disclosure provides a method for forming a memory array including a string of memory cells, wherein the method includes: forming a stack, the stack including a first layer and a second layer alternating vertically; forming horizontally elongated grooves in the stack to form laterally spaced memory block regions, the memory block regions including a portion of a memory plane region; and forming a wall extending in height in the memory plane region laterally between laterally adjacent memory block regions, the wall completely surrounding an island, the island being laterally between laterally adjacent memory block regions in the memory plane region.

[0015] Another aspect of the present disclosure provides a method for forming a memory array including a string of memory cells, wherein the method includes: forming a stack, the stack including a first layer and a second layer alternating vertically; forming horizontally elongated grooves in the stack to form laterally spaced memory block areas, the memory block areas including a portion of a memory plane area; and forming a pair of height-extending walls that are laterally spaced relative to each other and are respectively horizontally longitudinally elongated, the pair of walls being in an area that is a planar edge relative to the memory plane area.

[0016] Another aspect of the present disclosure provides a method for forming a memory array including a string of memory cells, wherein the method comprises: forming a stack, the stack comprising a first layer and a second layer alternating vertically, the stack comprising a memory array region and a step region; forming horizontally elongated trenches in the stack to form laterally spaced memory block regions, the memory block regions extending from the memory array region to the step region, the memory block regions in the step region comprising laterally spaced step structure regions; forming a pair of height-extending walls in the laterally spaced step structure regions, the walls being laterally spaced inwardly from the sides of the corresponding step structure regions, being laterally spaced relative to each other, and being respectively horizontally elongated longitudinally, the step structure regions being formed to include at least one of (a), (b) and (c), wherein: (a): each step structure region has no effective TAV laterally between the pair of walls; (b): at least one of the walls is neither horizontally parallel to the horizontal longitudinal orientation of its respective step structure region nor angled orthogonally relative to the horizontal longitudinal orientation; and (c): each step structure region has no interconnecting walls extending laterally between the pair of walls. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic top plan view of a die or a die region, which may be part of a larger substrate (eg, a semiconductor wafer, not shown).

[0018] Figure 2 is a process according to an embodiment of the present invention Figure 1 is an enlarged schematic cross-sectional view of a portion of Figure 3 Intercepted by line 2-2 in.

[0019] Figure 3 is through Figure 2 Schematic cross-sectional view taken along line 3-3 in FIG.

[0020] Figure 4-50 is a process according to some embodiments of the present invention Figure 1 Schematic sequential cross-sectional views and / or enlarged views of the structure or parts thereof. Due to drawing limitations, Figure 8 and 9 And the corresponding subsequent figure is approximately Figure 2 , 3 , 4, 5, 6 and half the proportion of 7.

[0021] Figure 51-59 Alternative and / or additional embodiments are shown. DETAILED DESCRIPTION

[0022] Some aspects of the invention are directed to overcoming problems associated with so-called "block bow" (the block stack tipping / tilting sideways relative to its longitudinal orientation during manufacture), although the invention is not limited thereto.

[0023] Embodiments of the present invention encompass methods for forming memory arrays (e.g., arrays of NAND or other memory cells) having peripheral control circuitry beneath the array (e.g., under-array CMOS). Embodiments of the present invention encompass so-called "gate last" or "generation gate" processing, so-called "gate first" processing, and other processes now known or developed in the future that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays (e.g., NAND architectures) that are independent of the method of manufacture. First, reference is made to Figures 1 to 50 An exemplary method embodiment is described, which may be considered a "gate last" or "generation gate" process. Further, and regardless, the following order of processing steps is provided as an example only, and other orders of the exemplary processing steps (with or without other processing steps) may be used, regardless of whether a "gate last / generation gate" process is used.

[0024] Figure 1 An exemplary illustrated embodiment is shown that includes a die or die area 100, which may be part of a larger substrate (e.g., a semiconductor wafer, not shown) and in which a memory array is to be fabricated. The exemplary die area 100 includes at least one memory plane area 105 (four are shown), memory block areas 58 in each memory plane area 105, step areas 60 (two are shown at the longitudinal ends of the memory plane), and peripheral circuitry areas PC (two are shown). In this document, a "block" generally includes a "sub-block". The step area 60 may be considered to include a platform area 62. Areas 105, 58, 60, 62 and / or PC may not be identifiable during processing. Figure 2-9 1 is a schematic enlarged and scaled view of portions of the die area 100 .

[0025] Reference Figure 2-9 , a construction 10 is shown in a method of forming an array / array region 12 of strings extending at a height of transistors and / or memory cells (not yet fabricated). Construction 10 includes a base substrate 11 having any one or more of conductive / conductor / conductive, semiconductive / semiconductor / semiconductive, or insulating / insulator / insulating (i.e., electrically herein) materials. Various materials have been formed at a height above base substrate 11. The materials may be located at Figure 2-9Next to, inwardly in height, or outwardly in height of the material shown. For example, other partially or fully manufactured components of the integrated circuit system may be provided somewhere above, around, or inside the base substrate 11. Control circuit systems and / or other peripheral circuit systems for components within an array (e.g., array 12 or memory array area 12) extending in height of the memory cells may also be manufactured, and may or may not be completely or partially within the array or sub-array. Further, multiple sub-arrays may also be manufactured and operated independently, in series, or in other ways relative to each other. In this document, a "sub-array" may also be considered an array.

[0026] A conductor layer 16 including conductive material 17 has been formed over substrate 11. Conductor layer 16 may include a portion of control circuitry (e.g., under-array peripheral circuitry and / or a common source line or plate) for controlling read and write access to transistors and / or memory cells to be formed in memory array region 12. A stack 18 including vertically alternating insulating layers 20 and conductive layers 22 has been formed over conductor layer 16. An exemplary thickness for each of layers 20 and 22 is 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown, and more likely stack 18 includes tens, a hundred, or more layers 20 and 22. Other circuitry that may or may not be part of the peripheral circuitry and / or control circuitry may be between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below the lowest layer of conductive layer 22 and / or above the highest layer of conductive layer 22. For example, one or more select gate layers (not shown) may be between the conductor layer 16 and the lowermost layer of the conductive layer 22, and one or more select gate layers may be above the uppermost layer of the conductive layer 22. Regardless, the conductive layer 22 (or first layer)) may not include conductive material, and the insulating layer 20 (or second layer) may not include insulating material or be insulating when processed in conjunction with the exemplary method embodiments initially described herein as "gate last" or "generation gate". The exemplary conductive layer 22 includes a first material 26 (e.g., silicon nitride) that may be sacrificial in whole or in part. The exemplary insulating layer 20 includes a second material 24 (e.g., silicon dioxide) that has a composition different from that of the first material 26 and may be sacrificial in whole or in part.

[0027] The stack 18 includes an array through (TAV) region (e.g., any one of regions 21, 21A, 21B) and an effective memory cell string region 23. The "effective memory cell string region" contains a circuit-effective memory cell string in a completed structure of an integrated circuit system that has been or is being manufactured. A dummy memory cell string (i.e., a circuit-ineffective memory cell string including an invalid channel material, not shown) may be between the TAV region and the effective memory cell string region 23 contained in the TAV region. The "TAV region" is a region in which an effective TAV exists or will be formed. An "effective TAV" is a circuit-effective conductive interconnect that extends through the stack 18 and between electronic components at different heights in the completed structure of an integrated circuit system that has been or is being manufactured. The TAV region may also contain one or more dummy TAVs (i.e., a circuit-ineffective structure extending through the stack 18, which may be in the completed structure of an integrated circuit system that has been or is being manufactured). When processed, in the structure 10, the regions 21 / 21A / 21B may be essentially indeterminate or indistinguishable relative to each other. The exemplary TAV region 21 is shown as being located at each memory plane 105 ( Figure 1 ). Area 21A( Figure 6 and 7 ) are shown as being located outside of the respective memory plane regions 105, and in one example are shown as being at the edge of the plane (i.e., being located outside of the memory plane regions 105 and adjacent to the lateral edge of the memory plane in question). Exemplary TAV regions 21B are shown as being located outside of the respective memory plane regions 105 in the step region 60. Laterally spaced apart step structure regions 64 are in the step region 60, may not be discernible during processing, and will comprise effective step structures 64 in the completed circuit system construction. The step structure regions 64 may be elongated horizontally and longitudinally (e.g., along the length of the step structure region 64). Figure 8 direction 55 as shown, near the stepped structure region 64).

[0028] Channel opening 25 has been formed (e.g., by etching) through insulating layer 20 and conductive layer 22 to conductor layer 16. In some embodiments, channel opening 25 may partially enter conductive material 17 of conductor layer 16 as shown or may stop on top thereof (not shown). Alternatively, as an example, channel opening 25 may stop on top of or inside the lowermost insulating layer 20. Extending channel opening 25 to at least conductive material 17 of conductor layer 16 is to ensure that subsequently formed channel material (not yet shown) is directly electrically coupled to conductor layer 16 without having to use alternative processes and structures to achieve such connection when such connection is desired. Etch stop material (not shown) may be inside or on top of conductive material 17 of conductor layer 16 to facilitate stopping etching of channel opening 25 relative to conductor layer 16 when desired. Such etch stop material may be sacrificial or non-sacrificial. Merely by way of example and for simplicity, the channel openings 25 are shown arranged in groups or columns of staggered rows of four and five openings 25 per row and arranged in laterally spaced memory block regions 58 that will comprise laterally spaced memory blocks 58 in the completed circuit system configuration. The memory block regions 58 and resulting memory blocks 58 (not yet shown) may be considered to be longitudinally elongated and oriented, e.g., along direction 55, which may be the same or different than the direction 55 referenced above with respect to the staircase structure region 64. Otherwise, the memory block regions 58 may not be discernible when processed. Any existing or future developed alternative arrangements and configurations may be used.

[0029] The transistor channel material may be formed in height in each channel opening along the insulating layer and the conductive layer, thereby including each channel material string, which is directly electrically coupled to the conductive material in the conductor layer. Each memory cell of the formed exemplary memory array may include a gate region (e.g., a control gate region) and a memory structure laterally interposed between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge passing material. The storage material of each memory cell (e.g., a floating gate material such as doped or undoped silicon or a charge trapping material such as silicon nitride, metal dots, etc.) is in height along each charge blocking region. The insulating charge passing material (e.g., a bandgap engineering structure having a nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally interposed between the channel material and the storage material.

[0030] Fig.10 , 10A, 11, 11A, 12 and 13 show an embodiment in which charge blocking material 30, storage material 32 and charge passing material 34 have been formed in each channel opening 25 along the insulating layer 20 and the conductive layer 22 in height. Transistor materials 30, 32 and 34 (e.g., memory cell materials) can be formed by, for example, depositing corresponding thin layers above the stack 18 and in each channel opening 25, and then flattening its backside to at least the top surface of the stack 18. Channel material 36 is also formed in the channel opening 25 along the insulating layer 20 and the conductive layer 22 in height, thereby including each effective channel material string 53. Due to the proportion, in Fig.10 , 11 , 12 and 13, materials 30, 32, 34 and 36 are collectively shown and designated only as material 37. Exemplary channel material 36 includes appropriately doped crystalline semiconductor materials, such as one or more silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP and GaN). Exemplary thicknesses of each of materials 30, 32, 34 and 36 are 25 to 100 angstroms. As shown, a perforation etch may be performed to remove materials 30, 32 and 34 from the bottom of channel opening 25, thereby exposing conductor layer 16 so that channel material 36 is directly against conductive material 17 of conductor layer 16. Such perforation etching may occur individually with respect to each of materials 30, 32 and 34 (as shown), or may occur collectively with respect to all materials after deposition of material 34 (not shown). Alternatively and by way of example only, the through-hole etching may not be performed and the channel material 36 may be electrically coupled directly to the conductive material 17 of the conductor layer 16 by a separate conductive interconnect (not shown). The channel opening 25 is shown as including a radially centered solid dielectric material 38 (e.g., spin dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, the radially centered portion within the channel opening 25 may contain void space (not shown) and / or be free of solid material (not shown). A conductive plug (not shown) may be formed on top of the channel material string 53 to better make a conductive connection with the overlying circuitry (not shown).

[0031] refer to Fig.14 and 15, and in one embodiment, a staircase structure 64 (e.g., having steps 63) has been formed in the stack 18 in the staircase region 60, and a terrace (e.g., 66X and / or 66Z, where 66X is the terrace top and 66Z is the terrace bottom) has been formed in the terrace region 62 of the staircase region 60. Alternatively, no terrace 66X may be immediately adjacent to the memory cell string region 23 (not shown), such as immediately adjacent to the uppermost step 63 (not shown). The staircase structure 64 in the exemplary "gate last" approach is circuit ineffective, but will include an effective staircase structure in the completed circuit construction system. An "effective staircase structure" is an effective circuit in which at least some of its conductive steps are electrically coupled to or between a) electronic components (such as transistors and / or memory cells) in the effective memory cell string region 23 and b) electronic components outside the effective memory cell string region 23. Such an effective staircase structure may be formed by any existing or later developed method. As one such example, a mask material (e.g., a photoimageable material such as a photoresist) may be formed atop the stack 18 and an opening formed therethrough. The mask material may then be used as a mask while etching (e.g., anisotropically) through the opening to extend the opening into the two outermost layers 20, 22. The resulting structure may then be subjected to a series of sequentially alternating lateral trim etches of the mask material, followed by a deeper etch into the two layers 20, 22 of the stack 18 using the trim mask material with the sequentially widening opening as a mask. Such an example may result in the formation of a stepped structure 64 as a stack 18 including vertically alternating layers 20, 22 of different constituent materials 24, 26, and the formation of another stepped structure (not shown) that is opposite and facing (e.g., a mirror image) the stepped structure 64. Such an opposite stepped structure (not shown) may be a dummy stepped structure. A "dummy step structure" is circuit inactive, has no current flowing in the conductive material of the step, and is a circuit dead end, and is not part of the current path of the circuit even if it extends to or from the electronic component. Multiple valid step structures (not shown) and multiple dummy step structures (not shown) can be formed, for example, longitudinally end to end in different parts of the step area 60 and to different depths within the stack 18 (not shown). Pairs of opposing mirrored valid and dummy step structures can be considered to define a certain field (e.g., a vertical recess with opposing step segments, not shown).

[0032] refer to Figure 16-21, an effective TAV 45 has been formed in one or more of regions 21, 21A and 21B. One or more circuit-effective conductive vias 39 may also be formed to each step 63. Before forming the effective TAV 45 and the via 39, an insulating material 51 (e.g., silicon dioxide) may be formed on top of the stepped structure 64. Exemplary effective TAVs 45 and vias 39 are shown as including a conductive material core 59 surrounded by an insulating material 61 (e.g., silicon dioxide and / or silicon nitride). The platform 62 in which at least some effective TAVs 45 are received can be the top (e.g., top 66X) of the effective stepped structure 64 to be activated. Additionally or alternatively, the platform in which at least some effective TAVs can be received can be the platform bottom (e.g., platform bottom 66Z, not shown) of the effective stepped structure 64 to be activated.

[0033] In one embodiment, a wall extending in height is formed in the memory plane region laterally between the laterally adjacent memory block regions and completely surrounds the island laterally between the laterally adjacent memory block regions in the memory plane region. In one embodiment, a pair of walls extending in height are formed that are laterally spaced apart from each other and are respectively horizontally longitudinally elongated, wherein the pair of walls are in the region of an edge that is planar relative to the memory plane region.

[0034] In one embodiment, a wall extending in height is formed in the memory plane region laterally between laterally adjacent memory block regions and completely surrounds the island laterally between laterally adjacent memory block regions in the memory plane region.

[0035] In one embodiment, a horizontally elongated trench is formed in the stack to form a laterally spaced memory block region to extend from the memory array region to the step region, wherein the memory block region in the step region includes a laterally spaced step structure region. A pair of height-extending walls are formed in the laterally spaced step structure region, which are laterally spaced inwardly from the side of the corresponding step structure region, are laterally spaced relative to each other, and are respectively horizontally elongated longitudinally. The step structure region is formed to include at least one of (a), (b), and (c), wherein:

[0036] (a): Each stepped structure region has no effective TAV in the lateral direction between the pair of walls;

[0037] (b): at least one of said walls is neither parallel to a horizontal longitudinal orientation of its respective stepped structure region nor angled orthogonally relative to said horizontal longitudinal orientation; and

[0038] (c): Each stepped structure region is free of any interconnecting walls extending laterally between the pair of walls.

[0039] In one embodiment, the stepped structure region is formed to include only one of (a), (b) and (c). In one embodiment, it includes two of (a), (b) and (c) [in one such embodiment, it includes only two of (a), (b) and (c)]; in one embodiment, it includes all three of (a), (b) and (c) [as shown and described below].

[0040] For example, any such wall extending in height can form its longitudinal and lateral extent in the groove extending in height, to define the shape, size and orientation of such wall. Alternatively, any such wall extending in height can be formed by other existing or future development methods.

[0041] As an example, and with reference to Figure 22-27 , a pair of wall openings 41 (e.g., grooves) extending in height and spaced laterally from each other and extending longitudinally horizontally have been formed. In one embodiment, the pair of wall openings 41 are arranged relative to the storage plane area 105 (e.g., Fig.24 , 25 ) is in the region 21A at the edge of the plane. In one embodiment, a pair of wall openings 41 are in the memory plane region 105 laterally interposed between laterally adjacent memory block regions 58 (e.g., Fig. 22 , 23 and in region 21). In one embodiment, a pair of wall openings 41 are spaced laterally apart in a stepped structure region 64 (e.g., Fig.26 , 27 ) wherein the wall openings are laterally spaced inwardly from the sides of the corresponding stepped structure areas, are laterally spaced from each other, and are each horizontally elongated longitudinally.

[0042] In one embodiment and as shown, more wall openings 42 extending in height (e.g., may include another pair of wall openings) have been formed, which are connected to a pair of wall openings 41, wherein the wall openings 41 and 42 together completely surround the island 19, which contains the space between the laterally spaced wall openings 41. Such wall openings may be in any one, two, or all three of the corresponding regions 21, 21A, and 60, wherein all three are shown. Regardless, in one embodiment, the island 19 is longitudinally elongated along a pair of wall openings 41. In one embodiment, at least one of the wall openings 41 in region 21A is horizontally parallel to the straight edge of region 21A. In one embodiment, the wall openings 41 are horizontally parallel relative to each other, and in one embodiment, the wall openings 42 are horizontally parallel relative to each other. In one embodiment in which the wall openings 42 are also formed, the wall openings 41 and 42 are formed simultaneously. For example, the wall openings 41 and / or 42 may be formed simultaneously with the formation of the channel openings 25, and similarly as disclosed in U.S. Pat. No. 10,014,309.

[0043] refer to Figure 28-33 , in one embodiment, material 35 has been formed in wall openings 41 and 42, thereby forming walls 43 and 44 in wall openings 41 and 42, respectively. Of course, walls 43 and / or 44 may have any of the properties described above with respect to wall openings 41 and 42, respectively, and / or shown in the accompanying drawings, regardless of whether wall openings are used to form walls 43 and / or 44. Walls 43 and 44 may be considered to have first sides 46 and second sides 47, respectively. In one embodiment, walls 43 and 44 may be collectively considered to be walls 43 / 44 extending at a height in memory plane region 105 that is laterally interposed between laterally adjacent memory block regions 58 (e.g., Fig.28 , 29 ), and which completely surrounds island 19, which is laterally interposed between laterally adjacent memory block regions 58 in memory plane region 105. In one embodiment, walls 43 / 44 completely surround island 19, which contains the space between laterally spaced walls 43 and is the edge of a planar surface (e.g., Fig.30 , 31 In one embodiment, walls 43 / 44 completely surround island 19, which includes spaces between walls 43 that are laterally spaced apart in step region 60 (e.g., Fig.32 , 33). Exemplary material 35 includes insulating materials such as silicon dioxide and silicon nitride, and channel materials and / or charge storage materials as disclosed in U.S. Pat. No. 10,014,309, and is independent of when formed. At least some conductive material may be used as material 35, as long as doing so does not provide a conductive short connection between any vertically spaced conductive layers 22 in the completed circuit system configuration (assuming walls 43 and / or 44 remain in the completed circuit system configuration).

[0044] Reference Figure 34-40 , horizontally elongated trenches 40 have been formed (e.g., by anisotropic etching) in stack 18 to form laterally spaced memory block regions 58 that are part of respective memory plane regions 105 and extend from memory array region 12 into step region 60 and form step structures 64 therein. Horizontally elongated trenches 40 may have respective bottoms that are directly against conductive material 17 of conductor layer 16 (e.g., on top or inside) (as shown), or may have respective bottoms that are above conductive material 17 of conductor layer 16 (not shown). The width of trench 40 may be the same as the width of walls 43 and / or 44 (not shown), or may be different from the width of walls 43 and / or 44 (as shown, where exemplary trench 40 is wider than walls 43 and 44). The above process shows that trench openings 25 are formed and filled before trench 40 is formed. This situation may be reversed. Alternatively, trench 40 may be formed between forming and filling trench openings 25 (a non-ideal situation).

[0045] refer to Figure 41-50 , and in one embodiment, material 26 (not shown) of conductive layer 22 laterally and / or radially outward of walls 43, walls 44, and / or combined walls 43 / 44 is removed, for example by isotropically etching away through trench 40 (e.g., using liquid or vapor H3PO4 as the primary etchant, where material 26 is silicon nitride, and the other materials include one or more oxides or polysilicon) ideally selectively relative to other exposed materials. During such an exemplary isotropic etch, walls 43, walls 44, and / or combined walls 43 / 44 restrict lateral ingress of etching fluid to prevent flow from first side 46 to second side 47 of walls 43, walls 44, and / or combined walls 43 / 44. Ideally, the exemplary isotropic etch is selective relative to at least some of the material of the walls, although this is not required. For example, and by way of example only, the wall may be made of a material that is etched by the etchant, although it is thick enough laterally to prevent the etchant from reaching the second side 47 from the first side 46, wherein the wall itself is thereby etched laterally, although not necessarily completely through. Thus, in any case, the wall may be etched by the etchant at least to some extent.

[0046] In an exemplary embodiment, material 26 in conductive layer 22 is sacrificial and has been replaced by conductive material 48 and has thereafter been removed from trenches 40, thereby forming individual conductive lines 29 (e.g., word lines) and elevated strings 49 of individual transistors and / or memory cells 56. Material 57 (a dielectric and / or silicon-containing material, such as undoped polysilicon) is then formed in each trench 40. Conductive interconnects (not shown) operably electrically couple each active TAV 45, each via 39, and each active channel material string 53 to other circuitry (not shown) that is not particularly important to the invention disclosed herein. A thin insulating liner (e.g., Al2O3, not shown) may be formed prior to forming conductive material 48. The approximate location of transistors and / or memory cells 56 is at Fig.50 In brackets, some Figure 42-44 4. In the example shown, the transistor and / or memory cell 56 is substantially annular or ring-shaped. Alternatively, the transistor and / or memory cell 56 may not be completely encircled relative to the respective channel openings 25, so that each channel opening 25 may have two or more strings 49 extending in height (e.g., multiple transistors and / or memory cells surrounding respective channel openings in respective conductive layers, each of which may have multiple word lines, not shown). The conductive material 48 may be considered to have a terminal 50 (corresponding to the control gate region 52 of each transistor and / or memory cell 56). Fig.50 ). In the illustrated embodiment, control gate region 52 includes various portions of various conductive lines 29. Materials 30, 32, and 34 may be viewed as a memory structure 65 laterally interposed between control gate region 52 and channel material 36. In one embodiment and as shown with respect to an exemplary "gate last" process, conductive material 48 of conductive layer 22 is formed after trench 40 is formed. Alternatively, for example with respect to a "gate first" process, conductive material of conductive layer 22 may be formed prior to trench 40 formation and / or prior to forming walls 43, 44, and / or 43 / 44 (not shown).

[0047] The charge blocking region (e.g., charge blocking material 30) is located between the storage material 32 and each control gate region 52. The charge block can have the following functions in the memory cell: in the programming mode, the charge block can prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge trapping material, etc.) in the direction of the control gate, and in the erase mode, the charge block can prevent charge carriers from flowing into the storage material from the control gate. Therefore, the charge block can play a role in preventing charge from migrating between the control gate region and the storage material of each memory cell. The exemplary charge blocking region shown includes an insulator material 30. By way of other examples, the charge blocking region can include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32), where such storage material is insulating (e.g., in the absence of any different composition material between the insulating storage material 32 and the conductive material 48). In any case, as an additional example, in the absence of any separate composition insulator material 30, the interface of the storage material and the conductive material of the control gate is sufficient to act as a charge blocking region. Further, the interface of conductive material 48 and material 30 (if present) in combination with insulator material 30 may function together as a charge blocking region and alternatively or additionally may function as a lateral outer region of insulating storage material, such as silicon nitride material 32. Exemplary material 30 is one or more of hafnium oxide of silicon and silicon dioxide.

[0048] With respect to the above-described embodiments, any other properties or aspects shown and / or described herein with respect to other embodiments may be used.

[0049] The above exemplary embodiments show the material between the walls 43, which in the completed construction includes a stack 18 of materials 24 and 26. Alternatively, the material between the walls 43 can be some other material, including some conductive material, because the walls 43 and / or 44 prevent the vertically spaced conductive layers 22 laterally located outside the walls 43 and / or 44 from being shorted by such conductive material. In any case, the stack 18 of materials 24, 26 can be removed and replaced with such other materials. A non-limiting reason for doing so is to better match the inherent material stress within the memory cell string region 23 compared to other regions located outside thereof. For example, the memory cell string region 23 may contain significantly more conductive material 48 than the region located outside the memory cell string region 23. This can create a stress imbalance, which may cause cracking at the interface between the memory cell string region 23 and the region outside thereof. For example, the memory cell string region 23 may thus have a lower or lower inherent tensile stress than the region outside thereof. Thus, one may desire less intrinsic tensile stress / higher intrinsic compressive stress to occur in regions outside of memory cell string region 23 than would occur by using a combination of material 24 and material 26. Thus, for example, relative to construction 10a, materials 24 and 26 may be removed and replaced with alternative materials, such as Figures 51-56 . Similar numerals to the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "a" or different numerals. Construction 10a shows material 70 constituting one or more islands 19 (all islands 19 are shown), as opposed to the combination of materials 24 and 26 (not shown) in the above-described and illustrated embodiments. Any other attributes or aspects shown and / or described herein for other embodiments may be used.

[0050] Embodiments of the present invention encompass memory arrays that are independent of the manufacturing method. However, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the above method embodiments may be combined and form any of the properties described with respect to the device embodiments.

[0051] Embodiments of the present invention include a memory array (or memory array region, such as 12) that includes strings of memory cells, such as 49. Such embodiments include laterally spaced memory blocks, such as 58, that each include a vertical stack, such as 18, that includes alternating insulating layers, such as 20, and conductive layers, such as 22. The active channel material strings, such as 53, of the memory cells, such as 56, extend through the insulating and conductive layers.

[0052] In one embodiment, the walls (eg, 43 / 44) extending in height are located at memory planes (eg, 105, 106) laterally between laterally adjacent memory blocks (eg, 58). Fig.41 , 44 , 45), and it completely surrounds an island (e.g., 19) that is laterally interposed between laterally adjacent memory blocks in the memory plane. Any other attributes or aspects shown and / or described herein for other embodiments may be used.

[0053] However, in another such embodiment, a pair of height-extending walls (e.g., 43) are laterally spaced relative to each other and are each horizontally longitudinally elongated (e.g., in directions 55, Fig.41 , 46 , 47) and are planar edges. In one such embodiment, walls (e.g., 44) extending at the height of more planar edges are included and connected to a pair of walls (e.g., 43). A pair of walls (e.g., 43) and more walls (e.g., 44) together completely surround an island (e.g., 19) that is included in the space between the laterally spaced walls (e.g., 43) of a pair of walls (e.g., 43) and are planar edges. Any other attributes or aspects shown and / or described herein for other embodiments may be used.

[0054] Regarding structure 10b Fig.57 Another such embodiment is shown in FIG. Similar numerals to the above-described embodiments have been used where appropriate, with some construction differences being indicated by a suffix "b" or a different numeral. Fig.57 Corresponding to the above described and shown embodiments Fig.44 Configuration 10b includes a pair of vertically extending walls (e.g., 43b) that are laterally interposed between laterally adjacent memory blocks in a memory plane (e.g., 105). The walls are laterally spaced relative to each other and are each horizontally longitudinally elongated (e.g., in direction 55). At least one of the walls (shown as two walls) is not horizontally parallel to the horizontally adjacent memory blocks between which at least one of the walls is laterally interposed (e.g., 55). Figure 44-49 In any one or more of the embodiments shown and described (not shown), this may occur relative to wall 43. Any other attributes or aspects shown and / or described herein for other embodiments may be used.

[0055] In one embodiment, the insulating layers and conductive layers of the laterally spaced memory blocks extend from the memory array region to a step region (e.g., 60) adjacent to the memory array region. The insulating layers and conductive layers of the memory blocks in the step region include an effective step structure (e.g., 64) that is laterally spaced relative to each other and each horizontally elongated longitudinally (e.g., along direction 55).

[0056] In one such embodiment, each stepped structure has no effective TAV in the lateral direction between a pair of walls (e.g., Fig.48 , 55 ). In one embodiment, each stepped structure includes a platform region (e.g., 66X) and a step region adjacent to the platform region that includes a step (e.g., 63). In one such embodiment, at least a portion of the wall is in the platform region, in one such embodiment, at least a portion of the wall is in the step region, and in one such embodiment and as shown in each of the platform region and the step region. In one embodiment, more walls extending in height (e.g., 44) are provided that are connected to a pair of walls (e.g., 43), wherein the pair of walls and the more walls together completely surround an island (e.g., 19), the island being contained in the space between the laterally spaced walls of the pair of walls, and in one such embodiment, the island is elongated in the longitudinal direction along the pair of walls. In one embodiment, the walls are horizontally parallel relative to each other (e.g., Fig.48 , 55 In one embodiment, at least one of the walls (e.g., wall 43) is oriented horizontally and longitudinally (e.g., along direction 55) parallel to the horizontal plane of the step structure in which it is located. In one embodiment, at least one of the walls (e.g., wall 43c) is not oriented horizontally and longitudinally (e.g., along direction 56) parallel to the horizontal plane of the step structure in which it is located. Fig.58 43c in). In one embodiment, at least one of the walls is vertical or within 10° of vertical, and in one embodiment, at least one of the walls is horizontally straight. Any other attributes or aspects shown and / or described herein for other embodiments may be used.

[0057] About construction 10c Fig.58 Another such embodiment is shown in . Similar numbers to the above-described embodiments have been used where appropriate, with some structural differences being indicated by the suffix "c" or different numbers. Construction 10c includes individual step structures (e.g., 64), each of which includes a pair of walls (e.g., 43c) extending in height, which are laterally spaced inward from the sides of the corresponding step structures, laterally spaced relative to each other, and are horizontally longitudinally elongated (e.g., along direction 55). At least one of the walls (e.g., wall 43c) is neither horizontally parallel to the horizontal longitudinal orientation (e.g., 55) of its respective step structure, nor is it angled orthogonally relative to the horizontal longitudinal orientation. In one embodiment, at least one of the walls 44c (shown as two) is not angled orthogonally relative to the horizontal longitudinal orientation. Any other attribute or aspect shown and / or described herein for other embodiments may be used.

[0058] About construction 10d Fig.59Another such embodiment is shown in FIG. Similar numerals to the above embodiments have been used where appropriate, with some construction differences indicated by the suffix "d" or different numerals. Construction 10d includes individual stepped structures (e.g., 64) without any interconnecting walls (e.g., Fig.59 Any walls 44, 44c from other embodiments are not shown in the drawings, and the interconnecting walls extend laterally between a pair of walls (eg, 43). Any other attributes or aspects shown and / or described herein for other embodiments may be used.

[0059] The above processing or construction may be considered to be relative to an array of components, the array of components being formed as a single stack or single layer of such components or formed in a single stack or single layer of such components above or as part of an underlying base substrate (although a single stack / layer may have multiple layers). Control circuitry and / or other peripheral circuitry for operating or accessing such components in the array may also be formed anywhere as part of the completed construction, and in some embodiments, may be below the array (e.g., under-array CMOS). In any case, one or more additional such stacks / layers may be provided or fabricated above and / or below the stacks / layers shown in the drawings or described above. Further, the arrays of components may be the same or different relative to each other in different stacks / layers, and different stacks / layers may have the same thickness or different thickness relative to each other. Intermediate structures (e.g., additional circuitry and / or dielectric layers) may be provided between vertically adjacent stacks / layers. In addition, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., one on top of another), or two or more stacks / layers may be fabricated substantially simultaneously.

[0060] The components and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of the following wide-ranging systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0061] In this document, unless otherwise specified, "height", "higher", "upper", "lower", "top", "on top", "bottom", "above", "below", "below", "below", "up", and "down" are generally with reference to a vertical direction. "Horizontal" refers to a general direction along the surface of the main substrate (i.e., within 10 degrees), and can be relative to the direction in which the substrate is processed during manufacturing, while vertical is a direction generally orthogonal thereto. Reference to "completely horizontal" refers to a direction along the surface of the main substrate (i.e., no angle with the main substrate surface), and can be relative to the direction in which the substrate is processed during manufacturing. Further, "vertical" and "horizontal" as used herein are generally with respect to directions perpendicular to each other and have nothing to do with the orientation of the substrate in three-dimensional space. In addition, "extending in height" and "extending in height" refer to directions that are at least 45° angles to the completely horizontal direction. Further, "extending in height", "extending in height", "extending in level", "extending horizontally", etc. with respect to a field effect transistor are with reference to the orientation of the channel length of the transistor along which current flows between the source / drain regions in operation. For bipolar junction transistors, "extending in height," "extending in height," "extending in level," "extending horizontally," etc., are referenced to the orientation of the base length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region extending in height extends vertically or within 10° of vertical.

[0062] Further, "directly above", "directly below" and "directly below" require that the two areas / materials / components have at least some lateral overlap (i.e., horizontally) relative to each other. Likewise, "above" without "directly" requires only that some portion of the areas / materials / components that are above the other is inward in height relative to the other (i.e., regardless of whether there is any lateral overlap between the two areas / materials / components). Similarly, "below" and "below" without "directly" require only that some portion of the areas / materials / components that are below / below the other is inward in height relative to the other (i.e., regardless of whether there is any lateral overlap between the two areas / materials / components).

[0063] Any material, region, and structure described herein may be homogeneous or inhomogeneous, and in any case may be continuous or discontinuous on any material overlying it. Where one or more exemplary compositions are provided for any material, the material may include, consist essentially of, or consist of such one or more compositions. Further, unless otherwise indicated, any existing or future developed technology may be used to form each material, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation as examples.

[0064] In addition, "thickness" itself (without a preceding directional adjective) is defined as the average straight-line distance through a given material or region perpendicular to the closest surface of an adjacent material or adjacent region having a different composition. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If the thickness is variable, then unless otherwise specified, the thickness refers to the average thickness, and since the thickness is variable, such a material or region will have some minimum thickness and some maximum thickness. As used herein, "different components" only require that those parts of the two materials or regions that may be directly against each other are chemically and / or physically different, for example, in the case where such materials or regions are not homogeneous. If the two materials or regions are not directly against each other, "different components" only require that those parts of the two materials or regions that are closest to each other are chemically and / or physically different, in the case where such materials or regions are not homogeneous. In this document, materials, regions or structures "directly against" each other when the materials, regions or structures are in at least some degree of physical contact relative to each other. In contrast, situations in which the word “directly” is not preceded by “over,” “on,” “adjacent,” “along,” and “against” include “directly against” as well as configurations in which intervening materials, regions, structures result in no physical contact between the materials, regions, or structures.

[0065] As used herein, regions-materials-components are "electrically coupled" relative to one another if, in normal operation, electrical current can flow continuously from one to the other, primarily through the movement of sufficiently generated subatomic positive and / or negative charges. Another electronic component may be between and electrically coupled to the region-material-components. In contrast, when the region-material-components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0066] Any use of "rows" and "columns" in this document is for convenience in distinguishing one series of features or feature orientations from another series of features or feature orientations, and multiple components have been or may be formed along rows and columns. "Rows" and "columns" are used synonymously for any series of regions, components and / or features that are not related to function. In any case, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, as can columns. Further, rows and columns can intersect each other at 90° or at one or more other angles.

[0067] The components of any conductive / conductor / conductive material herein may be metallic materials and / or conductively doped semiconductive / semiconductive / semiconductive materials. "Metallic material" is any one or more of an elemental metal, any mixture or alloy of two or more elemental metals, and any conductive metal compound.

[0068] As used herein, any use of "selective" with respect to etching, etching, removing, removing, depositing, forming, and / or forming, is an action on one of the described materials relative to the action on the other described material at a ratio of at least 2: 1 by volume. Further, any use of selective deposition, selective growth, or selective formation deposits, grows, or forms one material relative to the other material at a ratio of at least 2: 1 by volume, at least in the first 75 angstroms of the deposition, growth, or formation.

[0069] Unless stated otherwise, the use of "or" herein includes either or both.

[0070] in conclusion

[0071] In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, and the vertical stack includes alternating insulating layers and conductive layers. The effective channel material string of the memory cell extends through the insulating layer and the conductive layer in the memory array region. The insulating layer and the conductive layer of the laterally spaced memory block extend from the memory array region to a step region adjacent to the memory array region. The insulating layer and the conductive layer of the memory block in the step region include an effective step structure, which is laterally spaced relative to each other and is horizontally longitudinally extended respectively. Each step structure includes a pair of walls extending in height, which are laterally spaced inward from the side of the corresponding step structure, are laterally spaced relative to each other, and are horizontally longitudinally extended respectively. Each step structure has no effective TAV laterally between a pair of walls.

[0072] In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The effective channel material string of the memory cell extends through the insulating layer and the conductive layer in the memory array region. The insulating layer and the conductive layer of the laterally spaced memory block extend from the memory array region to a step region adjacent to the memory array region. The insulating layer and the conductive layer of the memory block in the step region include an effective step structure, which is laterally spaced relative to each other and is horizontally longitudinally elongated. Each step structure includes a pair of walls extending in height, which are laterally spaced inward from the side of the corresponding step structure, are laterally spaced relative to each other, and are horizontally longitudinally elongated. At least one of the walls is neither horizontally longitudinally oriented parallel to the horizontal of its respective step structure, nor is it orthogonally angled relative to the horizontal longitudinal orientation.

[0073] In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, wherein the vertical stack includes alternating insulating layers and conductive layers. The effective channel material string of the memory cell extends through the insulating layer and the conductive layer in the memory array region. The insulating layer and the conductive layer of the laterally spaced memory block extend from the memory array region to a step region adjacent to the memory array region. The insulating layer and the conductive layer of the memory block in the step region include an effective step structure, which is laterally spaced relative to each other and is horizontally longitudinally extended. Each step structure includes a pair of walls extending in height, which are laterally spaced inward from the side of the corresponding step structure, are laterally spaced relative to each other, and are horizontally longitudinally extended. Each step structure does not have any interconnecting walls extending laterally between the pair of walls.

[0074] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack including alternating insulating layers and conductive layers. The active channel material strings of the memory cells extend through the insulating layers and the conductive layers. The active channel material strings in the laterally spaced memory blocks include a portion of the memory plane. The walls extending in height are in the memory plane laterally between the laterally adjacent memory blocks, and they completely surround the island, which is laterally between the laterally adjacent memory blocks in the memory plane.

[0075] In some embodiments, a memory array including strings of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The active channel material strings of the memory cells extend through the insulating layers and the conductive layers. The active channel material strings in the laterally spaced memory blocks include a portion of the memory plane. A pair of height-extending walls are laterally spaced relative to each other in the memory plane laterally between laterally adjacent memory blocks, and are respectively horizontally longitudinally elongated. At least one of the walls is not horizontally longitudinally oriented parallel to the horizontal of the laterally adjacent memory blocks between which at least one of the walls is laterally interposed.

[0076] In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack, the vertical stack including alternating insulating layers and conductive layers. The active channel material string of the memory cell extends through the insulating layer and the conductive layer. The active channel material string in the laterally spaced memory block includes a portion of the memory plane. A pair of walls extending in height are laterally spaced relative to each other and are respectively horizontally elongated longitudinally, the pair of walls being edges of the plane.

[0077] In some embodiments, a method for forming a memory array including a memory cell string includes forming a stack including a first layer and a second layer that are vertically alternating. A horizontally elongated trench is formed in the stack to form a laterally spaced memory block region. The memory block region includes a portion of a memory plane region. A wall extending in height is formed in the memory plane region laterally between laterally adjacent memory block regions and completely surrounds an island that is laterally between laterally adjacent memory block regions in the memory plane region.

[0078] In some embodiments, a method for forming a memory array including a memory cell string includes forming a stack, the stack including a first layer and a second layer that alternate vertically. A horizontally elongated groove is formed in the stack to form a laterally spaced memory block region. The memory block region includes a portion of a memory plane region. A pair of walls extending in height are formed, the walls are laterally spaced relative to each other and are respectively horizontally elongated longitudinally. The pair of walls are in a region that is a planar edge relative to the memory plane region.

[0079] In some embodiments, a method for forming a memory array including a memory cell string includes forming a stack, the stack including a first layer and a second layer that alternate vertically. The stack includes a memory array region and a step region. A horizontally elongated groove is formed in the stack to form a laterally spaced memory block region to extend from the memory array region to the step region, wherein the memory block region in the step region includes a laterally spaced step structure region. A pair of walls extending in height are formed in the laterally spaced step structure region, the walls are laterally spaced inwardly from the side of the corresponding step structure region, are laterally spaced relative to each other, and are respectively horizontally elongated longitudinally. The step structure region is formed to include at least one of (a), (b), and (c), wherein:

[0080] (a): Each stepped structure region has no effective TAV in the lateral direction between the pair of walls;

[0081] (b): at least one of said walls is neither parallel to a horizontal longitudinal orientation of its respective stepped structure region nor angled orthogonally relative to said horizontal longitudinal orientation; and

[0082] (c): Each stepped structure region is free of any interconnecting walls extending laterally between the pair of walls.

[0083] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, since the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims should be given the full scope in a literal sense and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A memory array comprising a memory cell string, comprising: laterally spaced memory blocks, the memory blocks each comprising a vertical stack including alternating insulating and conductive layers through which strings of active channel material of memory cells extend in a memory array region; the insulating layer and the conductive layer of the laterally spaced memory blocks extend from the memory array region to a step region adjacent to the memory array region, the insulating layer and the conductive layer of the memory blocks in the step region comprising an effective step structure, the effective step structure being laterally spaced relative to each other via trenches extending vertically through a plurality of layers of the insulating layer and the conductive layer, each of the effective step structure and the trenches being respectively horizontally elongated longitudinally; Each step structure includes a pair of height-extending walls spaced laterally inwardly from the sides of the respective step structure, spaced laterally relative to each other, and each horizontally longitudinally elongated; and Each of the stepped structures has an effective array of through TAVs along the trench and no effective TAVs laterally between the pair of walls. 2 . The memory array according to claim 1 , wherein each of the stepped structures includes a terrace region and a step region adjacent to the terrace region and including a step, and at least a portion of the wall is in the terrace region. 3 . The memory array according to claim 1 , wherein each of the stepped structures includes a terrace region and a step region adjacent to the terrace region and including a step, and at least a portion of the wall is in the step region. 4 . The memory array according to claim 1 , wherein each of the stepped structures includes a terrace region and a step region adjacent to the terrace region including a step, the wall being in each of the terrace region and the step region.

5. The memory array of claim 1 , comprising further height-extending walls connected to the pair of walls, the pair of walls and the further walls together completely surrounding an island, the island comprising a space between laterally spaced-apart walls of the pair of walls.

6. The memory array of claim 5 wherein the island is longitudinally elongated along the pair of walls.

7. The memory array of claim 1 wherein the walls are horizontally parallel relative to each other.

8. The memory array of claim 1, wherein at least one of the walls is horizontally longitudinally oriented parallel to a horizontal plane of the stair structure in which it is located.

9. The memory array of claim 1 wherein at least one of the walls is not oriented horizontally and longitudinally parallel to the level of the stair structure in which it is located.

10. The memory array of claim 1 wherein at least one of the walls is vertical or within 10° of vertical.

11. The memory array of claim 1 wherein at least one of the walls is horizontally rectilinear.

12. The memory array of claim 1 comprising NAND.

13. A memory array comprising a memory cell string, comprising: laterally spaced memory blocks, the memory blocks each comprising a vertical stack including alternating insulating and conductive layers through which strings of active channel material of memory cells extend in a memory array region; The insulating layer and the conductive layer of the laterally spaced memory blocks extend from the memory array region to a step region adjacent to the memory array region, the insulating layer and the conductive layer of the memory blocks in the step region comprising an effective step structure, the effective step structure being laterally spaced relative to each other via trenches extending vertically through a plurality of layers of the insulating layer and the conductive layer, each of the effective step structure and the trenches being respectively horizontally elongated longitudinally; and Each step structure includes a pair of height-extending walls that are laterally spaced inward from the sides of the corresponding step structure, laterally spaced relative to each other, and are respectively horizontally elongated longitudinally; at least one of the walls is neither parallel to the horizontal longitudinal orientation of its respective step structure nor angled orthogonally relative to the horizontal longitudinal orientation.

14. A memory array comprising a memory cell string, comprising: laterally spaced memory blocks, the memory blocks each comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers, strings of active channel material of memory cells extending through the insulating and conductive layers, the strings of active channel material in the laterally spaced memory blocks comprising a portion of a memory plane; and A material wall extending in height, the material wall extending vertically through multiple layers of alternating insulating layers and conductive layers, the material wall is located in the memory plane laterally between laterally adjacent memory blocks, and it completely surrounds an island, the island is laterally between laterally adjacent memory blocks in the memory plane.

15. A memory array comprising a memory cell string, comprising: laterally spaced memory blocks, the memory blocks each comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers, strings of active channel material of memory cells extending through the insulating and conductive layers, the strings of active channel material in the laterally spaced memory blocks comprising a portion of a memory plane; and a pair of height-extending material walls extending vertically through the plurality of layers of alternating insulating and conductive layers, the material walls being laterally spaced relative to each other in the memory plane laterally interposed between laterally adjacent memory blocks and being respectively horizontally longitudinally elongated; at least one of the walls being not in a horizontally parallel longitudinal orientation to the horizontally adjacent memory blocks between which at least one of the walls is laterally interposed.

16. A memory array comprising a memory cell string, comprising: laterally spaced memory blocks, the memory blocks each comprising a vertical stack, the vertical stack comprising alternating insulating and conductive layers, strings of active channel material of memory cells extending through the insulating and conductive layers, the strings of active channel material in the laterally spaced memory blocks comprising a portion of a memory plane; and A pair of height-extending walls of material extend vertically through the plurality of alternating insulating and conductive layers, the height-extending walls being laterally spaced relative to one another and each being longitudinally elongated horizontally, the pair of walls being planar edges.

17. The memory array of claim 16 , comprising more walls extending in height that are planar edges and connected to the pair of walls, the pair of walls and the more walls together completely surrounding an island, the island comprising the space between the laterally spaced walls of the pair of walls and having planar edges.

18. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers; forming horizontally elongated trenches in the stack to form laterally spaced memory block regions, the memory block regions comprising a portion of a memory plane region; as well as In the memory plane region laterally interposed between laterally adjacent memory block regions, a wall extending in height is formed, which completely surrounds an island which is laterally interposed between laterally adjacent memory block regions in the memory plane region.

19. The method of claim 18, comprising, after forming the walls, isotropically etching away and replacing sacrificial material in the first layer circumferentially outside of the islands with conductive material of individual conductive lines.

20. The method of claim 18, comprising forming each memory cell of the memory cell string to include a channel material of an active channel material string, a gate region as part of a conductive line in each first layer, and a memory structure laterally interposed between the gate region and the channel material of the active channel material string in each first layer, the conductive material of the first layer being formed after forming the wall.

21. The method of claim 18, comprising forming an active channel material string through the second layer and the first layer in the memory block region before forming the wall.

22. The method of claim 18, comprising forming an active channel material string through the second layer and the first layer after forming the wall.

23. The method of claim 18, comprising forming the island to be longitudinally elongated along the pair of walls.

24. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack on the conductor layer, the stack comprising vertically alternating first and second layers; forming a plurality of channel openings extending through the stack; forming a channel material within the plurality of channel openings, the channel material being in direct physical contact with the conductive material of the conductor layer; forming horizontally elongated trenches in the stack to form laterally spaced memory block regions, the memory block regions comprising a portion of a memory plane region; as well as A pair of vertically extending walls are formed that are laterally spaced relative to each other and are respectively horizontally elongated longitudinally, the pair of walls being in the region of an edge that is planar relative to the planar region of the reservoir.

25. The method of claim 24, comprising forming further height-extending walls connected to the pair of walls, the pair of walls and the further walls together completely surrounding an island, the island comprising a space between laterally spaced walls of the pair of walls.

26. The method of claim 25, wherein the pair of walls and the further walls are formed simultaneously.

27. The method of claim 25, wherein the island is longitudinally elongated along the pair of walls.

28. The method of claim 24, wherein the walls are horizontally parallel relative to each other.

29. The method of claim 24, wherein at least one of the walls is horizontally parallel to a linear edge of a region that is an edge of the plane.

30. The method of claim 24, wherein at least one of the walls is not horizontally parallel to a linear edge of a region that is an edge of the plane.

31. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack, the stack comprising vertically alternating first and second layers, the stack comprising a memory array region and a step region; forming horizontally elongated trenches in the stack to form laterally spaced apart memory block regions extending from the memory array region to the staircase region, the memory block regions in the staircase region including laterally spaced apart staircase structure regions; A pair of walls extending in height are formed in the laterally spaced apart stepped structure regions, the walls being laterally spaced inwardly from the sides of the corresponding stepped structure regions, being laterally spaced relative to each other, and being respectively horizontally longitudinally elongated, the stepped structure regions being formed to include at least one of (a), (b) and (c), wherein: (a): Each stepped structure region has no effective TAV in the lateral direction between the pair of walls; (b): at least one of said walls is neither parallel to a horizontal longitudinal orientation of its respective stepped structure region nor angled orthogonally relative to said horizontal longitudinal orientation; as well as (c): Each stepped structure region is free of any interconnecting walls extending laterally between the pair of walls.

32. The method of claim 31 , comprising (a).

33. The method of claim 31 , comprising (b).

34. The method of claim 31, comprising (c).

35. The method of claim 31, comprising only one of (a), (b) and (c).

36. The method of claim 31, comprising at least two of (a), (b), and (c).

37. The method of claim 36, comprising only two of (a), (b) and (c).

38. The method of claim 36, comprising all three of (a), (b) and (c).

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