Multi-chip package with reduced calibration time and its ZQ calibration method

Abstract

A multi-chip package with reduced calibration time and its impedance control (ZQ) calibration method are provided. The master chip of the multi-chip package performs a first ZQ calibration operation using ZQ resistors. Then, other slave chips simultaneously perform a second ZQ calibration operation on the data input / output (DQ) pads of the slave chips using the terminating resistance values ​​of the master chip's DQ pads, based on a one-to-one correspondence with the master chip's DQ pads. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby reducing ZQ calibration time.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0108936, filed on September 3, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] At least some exemplary embodiments of the present invention relate to a semiconductor device, and more specifically, to a multi-chip package in which two ZQ calibration operations are performed. For example, in a multi-chip package, the master chip among a plurality of memory chips performs a ZQ calibration operation, and then other slave chips simultaneously perform ZQ calibration operations, thereby reducing calibration time. Background Technology

[0004] Electronic devices comprise multiple semiconductor integrated circuits (or semiconductor chips) and have complex hardware configurations. To meet the demands for miniaturization and weight reduction in electronic devices, multi-chip packages, including multiple semiconductor chips housed in a single package, have been developed to reduce the number of components mounted within the device. Furthermore, reducing the swing width of each signal minimizes the transmission time of each signal between semiconductor chips. As the swing width of each signal decreases, the impact of external noise on the semiconductor chips increases, and signal reflections caused by impedance mismatch become severe at the interface. To address impedance mismatch, semiconductor chips include ZQ pins and receive ZQ calibration commands from the outside to perform ZQ calibration operations, thereby controlling impedance mismatch.

[0005] Due to the need for high-capacity memory, a multi-chip package is provided, in which multiple memory chips (or dies) operating independently via different channels are arranged within a single package. In the multi-chip package channels, each memory chip performs a ZQ calibration operation on signal lines through which commands, addresses, and data for the corresponding memory chip are transmitted. In this case, multiple ZQ calibration operations must be performed, the number of which equals the number of memory chips arranged in the multi-chip package. For example, when eight memory chips are arranged in a multi-chip package, eight ZQ calibration operations must be performed, and each of the eight memory chips must complete its ZQ calibration operation within the ZQ calibration time defined in the package specifications.

[0006] However, when multiple ZQ calibration operations must be performed (the number of times equals the number of memory chips in a multi-chip package), the time required to sequentially input ZQ calibration commands into each memory chip and wait for the ZQ calibration operations to be executed sequentially based on the calibration commands for the corresponding memory chip is too long. Summary of the Invention

[0007] At least some exemplary embodiments of the present invention provide a multi-chip package and a ZQ calibration method thereof, wherein the ZQ calibration operation is performed twice. For example, in a multi-chip package, the master chip among multiple memory chips performs one ZQ calibration operation while the other slave chips simultaneously perform one ZQ calibration operation, thereby reducing calibration time.

[0008] A multi-chip package includes: a printed circuit board; and a plurality of memory chips stacked on the printed circuit board and including a master memory chip and a plurality of slave memory chips. Each of the plurality of memory chips includes an impedance control (ZQ) pad and a plurality of data input / output (DQ) pads. The master memory chip is configured to perform a first ZQ calibration operation on the ZQ pads of the master memory chip by using a ZQ resistor connected to a ZQ terminal of the multi-chip package and to control the terminating resistance value of the DQ pads of the master memory chip based on the result of the first ZQ calibration operation. Each of the plurality of slave memory chips is configured to perform a second ZQ calibration operation on the DQ pads of the first slave memory chip to the mth slave memory chip by using the terminating resistance value of the first DQ pads to the mth slave memory chip of the master memory chip, based on a ZQ calibration option between the first DQ pads to the mth DQ pads of the master memory chip and the DQ pads of the first slave memory chip to the mth slave memory chip.

[0009] A multi-chip package includes: a printed circuit board; a buffer chip on the printed circuit board, the buffer chip including a first impedance control (ZQ) pad and a first data input / output (DQ) pad; and a plurality of memory chips stacked on the printed circuit board and spaced apart from the buffer chip, each of the plurality of memory chips including a second ZQ pad and a second DQ pad; wherein the buffer chip is configured to: perform a first ZQ calibration operation on the first ZQ pad by using a ZQ resistor connected to the first ZQ pad; and control the terminating resistance value of the first DQ pad of the buffer chip based on the result of the first ZQ calibration operation; and each of the plurality of memory chips is configured to: perform a second ZQ calibration operation on the second DQ pad of the corresponding memory chip by using the terminating resistance value of the corresponding DQ pad of the buffer chip based on a ZQ calibration option disposed between the first DQ pad of the buffer chip and the second DQ pad of the corresponding memory chip among the plurality of memory chips.

[0010] According to at least some exemplary embodiments of the present invention, an impedance control (ZQ) calibration method for a multi-chip package including multiple memory chips is provided. The ZQ calibration method includes: performing a first ZQ calibration operation on the ZQ pads using ZQ resistors connected to ZQ pads in a main memory chip among the multiple memory chips; controlling the terminating resistance values ​​of data input / output (DQ) pads of the main memory chip based on the result of the first ZQ calibration operation in the main memory chip; and performing a second ZQ calibration operation on the DQ pads of a first slave memory chip to the m-th slave memory chip using the terminating resistance values ​​of the first DQ pad to the m-th DQ pad of the main memory chip, based on ZQ calibration options disposed between the DQ pads of the main memory chip and the DQ pads of each of the slave memory chips other than the main memory chip.

[0011] According to at least some exemplary embodiments of the present invention, an impedance control (ZQ) calibration method for a multi-chip package including multiple memory chips is provided. The ZQ calibration method includes: performing a first ZQ calibration operation on ZQ pads of a buffer chip using a ZQ resistor connected to a ZQ terminal of the multi-chip package in a buffer chip of the multi-chip package; controlling the terminating resistance value of a data input / output (DQ) pad of the buffer chip based on the result of the first ZQ calibration operation in the buffer chip; and performing a second ZQ calibration operation on the DQ pad of a corresponding memory chip using the terminating resistance value of the corresponding DQ pad of the buffer chip based on a ZQ calibration option disposed between the DQ pad of the buffer chip and the DQ pad of a corresponding memory chip in each of the multiple memory chips. Attached Figure Description

[0012] The above and other features and advantages of the exemplary embodiments of the inventive concept will become more apparent from the detailed description of these embodiments with reference to the accompanying drawings. The drawings are intended to illustrate exemplary embodiments of the inventive concept and should not be construed as limiting the intended scope of the claims. Unless explicitly stated otherwise, the drawings should not be considered as being drawn to scale.

[0013] Figure 1 This is a schematic diagram illustrating at least one exemplary embodiment of a multi-chip package according to the concept of the present invention;

[0014] Figure 2 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 1 A schematic diagram of the ZQ calibration method for multi-chip packages;

[0015] Figure 3 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 2A block diagram of the memory chip;

[0016] Figure 4 This is a schematic diagram illustrating a ZQ calibration operation performed by a main chip according to at least one exemplary embodiment of the concept of the present invention;

[0017] Figure 5 This is a schematic diagram illustrating a ZQ calibration operation performed by a chip according to at least one exemplary embodiment of the concept of the present invention;

[0018] Figure 6 This is a schematic diagram illustrating a ZQ calibration operation performed by a chip according to at least one exemplary embodiment of the concept of the present invention;

[0019] Figure 7 This is a schematic diagram illustrating a ZQ calibration method for a multi-chip package according to at least one exemplary embodiment of the present invention.

[0020] Figure 8 Based on at least one exemplary embodiment of the concept of the present invention Figure 7 Operation timing diagram of ZQ calibration method for multi-chip package;

[0021] Figure 9A and Figure 9B This is a schematic diagram illustrating a ZQ calibration method for existing multi-chip packages;

[0022] Figure 10 This is a schematic diagram illustrating at least one exemplary embodiment of a multi-chip package according to the concept of the present invention;

[0023] Figure 11 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 10 A schematic diagram of the ZQ calibration method for multi-chip packages;

[0024] Figure 12 This is a schematic diagram illustrating at least one exemplary embodiment of a multi-chip package according to the concept of the present invention;

[0025] Figure 13 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 1 A schematic diagram of the ZQ calibration method for multi-chip packages; and

[0026] Figure 14 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 13 A block diagram of a memory chip.

[0027] Specific implementation method

[0028] As is common in the field of the inventive concept, embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors, etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) performing other functions. Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of the embodiments can be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the embodiments can be physically combined into more complex blocks, units, and / or modules.

[0029] Figure 1 This is a schematic diagram illustrating at least one exemplary embodiment of a multi-chip package 100 according to the concept of the present invention.

[0030] refer to Figure 1 The multi-chip package 100 may include a plurality of memory chips 141 to 148 stacked on a printed circuit board (PCB) 120. The PCB 120 may include a plurality of conductive layers and through-silicon vias (TSVs) 122, which are separated from each other by insulating layers. The conductive layers and TSVs 122 of the PCB 120 may be connected to external terminals 110 of the multi-chip package 100. For example, the external terminals 110 of the multi-chip package 100 may be implemented as package balls or package leads.

[0031] In some embodiments, the terms “connection” and “coupled” and their derivatives may be used together in a description. These terms may not be intended to be synonymous. For example, a description using the terms “connection” and / or “coupled” may indicate that two or more elements are in direct and physical or electrical contact with each other. Furthermore, the term “coupled” may indicate that two or more elements are not in direct contact with each other, but rather cooperate or collaborate with each other.

[0032] The multi-chip package 100 can be implemented as, for example, a stacked package (PoP), a ball grid array (BGA), a chip-scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in a waffle, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline (SOIC), a compact outline package (SSOP), a thin small outline package (TSOP), a system-in-package (SIP), a multi-chip package (MCP), a wafer-level fabricated package (WFP), or a wafer-level fabricated stacked package (WSP).

[0033] Multi-chip package 100 can be a memory system including high-capacity and high-speed memory chips. Memory chips 141 to 148 can all be implemented as non-volatile memory devices. In non-limiting embodiments, non-volatile memory devices may include flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), electrically erasable programmable read-only memory (EEPROM), nanofloating gate memory (NFGM), and polymer random access memory (PoRAM). In some embodiments, multi-chip package 1000 (see...) Figure 10 This may include solid-state drives (SSDs), embedded universal flash memory (UFS) cards, embedded multimedia cards (eMMCs), compact flash memory (CF), secure digital (SDs), micro secure digital (micro-SDs), mini secure digital (mini-SDs), extreme digital (xDs), or memory sticks, which include buffer chips (or memory controllers) for controlling non-volatile memory chips and volatile memory chips.

[0034] According to at least one exemplary embodiment of the present invention, memory chips 141 to 148 can all be configured to include a plurality of volatile memory devices. In non-limiting embodiments, the volatile memory devices may include dynamic random access memory (DRAM), static random access memory (SRAM), mobile DRAM, double data rate synchronous dynamic random access memory (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, and Rambus dynamic random access memory (RDRAM). In some embodiments, the multi-chip package 100 may be a DRAM multi-chip package (MCP) or high bandwidth memory (HBM).

[0035] According to at least one exemplary embodiment of the present invention, memory chips 141 to 148 may be configured with different types of memory devices, including non-volatile memory devices and volatile memory devices. Hereinafter, each of memory chips 141 to 148 will be described as an example of NAND flash memory (e.g., a NAND non-volatile memory device), but the spirit of this disclosure is not limited thereto.

[0036] Each of the memory chips 141 to 148 may be configured with NAND flash memory. The NAND flash memory may include a memory cell array comprising memory cells arranged in rows (word lines) and columns (bit lines). Each of the memory cells may store 1 bit (single bit) of data or M bits (multiple bits) of data (where M is an integer of 2 or greater). Each memory cell may be implemented as a memory cell including a charge storage layer such as a charge trapping layer or a floating gate, or a memory cell including a variable resistor.

[0037] The memory cell array can be implemented as a single-layer array structure (or, a two-dimensional (2D) array structure) or a multi-layer array structure (or, a three-dimensional (3D) array structure). A 3D memory array may include active regions disposed on a silicon substrate and circuitry associated with the operation of each memory cell, and may be configured monolithically at at least one physical level in the memory cell array, each memory cell array including circuitry disposed on or within the substrate. The monolithic configuration may indicate that layers of the array are stacked only on top of layers of the lower-level array.

[0038] In embodiments, a 3D memory cell array may include a plurality of NAND strings arranged in a vertical direction to accommodate at least one memory cell on top of another. The at least one memory cell may include a charge trapping layer. U.S. Patent Publications 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Application No. 2011 / 0233648 disclose suitable elements of a 3D memory cell array comprising multiple levels and sharing word lines and / or bit lines between the levels. References are incorporated herein by reference. Furthermore, U.S. Patent Application No. 2014-0334232 and U.S. Patent Publication No. 8,488,381 are incorporated herein by reference. According to at least some exemplary embodiments conceived in the invention, 100 or more stacked word lines may be arranged in the vertical NAND channels of the 3D memory array.

[0039] In other embodiments, the 3D memory array may have a cell-on-periphery (COP) structure. A COP structure can represent a structure in which memory cell structures are stacked on peripheral circuitry, and each of the memory cell structures may include a channel extending in a direction perpendicular to the upper surface of the silicon substrate. Suitable elements of a COP structure are disclosed in U.S. Patent Nos. 9,666,289 and 9,548,316. ​​References are incorporated herein by reference.

[0040] The multi-chip package 100 can be incorporated into, for example, an SSD. The SSD may include multiple independent interfaces referred to as channels. Multiple flash memory devices can be connected to a channel, and the number of flash memory devices connected to a channel can be defined as a path or a memory bank. The multi-chip package 100 can be used as one channel of the SSD, and each of multiple memory chips (e.g., first to eighth memory chips) 141 to 148 can be configured with a memory bank.

[0041] Each of memory chips 141 to 148 can be connected to an adjacent memory chip via corresponding bonding lines B1 to B7. For example, the first memory chip 141 can be connected to the second memory chip 142 via bonding line B1. The second memory chip 142 can be connected to the third memory chip 143 via bonding line B2. The third memory chip 143 can be connected to the fourth memory chip 144 via bonding line B3. The fourth memory chip 144 can be connected to the fifth memory chip 145 via bonding line B4. The fifth memory chip 145 can be connected to the sixth memory chip 146 via bonding line B5. The sixth memory chip 146 can be connected to the seventh memory chip 147 via bonding line B6. The seventh memory chip 147 can be connected to the eighth memory chip 148 via bonding line B7. In this embodiment, eight memory chips are described in the multi-chip package 100. However, this is only an embodiment, and the number of memory chips is not limited to this.

[0042] The first memory chip 141 through the eighth memory chip 148 may each include multiple input / output (I / O) pads. The I / O pads may include data I / O pads (hereinafter referred to as DQ pads), impedance control pads (hereinafter referred to as ZQ pads), command pads, and address pads. Figure 1For the sake of brevity in the conceptual description and accompanying drawings of this embodiment, each of the first memory chip 141 to the eighth memory chip 148 may include a DQ pad, and may include DQ pads 1412, 1422, 1432, 1442, 1452, 1462, 1472 and 1482 respectively. The DQ pads 1412, 1422, 1432, 1442, 1452, 1462, 1472 and 1482 may be configured to be adjacent to a corner of a corresponding memory chip in the first memory chip 141 to the eighth memory chip 148 and may be connected to each other via bonding lines B1 and B2. The first memory chip 141 to the eighth memory chip 148 may be stacked in a stepped configuration, thereby exposing the DQ pads 1412, 1422, 1432, 1442, 1452, 1462, 1472 and 1482 for bonding wiring.

[0043] Regarding I / O pads, the term "pad" can refer comprehensively to the electrical interconnection of an integrated circuit, and may include, for example, a pin or another electrical contact of an integrated circuit.

[0044] The first memory chip 141 may be disposed at the lowest level of the stacked memory chips 141 to 148, connected to the conductive layer of the PCB 120 and the TSV 122, and coupled to the external terminal 110 of the multi-chip package 100. Therefore, the first memory chip 141 may be referred to as the master chip, and the second memory chips 142 to the eighth memory chips 148 other than the first memory chip 141 may be referred to as slave chips.

[0045] The first memory chip 141 may include a ZQ pad 1411, which can be connected to a corresponding conductive electrode and TSV 122 of the PCB 120 via bonding wire A1, and can also be connected to a corresponding external terminal 110 of the multi-chip package 100. The external terminal 110 connected to the ZQ pad 1411 may be referred to as the ZQ terminal 110. A resistor RZQ may be connected between the ZQ terminal 110 and ground voltage VSS. The resistance value of the resistor RZQ may be, for example, approximately 240Ω.

[0046] Each of the second memory chips 142 to the eighth memory chip 148 may include a ZQ pad. For example... Figure 2 As shown, the ZQ pads of the second memory chip 142 to the eighth memory chip 148 can be connected to the source voltage VDDQ via source voltage lines. The source voltage VDDQ can be the source voltage used to drive the ZQ engine 310 and multiple I / O drivers 320 and 330 (see [reference]). Figure 3Both I / O drivers 320 and 330 can be implemented by circuits or electronic circuits. I / O drivers 320 and 330 may also be referred to in this disclosure as DQ drivers 320 and 330.

[0047] Figure 2 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 1 A schematic diagram of the ZQ calibration method for a multi-chip package 100.

[0048] refer to Figure 2 The first memory chip 141 to the eighth memory chip 148 of the multi-chip package 100 may include a plurality of DQ pads DQ0 to DQ7 and a ZQ pad. The DQ pads DQ0 to DQ7 of the first memory chip 141 to the eighth memory chip 148 can be connected to each other via bonding lines B1 to B7. For example, the DQ pads DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7 of the first memory chip 141 to the eighth memory chip 148 can be connected to each other. The ZQ pad 1411 of the first memory chip 141 can be connected to one end of a resistor RZQ, and the other end of the resistor RZQ can be connected to ground voltage VSS, for example, via a ground voltage line. The ZQ pads of the second memory chip 142 to the eighth memory chip 148 can be connected to the signal line (or source voltage line) 210, which is connected to the source voltage VDDQ.

[0049] The first memory chip 141 can control the termination resistance value of each of the DQ pads DQ0 to DQ7 of the first memory chip 141 based on the result of the ZQ calibration operation performed by the ZQ engine 310 connected to the ZQ pad 1411, with reference to... Figure 4 This is described below. The ZQ engine 310 of the first memory chip 141 can perform a ZQ calibration operation to generate pull-up / pull-down calibration codes by using resistors RZQ connected to the ZQ pads 1411. The generated pull-up / pull-down calibration codes can be provided to I / O drivers 320 and 330 connected to the DQ pads DQ0 to DQ7 of the first memory chip 141, thereby controlling the termination resistance value of each of the DQ pads DQ0 to DQ7 of the first memory chip 141. Therefore, the DQ pads DQ0 to DQ7 of the first memory chip 141, which is the main chip, can be configured to have specific termination resistance values.

[0050] Each of the second memory chips 142 to the eighth memory chip 148 can perform a ZQ calibration operation based on a ZQ calibration option, which represents a one-to-one correspondence between the corresponding memory chip's DQ pads DQ0 to DQ6 and the DQ pads DQ0 to DQ6 of the first memory chip 141, which is the main chip. Each of the second memory chips 142 to the eighth memory chip 148 can perform a ZQ calibration operation on the DQ pads coupled to the corresponding memory chip by using the terminating resistance value set for the corresponding DQ pad of the first memory chip 141, thereby controlling the terminating resistance value of the corresponding memory's DQ pads DQ0 to DQ6.

[0051] In this embodiment, the multi-chip package may include eight stacked memory chips 141 to 148, and each of the memory chips 141 to 148 may include eight DQ pads. The number of DQ pads used to perform ZQ calibration operations between the first memory chip 141 as a master chip and the second to eighth memory chips 142 as slave chips at a given time may be determined to be 7. In at least one exemplary embodiment of the present invention, the multi-chip package 100 may include an odd number of stacked memory chips, and each of the odd number of memory chips may include an odd number of DQ pads.

[0052] A ZQ calibration operation 200 can be performed between the DQ pad DQ0 of the first memory chip 141 and the DQ pad DQ0 of the second memory chip 142, thus controlling the terminating resistance values ​​of the DQ pads DQ0 to DQ6 of the second memory chip 142. For example, the ZQ calibration operation 200 of the DQ pad DQ0 of the second memory chip 142 can be performed using the terminating resistance value set for the DQ pad DQ0 of the first memory chip 141, with reference to... Figure 5 This is described in detail. The second memory chip 142 can generate pull-up / pull-down calibration codes as a result of the ZQ calibration operation 200, and can provide the generated pull-up / pull-down calibration codes to I / O drivers 320 and 330 connected to the DQ pads DQ0 to DQ6 of the second memory chip 142, thereby controlling the termination resistance values ​​(e.g., pull-up and / or pull-down termination resistance values) of the DQ pads DQ0 to DQ6 of the second memory chip 142.

[0053] A ZQ calibration operation 201 can be performed between the DQ pad DQ1 of the first memory chip 141 and the DQ pad DQ1 of the third memory chip 143, thereby controlling the termination resistance values ​​of the DQ pads DQ0 to DQ6 of the third memory chip 143. A ZQ calibration operation 202 can be performed between the DQ pad DQ2 of the first memory chip 141 and the DQ pad DQ2 of the fourth memory chip 144, thereby controlling the termination resistance values ​​of the DQ pads DQ0 to DQ6 of the fourth memory chip 144. A ZQ calibration operation 203 can be performed between the DQ pad DQ3 of the first memory chip 141 and the DQ pad DQ3 of the fifth memory chip 145, thereby controlling the termination resistance values ​​of the DQ pads DQ0 to DQ6 of the fifth memory chip 145. A ZQ calibration operation 204 can be performed between the DQ pad DQ4 of the first memory chip 141 and the DQ pad DQ4 of the sixth memory chip 146, thereby controlling the terminating resistance values ​​of the DQ pads DQ0 to DQ6 of the sixth memory chip 146. A ZQ calibration operation 205 can be performed between the DQ pad DQ5 of the first memory chip 141 and the DQ pad DQ5 of the seventh memory chip 147, thereby controlling the terminating resistance values ​​of the DQ pads DQ0 to DQ6 of the seventh memory chip 147.

[0054] A ZQ calibration operation 206 can be performed between the DQ pad DQ6 of the first memory chip 141 and the DQ pad DQ6 of the eighth memory chip 148, thus controlling the terminating resistance values ​​of the DQ pads DQ0 to DQ6 of the eighth memory chip 148. For example, the ZQ calibration operation 206 of the DQ pad DQ6 of the eighth memory chip 148 can be performed using the terminating resistance value set for the DQ pad DQ6 of the first memory chip 141, referencing... Figure 6 This is described in detail. The eighth memory chip 148 can generate pull-up / pull-down calibration codes as a result of the ZQ calibration operation 206, and can provide the generated pull-up / pull-down calibration codes to I / O drivers 320 and 330 connected to the DQ pads DQ0 to DQ6 of the eighth memory chip 148, thereby controlling the termination resistance values ​​(e.g., pull-up and / or pull-down termination resistance values) of the DQ pads DQ0 to DQ6 of the eighth memory chip 148.

[0055] In this embodiment, the multi-chip package 100 is described to have a stack of 8 memory chips 141 to 148 and 7 DQ pads DQ0 to DQ6 for the memory chips 141 to 148. When the number of stacked memory chips in the multi-chip package 100 is set to 2n (where n is an integer of 1 or greater) or greater, ZQ calibration operations can be performed on m DQ pads of the memory chips (where m is an integer equal to or less than 2n-1 (m≤2n-1)).

[0056] According to at least one example embodiment of the present invention, when n memory chips (where m is an integer of 1 or greater) including m DQ pads are stacked in a multi-chip package, the number of stacked memory chips used to perform ZQ calibration operations between the master chip and the slave chip at a certain time can be determined as n ≤ m + 1.

[0057] According to at least one example embodiment of the present invention, when n (n>m+1) memory chips including m (where m is an integer of 1 or greater) DQ pads are stacked in a multi-chip package, “i” times (i = [(n-1) / m]+1) ZQ calibration operations can be performed in the multi-chip package.

[0058] Figure 3 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 2 Block diagram of memory chips 141 to 148.

[0059] refer to Figure 3 Each of the memory chips 141 to 148 may include a ZQ engine 310 connected to the ZQ pads and multiple I / O drivers 320 and 330 connected to the DQ pads DQ0 to DQ6. For simplicity of the figures, I / O driver 320 connected to DQ pad DQ0 and I / O driver 330 connected to DQ pad DQ6 are shown. I / O drivers identical to I / O drivers 320 and 330 may be connected to DQ pads DQ1 to DQ5. Each of the I / O drivers 320 and 330 may include multiple comparators 323 and 333, multiple pull-up units 325 and 335, and multiple pull-down units 326 and 336.

[0060] ZQ engine 310 can perform ZQ calibration operations on the corresponding memory chip. ZQ calibration operations may include pull-up calibration operations and pull-down calibration operations. ZQ engine 310 may include a master / slave determiner 311, a first pull-up unit 312, a first comparator 313, a multiplexer 314, a second pull-up unit 315, a pull-down unit 316, and a second comparator 317.

[0061] The master / slave determiner 311 can be connected to the ZQ pads. The master / slave determiner 311 can be a circuit or electronic circuit configured to detect the voltage level of the ZQ pads of a corresponding memory chip and determine whether the corresponding memory chip is a master chip or a slave chip based on the detected voltage level. The master / slave determiner 311 may also be referred to in this disclosure as a master / slave circuit 311 or a master / slave electronic circuit 311. When the voltage level of the ZQ pads is the VDDQ voltage level (e.g., the source voltage level), the master / slave determiner 311 can determine the corresponding memory chip as a slave chip. When the voltage level of the ZQ pads is not the VDDQ voltage level (e.g., the source voltage level), the master / slave determiner 311 can determine the corresponding memory chip as a master chip. The master / slave determiner 311 can store ZQ calibration options, which represent each of 200 to 206 one-to-one correspondences of performing ZQ calibration operations between the DQ pads DQ0 to DQ6 of the master chip and the DQ pads DQ0 to DQ6 of the slave chip.

[0062] When the master / slave determiner 311 determines that the corresponding memory chip is the master chip, the first comparator 313 may be, or may include, circuitry or electronic circuitry configured to compare the voltage of the ZQ pad with a reference voltage VREF_ZQ. The reference voltage VREF_ZQ may have a voltage level corresponding to half (VDDQ / 2) of the VDDQ voltage level (e.g., the source voltage level).

[0063] The output of the first comparator 313 can be provided as the first input of the multiplexer 314. The outputs of each of the comparators 323 and 333 of the I / O drivers 320 and 330 can be provided as the second input of the multiplexer 314. Both comparators 323 and 333 can be implemented by circuitry or electronic circuitry. When the master / slave determiner 311 determines that the corresponding memory chip is the master chip, the multiplexer 314 can output the output of the first comparator 313, which is its first input, and when the master / slave determiner 311 determines that the corresponding memory chip is the slave chip, the multiplexer 314 can output the outputs of each of the comparators 323 and 333 of the I / O drivers 320 and 330, which are their second inputs.

[0064] The first pull-up unit 312 may be or may include circuitry or electronic circuitry configured to perform a pull-up calibration operation based on the output of the first comparator 313. The first pull-up unit 312 may generate a pull-up calibration code based on the output of the first comparator 313, and in this case, the pull-up calibration operation can be performed by changing the pull-up calibration code until the voltage of the ZQ pad equals the reference voltage VREF_ZQ. The first pull-up unit 312 may provide the pull-up calibration code for when the voltage of the ZQ pad equals the reference voltage VREF_ZQ to the second pull-up unit 315 and the pull-up units 325 and 335 of the I / O drivers 320 and 330. Both pull-up units 325 and 335 can be implemented by circuitry or electronic circuitry.

[0065] The second pull-up unit 315 may be, or may include, a circuit or electronic circuit having a configuration substantially the same as that of the first pull-up unit 312. The impedance of the second pull-up unit 315 may be controlled based on a pull-up calibration code. Therefore, the impedance of the second pull-up unit 315 may be substantially the same as that of the first pull-up unit 312.

[0066] The second comparator 317 may be or may include circuitry or electronic circuitry configured to compare the reference voltage VREF_ZQ with the voltage at the connection node between the second pull-up unit 315 and the pull-down unit 316.

[0067] Pull-down unit 316 may be or may include circuitry or electronic circuitry configured to perform a pull-down calibration operation based on the output of the second comparator 317. Pull-down unit 316 may generate a pull-down calibration code based on the output of the second comparator 317, and in this case, a pull-down calibration operation can be performed by changing the pull-down calibration code until the voltage at the connection node between the second pull-up unit 315 and the pull-down unit 316 equals the reference voltage VREF_ZQ. Pull-down unit 316 may provide the pull-down calibration code to the pull-down units 326 and 336 of I / O drivers 320 and 330 when the voltage at the connection node between the second pull-up unit 315 and the pull-down unit 316 equals the reference voltage VREF_ZQ. Both pull-down units 326 and 336 may be implemented by circuitry or electronic circuitry.

[0068] The pull-up / pull-down calibration codes generated by the ZQ engine 310 can be provided to the I / O drivers 320 and 330 connected to the DQ pads DQ0 to DQ6, thus controlling the termination resistance values ​​(e.g., pull-up and / or pull-down termination resistance values) of the DQ pads DQ0 to DQ6.

[0069] Figure 4 This is a schematic diagram illustrating a ZQ calibration operation performed by a main chip according to at least one exemplary embodiment of the concept of the present invention.

[0070] refer to Figure 2 and Figure 4 The following describes the ZQ calibration operation of the first memory chip 141, which serves as the master chip. The ZQ pad 1411 of the first memory chip 141 can be connected to a resistor RZQ. The master / slave determiner 311 can detect that the voltage level of the ZQ pad 1411 is not the VDDQ voltage level (e.g., the source voltage level), and therefore can determine the first memory chip 141 as the master chip.

[0071] The first comparator 313 can compare the voltage of the ZQ pad 1411 with the reference voltage VREF_ZQ, and the comparison result can be provided to the first pull-up unit 312 through the multiplexer 314. The first pull-up unit 312 can perform a pull-up calibration operation based on the output of the first comparator 313, and can provide the pull-up calibration code (410) when the voltage of the ZQ pad 1411 is equal to the reference voltage VREF_ZQ to the second pull-up unit 315 and the pull-up units 325 and 335 of the I / O drivers 320 and 330.

[0072] The impedance of the second pull-up unit 315 can be controlled based on the pull-up calibration code. The second comparator 317 can compare the level of the reference voltage VREF_ZQ with the level of the voltage at the connection node between the second pull-up unit 315 and the pull-down unit 316. The pull-down unit 316 can perform a pull-down calibration operation based on the output of the second comparator 317, and can provide the pull-down calibration code (420) to the pull-down units 326 and 336 of the I / O drivers 320 and 330 when the voltage at the connection node between the second pull-up unit 315 and the pull-down unit 316 is equal to the reference voltage VREF_ZQ.

[0073] The ZQ engine 310 can perform ZQ calibration operations using resistor RZQ connected to ZQ pad 1411. The ZQ engine 310 can be configured such that the pull-up calibration code generated as a result of the ZQ calibration operation is simultaneously provided to pull-up units 325 and 335 (410) of I / O drivers 320 and 330 connected to DQ pads DQ0 to DQ6. Furthermore, the ZQ engine 310 can also be configured such that pull-down calibration codes are simultaneously provided to pull-down units 326 and 336 (420) of I / O drivers 320 and 330 connected to DQ pads DQ0 to DQ6. Therefore, the DQ pads DQ0 to DQ6 of the first memory chip 141, which is the main chip, can be set to have specific termination resistor values.

[0074] Figure 5 This is a schematic diagram illustrating a ZQ calibration operation performed by a chip according to at least one exemplary embodiment of the concept of the present invention.

[0075] refer to Figure 2 and Figure 5 The ZQ calibration operation 200 performed between the DQ pad DQ0 of the first memory chip 141, which is the master chip, and the DQ pad DQ0 of the second memory chip 142, which is the slave chip, will be described, for example, the ZQ calibration operation 200 performed by the second memory chip 142.

[0076] The DQ pad DQ0 of the first memory chip 141 can be connected to the DQ pad DQ0 of the second memory chip 142 via bonding wire B1. Furthermore, the ZQ pad 1421 of the second memory chip 142 can be connected to the VDDQ voltage line. The master / slave determiner 311 can detect that the voltage level of the ZQ pad 1421 is the VDDQ voltage level (e.g., the source voltage level), and therefore can determine the second memory chip 142 as the slave chip.

[0077] When the master / slave determiner 311 determines that the second memory chip 142 is a slave chip, the output of comparator 323 of the I / O driver 320 connected to the DQ pad DQ0 of the second memory chip 142 can be provided to multiplexer 314 (502). Comparator 323 can compare the level of the reference voltage VREF_ZQ with the voltage level of the DQ pad DQ0 of the second memory chip 142. The output of comparator 323 can be provided to the second pull-up unit 315 (503) via multiplexer 314. Pull-up calibration operations can be performed in the first pull-up unit 312 and the second pull-up unit 315 based on the output of comparator 323, and the pull-up calibration code generated as a result of the pull-up calibration operation can be provided to the pull-up units 325 and 335 (510) of I / O drivers 320 and 330.

[0078] The impedance of the second pull-up unit 315 can be controlled based on the pull-up calibration code, and the second comparator 317 can compare the level of the reference voltage VREF_ZQ with the voltage level of the connection node between the second pull-up unit 315 and the pull-down unit 316. The pull-down unit 316 can perform a pull-down calibration operation based on the output of the second comparator 317, and can provide the pull-down calibration code (520) to the pull-down units 326 and 336 of the I / O drivers 320 and 330 when the voltage of the connection node between the second pull-up unit 315 and the pull-down unit 316 is equal to the reference voltage VREF_ZQ.

[0079] ZQ engine 310 can perform ZQ calibration operations on DQ pads DQ0 of the second memory chip 142 by using the terminating resistor value set for DQ pads DQ0 of the first memory chip 141. ZQ engine 310 can be configured such that pull-up calibration codes generated as a result of the ZQ calibration operation are simultaneously provided to pull-up units 325 and 335 (510) of I / O drivers 320 and 330 connected to DQ pads DQ0 to DQ6. Furthermore, ZQ engine 310 can also be configured such that pull-down calibration codes are simultaneously provided to pull-down units 326 and 336 (520) of I / O drivers 320 and 330 connected to DQ pads DQ0 to DQ6. Therefore, DQ pads DQ0 to DQ6 of the second memory chip 142, as slave chips, can be set to have specific terminating resistor values.

[0080] Figure 6 This is a schematic diagram illustrating a ZQ calibration operation performed by a chip according to at least one exemplary embodiment of the concept of the present invention.

[0081] refer to Figure 2 and Figure 6 The ZQ calibration operation 207 performed between the DQ pad DQ6 of the first memory chip 141, which is the master chip, and the DQ pad DQ6 of the eighth memory chip 148, which is the slave chip, will be described, for example, the ZQ calibration operation 207 performed by the eighth memory chip 148.

[0082] The DQ pad DQ6 of the first memory chip 141 can be connected to the DQ pad DQ6 of the eighth memory chip 148 via bonding lines B1 to B7. Furthermore, the ZQ pad 1481 of the eighth memory chip 148 can be connected to the VDDQ voltage line. The master / slave determiner 311 can detect that the voltage level of the ZQ pad 1481 is the VDDQ voltage level (e.g., the source voltage level), and therefore can determine the eighth memory chip 148 as the slave chip.

[0083] When the master / slave determiner 311 determines that the eighth memory chip 148 is a slave chip, the output of comparator 323 of the I / O driver 320 connected to the DQ pad DQ6 of the eighth memory chip 148 can be provided to multiplexer 314 (602). Comparator 323 can compare the level of the reference voltage VREF_ZQ with the voltage level of the DQ pad DQ6 of the eighth memory chip 148. The output of comparator 323 can be provided to the second pull-up unit 315 (603) via multiplexer 314. Pull-up calibration operations can be performed in the first pull-up unit 312 and the second pull-up unit 315 based on the output of comparator 323, and the pull-up calibration code generated as a result of the pull-up calibration operation can be provided to the pull-up units 325 and 335 (610) of I / O drivers 320 and 330.

[0084] The impedance of the second pull-up unit 315 can be controlled based on the pull-up calibration code, and the second comparator 317 can compare the level of the reference voltage VREF_ZQ with the voltage level of the connection node between the second pull-up unit 315 and the pull-down unit 316. The pull-down unit 316 can perform a pull-down calibration operation based on the output of the second comparator 317, and can provide the pull-down calibration code (620) to the pull-down units 326 and 336 of the I / O drivers 320 and 330 when the voltage of the connection node between the second pull-up unit 315 and the pull-down unit 316 is equal to the reference voltage VREF_ZQ.

[0085] ZQ engine 310 can perform ZQ calibration operations on DQ pads DQ6 of the eighth memory chip 148 by using the terminating resistor value set for DQ pads DQ6 of the first memory chip 141. ZQ engine 310 can be configured such that pull-up calibration codes generated as a result of the ZQ calibration operation are simultaneously provided to pull-up units 325 and 335 (610) of I / O drivers 320 and 330 connected to DQ pads DQ0 to DQ6. Furthermore, ZQ engine 310 can also be configured such that pull-down calibration codes are simultaneously provided to pull-down units 326 and 336 (620) of I / O drivers 320 and 330 connected to DQ pads DQ0 to DQ6. Therefore, DQ pads DQ0 to DQ6 of the eighth memory chip 148, as slave chips, can be set to have specific terminating resistor values.

[0086] Figure 7 This is a schematic diagram illustrating a ZQ calibration method for a multi-chip package according to at least one exemplary embodiment of the concept of the present invention.

[0087] refer to Figure 1 , Figure 2 , Figure 3 and Figure 7In operation S710, ZQ calibration options for the multi-chip package 100 can be set. The ZQ calibration options may include a one-to-one correspondence 200 to 206 between the DQ pads DQ0 to DQ6 of the master chip and the DQ pads DQ0 to DQ6 of the slave chip, performing ZQ calibration operations. The ZQ calibration options can be set in the registers of the first memory chip 141, which serves as the master chip. Alternatively, the ZQ calibration options can be set in the registers of each of the first memory chips 141 to the eighth memory chips 148. Alternatively, the ZQ calibration options can be set in the master / slave determiner 311 of each of the first memory chips 141 to the eighth memory chips 148.

[0088] For example, the ZQ calibration option can be configured to perform a ZQ calibration operation 200 between the DQ pad DQ0 of the first memory chip 141 and the DQ pad DQ0 of the second memory chip 142. Furthermore, the ZQ calibration option can be configured to perform a ZQ calibration operation 201 between the DQ pad DQ1 of the first memory chip 141 and the DQ pad DQ1 of the third memory chip 143, a ZQ calibration operation 202 between the DQ pad DQ2 of the first memory chip 141 and the DQ pad DQ2 of the fourth memory chip 144, a ZQ calibration operation 203 between the DQ pad DQ3 of the first memory chip 141 and the DQ pad DQ3 of the fifth memory chip 145, a ZQ calibration operation 204 between the DQ pad DQ4 of the first memory chip 141 and the DQ pad DQ4 of the sixth memory chip 146, a ZQ calibration operation 205 between the DQ pad DQ5 of the first memory chip 141 and the DQ pad DQ5 of the seventh memory chip 147, and a ZQ calibration operation 206 between the DQ pad DQ6 of the first memory chip 141 and the DQ pad DQ6 of the eighth memory chip 148.

[0089] In operation 720, a ZQ calibration command ZQCL can be received via terminal 110 of the multi-chip package 100. The ZQ calibration command ZQCL can be provided by a memory controller of an electronic device including the multi-chip package 100. The electronic device may include, for example, a computing system, a server, a server array or server cluster, a web server, a network server, an internet server, a workstation, a minicomputer, a mainframe computer, a network tool, or a combination thereof.

[0090] In operation S730, the multi-chip package 100 can detect the voltage level of each of the ZQ pads by using the master / slave determiner 311 of each of the first memory chips 141 to the eighth memory chips 148 in response to the ZQ calibration command ZQCL.

[0091] When the voltage level of the ZQ pad of the corresponding memory chip is the VDDQ voltage level (e.g., the source voltage level), in operation S740, the master / slave determiner 311 of each of the first memory chips 141 to the eighth memory chips 148 can determine the corresponding memory chip as a slave chip and can perform operation S760.

[0092] When the voltage level of the ZQ pad of the corresponding memory chip is not the VDDQ voltage level, in operation S740, the master / slave determiner 311 of each of the first memory chip 141 to the eighth memory chip 148 can determine the corresponding memory chip as the master chip and can execute operation S751.

[0093] When the corresponding memory chip (e.g., the first memory chip 141) is the main chip in operation S740, in operation S751, the ZQ engine 310 of the first memory chip 141 can perform a ZQ calibration operation by using a resistor RZQ connected to the ZQ pad 1411. The ZQ engine 310 of the first memory chip 141 can perform a pull-up calibration operation to generate a pull-up calibration code based on the result obtained by comparing the voltage of the ZQ pad 1411 with a reference voltage VREF_ZQ, and can perform a pull-down calibration operation to generate a pull-down calibration code based on the result obtained by comparing the level of the reference voltage VREF_ZQ with the voltage level of the connection node between the second pull-up unit 315 and the pull-down unit 316, wherein the voltage level of the connection node is controlled based on the pull-up calibration code.

[0094] In operation S752, the ZQ engine 310 of the first memory chip 141, which is the main chip, can provide the pull-up / pull-down calibration codes generated as a result of the ZQ calibration operation (S751) to the I / O drivers 320 and 330 connected to the DQ pads DQ0 to DQ6 of the first memory chip 141. Therefore, the DQ pads DQ0 to DQ6 of the first memory chip 141, which is the main chip, can be set to have specific termination resistor values.

[0095] Subsequently, in operation S753, the first memory chip 141, which is the main chip, can end the ZQ calibration operation and can wait until the ZQ calibration operation of the slave chip ends.

[0096] When the corresponding memory chip (e.g., the second memory chip 142) is a slave chip in operation S740, in operation S760, the second memory chip 142, as a slave chip, can wait until the ZQ calibration operation of the first memory chip 141, as the master chip, is completed.

[0097] When the ZQ calibration operation of the first memory chip 141, which is the master chip, ends in operation S751, in operation S761, the ZQ engine 310 of the second memory chip 142, which is the slave chip, can perform a ZQ calibration operation coupled to the DQ pad of the second memory chip 142 by using the terminating resistor value set for the DQ pad of the first memory chip 141, which is the master chip. The ZQ engine 310 of the second memory chip 142 can perform a pull-up calibration operation to generate a pull-up calibration code based on the result obtained by comparing the reference voltage VREF_ZQ with the voltage of the DQ pad DQ0 connected to the first memory chip 141, and can perform a pull-down calibration operation to generate a pull-down calibration code based on the result obtained by comparing the level of the reference voltage VREF_ZQ with the voltage level of the connection node between the second pull-up unit 315 and the pull-down unit 316, wherein the voltage level of the connection node is controlled based on the pull-up calibration code.

[0098] In operation S762, the ZQ engine 310 of the second memory chip 142, which is a slave chip, can provide the pull-up / pull-down calibration codes generated as a result of the ZQ calibration operation (S751) to the I / O drivers 320 and 330 connected to the DQ pads DQ0 to DQ6 of the second memory chip 142. Therefore, the DQ pads DQ0 to DQ6 of the second memory chip 142, which is a slave chip, can be set to have specific termination resistor values.

[0099] Operations S760, S761, and S762 described for the second memory chip 142 as a slave chip can be applied equivalently and simultaneously to the third to eighth memory chips 143 as slave chips. That is, in operation S760, each of the second to eighth memory chips 148 as slave chips can wait until the ZQ calibration operation of the first memory chip 141 as the master chip is completed. In operation S761, each of the second to eighth memory chips 148 can perform the ZQ calibration operation based on the one-to-one correspondence between the DQ pads DQ0 to DQ6 of the corresponding memory chip and the DQ pads DQ0 to DQ6 of the first memory chip 141 as the master chip, by using the terminating resistor value set for each of the DQ pads DQ0 to DQ6 of the first memory chip 141. In operation 762, each of the second memory chips 142 to the eighth memory chips 148 can perform a ZQ calibration operation coupled to the DQ pad of the corresponding memory chip by using the terminating resistance value set for the corresponding DQ pad of the first memory chip 141, so as to control the terminating resistance value of the DQ pads DQ0 to DQ6 of the corresponding memory chip.

[0100] Figure 8Based on at least one exemplary embodiment of the concept of the present invention Figure 7 The timing diagram of the operation of the ZQ calibration method for the multi-chip package 100. Figure 8 A timing diagram is shown illustrating the operation of a multi-chip package 100 performed based on a clock signal CLK according to a communication protocol or specification. It should be noted that the timing diagrams described herein are not shown at scale.

[0101] refer to Figure 8 At time T1, the multi-chip package 100 can receive the ZQ calibration command ZQCL. In response to the ZQ calibration command ZQCL, the first memory chip 141, acting as the main chip of the multi-chip package 100, can perform a ZQ calibration operation using a resistor RZQ connected to the ZQ pad 1411. Due to the ZQ calibration operation of the first memory chip 141, the DQ pads DQ0 to DQ6 of the first memory chip 141 can be set to have specific terminating resistance values.

[0102] At time T2, when the ZQ calibration operation of the first memory chip 141, which serves as the main chip, is completed, each of the second memory chips 142 to the eighth memory chip 148, which serves as the main chip, can perform a ZQ calibration operation on the DQ pads of the corresponding memory chip by using the terminating resistor values ​​set for the corresponding DQ pads of the first memory chip 141, which serves as the main chip. Due to the ZQ calibration operation of each of the second memory chips 142 to the eighth memory chip 148, the DQ pads DQ0 to DQ6 of each of the second memory chips 142 to the eighth memory chip 148 can be set with specific terminating resistor values.

[0103] During the interval between time T2 and time T3, the ZQ calibration operations of the second memory chip 142 to the eighth memory chip 148 can be completed. The interval between time T2 and time T3 can represent the time elapsed until the second ZQ calibration operations of all memory chips have been completed. The interval between time T2 and time T3 can be longer than the time elapsed until the second ZQ calibration operation of one memory chip is completed. For example, the interval between time T2 and time T3 can be shorter than twice the time elapsed until the second ZQ calibration operation of one memory chip is completed.

[0104] As described above, the first memory chip 141, corresponding to the master chip among the multiple memory chips 141 to 148, can perform one ZQ calibration operation. Then, the second to eighth memory chips 142, which are slave chips, can simultaneously perform one ZQ calibration operation, thereby completing the ZQ calibration operation of the multi-chip package 100. In other words, the ZQ calibration operation of the multi-chip package 100 can be completed by performing two ZQ calibration operations. Therefore, it can be seen that, as shown in the following reference... Figure 9A and Figure 9B Compared to existing techniques that perform eight ZQ calibration operations, the described method significantly reduces ZQ calibration time.

[0105] Figure 9A and Figure 9B This is a schematic diagram illustrating a ZQ calibration method for prior art multi-chip packages. An example of such a method will be described below, where... Figure 1 The same multi-chip package 100 includes eight memory chips 141 to 148. Figure 9A and Figure 9B The ZQ calibration method.

[0106] refer to Figure 9A and Figure 9B In operation S910, a chip selection signal CSn for selecting one memory chip from memory chips 141 to 148 can be received. For example, in operation S910, at time Ta0, the chip selection signal CSn for selecting the first memory chip 141 can be applied to the first memory chip 141. In operation S920, at time Tb0, a ZQ calibration command ZQCL corresponding to the first memory chip 141 can be received. In operation S930, a ZQ calibration operation of the first memory chip 141 can be performed in response to the ZQ calibration command ZQCL, and at time Tc0, the ZQ calibration operation of the first memory chip 141 can end.

[0107] After the ZQ calibration operation of the first memory chip 141 is completed, in operation S910, a chip selection signal CSn for selecting the second memory chip 142 can be applied to the second memory chip 142 at time Ta1. In operation S920, at time Tb1, a ZQ calibration command ZQCL corresponding to the second memory chip 141 can be received, and in operation S930, the ZQ calibration operation of the second memory chip 142 can be performed in response to the ZQ calibration command ZQCL. At time Tc1, the ZQ calibration operation of the second memory chip 142 can be completed.

[0108] In this way, ZQ calibration operations for the third memory chip 143 to the eighth memory chip 148 can be performed sequentially, and the ZQ calibration operation for the multi-chip package 100 can end when the ZQ calibration operation for the eighth memory chip 148 ends at time Tc7. That is, since ZQ calibration operations are performed for each of the first memory chip 141 to the eighth memory chip 148, the ZQ calibration operation for the multi-chip package 100 can include eight ZQ calibration operations. Existing ZQ calibration methods for multi-chip packages may have the problem that the ZQ calibration time is proportionally long to the number of memory chips stacked in the multi-chip package 100.

[0109] Figure 10 This is a schematic diagram illustrating at least one exemplary embodiment of a multi-chip package 1000 according to the concept of the present invention.

[0110] refer to Figure 10 The multi-chip package 1000 may include a buffer chip 130 and first memory chips 141 to eighth memory chips 148 mounted on a PCB 120. The buffer chip 130 can be electrically connected to an external terminal 1010 of the multi-chip package 1000 via a bonding wire C1. The buffer chip 130 may include a ZQ pad 1031 and a DQ pad 1032. The ZQ pad 1031 can be connected to a TSV 1022 and a conductive electrode on the PCB 120 via a bonding wire C1, and can be coupled to the external terminal 1010 of the multi-chip package 1000. The external terminal 1010 connected to the ZQ pad 1031 can be a ZQ terminal. A resistor RZQ can be connected between the ZQ terminal 110 and the ground voltage VSS. DQ pad 1032 can be connected via bonding wire C2 to DQ pads 1412, 1422, 1432, 1442, 1452, 1462, 1472, and 1482 of the first memory chip 141 to the eighth memory chip 148. (In the following text, the connection to...) Figure 1 The description of the multi-chip package 1000 is the same as or similar to the description of the multi-chip package 1000.

[0111] Buffer chip 130 can control first memory chips 141 through eighth memory chips 148. First memory chips 141 through eighth memory chips 148 can perform specific operations based on the control of buffer chip 130. For example, buffer chip 130 can be used as a memory controller. When controlling the ZQ calibration operation of the DQ pads 1412, 1422, 1432, 1442, 1452, 1462, 1472, and 1482 of the first memory chips 141 through eighth memory chips 148, buffer chip 130 can act as... Figure 1It operates as the first memory chip 141, which serves as the master chip. In this case, the first memory chip 141 can be a slave chip and can operate like the second memory chip 142 through the eighth memory chip 148.

[0112] Figure 11 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 10 A schematic diagram of the ZQ calibration method for the multi-chip package 1000.

[0113] refer to Figure 11 The buffer chip 130 of the multi-chip package 1000 may include the reference above. Figure 4 The components of the first memory chip 141 described are the same as those in the first memory chip 141. However, in addition to the DQ pad, the buffer chip 130 and the first memory chips 141 through the eighth memory chips 148 may also include the DQ pad DQ7.

[0114] The buffer chip 130 can store ZQ calibration options in a register, which represent each of the one-to-one correspondences between the DQ pads of the buffer chip 130 and the DQ pads of the first memory chip 141 to the eighth memory chip 148.

[0115] The buffer chip 130 can perform a ZQ calibration operation by using a resistor RZQ connected to the ZQ pad 1031, and the termination resistance values ​​of the DQ pads 1301 to 1308 of the buffer chip 130 can be controlled and set based on the results obtained by performing the ZQ calibration operation.

[0116] When the ZQ calibration operation of buffer chip 130 is completed, each of the first memory chips 141 to the eighth memory chips 148, which are slave chips, can perform a ZQ calibration operation coupled to the DQ pad of the corresponding slave memory chip by using the terminating resistor value set for the corresponding DQ pad of buffer chip 130. The ZQ pads 1411, 1421, 1431, 1441, 1451, 1461, 1471, and 1481 of the first memory chips 141 to the eighth memory chips 148 can be connected to the VDDQ voltage line.

[0117] A ZQ calibration operation 1100 can be performed between the DQ0 pad 1301 of the buffer chip 130 and the DQ0 pad 1412 of the first memory chip 141 to control the termination resistance values ​​of the DQ pads DQ0 to DQ7 of the first memory chip 141.

[0118] A ZQ calibration operation 1101 can be performed between the DQ1 pad 1302 of the buffer chip 130 and the DQ1 pad 1422 of the second memory chip 142 to control the terminating resistance values ​​of the DQ pads DQ0 to DQ7 of the second memory chip 142.

[0119] ZQ calibration operation 1102 can be performed between the DQ2 pad 1303 of the buffer chip 130 and the DQ2 pad 1432 of the third memory chip 143 to control the termination resistance values ​​of the DQ pads DQ0 to DQ7 of the third memory chip 143.

[0120] A ZQ calibration operation 1103 can be performed between the DQ3 pad 1304 of the buffer chip 130 and the DQ3 pad 1442 of the fourth memory chip 144 to control the terminating resistance values ​​of the DQ pads DQ0 to DQ7 of the fourth memory chip 144.

[0121] A ZQ calibration operation 1104 can be performed between the DQ4 pad 1305 of the buffer chip 130 and the DQ4 pad 1452 of the fifth memory chip 145 to control the terminating resistance values ​​of the DQ pads DQ0 to DQ7 of the fifth memory chip 145.

[0122] A ZQ calibration operation 1105 can be performed between the DQ5 pad 1306 of the buffer chip 130 and the DQ5 pad 1462 of the sixth memory chip 146 to control the terminating resistance values ​​of the DQ pads DQ0 to DQ7 of the sixth memory chip 146.

[0123] A ZQ calibration operation 1106 can be performed between the DQ6 pad 1307 of the buffer chip 130 and the DQ6 pad 1472 of the seventh memory chip 147 to control the terminating resistance values ​​of the DQ pads DQ0 to DQ7 of the seventh memory chip 147.

[0124] A ZQ calibration operation 1107 can be performed between the DQ7 pad 1308 of the buffer chip 130 and the DQ7 pad 1482 of the eighth memory chip 148 to control the terminating resistance values ​​of the DQ pads DQ0 to DQ7 of the eighth memory chip 148.

[0125] In this embodiment, the multi-chip package 1000 is described to have a stack of 8 memory chips 141 to 148, and the memory chips 141 to 148 have 8 DQ pads DQ0 to DQ7. When the number of DQ pads of the memory chips is set to n, n memory chips equal to the number of DQ pads can be stacked in the multi-chip package 1000, and ZQ calibration operations can be performed on all n DQ pads.

[0126] Figure 12This is a schematic diagram illustrating at least one exemplary embodiment of a multi-chip package 1200 according to the concept of the present invention.

[0127] refer to Figure 12 Multi-chip package 1200 and Figure 11 The difference between the multi-chip package 1000 and the multi-chip package 1000 lies in that multiple memory chips 141a to 148a are grouped into a first group and a second group, and connected to the buffer chip 130. In the following text, the details of the multi-chip package 1000 are omitted. Figure 1 and Figure 11 The description is the same as or similar to the description of the multi-chip package 1200.

[0128] As the number of memory chips stacked in the multi-chip package 1200 increases, the number of memory chips connected to the DQ pads 1032 of the buffer chip 130 can also increase. Therefore, the load on the DQ pads 1032 of the buffer chip 130 may increase, and instability may increase. The load on the DQ pads 1032 may not be suitable for accurate ZQ calibration operations of the memory chips connected to the DQ pads 1032 of the buffer chip 130. The load on the DQ pads 1032 of the buffer chip 130 can be controlled to a level suitable for accurate ZQ calibration operations of the memory chips.

[0129] The DQ pads 1512, 1522, 1532, and 1542 of the memory chips 141a to 144a in the first group can be connected to the DQ pad 1032 of the buffer chip 130 via the first bonding line C2. The DQ pads 1552, 1562, 1572, and 1582 of the memory chips 145a to 148a in the second group can be connected to the DQ pad 1032 of the buffer chip 130 via the second bonding line C3. In this embodiment, multiple memory chips 141a to 148a are grouped into two groups. However, this is only an embodiment, and the number of groups is not limited to this.

[0130] The buffer chip 130 can perform a ZQ calibration operation by using a resistor RZQ connected to the ZQ pad 1031, and the termination resistance value of the DQ pad 1302 of the buffer chip 130 can be controlled and set based on the result obtained by performing the ZQ calibration operation.

[0131] When the ZQ calibration operation of buffer chip 130 is completed, a first ZQ calibration operation for each of the memory chips 141a to 144a in the first group and a second ZQ calibration operation for each of the memory chips 145a to 148a in the second group can be performed simultaneously. In the first ZQ calibration operation, the ZQ calibration operation of the DQ pads coupled to each of the memory chips 141a to 144a in the first group can be performed using the terminating resistor values ​​set for the corresponding DQ pads of buffer chip 130. In the second ZQ calibration operation, the ZQ calibration operation of the DQ pads coupled to each of the memory chips 145a to 148a in the second group can be performed using the terminating resistor values ​​set for the corresponding DQ pads of buffer chip 130.

[0132] According to at least one exemplary embodiment of the present invention, the ZQ calibration operation of the buffer chip 130 can be completed, and then the first ZQ calibration operation of each of the memory chips 141a to 144a in the first group and the second ZQ calibration operation of each of the memory chips 145a to 148a in the second group can be performed in parallel. In other embodiments, the first ZQ calibration operation and the second ZQ calibration operation can be performed sequentially.

[0133] Figure 13 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 1 A schematic diagram of the ZQ calibration method for a multi-chip package 100.

[0134] refer to Figure 13 ,and Figure 2 There might be a difference where the other end of the resistor RZQ connected to the ZQ pad 1411 of the first memory chip 141 is connected to the source voltage VDDQ line, and the ZQ pads of the second memory chip 141 to the eighth memory chip 148 are connected to a signal line (or, ground line) 210 connected to the ground voltage VSS. In the following text, details related to... Figure 2 The description of the multi-chip package 100 is the same as or similar to the description of the multi-chip package 100.

[0135] The first memory chip 141, acting as the master chip, can perform a first ZQ calibration operation by using a resistor RZQ connected to the ZQ pad 1411 to control the terminating resistance values ​​of the DQ pads DQ0 to DQ6 of the first memory chip 141. A second ZQ calibration operation for the slave memory chips can be performed simultaneously based on the ZQ calibration options set between the DQ pads DQ0 to DQ6 of the first memory chip 141 and the DQ pads DQ0 to DQ7 of the second to eighth memory chips 148, which are slave memory chips.

[0136] In the second ZQ calibration operation, the second memory chip 142, acting as the first slave memory chip, can perform a ZQ calibration operation coupled to the DQ pad DQ0 of the first memory chip 141 using the terminating resistance value of the DQ pad DQ0 of the second memory chip 142, thereby controlling the terminating resistance values ​​of the DQ pads DQ0 to DQ6 of the second memory chip 142. Similarly, the third memory chip 143, acting as the second slave memory chip, can perform a ZQ calibration operation coupled to the DQ pad DQ1 of the first memory chip 141 using the terminating resistance value of the DQ pad DQ1 of the third memory chip 143, thereby controlling the terminating resistance values ​​of the DQ pads DQ0 to DQ6 of the third memory chip 143. In this way, the eighth memory chip 148, which is the seventh slave memory chip, can perform a ZQ calibration operation coupled to the DQ pad DQ6 of the eighth memory chip 148 by using the terminating resistance value of the DQ pad DQ6 of the first memory chip 141, so as to control the terminating resistance values ​​of the DQ pads DQ0 to DQ6 of the eighth memory chip 148.

[0137] Figure 14 This is for describing at least one exemplary embodiment of the concept according to the present invention. Figure 13 Block diagram of memory chips 141 to 148.

[0138] refer to Figure 14 ,and Figure 3 In contrast, each of the memory chips 141 to 148 may differ in that the ZQ engine 310 for performing pull-up and pull-down calibration operations includes a first pull-down unit 312_14, a pull-up unit 315_14, and a second pull-down unit 316_14, instead of a first pull-up unit 312, a second pull-up unit 315, and a pull-down unit 316. The first pull-down unit 312_14, the pull-up unit 315_14, and the second pull-down unit 316_14 can all be implemented using circuitry or electronic circuitry. In the following text, [the following text is omitted as it is not part of the original document]. Figure 3 The descriptions of memory chips 141 to 148 are the same as or similar to those of memory chips 141 to 148.

[0139] The master / slave determiner 311 can detect the voltage level of the ZQ pads of the corresponding memory chip to determine whether the corresponding memory chip is a master chip or a slave chip. When the voltage level of the ZQ pads is the VSS voltage level (e.g., ground voltage level), the master / slave determiner 311 can determine the corresponding memory chip as a slave chip. When the voltage level of the ZQ pads is not the VSS voltage level (e.g., ground voltage level), the master / slave determiner 311 can determine the corresponding memory chip as a master chip. The master / slave determiner 311 can store ZQ calibration options, which represent each of the one-to-one correspondences 200 to 206 between the DQ pads DQ0 to DQ6 of the master chip and the DQ pads DQ0 to DQ6 of the slave chip to perform a ZQ calibration operation.

[0140] When the master / slave determiner 311 determines that the corresponding memory chip is the master chip, the first comparator 313 can compare the voltage of the ZQ pad with the reference voltage VREF_ZQ. The reference voltage VREF_ZQ can have a voltage level corresponding to half (VDDQ / 2) of the VDDQ voltage level (e.g., the source voltage level).

[0141] The output of the first comparator 313 can be provided as the first input of the multiplexer 314. The outputs of each of the comparators 323 and 333 of the I / O drivers 320 and 330 can be provided as the second input of the multiplexer 314. When the master / slave determiner 311 determines that the corresponding memory chip is the master chip, the multiplexer 314 can output the output of the first comparator 313, which is its first input, and when the master / slave determiner 311 determines that the corresponding memory chip is the slave chip, the multiplexer 314 can output the outputs of each of the comparators 323 and 333 of the I / O drivers 320 and 330, which are its second inputs.

[0142] The first pull-down unit 312_14 can perform a pull-down calibration operation based on the output of the first comparator 313. The first pull-down unit 312_14 can generate a pull-down calibration code based on the output of the first comparator 313, and in this case, the pull-down calibration operation can be performed by changing the pull-down calibration code until the voltage of the ZQ pad is equal to the reference voltage VREF_ZQ. The first pull-down unit 312_14 can provide the pull-down calibration code when the voltage of the ZQ pad is equal to the reference voltage VREF_ZQ to the second pull-down units 316_14 and pull-down units 326 and 336 of the I / O drivers 320 and 330.

[0143] The second pull-down unit 316_14 can have a configuration substantially the same as that of the first pull-down unit 312_14. The impedance of the second pull-down unit 316_14 can be controlled based on a pull-down calibration code. Therefore, the impedance of the second pull-down unit 316_14 can be substantially the same as that of the first pull-down unit 312_14.

[0144] The second comparator 317 can compare the reference voltage VREF_ZQ with the voltage of the connection node between the second pull-down unit 316_14 and the pull-up unit 315_14.

[0145] Pull-up unit 315_14 can perform a pull-up calibration operation based on the output of the second comparator 317. Pull-up unit 315_14 can generate a pull-up calibration code based on the output of the second comparator 317, and in this case, the pull-up calibration operation can be performed by changing the pull-up calibration code until the voltage of the connection node between the second pull-down unit 316_14 and the pull-up unit 315_14 equals the reference voltage VREF_ZQ. Pull-up unit 315_14 can provide the pull-up calibration code to the pull-up units 325 and 335 of I / O drivers 320 and 330 when the voltage of the connection node between the second pull-down unit 316_14 and the pull-up unit 315_14 equals the reference voltage VREF_ZQ.

[0146] The pull-up / pull-down calibration codes generated by the ZQ engine 310 can be provided to the I / O drivers 320 and 330 connected to the DQ pads DQ0 to DQ7, thus controlling the termination resistance values ​​of the DQ pads DQ0 to DQ7.

[0147] Exemplary embodiments of the inventive concept have been described herein, and it will be apparent that they can be modified in various ways. Such changes should not be considered as departing from the intended spirit and scope of the exemplary embodiments of the inventive concept, and it will be apparent to those skilled in the art that all such modifications are intended to be included within the scope of the appended claims.

Claims

1. A multi-chip package, comprising: Printed circuit boards; as well as Multiple memory chips are stacked on the printed circuit board and include a master memory chip and multiple slave memory chips. Each memory chip includes an impedance control ZQ pad and multiple data input / output DQ pads. The multi-chip package is configured to receive a ZQ calibration command once from outside the multi-chip package. The main memory chip is configured to receive the ZQ calibration command, perform a first ZQ calibration operation on the ZQ pads of the main memory chip using a ZQ resistor connected to the ZQ terminal of the multi-chip package, and control the termination resistance value of the DQ pads of the main memory chip based on the result of the first ZQ calibration operation. Based on the ZQ calibration command received by the main memory chip, each of the plurality of slave memory chips is configured to perform a second ZQ calibration operation on the DQ pads of the first slave memory chip to the m-th slave memory chip using the terminating resistance values ​​of the first DQ pad to the m-th DQ pad of the main memory chip, based on the ZQ calibration options between the first DQ pad to the m-th DQ pad of the main memory chip and the DQ pads of the first slave memory chip to the m-th slave memory chip. Here, m is an integer greater than 1. Each of the plurality of memory chips includes a ZQ engine connected to the ZQ pads, and This includes the ZQ engine in each of the plurality of memory chips, comprising: The master / slave determiner circuit is configured to detect the voltage level of the ZQ pad and compare the detected voltage level of the ZQ pad with the source voltage level or the ground voltage level to determine whether the corresponding memory chip is the master memory chip or one of the plurality of slave memory chips.

2. The multi-chip package according to claim 1, wherein, The plurality of slave memory chips are configured to perform the second ZQ calibration operation simultaneously.

3. The multi-chip package according to claim 2, wherein, The plurality of slave memory chips are configured such that the time required to complete the second ZQ calibration operation performed by the plurality of slave memory chips is less than twice the time required to complete the second ZQ calibration operation performed by a single slave memory chip.

4. The multi-chip package according to claim 1, wherein, The ZQ pad of each of the plurality of slave memory chips is connected to the source voltage line or the ground voltage line.

5. The multi-chip package according to claim 1, wherein, The first DQ pad to the m-th DQ pad of the main memory chip are respectively connected to the first DQ pad to the m-th DQ pad of each of the first slave memory chips to the m-th slave memory chips.

6. The multi-chip package according to claim 1, wherein, The ZQ calibration option is stored in the registers of the main memory chip.

7. The multi-chip package according to claim 1, wherein, The ZQ calibration option is stored in the register of each of the plurality of memory chips.

8. The multi-chip package according to claim 1, wherein, The ZQ engine also includes: A first comparator is configured to compare the voltage level of the ZQ pad with a reference voltage level in response to the master / slave determiner circuit determining that the corresponding memory chip is the master memory chip; The multiplexer is configured to provide the output of the first comparator in the main memory chip as a first input and the output of the third comparator of each of the DQ drivers connected to the DQ pads in the plurality of slave memory chips as a second input; A first pull-up circuit is configured to perform a pull-up calibration operation, the pull-up calibration operation including generating a pull-up calibration code based on the output of the multiplexer; The second pull-up circuit is capable of controlling the impedance of the second pull-up circuit to be equal to the impedance of the first pull-up circuit based on the pull-up calibration code; A second comparator is configured to compare the reference voltage level with the voltage level of the connection node between the second pull-up circuit and the first pull-down circuit; and The first pull-down circuit is configured to perform a pull-down calibration operation, which generates a pull-down calibration code based on the output of the second comparator.

9. The multi-chip package according to claim 1, wherein, The ZQ calibration option is stored in the master / slave determiner circuit.

10. The multi-chip package according to claim 8, wherein, Each of the DQ drivers includes: The third pull-up circuit is configured to control the pull-up termination resistor of each DQ pad in the DQ pads based on the pull-up calibration code. The second pull-down circuit is configured to control the pull-down termination resistor based on the pull-down calibration code; and The third comparator is configured to compare the voltage level of each DQ pad in the DQ pads with the reference voltage level.

11. The multi-chip package according to claim 1, wherein, The multi-chip package comprises 2n memory chips, and the multiple memory chips are configured to perform the ZQ calibration operation on m DQ pads. Where n is an integer of 1 or greater, m is an integer less than or equal to 2n-1, and m ≤ 2n-1.

12. A multi-chip package, comprising: Printed circuit boards; The buffer chip on the printed circuit board includes a first impedance control ZQ pad and a first data input / output DQ pad. as well as Multiple memory chips are stacked on the printed circuit board and arranged spaced apart from the buffer chip, each of the multiple memory chips including a second ZQ pad and a second DQ pad; The multi-chip package is configured to receive a ZQ calibration command once from outside the multi-chip package. The buffer chip is configured as follows: Receive the ZQ calibration command, and perform a first ZQ calibration operation on the first ZQ pad using a ZQ resistor connected to the first ZQ pad, and The termination resistance value of the first DQ pad of the buffer chip is controlled based on the result of the first ZQ calibration operation. Based on the ZQ calibration command received by the buffer chip, each of the plurality of memory chips is configured to perform a second ZQ calibration operation on the second DQ pad of the corresponding memory chip by using the terminating resistance value of the corresponding DQ pad of the buffer chip, based on a ZQ calibration option representing a one-to-one correspondence between the first DQ pad of the buffer chip and the second DQ pad of the corresponding memory chip.

13. The multi-chip package according to claim 12, wherein, The plurality of memory chips are configured to perform the second ZQ calibration operation simultaneously.

14. The multi-chip package according to claim 13, wherein, The time required to complete the second ZQ calibration operation performed by the plurality of memory chips is less than twice the time required to complete the second ZQ calibration operation performed by one of the plurality of memory chips.

15. The multi-chip package according to claim 12, wherein, The second ZQ pad of each of the plurality of memory chips is connected to the source voltage line or the ground voltage line.

16. The multi-chip package according to claim 12, wherein, The first DQ pad of the buffer chip is connected to the second DQ pad of each of the plurality of memory chips.

17. The multi-chip package according to claim 12, wherein, The ZQ calibration option is stored in the register of the buffer chip.

18. The multi-chip package according to claim 12, wherein, The ZQ calibration option is stored in the register of each of the plurality of memory chips.

19. The multi-chip package according to claim 12, wherein, The number of the plurality of memory chips stacked in the multi-chip package is equal to the number of the second DQ pads of the plurality of memory chips.

20. The multi-chip package according to claim 12, wherein, The plurality of memory chips includes a first group of memory chips and a second group of memory chips, and the second ZQ calibration operation is performed by memory chips in the first group of memory chips and by memory chips in the second group of memory chips.

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