Method of controlling repair of volatile memory devices and memory devices

Abstract

A method of controlling repair of a volatile memory device and a memory device are provided. A test operating condition of the volatile memory device is set such that a probability of error is increased based on the test operating condition as compared to a normal operating condition for normal operation of the volatile memory device. A test pattern is set for a test target area corresponding to at least a portion of an array of memory cells included in the volatile memory device. A test operation of the volatile memory device is performed based on the test operating condition during the test pattern to detect error location information of an error in data stored in the test target area. A runtime repair operation is performed for the volatile memory device based on the error location information.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0107343, filed on August 30, 2019, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to semiconductor integrated circuits, and more specifically, to a method for controlling the repair of a volatile memory device and a memory device for performing the method. Background Technology

[0003] Semiconductor memory devices can be classified into non-volatile memory devices (such as flash memory devices) and volatile memory devices (such as dynamic random access memory (DRAM) devices). The high-speed operation and cost efficiency of DRAM have prepared it for effective use as system memory. However, due to the continuous shrinking of manufacturing design specifications for DRAM, bit errors in DRAM memory cells increase rapidly, and the yield of DRAM devices decreases.

[0004] Storage devices (such as flash-based solid-state drives (SSDs)) can be widely used as high-capacity storage media in computing devices. SSDs can store data in non-volatile memory devices (such as flash memory devices) and use volatile memory devices (such as DRAM devices) as buffer memory to manage various information used to control the flash memory devices. When a fault is discovered during the manufacturing process of a DRAM device, the faulty device or faulty cell can be repaired using various repair schemes. However, when a fault occurs after the DRAM device has been installed in the SSD and the product has been supplied to the user (i.e., after the SSD has been used at the user level), the SSD itself may also fail to operate correctly, in addition to the DRAM device. Summary of the Invention

[0005] Some example embodiments may provide a method for controlling the repair of volatile memory devices to enhance the reliability of volatile memory devices.

[0006] Some example embodiments may provide a storage device with enhanced reliability and lifespan by employing the method described above.

[0007] According to an example embodiment, a method for controlling the repair of a volatile memory device including a memory cell array includes: setting test operating conditions for the volatile memory device such that the error probability increases based on the test operating conditions compared to normal operating conditions used for normal operation; setting a test mode for a test object region corresponding to at least a portion of the memory cell array; performing test operations on the volatile memory device based on the test operating conditions during the test mode to detect error location information of errors in data stored in the test object region; and performing runtime repair operations on the volatile memory device based on the error location information.

[0008] According to an example embodiment, a method for controlling the repair of a volatile memory device included in a storage device includes: setting test operation conditions for the volatile memory device such that the error probability increases based on the test operation conditions compared to normal operation conditions for normal operation of the volatile memory device; setting a test mode for a test object region corresponding to at least a portion of a memory cell array included in the volatile memory device; performing test operations on the volatile memory device based on the test operation conditions during the test mode to detect error location information of errors in data stored in the test object region; generating cumulative error information by accumulating the error location information during repeated execution of the test operations; identifying error attribute information based on the cumulative error information, the error attribute information indicating the correlation between errors and the structure of the volatile memory device; and performing runtime repair operations on the volatile memory device based on the cumulative error information and the error attribute information. The cumulative error information includes candidate faulty row addresses among all row addresses of the volatile memory device and the number of correctable errors corresponding to each candidate faulty row address.

[0009] According to an example embodiment, a storage device includes: a non-volatile memory device; and a storage controller including the volatile memory device, the storage controller being configured to control access to both the non-volatile memory device and the volatile memory device. The storage controller includes an error checking and correction (ECC) engine configured to perform error detection and correction for access data of the volatile memory device. The storage controller is configured to: set test operating conditions for the volatile memory device such that the probability of an error increases based on the test operating conditions compared to normal operating conditions for normal operation of the volatile memory device; set a test mode for a test object region corresponding to at least a portion of a memory cell array included in the volatile memory device; perform test operations on the volatile memory device based on the test operating conditions during the test mode to detect error location information in data stored in the test object region; and perform runtime repair operations on the volatile memory device based on the error location information.

[0010] The method and storage device according to the example embodiments can efficiently manage errors to prevent failure of volatile memory devices, thereby enhancing the performance and lifespan of volatile memory devices and storage devices including volatile memory devices. Attached Figure Description

[0011] The exemplary embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a flowchart illustrating a method for repairing a volatile memory device according to an example embodiment.

[0013] Figure 2 This is a block diagram illustrating a memory system according to an example embodiment.

[0014] Figure 3 This is a diagram illustrating the on-chip ECC level based on data bits and parity bits.

[0015] Figure 4 This is a block diagram illustrating a volatile memory device according to an example embodiment.

[0016] Figure 5 It is shown Figure 4 A diagram of a portion of a volatile memory device.

[0017] Figure 6 This is a diagram illustrating the control of a test mode for a volatile memory device according to an example embodiment.

[0018] Figure 7 This is a diagram illustrating the test operation conditions for a test operation of a volatile memory device according to an example embodiment.

[0019] Figure 8A and Figure 8B This is a diagram illustrating the operating parameters of a volatile memory device according to an example embodiment.

[0020] Figure 9 and Figure 10 This is a diagram illustrating the setting of a test object area in a method for controlling a volatile memory device according to an example embodiment.

[0021] Figure 11 and Figure 12 This is a diagram illustrating a method for repairing a volatile memory device according to an example embodiment.

[0022] Figure 13 This is a flowchart illustrating the execution of a repair operation of a volatile memory device according to an example embodiment.

[0023] Figure 14A and Figure 14B This is a diagram illustrating a patrol read operation of a method for repairing a volatile memory device according to an example embodiment.

[0024] Figure 15 This is a diagram illustrating a cumulative error table of a method for repairing a volatile memory device according to an example embodiment.

[0025] Figure 16 This is a flowchart illustrating a method for repairing a volatile memory device according to an example embodiment.

[0026] Figure 17 This is a block diagram illustrating a volatile memory device performing a post-package repair operation according to an example embodiment.

[0027] Figure 18 This is a timing diagram showing the signals used for post-packaging repair operations.

[0028] Figure 19 and Figure 20 This is a diagram illustrating a patrol read operation of a method for repairing a volatile memory device according to an example embodiment.

[0029] Figure 21 This is a diagram illustrating the layout of a memory cell array included in a volatile memory device according to an example embodiment.

[0030] Figure 22 and Figure 23 This is a diagram illustrating the determination of error attributes in a method for repairing a volatile memory device according to an example embodiment.

[0031] Figure 24 This is a block diagram illustrating a storage device according to an example embodiment.

[0032] Figure 25 This is a flowchart illustrating a method for controlling the repair of a volatile memory device included in a storage device according to an example embodiment. Detailed Implementation

[0033] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, which illustrate some exemplary embodiments. In the drawings, the same reference numerals always denote the same elements. Repeated descriptions may be omitted.

[0034] Figure 1 This is a flowchart illustrating a method for repairing a volatile memory device according to an example embodiment.

[0035] Reference Figure 1The test operating conditions for the volatile memory device are set such that the error probability is increased to a higher level than that of normal operating conditions used for normal operation or normal access operation (S100). Normal operation or normal access operation can refer to either a read operation or a write operation. Normal operating conditions can be predetermined by the user or by standard specifications. The following will refer to... Figure 7 , Figure 8A and Figure 8B Describe an example implementation of setting test operation conditions.

[0036] A test mode is set for a test target region corresponding to at least a portion of the memory cell array included in the volatile memory device (S200). The test target region can be the entire region of the memory cell array or a sub-region of the memory cell array. The following will refer to... Figure 6 , Figure 9 and Figure 10 This describes an example implementation of setting up the test object area and test mode.

[0037] During the test mode, a test operation is performed based on the test operation conditions to detect error location information (such as the erroneous row address in the data stored in the test object area) (S300). A runtime repair operation is performed on the volatile memory device based on the error location information (S400).

[0038] Defense code schemes (such as additional patrol read operations) are being researched to enhance the reliability of systems including volatile memory devices (such as DRAM). Conventional approaches continuously monitor the state of memory cells by scanning memory regions of the DRAM and analyze fault locations to perform post-package repair (PPR). In the case of progressive failures associated with DRAM reliability, potential errors may not be apparent during normal operation. Because the entire memory cell must be scanned repeatedly, a relatively long time is required to collect and accumulate error information and analyze the errors. If the time spent on scanning and analysis increases, uncorrectable errors (i.e., failures of the volatile memory device) may occur before PPR is performed, potentially leading to data loss in the volatile memory device or system shutdown using the volatile memory device.

[0039] According to an example embodiment, potential faults can be detected and repaired in advance by setting test operating conditions to increase the probability of errors to a higher level than normal operating conditions (e.g., through a fault acceleration scheme).

[0040] Thus, the method and storage device according to the example embodiment can efficiently manage errors to prevent failure of the volatile memory device, thereby enhancing the performance and lifespan of the volatile memory device and the storage device including the volatile memory device.

[0041] Figure 2 This is a block diagram illustrating a memory system according to an example embodiment.

[0042] Reference Figure 2 The memory system 20 includes a memory controller 100 and a volatile memory device 200. In some embodiments, the memory system 20 may be as follows: Figure 24 The storage device 3000 shown is shown.

[0043] The memory controller 100 can control all operations of the memory system 20, and can also control all data exchanges between the external host device and the volatile memory device 200. For example, the memory controller 100 can write data to or read data from the volatile memory device 200 in response to a request from the external host device. Additionally, the memory controller 100 can issue operation commands to the volatile memory device 200 to control it.

[0044] In some example embodiments, the volatile memory device 200 may be a volatile memory such as dynamic random access memory (DRAM), synchronous DRAM (SRAM), low-power double data rate (LPDDR) SDRAM, etc. The example embodiments are not limited to a specific type of memory and can be applied to any type of memory that requires repair operations using a post-packaging repair (PPR) scheme.

[0045] The memory controller 100 sends the clock signal CLK, the command CMD, and the address (signal) ADDR (CMD / ADDR) to the volatile memory device 200, and exchanges data MD with the volatile memory device 200.

[0046] The volatile memory device 200 includes a memory cell array (MCA) 300 for storing data MD, error correction code or error checking and correction (ECC) circuitry 400, and control logic circuitry (or, control logic) 210. Figure 2 ECC circuitry 400 is shown to be included in volatile memory device 200; however, according to another example embodiment, ECC circuitry 400 may be included in memory controller 100.

[0047] The memory controller 100 may include a repair manager RMNG, which is configured to perform a method for repairing a volatile memory device according to an example embodiment. For example, the repair manager RMNG may be configured to perform... Figure 1 The method involves, for example, a repair manager RMNG controlling a routine read operation to generate accumulated error information and determine error attributes. Runtime repair operations can be controlled by the repair manager RMNG or by an external host device. In some example embodiments, the repair manager RMNG can store and manage accumulated error information in the accumulated error table AET 120 based on information CNFINF provided from the volatile memory device 200. Figure 2 The example shown is that AET 120 is included in memory controller 100; however, the example embodiment is not limited thereto. Reference will be made below. Figure 15 An example embodiment of AET 120 is described.

[0048] In some example embodiments, the volatile memory device 200 may provide the memory controller 100 with information about the configuration of the volatile memory device 200 via CNFINF. In this case, the repair manager RMNG in the memory controller 100 may determine the error attributes based on the information provided by the volatile memory device 200 via CNFINF.

[0049] Figure 3 This is a diagram illustrating the on-die ECC level based on the data bits and parity bits.

[0050] exist Figure 3 In Chinese, SEC stands for Single Error Correction, DED stands for Double Error Detection, and DEC stands for Double Error Correction. Figure 3 The parity bits and their corresponding size overhead (parity O / H) are shown. The parity bits correspond to Hamming codes or extended Hamming codes. The parity overhead corresponds to the ratio of the number of parity bits in the parity data corresponding to the written data to the number of data bits in the written data. Figure 3 The cases described are non-restrictive examples. For instance, if Bose-Chaudhuri-Hocquenghem (BCH) codes, Reed-Solomon codes, etc., are used, the number and size overhead of parity bits can be determined differently.

[0051] like Figure 3As shown, as the number of parity bits increases relative to the same number of data bits (e.g., as the ratio of parity bits to data bits increases), the ability to detect and correct errors increases. Conversely, as the number of data bits increases relative to the same error detection and correction capability, the corresponding number of parity bits increases, but the ratio of parity bits to data bits decreases.

[0052] Thus, error detection and / or error correction capabilities can increase with the ratio of the number of parity bits to the corresponding number of data bits. Consequently, the on-chip ECC level can increase with the ratio of the number of parity bits to the corresponding number of data bits. However, because the actual memory capacity decreases as the number of parity bits increases, the error correction capability is limited.

[0053] According to an example embodiment, failures of volatile memory devices can be prevented by performing runtime repair operations with relatively low error correction capabilities based on accumulated error information and error attributes. Here, a failure of the volatile memory device indicates an error in the volatile memory device that cannot be corrected by the ECC function.

[0054] Figure 4 This is a block diagram illustrating a volatile memory device according to an example embodiment. Figure 4 A dynamic random access memory (DRAM) device is shown as an example.

[0055] Reference Figure 4 The volatile memory device 200 may include control logic circuitry 210, address register 220, memory bank control logic 230, refresh counter 245, row address multiplexer 240, column address latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, I / O gate block (or I / O gate circuit) 290, ECC circuitry 400, and data I / O buffer 295.

[0056] ECC circuit 400 includes a first ECC engine 400a to an eighth ECC engine 400h, and I / O gate circuit block 290 includes multiple I / O gate circuits corresponding to multiple memory arrays.

[0057] The memory cell array 300 includes first memory cell arrays 310 to eighth memory cell arrays 380. The row decoder 260 includes first memory cell row decoders 260a to eighth memory cell row decoders 260h respectively connected to the first memory cell arrays 310 to eighth memory cell arrays 380. The column decoder 270 includes first memory cell column decoders 270a to eighth memory cell column decoders 270h respectively connected to the first memory cell arrays 310 to eighth memory cell arrays 380. The sense amplifier unit 285 includes first memory cell sense amplifiers 285a to eighth memory cell sense amplifiers 285h respectively connected to the first memory cell arrays 310 to eighth memory cell arrays 380. First memory arrays 310 to 380, first memory row decoders 260a to 260h, first memory column decoders 270a to 270h, and first memory sense amplifiers 285a to 285h can form first to eighth memory banks. Each of the first memory arrays 310 to 380 includes multiple memory cells MC formed at the intersections of multiple word lines WL and multiple bit lines BTL.

[0058] Address register 220 receives address ADDR from memory controller 100, which includes bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR. Address register 220 provides the received bank address BANK_ADDR to bank control logic 230, the received row address ROW_ADDR to row address multiplexer 240, and the received column address COL_ADDR to column address latch 250.

[0059] The memory bank control logic 230 generates a memory bank control signal in response to the memory bank address BANK_ADDR. The memory bank row decoders corresponding to the memory bank address BANK_ADDR in the first memory bank row decoders 260a to the eighth memory bank row decoders 260h are activated in response to the memory bank control signal, and the memory bank column decoders corresponding to the memory bank address BANK_ADDR in the first memory bank column decoders 270a to the eighth memory bank column decoders 270h are activated in response to the memory bank control signal.

[0060] Row address multiplexer 240 receives row address ROW_ADDR from address register 220 and refresh row address REF_ADDR from refresh counter 245. Row address multiplexer 240 selectively outputs row address ROW_ADDR or refresh row address REF_ADDR as row address RA. Row address RA output from row address multiplexer 240 is applied to first memory bank row decoders 260a to eighth memory bank row decoders 260h.

[0061] The active bank row decoder in the first bank row decoder 260a to the eighth bank row decoder 260h decodes the row address RA output from the row address multiplexer 240 and activates the word line of the memory array corresponding to the row address RA. For example, the active bank row decoder applies a word line drive voltage to the word line corresponding to the row address RA. The column address latch 250 receives the column address COL_ADDR from the address register 220 and temporarily stores the received column address COL_ADDR. In some example embodiments, in burst mode, the column address latch 250 generates a column address incremented from the received column address COL_ADDR. The column address latch 250 applies the temporarily stored or generated column address COL_ADDR' to the first bank column decoder 270a to the eighth bank column decoder 270h.

[0062] The active bank column decoders in the first bank column decoders 270a to the eighth bank column decoders 270h activate the sense amplifiers corresponding to the bank address BANK_ADDR and column address COL_ADDR' via the I / O gating circuit block 290. Each I / O gating circuit in the I / O gating circuit block 290 includes circuitry for gating input / output data, and further includes a read data latch for storing data output from the first bank memory array 310 to the eighth bank memory array 380, and a write driver for writing data to the first bank memory array 310 to the eighth bank memory array 380.

[0063] A codeword CW read from one of the memory arrays 310 to 380 is sensed by a sense amplifier coupled to the memory array from which the data will be read and stored in a read data latch. The codeword CW stored in the read data latch can be provided to the memory controller 100 via a data I / O buffer 295 after ECC decoding is performed on the codeword CW by the corresponding ECC engine. Data (or master data) MD to be written to one of the memory arrays 310 to 380 can be provided from the memory controller 100 to the data I / O buffer 295 and written to the memory array by a write driver after ECC encoding is performed on the data MD by the corresponding ECC engine.

[0064] The data I / O buffer 295 can provide data MD from the memory controller 100 to the ECC circuit 400 based on the clock signal CLK during write operations of the volatile memory device 200, and can also provide data MD from the ECC circuit 400 to the memory controller 100 during read operations of the volatile memory device 200.

[0065] During a write operation, ECC circuit 400 generates parity data (e.g., parity bits) based on master data MD from data I / O buffer 295 and provides codeword CW, including master data MD and parity bits, to I / O gate block 290. I / O gate block 290 can write codeword CW into a memory bank array.

[0066] Additionally, during a read operation, the ECC circuit 400 can receive a codeword CW read from a memory array from the I / O gate block 290. The ECC circuit 400 can perform ECC decoding on the data MD based on the parity bits in the codeword CW, correcting single-bit or double-bit errors in the data MD, and providing the corrected main data to the data I / O buffer 295. Furthermore, the ECC circuit 400 can provide error location information EPOS indicating the location of the error (e.g., address) through ECC decoding, and the error location information EPOS can be provided to the repair manager RMNG in the memory controller 100.

[0067] Control logic circuitry 210 can control the operation of volatile memory device 200. For example, control logic circuitry 210 can generate control signals for volatile memory device 200 to perform write or read operations. Control logic circuitry 210 includes command decoder 211 for decoding commands CMD received from memory controller 100 and mode register 212 for setting the operating mode of volatile memory device 200. For example, the value of mode register 212 can indicate the operating mode.

[0068] For example, the command decoder 211 can generate control signals corresponding to the command CMD by decoding the write enable signal ( / WE), row address strobe signal ( / RAS), column address strobe signal ( / CAS), chip select signal ( / CS), etc. The control logic circuit 210 can generate the column control signal CCS and the first control signal CTL1 to control the I / O gate circuit block 290, and generate the second control signal CTL2 to control the ECC circuit 400.

[0069] Figure 5 It is shown Figure 4 A diagram of a portion of a volatile memory device.

[0070] Reference Figure 5 The volatile memory device 200a may include control logic 210, a first memory bank array 310, I / O gating circuitry 290, and ECC circuitry 400. The first memory bank array 310 may include a normal cell array (NCA) and a redundant cell array (RCA). The normal cell array (NCA) may include multiple first memory blocks MB0 to MBk (e.g., 311 to 313), and the redundant cell array (RCA) may include at least a second memory block EDB (e.g., 314), where k is an integer greater than 1. The first memory blocks 311 to 313 are memory blocks that determine the memory capacity of the volatile memory device 200a. The second memory block 314 is used for ECC and / or redundancy repair. Because the second memory block 314 used for ECC and / or redundancy repair is used for ECC, data line repair, or block repair to repair one or more faulty cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block.

[0071] In each of the first memory blocks 311 to 313, a plurality of first memory cells are arranged in rows and columns. In the second memory block 314, a plurality of second memory cells are arranged in rows and columns. The first and second memory cells connected to the intersection of word line WL and bit line BTL (for the first memory blocks 311 to 313) and bit line RBTL (for the second memory block 314) can be dynamic memory cells.

[0072] I / O gating circuitry 290 may include a first switching circuit 291 connected to first memory blocks 311-313 and a second switching circuit 292 connected to second memory block 314. The first switching circuit 291 may include multiple column selectors MUX1 to MUXk, and the second switching circuit 292 may include a column selector MUXp. In volatile memory device 200a, bit lines corresponding to burst length (BL) data can be accessed simultaneously to support a maximum number of BLs indicating accessible column locations. For example, BL may be set to 8. In this case, each of bit lines BTL and RBTL may be connected to a corresponding one of column selectors MUX1 to MUXk and MUXp.

[0073] ECC circuit 400 can be connected to first switch circuit 291 and second switch circuit 292 via first data line GIO and second data line EDBIO, respectively. First data line GIO can be connected to data node NDd of ECC circuit 400, and second data line EDBIO can be connected to parity node NDp of ECC circuit 400.

[0074] The control logic circuit 210 can decode the command CMD to generate a first control signal CTL1 for controlling the first switch circuit 291 and the second switch circuit 292, and a second control signal CTL2 for controlling the ECC circuit 400.

[0075] The ECC cell, the object of each ECC operation, can be identified as various combinations of data corresponding to the same row address. If the ECC cell contains more errors than can be corrected, the data may be permanently lost, causing serious damage to systems using volatile memory devices. According to an example embodiment, runtime repair operations can be performed by efficiently managing correctable errors before uncorrectable errors occur.

[0076] Figure 6 This is a diagram illustrating the control of a test mode for a volatile memory device according to an example embodiment.

[0077] Reference Figure 6The volatile memory device can initiate test mode based on the test enter command (TENT) provided by the memory controller. Additionally, the volatile memory device can complete test mode based on the test exit command (TEXT) provided by the memory controller. During test mode, the volatile memory device can perform test operations based on the test operation condition (TOC) to detect error location information in the data stored in the test area of ​​the memory cell array. During normal mode, the volatile memory device can perform normal operations on areas other than the test area based on the normal operation condition (NOC). See below for further details. Figure 7 Further described, the Test Operating Condition (TOC) can be set such that the error probability is increased based on the Test Operating Condition (TOC) to be higher than the Normal Operating Condition (NOC). The Normal Operating Condition (NOC) and the Test Operating Condition (TOC) can be provided to the volatile memory device from the memory controller via a Mode Register Setting (MRS) command to be stored... Figure 4 In mode register 212.

[0078] In some example embodiments, the test entry command (TENT) may include test address information (TAI) indicating the test target region. The test address information (TAI) may be included within the test entry command (TENT), or it may be provided via a specified data line simultaneously with the test entry command (TENT) provided via the command address line.

[0079] Figure 7 This is a diagram illustrating the test operation conditions for a test operation of a volatile memory device according to an example embodiment.

[0080] Reference Figure 7 The test operating condition TOC according to the example embodiment can be related to refresh, voltage, timing, etc. Furthermore, in order to compare with the test operating condition TOC, in Figure 7 The normal operating conditions (NOC) are shown in the figure.

[0081] In some example embodiments, a test refresh interval tREFi' for test operations, which is longer than the normal refresh interval tREFi for normal operation, can be set as the test operation condition TOC.

[0082] The normal refresh interval time tREFi can represent the average time between two consecutive refresh operations on two rows of the same memory bank. For example, in the case of 8Gb DDR4 (Double Data Rate 4) DRAM (Dynamic Random Access Memory), the normal refresh interval time tREFi can be 7.8 μs (microseconds), and the refresh cycle time tRFC for each row refresh operation can be 350 ns (nanoseconds). In this case, the memory controller can issue a refresh command every 7.8 μs and wait 350 ns after issuing each refresh command to access the volatile memory device. In some example embodiments, the normal refresh interval time tREFi can be varied according to the operating temperature of the memory device. The normal refresh interval time tREFi can decrease as the operating temperature of the memory device increases. As the normal refresh interval time tREFi increases, more charge stored in the memory cells is discharged, and for memory cells with weak retention capabilities, the probability of error increases. Thus, potential failures can be accelerated by increasing the refresh interval time in test mode to be longer than in normal mode.

[0083] In some example embodiments, a test select word line voltage PXID' for test operations, which is lower than the normal select word line voltage PXID used for normal operation, can be set as the test operation condition TOC. When the select word line voltage is reduced, the charge stored in the memory cell during write operations is reduced, and the charge developed from the memory cell to the bit line during read operations is reduced, thus increasing the probability of errors. Thus, potential failures can be accelerated by reducing the select word line voltage in test mode to be lower than in normal mode.

[0084] In some example embodiments, a test timing parameter for test operation that is smaller than the normal timing parameter used for normal operation can be set as the test operation condition TOC. Figure 7 Two timing parameters, tWR and tRRD (or tWR' and tRRD'), are shown as examples, and timing parameters can include those described below (see reference). Figure 8A and Figure 8B Various other values ​​are described. Thus, potential failures can be accelerated by reducing timing parameters in test mode to be smaller than in normal mode.

[0085] Figure 8A and Figure 8B This is a diagram illustrating the operating parameters of a volatile memory device according to an example embodiment.

[0086] In volatile memory devices, timing parameters may include row cycle time tRC, / RAS to / CAS time tRCD, write recovery time tWR, row precharge time tRP, and row activation to row activation time tRRD, etc.

[0087] Row cycle time tRC represents the time between an activation command and the next activation command. / RAS to / CAS time tRCD represents the time between applying the / RAS signal and applying the / CAS signal, for example, the time between a row activation command and a column activation command. Write recovery time tWR represents the time between enabling the word line and writing data to the memory cell. Row precharge time tRP represents the time between the end of write recovery time tWR and precharging the bit line in preparation for the next activation command. Row activation to row activation time tRRD represents the time between two row activation commands, such as the row activation to row activation time between different sub-banks.

[0088] For example, as the write recovery time tWR increases, the data write time to the memory cell can increase. Therefore, volatile memory devices can obtain sufficient time margin for writing data.

[0089] Reference Figure 8A In the interleave method, the first through eighth memory banks are operated in an interleave manner, that is, they are operated sequentially, one memory bank at a time. The interleave method may include, for example, operations on the first memory bank and operations on any of the other memory banks. For example, operations on different memory banks can be alternated, such that row cycles occur on the first memory bank, then row cycles occur on the second memory bank, and then the alternation pattern repeats. Optionally, the interleave method may include: operations on the first memory bank and operations on the first memory bank. Figure 8A The memory interleaving access method corresponds to the continuous operation of the first memory.

[0090] A first activation command ACT0 is applied to the first memory bank. After a time interval tRCD from / RAS to / CAS, the first word line WL0 is enabled. The first word line WL0 is connected to a selected memory cell in the first memory bank. A data write operation WR0 is performed on the selected memory cell connected to the first word line WL0. The data write operation WR0 on the selected memory cell connected to the first word line WL0 in the first memory bank is performed within a write recovery time tWR. After the write recovery time tWR, the bit lines of the memory cells in the first memory bank can be precharged due to a first precharge command PRE0. A bit line precharge operation of the first memory bank is performed within a row precharge time tRP. The first write operation of the first memory bank is performed within a total interval tRCD + tWR + tRP.

[0091] Next, a second activation command ACT1 is applied to the first memory bank. After the / RAS to / CAS time tRCD, the second word line WL1 is enabled. The second word line WL1 is connected to a selected memory cell in the first memory bank. A data write operation WR1 is performed on the selected memory cell connected to the second word line WL1. The data write operation WR1 on the selected memory cell connected to the second word line WL1 in the first memory bank is performed within the write recovery time tWR. After the write recovery time tWR, the bit lines of the memory cells in the first memory bank can be precharged by the second precharge command PRE1. The bit line precharge operation of the first memory bank is performed within the row precharge time tRP. The second write operation of the first memory bank is performed within a total of tRCD + tWR + tRP. Then, additional write operations can be performed for additional word lines WL2, WL3, etc.

[0092] In the interleaved access method, the first write operation and the second write operation of the first memory bank are each executed at an interval of tRC corresponding to tRCD+tWR+tRP. The row cycle time tRC can be, for example, about 50 ns or more.

[0093] Reference Figure 8B In the sub-memory interleaved access method, the first and second sub-memories in each memory bank operate in an interleaved access manner (e.g., continuously in overlapping but out-of-phase cycles). The sub-memory interleaved access method can be explained by referring to, for example, the operation of the first and second sub-memories of the first memory bank. Assume a first activation command ACT0 is applied to the first sub-memory bank, and a second activation command ACT1 is applied to the second sub-memory bank. The first activation command ACT0 is applied to the first sub-memory bank, and after a time interval tRCD from / RAS to / CAS, the first word line WL0 of the first sub-memory bank is enabled. The first word line WL0 is connected to a selected memory cell in the first sub-memory bank. A data write operation WR0 is performed on the selected memory cell connected to the first word line WL0. The data write operation WR0 of the first sub-memory bank is performed within a write recovery time tWR'. After the write recovery time tWR', the bit lines of the memory cells in the first sub-memory bank can be precharged by a first precharge command PRE0. The bit line precharge operation of the first sub-memory bank is performed within a row precharge time tRP. Next, the first activation command ACT0 for the first sub-memory can be applied again, which can enable the second word line WL1 of the first sub-memory, perform a data write operation WR0 on the selected memory cell connected to the second word line WL1, and perform a bit line precharge operation, etc. This process can be repeated multiple times to write to the additional word lines of the first sub-memory.

[0094] A second activation command ACT1 is applied to the second sub-memory. After a time interval tRCD from / RAS to / CAS, the first word line WL0 of the second sub-memory is enabled. The first word line WL0 is connected to a selected memory cell in the second sub-memory. A data write operation WR1 is performed on the selected memory cell in the second sub-memory connected to the first word line WL0. The data write operation WR1 on the memory cell in the second sub-memory connected to the first word line WL0 is performed within a write recovery time tWR'. After the write recovery time tWR', the bit lines of the memory cells in the second sub-memory can be precharged by a second precharge command PRE1. The bit line precharge operation of the second sub-memory is performed within a row precharge time tRP. Next, the second activation command ACT1 can be applied again to the second sub-memory, the second word line WL1 of the second sub-memory can be enabled, the data write operation WR1 on the memory cell in the second sub-memory connected to the second word line WL1 can be performed, and the bit line precharge operation of the second sub-memory can be performed, etc. This process can be repeated multiple times to write to additional word lines of the second sub-memory.

[0095] In the sub-memory interleaved access method, a first activation command ACT0 for the first sub-memory and a second activation command ACT1 for the second sub-memory can be applied at tRRD intervals, where the tRRD interval corresponds to the row activation to row activation time between different sub-memory units. The row activation to row activation time tRRD can be, for example, about 6 ns or more.

[0096] Because two word lines cannot be enabled in a single memory bank (e.g., the first memory bank), continuous data write operations to the first memory bank can be performed at intervals of tRC. However, in the sub-bank interleaved access method, data write operations to the first and second sub-banks within the first memory bank can be performed at intervals of tRRD. The row activation to row activation time tRRD can be much shorter than the row cycle time tRC. Therefore, in the sub-bank interleaved access method, because continuous data write operations are performed at intervals of tRRD, the memory cell data write time tWR' in each data write operation may increase.

[0097] Figure 9 and Figure 10 This is a diagram illustrating the setting of a test object area in a method for controlling a volatile memory device according to an example embodiment.

[0098] Reference Figure 9 The memory cell array 300 can be divided into multiple sub-regions (e.g., first sub-region 301 to fourth sub-region 304), and one of the sub-regions 301 to 304 can be designated as the test object region. For example, as Figure 9 As shown, the second sub-region 302 can be set as the test target region. The memory controller can store test address information (TAI) indicating the second sub-region 302 corresponding to the test target region. When the second sub-region 302 is designated for test mode, the memory controller can prevent normal access operations to the second sub-region 302 (inaccessible) based on the test address information (TAI) and allow normal access operations to other sub-regions 301, 303, and 304.

[0099] Reference Figure 10 The memory controller can sequentially set multiple sub-regions 301 to 304 as test object regions one by one with respect to time. Figure 10 The example illustrates multiple sub-regions 301 to 304 set as test target regions in test mode TMD at an even frequency, but the example embodiment is not limited to this. For example, a specific sub-region considered to have a higher failure probability may be set as a test target region at a higher frequency than other sub-regions.

[0100] Figure 11 and Figure 12 This is a diagram illustrating a method for repairing a volatile memory device according to an example embodiment.

[0101] Reference Figure 11 and Figure 12 When the test object region 300t is operating in test mode TMD, data stored in the test object region 300t can be read and stored in the backup region 300b of the memory cell array 300. When the test mode TMD for the test object region 300t is completed, data stored in the backup region 300b can be read and stored in the test object region 300t.

[0102] Reference Figure 12 The volatile memory device can initiate a test mode for the test target region 300t based on the test entry command TENT provided from the memory controller 100 (S10). When the test mode is initiated, the memory controller 100 can perform a backup read operation BRD that reads data stored in the test target region 300t and a backup write operation BWR that stores the read data in the backup region 300b (S20). As described above, the volatile memory device can perform test operations on the test target region 300t based on test operation conditions, such that the error probability is increased to a higher level than the normal operation conditions used for normal operation based on the test operation conditions (S30). The volatile memory device can also perform normal operation on other regions set in the normal mode NMD (S40).

[0103] When data in the test area 300t is backed up to the backup area 300b, the memory controller 100 can generate a mapping table (MTB) containing mapping information about the mapping relationship between the addresses of the test area and the backup area. For example... Figure 11 As shown, the mapping table MTB includes the addresses ADDTS, ADDTS+OFS, ADDTS+2OFS, ..., and ADDTE of the test object region 300t, which are mapped one-to-one, and the addresses ADDBS, ADDBS+OFS, ADDBS+2OFS, ..., and ADDBE of the backup region 300b.

[0104] While performing test operations on the test target area 300t, the memory controller 100 can perform normal access operations on the backup area 300b instead of the test target area 300t based on the mapping table MTB.

[0105] When the test mode is completed, the memory controller 100 can execute a recovery read operation RRD to read data stored in the backup area 300b and a recovery write operation RWR to store the read data in the test object area 300t (S50). The volatile memory device can change to normal mode based on the test exit command TEXT provided by the memory controller 100 (S60).

[0106] Figure 13 This is a flowchart illustrating the execution of a repair operation of a volatile memory device according to an example embodiment.

[0107] Reference Figure 13 Accumulated error information can be generated by accumulating error location information during repeated execution of test operations (S410). The accumulated error information may be information reflecting the spatial and / or temporal history of the volatile memory device.

[0108] Error attribute information can be identified based on accumulated error information, which indicates the correlation between errors and the structure of the volatile memory device (S420). Accumulated error information can be stored in a accumulated error table (e.g., Figure 15 Storage and management are performed as shown in the diagram. Error attributes can be determined and assigned (or associated) based on the distribution of errors according to the structure of the volatile memory device. In some embodiments, the structure of the volatile memory device may include, for example, [details omitted]. Figure 21 The word line structure shown.

[0109] Runtime repair operations (S430) can be performed on the volatile memory device based on accumulated error information and error attribute information. The runtime repair operation instructs the operation of replacing the address where the error has occurred with a repair address, so that correctable errors that occur during normal operation of the volatile memory device do not develop into uncorrectable errors that cause failure of the volatile memory device.

[0110] Figure 14A and Figure 14B This is a diagram illustrating a patrol read operation of a method for repairing a volatile memory device according to an example embodiment.

[0111] A polling read operation can be performed regardless of an access read operation (or a normal read operation) to provide data read from the volatile memory device to an external device. The polling read operation can be performed repeatedly across all row addresses of the volatile memory device.

[0112] Reference Figure 14A and Figure 14B The multiple time-segmented patrol read operations PROPR1, PROPR2, and PROPR3 can be sequential. A patrol read operation can be performed during each time-segment of PROPR1, PROPR2, and PROPR3. For example, a patrol read operation can be performed from the start row address STADD to the end row address EDADD in the entire row address set of the volatile memory device during each time-segment of PROPR1, PROPR2, and PROPR3. Figure 14A A non-limiting example is shown of performing multiple time-segment inspection read operations PROPR1, PROPR2, and PROPR3 in the same mode. In some example embodiments, repeated inspection read operations may be performed in different modes.

[0113] Figure 14B The timing diagram for a patrol read operation PROPRi is shown. The patrol read operation can be suspended while performing an access operation to the volatile memory device (i.e., during normal mode NMD), and can be performed only during test mode TMD. A pointer PADD indicating the address where the patrol read operation is suspended can be stored in the repair manager RMNG. When test mode TMD resumes, patrol read operations can be performed continuously based on the stored pointer PADD.

[0114] Figure 15 This is a diagram illustrating a cumulative error table of a method for repairing a volatile memory device according to an example embodiment.

[0115] Accumulated error tables can be generated and managed for each of multiple memory banks. As an example, Figure 15Three cumulative error tables, AET1, AET2, and AET3, corresponding to three memory banks are shown, and a detailed example of a cumulative error message stored in one of the cumulative error tables, AET1, is included.

[0116] The Repair Manager (RMNG) can store accumulated error information in the accumulated error table AET1, such as candidate fault row addresses (PFRADD), the number of correctable errors (EN), and error attributes (ATT). Among all row addresses in the volatile memory device, candidate fault row addresses RAa to RAf can have the numbers of correctable errors corresponding to candidate fault row addresses RAa to RAf, respectively: 2, 1, 5, 4, 0, and 2. For example, Figure 15 The diagram shows that the number of correctable errors for candidate faulty row address RAa is 2, and the number of correctable errors for candidate faulty row address RAd is 4, etc. For example, the number of correctable errors EN is the number of correctable errors in the candidate faulty row addresses. ATT indicates the above error attributes. N / A indicates that the error attribute was not identified and assigned to the corresponding candidate faulty row address. In some embodiments, ATT can be indicated as N / A when the number of correctable errors is equal to or less than 2. Figure 15 An example is shown where the error attribute ATT1 is assigned to candidate faulty row addresses RAc, RAD, and RAE (or associated with candidate faulty row addresses RAc, RAD, and RAE). In some embodiments, ATT can be indicated as ATT1 when the number of correctable errors is greater than 2. The candidate faulty row address RAE to which the error attribute is assigned can have a number of correctable errors of zero. For example, if the error attribute is assigned to a row address even though the row address has no errors, then that row address can be included in the cumulative error table, which will be referred to below. Figures 21 to 23 To describe.

[0117] Figure 16 This is a flowchart illustrating a method for repairing a volatile memory device according to an example embodiment.

[0118] Reference Figure 16Each time a patrol read operation is performed, the accumulated error information AEI can be updated (S11). For each candidate fault line address included in the accumulated error information AEI, it is determined whether the number of correctable errors EN is greater than the reference number RN1 (S12). When the number of correctable errors EN of at least one of the candidate fault line addresses is greater than the reference number RN1 (S12: "Yes"), a post-packaging repair (PPR) operation is performed for all candidate fault line addresses corresponding to the number of correctable errors EN greater than the reference number RN1 (S13). When the number of correctable errors EN of all candidate fault line addresses is not greater than the reference number RN1 (S12: "No"), the patrol read operation is performed again to update the accumulated error information AEI, and it is determined again whether a post-packaging repair operation is needed based on the updated accumulated error information AEI. In some embodiments, before performing the PPR operation, the repair manager RMNG can determine the error attribute ATT based on the accumulated error information AEI, so that the PPR operation can be performed based on the accumulated error information AEI and the error attribute ATT.

[0119] This sequence of operations can be repeated until the volatile memory device is powered off (S14: "No"). When the volatile memory device is powered off (S14: "Yes"), the accumulated error information AEI and error attribute ATT can be stored in the non-volatile memory device (S15). When the volatile memory device is powered on again, the accumulated error information AEI and error attribute ATT can be loaded from the non-volatile memory device into the volatile memory device, so that even if the volatile memory device is powered off, the method for controlling the repair of the volatile memory device according to the example embodiment can be continuously executed.

[0120] Figure 17 This is a block diagram illustrating a volatile memory device performing a post-packaging repair operation according to an example embodiment.

[0121] Reference Figure 17 The DRAM device 500 may include a memory cell array 510, a row decoder (XDEC) 520, a column decoder (CDEC) 530, control logic circuitry 540, and fuse circuitry 550.

[0122] The memory cell array 510 may include multiple DRAM cells. DRAM cells may be connected to word lines NWL and RWL, and bit lines BTL, respectively. Some of the multiple DRAM cells may be normal cells, and another portion of the multiple DRAM cells may be redundant cells used to replace faulty cells among the normal cells. Word lines NWL may be normal word lines connected to normal cells, and word lines RWL may be redundant word lines connected to redundant cells.

[0123] Row decoder 520 can be connected to memory cell array 510 via word lines NWL and RWL. Row decoder 520 can select one word line from multiple word lines based on address ADDR (i.e., the row address in address ADDR) and control the voltage of the selected word line. Column decoder 530 can be connected to memory cell array 510 via bit line BTL. Column decoder 530 can select a portion of bit lines from multiple bit lines based on address ADDR (i.e., the column address in address ADDR) and control or detect the voltage of the selected bit lines.

[0124] Control logic circuit 540 can control all operations of DRAM device 500. Fuse setting operations can be performed under the control of control logic circuit 540. Control logic circuit 540 can be configured to set the fuse settings of fuse circuit 550 through a runtime repair operation. Through the fuse setting of fuse circuit 550, normal cells can be replaced with redundant cells. For example, fuse circuit 550 can receive address ADDR from the memory controller. When the row address in address ADDR corresponds to a normal word line NWL that has been determined to be a faulty word line, fuse circuit 550 can output a repair address, allowing row decoder 520 to select redundant word line RWL instead of normal word line NWL.

[0125] For example, fuse circuit 550 can determine the fuse setting such that the row address corresponding to the fault address can be translated into a repair address. Row decoder 520 can select redundant word lines (RWLs) based on the repair address from fuse circuit 550. Fuse circuit 550 can also transmit row addresses that do not correspond to the fault address to row decoder 520 without translation.

[0126] In this way, the DRAM device 500 can perform post-packaging repair operations for fault addresses by setting the electric fuse of the fuse circuit 550.

[0127] Figure 18 This is a timing diagram showing the signals used for post-packaging repair operations.

[0128] For example, runtime repair operations can be performed based on hard post-package repair (hPPR). In response to... Figure 18 The signals in the timing diagram can be executed. Figure 17 The fuse circuit 550 in the middle is set with an electric fuse.

[0129] Reference Figure 18During time points t1 to t2, a DRAM device operating based on clock signals CK_c and CK_t can enter hPPR mode in response to mode register set commands MRS4 and MRS0 provided from the memory controller, along with addresses (bank group address BG, bank addresses in bank group BA, and ADDR). Addresses BG, BA, and ADDR accompanying the deselect command DES and the refresh command REF may include invalid (i.e., no address) values ​​(NA), while addresses BG, BA, and ADDR accompanying other commands may include valid values ​​(VAL). For example, the value of address bit A13 (VAL) can be set to "1" to indicate activation of hPPR operation. In some example embodiments, data stored in memory banks including faulty rows can be flushed to the non-volatile memory device before entering hPPR mode. Additionally, all memory banks of the DRAM device can be precharged before entering hPPR mode. For example, the bit lines of all memory banks can be precharged before entering hPPR mode.

[0130] During time point t2 to time point t3, the DRAM device can perform hPPR operation in response to the activation command ACT, the automatic precharge write command WRA, and the address signals BGF and BAF. For example, the address signals BGF and BAF can correspond to a faulty row. This can be achieved by referring to... Figure 17 The described fuse circuit 550 is configured to perform hPPR operation.

[0131] During time points t3 to t4, the DRAM device can perform hPPR identification in response to the precharge command PRE, and during time points t4 to t5, the DRAM device can exit hPPR mode in response to the mode register set command MRS4 and the value of address bit A13 being "0". After exiting hPPR mode, the DRAM device can recover data based on the flushed data in the non-volatile memory device.

[0132] Figure 18 A non-limiting example of direct repair is shown, and the example embodiments are not limited thereto. In some example embodiments, a normal write command can be used instead of the automatic precharge write command (WRA) to perform the hPPR operation. In this case, backup or flushing of data stored in all memory banks of the DRAM device can be performed before entering hPPR mode. Alternatively, direct repair can be performed based on soft post-package repair (sPPR).

[0133] Figure 19 and Figure 20This is a diagram illustrating a patrol read operation of a method for repairing a volatile memory device according to an example embodiment.

[0134] Reference Figure 19 A full scan read operation (FSR) can be performed sequentially over all row addresses of the volatile memory device (S21). Furthermore, a deep scan read operation (DSR) can be performed more frequently than the full scan read operation (FSR) over candidate faulty row addresses included in the accumulated error table (S22). For example, two or more deep scan read operations (DSR) can be performed simultaneously with one full scan read operation (FSR). This allows monitoring of candidate faulty row addresses with errors or a high probability of future errors through the check read operations, and also helps prevent failures of the volatile memory device.

[0135] Figure 20 An example of a patrol read operation PROPRi is shown, comprising a full scan read operation FSR and multiple deep scan read operations DSR1 to DSRn. A full scan read operation FSR can be divided into multiple partial scan read operations PFSR1 to PFSRn. Each of the deep scan read operations DSR1 to DSRn can be initiated whenever the full scan read operation reaches an intermediate row address among row addresses PADD1 to PADDn-1. According to the example embodiment, for ease of explanation... Figure 20 The candidate faulty row addresses PFRADD for deep scan read operations are shown to be adjacent to each other. The candidate faulty row addresses PFRADD can be irregularly distributed across all row addresses between the start row address STADD and the end row address EDADD.

[0136] For example, multiple (n) deep scan read operations corresponding to the candidate faulty row address PFRADD can be performed, while a full scan read operation is performed for all other row addresses except the candidate faulty row address PFRADD, where n is an integer greater than 3.

[0137] Figure 21 This is a diagram illustrating the layout of a memory cell array included in a volatile memory device according to an example embodiment.

[0138] Figure 21 The memory cell array region (MCA), column decoder (CDEC), and row decoder (XDEC) are shown, and other components of the volatile memory device are omitted for clarity. The memory cell array region (MCA) includes a dual word line structure, a junction region (CJ), a sub-word line driver region (SWD), a sense amplifier region (SA), and a sub-memory cell array region (SMCA). The dual word line structure includes a main word line (NWE) and multiple sub-word lines (SWL).

[0139] In some example embodiments, the word select signal line PX, main word line NWE, sub-word line SWL, column select signal line CSL, local input-output data line LIO, and global input-output data line GIO can be formed in the upper vertical portion of the memory cell array region MCA. For ease of explanation, Figure 21 The power cord is omitted.

[0140] In the memory cell array region MCA, the connection region CJ, the sub-word line driver region SWD, the sense amplifier region SA, and the sub-memory cell array region SMCA are repeatedly arranged along the row direction X and the column direction Y. Memory cells MC are formed in the sub-memory cell array region SMCA and are connected to the sub-word line SWL and the bit line BL. Data can be written to or read from the memory cell MC in response to signals transmitted via the word select signal line PX, the master word line NWE, and the column select signal line CSL.

[0141] The column decoder CDEC generates signals on the column select signal line CSL based on the supplied column address COL_ADDR to select one or more columns of the array for reading or writing. The row decoder XDEC decodes the row address ROW_ADDR to generate signals for selecting one of the master word lines NWE and for selecting one of the word line select signal lines PX.

[0142] The main word line NWE extends along the row direction X on the sub-word line driver region SWD and the sub-memory cell array region SMCA. The word select signal line PX and the local input / output data line LIO extend along the row direction X on the connection region CJ and the sense amplifier region SA. The column select signal line CSL and the global input / output data line GIO extend along the column direction Y on the sense amplifier region SA and the sub-memory cell array region SMCA.

[0143] Figure 22 and Figure 23 This is a diagram illustrating the determination of error attributes in a method for controlling the repair of a volatile memory device according to an example embodiment.

[0144] Figure 22 An example is shown where multiple sub-word lines SWL1 to SWL4 are connected to a main word line NWE via a sub-word line driver SWD. Signals PXID1 to PXID4 and PXIB1 to PXIB4 are generated through address decoding. As mentioned above, each of signals PXID1 to PXID4 can be one of a test select word line voltage PXID' for test operation and a normal select word line voltage PXID for normal operation. Figure 22 In the diagram, BL1 to BL6 represent bit lines.

[0145] Sub-word lines SWL1 to SWL4, connected to the same main word line NWE, have structural dependencies. For example, a fault in the main word line NWE or in the driver that drives the main word line NWE can increase the number of faulty sub-word lines or the sum of errors in sub-word lines SWL1 to SWL4. Figure 22 and Figure 23 In the example case shown, the number of errors on sub-word line SWL3 is zero, but sub-word line SWL3 may rapidly develop into a failure. To prevent this possibility of failure, error attributes can be assigned to an address group that includes row addresses RA1 to RA4 corresponding to all sub-word lines SWL1 to SWL4 connected to the same main word line NWE, and address groups RA1 to RA4 can be stored in a cumulative error table as candidate failure row addresses.

[0146] In some example embodiments, when the sum of the number of correctable errors in the address group is greater than the number of risky errors (the number of risky errors is greater than the first reference number), a post-encapsulation repair operation can be performed on all row addresses RA1 to RA4 included in the address group. For example, a post-encapsulation repair operation can be performed on row address RA3, which may not even have any errors. In some embodiments, the first reference number may be stored in a register.

[0147] exist Figure 23 In the table, AETb indicates the cumulative error table before the error attribute ATT1 is determined, and AETA indicates the cumulative error table after the error attribute ATT1 is determined. The address group includes row addresses that each have the same error attribute information. Therefore, according to the embodiment, the cumulative error table can be generated or modified based on the error attribute determination.

[0148] In some example embodiments, when the number of candidate faulty row addresses included in the address group is greater than the second reference number, a main address error attribute can be determined for an address group that includes row addresses of multiple subword lines corresponding to the main word line of the volatile memory device. Figure 22 and Figure 23 In the example, the number of candidate fault line addresses corresponds to three, and the number of second references is assumed to be two. In some embodiments, the number of second references may be stored in a register.

[0149] In some example embodiments, when the sum of the number of correctable errors corresponding to all row addresses included in the address group is greater than a third reference number, a main address error attribute can be determined for an address group including row addresses of multiple subword lines corresponding to the main word line of the volatile memory device. Figure 22 and Figure 23 In the example, the sum of the number of correctable errors corresponds to eight, and the third reference number is assumed to be seven. In some embodiments, the third reference number may be stored in a register.

[0150] Figure 24 This is a block diagram illustrating a storage device according to an example embodiment.

[0151] Reference Figure 24 The system 1000 includes a host device 2000 and a storage device 3000. For example, the host device 2000 may be an embedded multimedia card (eMMC).

[0152] The host device 2000 can be configured to control data processing operations, such as data read operations and data write operations. The data processing operations can be performed at Single Data Rate (SDR) or Double Data Rate (DDR).

[0153] The host device 2000 can be a data processing device capable of processing data, such as a central processing unit (CPU), processor, microprocessor, or application processor. The host device 2000 and the storage device 3000 can be embedded in an electronic device or implemented in an electronic device. Figure 24 The system 1000 can be any electronic device.

[0154] Storage device 3000 can be electrically connected to other components of system 1000 (electronic device) via connection means (e.g., pads, pins, buses, or communication lines) to communicate with host device 2000. Host device 2000 may include processor (CPU) 2100, memory (MEM) 2200, and host controller interface (HCI) 2300 connected via bus 1320. Operating system (OS) and / or host firmware (FW) 2110 may be driven by processor 2100. Processor 2100 may include hardware and / or software for generating control commands (CMD), analyzing responses to RES, storing data in registers of storage device 3000 (e.g., extended (EXT)_CSD registers (not shown)), and / or processing data. Processor 2100 may drive the operating system and host firmware 2110 to perform these operations. Host controller interface 2300 may interface with storage device 3000.

[0155] Storage device 3000 may include a plurality of non-volatile memory devices (NVMs) 3100 and a storage controller 3200. In some embodiments, the storage controller 3200 may be a memory controller. The non-volatile memory devices 3100 may be selectively supplied with an external high voltage VPP. The non-volatile memory devices 3100 may be implemented using flash memory, FRAM, PRAM, MRAM, etc.

[0156] The storage controller 3200 can be connected to the non-volatile memory device 3100 via multiple channels CH1 to CHi. The storage controller 3200 may include one or more processors (CPUs) 3210, an ECC block 3220, a host interface 3230, a volatile memory device (VM) 3240, a non-volatile memory interface 3250, and a task queue (TQ) 3260 connected via bus 1330. In some example embodiments, the non-volatile memory device 3100 may include an on-chip ECC engine (not shown), in which case the ECC block 3220 may be omitted.

[0157] The volatile memory device 3240 can store data used to drive the memory controller 3200. Although Figure 24 An example embodiment in which a volatile memory device 3240 is included in a memory controller 3200 is shown, but the volatile memory device 3240 is not limited thereto. For example, the volatile memory device 3240 may be placed outside the memory controller 3200. The volatile memory device 3240 may be implemented as one of the volatile memory devices 200, 200a, and 500 disclosed herein.

[0158] ECC block 3220 can calculate the error correction code value of the data to be programmed during a write operation, and can use the error correction code value to correct errors in the read data during a read operation.

[0159] The processor 3210 is configured to control all operations of the storage controller 3200. For example, the processor 3210 can operate firmware including the flash translation layer (FTL). The FTL can perform various functions, such as address mapping, read calibration, error correction, etc.

[0160] Processor 3210 may have the function of controlling volatile memory device 3240. In this case, the aforementioned repair manager 3211 and cumulative error table AET can be implemented in processor 3210. Repair manager 3211 can be implemented in processor 3210 as hardware, software, or a combination of hardware and software.

[0161] Task queue 3260 can store tasks (e.g., write and read tasks provided from host device 2000) and status information for each task. Host interface 3230 can provide an interface with external devices (such as host device 2000). Non-volatile memory interface 3250 can provide an interface with non-volatile memory device 3100. Host device 2000 and storage device 3000 can be connected via bus 1310.

[0162] Figure 25This is a flowchart illustrating a method for controlling the repair of a volatile memory device included in a storage device according to an example embodiment.

[0163] Reference Figure 24 and Figure 25 The processor 3210 can load repair information including accumulated error information AEI from the non-volatile memory device 3100 (S51) and store the accumulated error information AEI in the accumulated error table AET. As described above, the repair manager 3211 can repeatedly execute the test operation TOPR (e.g., inspection read operation) based on the test operation conditions through a fault acceleration scheme (S52) to update the accumulated error information AEI (S53). The repair manager 3211 can determine the error attribute ATT based on the accumulated error information AEI (S54) and perform a runtime repair operation (e.g., post-packaging repair operation) based on the accumulated error information AEI and the error attribute ATT (S55). When the storage device 3000 is powered off, the accumulated error information AEI can be backed up or flushed to the non-volatile memory device 3100 (S56). Even if the storage device 3000 is not powered off, the accumulated error table can be backed up periodically.

[0164] The inventive concept can be applied to any volatile memory device requiring repair and systems including volatile memory devices. For example, the inventive concept can be applied to systems such as: memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMC), universal flash memory (UFS), mobile phones, smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, camcorders, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, etc.

[0165] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A method for controlling the repair of a volatile memory device comprising an array of memory cells, the method comprising: The test operating conditions for the volatile memory device are set such that the probability of error increases based on the test operating conditions compared to the normal operating conditions used for normal operation of the volatile memory device. Set the test mode for the test object region corresponding to at least a portion of the memory cell array; During the test mode, test operations on the volatile memory device are performed based on test operation conditions to detect error location information in the data stored in the test object area; Accumulated error information is generated by accumulating error location information during repeated execution of test operations; Error attribute information is identified based on accumulated error information, which indicates the correlation between errors and the dual-word structure of volatile memory devices, including main word lines and multiple sub-word lines. as well as Runtime repair operations are performed on volatile memory devices based on accumulated error information and error attribute information.

2. The method according to claim 1, wherein, The steps to set up test operation conditions include: Set a refresh interval that is longer than the refresh interval corresponding to the normal operation of volatile memory devices.

3. The method according to claim 1, wherein, The steps to set up test operation conditions include: Set the select word line voltage to be lower than the corresponding select word line voltage for normal operation of volatile memory devices.

4. The method according to claim 1, wherein, The steps to set up test operation conditions include: Set the timing parameter value to be smaller than the value of the timing parameter corresponding to the normal operation of the volatile memory device.

5. The method according to claim 1, wherein, The steps to set up the test mode include: Prevent normal operations on the test target area.

6. The method according to claim 1, further comprising: Read the data stored in the test object area to store the data in the backup area of ​​the memory cell array; Generate a mapping table that includes mapping information about the mapping relationship between the addresses of the test object region and the addresses of the backup region; as well as While performing test operations on the test target area, normal operations are performed on the backup area instead of the test target area based on the mapping table.

7. The method according to claim 6, further comprising: When the test operation for the test object area is completed, the data stored in the backup area is read to store the data in the test object area.

8. The method according to claim 1, wherein, The steps to set up the test mode include: Divide the memory cell array into multiple sub-regions; and Set one of the multiple sub-regions as the test object region.

9. The method according to claim 8, wherein, The multiple sub-regions are sequentially set as test object regions relative to time.

10. The method according to claim 1, wherein, The steps to set up the test mode include: The test mode is initiated based on a test enter command provided by a memory controller external to the volatile memory device; and The test mode is completed based on the test exit command provided by the memory controller.

11. The method of claim 10, wherein, The test entry command includes test address information indicating the test target area.

12. The method according to claim 1, in, The accumulated error information includes the candidate faulty row addresses among all row addresses of the volatile memory device, as well as the number of correctable errors corresponding to each candidate faulty row address.

13. The method according to claim 12, wherein, The steps to generate cumulative error information include: Store the addresses of candidate faulty rows in the cumulative error table.

14. The method according to claim 12, wherein, The steps for performing runtime repair operations based on accumulated error information and error attribute information include: Perform a post-encapsulation repair operation on the first candidate faulty row address among the candidate faulty row addresses, wherein the number of correctable errors in the first candidate faulty row address is greater than the number of stored references.

15. The method according to claim 12, wherein, The steps for performing a test include: During a given time period, a full scan read operation is sequentially performed on all row addresses of the volatile memory device; and During the time period, deep scan read operations are performed sequentially for candidate faulty row addresses, and In this process, two or more depth scan read operations are performed simultaneously with a full scan read operation.

16. The method according to claim 13, wherein, The steps for generating cumulative error information also include: The cumulative error table stores address groups that include row addresses that each have the same error attribute information.

17. The method according to claim 16, wherein, The steps for performing runtime repair operations based on accumulated error information and error attribute information include: When the sum of the number of correctable errors in an address group exceeds the reference number, perform a post-encapsulation repair operation on all row addresses included in the address group.

18. The method according to claim 12, further comprising: When the volatile memory device is powered off, the accumulated error information and error attribute information are stored in the non-volatile memory device; as well as When the volatile memory device is powered on, accumulated error information and error attribute information are loaded from the non-volatile memory device into the volatile memory device.

19. A method for controlling the repair of a volatile memory device included in a storage device, the method comprising: The test operating conditions for the volatile memory device are set such that the probability of error increases based on the test operating conditions compared to the normal operating conditions used for normal operation of the volatile memory device. A test mode is set for the test object region corresponding to at least a portion of the memory cell array included in the volatile memory device; During the test mode, test operations on the volatile memory device are performed based on test operation conditions to detect error location information in the data stored in the test object area; Accumulated error information is generated by accumulating error location information during repeated execution of test operations; Error attribute information is identified based on accumulated error information, which indicates the correlation between errors and the dual-word structure of volatile memory devices, including main word lines and multiple sub-word lines. as well as Runtime repair operations are performed on volatile memory devices based on accumulated error information and error attribute information.

20. A storage device, the storage device comprising: Non-volatile memory devices; as well as A memory controller, including volatile memory devices, is configured to control access to both non-volatile and volatile memory devices. The storage controller includes an error checking and correction engine, which is configured to perform error detection and correction for access data of the volatile memory device. The storage controller is also configured as follows: The test operating conditions for the volatile memory device are set such that the probability of error increases based on the test operating conditions compared to the normal operating conditions used for normal operation of the volatile memory device. A test mode is set for the test object region corresponding to at least a portion of the memory cell array included in the volatile memory device; During the test mode, test operations on the volatile memory device are performed based on test operation conditions to detect error location information in the data stored in the test object area; Accumulated error information is generated by accumulating error location information during repeated execution of test operations; Error attribute information is identified based on accumulated error information, indicating the correlation between errors and the dual-word structure of the volatile memory device, which includes main word lines and multiple sub-word lines; and Runtime repair operations are performed on volatile memory devices based on accumulated error information and error attribute information.

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