Integrated circuits and methods of their formation

Abstract

Various embodiments of the present disclosure relate to a method of forming an integrated circuit (IC). The method includes: forming a stacked gate electrode and a gate dielectric on a substrate. Depositing a sidewall spacer layer on the substrate and the gate electrode, wherein the sidewall spacer layer lines the sidewalls of the gate electrode. Etching back the sidewall spacer layer to form sidewall spacers on the sidewalls of the gate electrode. The etching back is performed using an etchant containing hydrogen fluoride at an etching rate of less than about 8 angstroms per minute. In addition, the substrate is doped with the sidewall spacers and the gate electrode in place to form a pair of source / drain regions on opposite sides of the gate electrode, respectively.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit and a method for forming the same. Background Art

[0002] Today's integrated circuits (ICs) include millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). ICs may use many different types of transistor devices depending on the application. In recent years, the growth of the cellular and radio frequency (RF) device markets has led to a significant increase in the demand for RF switch devices. For example, a smartphone may include 10 or more RF switch devices in its receive chain to switch the received signal to the appropriate frequency band. Summary of the invention

[0003] An embodiment of the present invention provides a method for forming an integrated circuit, comprising: forming a stacked gate electrode and a gate dielectric on a substrate; depositing a sidewall spacer layer covering the substrate and the gate electrode and further lining the sidewall of the gate electrode; etching back the sidewall spacer layer to form a sidewall spacer on the sidewall of the gate electrode, wherein the etching back is performed using an etchant containing hydrogen fluoride at an etching rate of less than about 8 angstroms per minute; and doping the substrate with the sidewall spacer and the gate electrode in place to form a pair of source / drain regions on opposite sides of the gate electrode, respectively.

[0004] An embodiment of the present invention provides a method for forming an integrated circuit, comprising: depositing a first pad layer covering a substrate; depositing a second pad layer covering the first pad layer; patterning the first pad layer and the second pad layer using a pattern of an isolation structure; etching into the substrate with the first pad layer and the second pad layer in place to form a groove located in the substrate and having the pattern, wherein the groove surrounds a device area and divides the device area; filling the groove with a dielectric material; forming a stacked gate electrode and a gate dielectric layer on the device area; depositing a first dielectric layer covering the substrate and the gate electrode and further lining the sidewall of the gate electrode, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of the first pad layer and less than the dielectric constant of the second pad layer; etching back the first dielectric layer to form a sidewall spacer on the sidewall of the gate electrode; and doping the substrate with the sidewall spacer and the gate electrode in place to form a pair of source / drain regions on opposite sides of the gate electrode, respectively.

[0005] An embodiment of the present invention provides an integrated circuit, comprising: a semiconductor substrate on an insulator, comprising a device layer overlying an insulator layer and a high resistivity layer located below the insulator layer; a pair of source / drain regions located in the device layer; a gate dielectric layer located on the device layer and laterally located between the source / drain regions; a gate electrode overlying the gate dielectric layer; a sidewall liner disposed along the sidewall of the gate electrode and along the upper surface of the device layer; and a sidewall spacer overlying the device layer and located on the sidewall and upper surface of the sidewall liner, wherein the sidewall spacer has a pair of segments respectively located on opposite sides of the gate electrode, wherein the sidewall spacer has a dielectric constant less than about 7, and wherein the dielectric constant of the sidewall spacer is greater than the dielectric constant of the sidewall liner and greater than the dielectric constant of the insulator layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 Cross-sectional views illustrating some embodiments of radio frequency (RF) switching devices having low dielectric constant sidewall spacers.

[0008] Figure 2 Examples include Figure 1 A cross-sectional view of some embodiments of an integrated circuit (IC) having an RF switching device located on a fully depleted (FD) semiconductor-on-insulator (SOI) substrate for RF.

[0009] FIG. 3A to FIG. 3E exemplify Figure 2 Cross-sectional views of some alternative embodiments of an IC.

[0010] Figure 4 Cross-sectional views illustrating some embodiments of an interconnect structure overlying an RF switching device having sidewall spacers with a low dielectric constant.

[0011] Figures 5 to 12 A series of cross-sectional views illustrating some embodiments of methods of forming an RF switching device having low dielectric constant sidewall spacers.

[0012] Fig.13 Examples with Figures 5 to 12 Flowcharts of some embodiments corresponding to the method. DETAILED DESCRIPTION

[0013] The present disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description in which a first feature is formed on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of brevity and clarity, rather than indicating the relationship between the various embodiments and / or configurations discussed by itself.

[0014] Furthermore, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature illustrated in a figure to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0015] In some embodiments, an RF switching device includes: a drain region; a source region; a gate electrode laterally located between the drain region and the source region; and a sidewall spacer including, for example, silicon nitride, located on a sidewall of the gate electrode. However, silicon nitride has a high dielectric constant, such as, for example, a dielectric constant between about 7 and 11. The high dielectric constant can result in a large parasitic capacitance from the gate electrode to the drain region. The large parasitic capacitance provides a leakage path from the gate electrode to the drain region and can also result in insertion loss. Therefore, the large parasitic capacitance can degrade the overall switching performance and degrade electrical isolation.

[0016] In some embodiments, to form an RF switching device, a gate electrode is formed on a substrate. A spacer layer comprising, for example, silicon nitride is deposited over the substrate and the gate electrode, and an etch back is performed into the spacer layer to form a sidewall spacer. In addition, in some embodiments, the etch back is performed by a solution comprising 1 weight percent hydrogen fluoride. However, such a solution has a high etching rate for the silicon nitride of the spacer layer, making it difficult to control the etch back. This in turn may result in overetching and / or damage to the substrate on which the RF switching device is located. Damage to the substrate may in turn result in leakage, further degrading the overall switching performance of the RF switching device.

[0017] Various embodiments of the present application relate to an RF switching device including a sidewall spacer having a low dielectric constant relative to silicon nitride, and a method of forming an RF switching device. It has been recognized that by using a low dielectric constant for the sidewall spacer, the parasitic capacitance from the gate electrode to the drain region is low. Therefore, the leakage at this parasitic capacitance is low and the isolation is high, so that the performance of the RF switching device is high. In some embodiments, the sidewall spacer is or includes a dielectric material, such as silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), or some other suitable material. It has been further recognized that a solution containing 1 weight percent hydrogen fluoride has a low etching rate for dielectric materials (e.g., SiOCN) relative to silicon nitride. In this way, the etch back of the RF switching device can be better controlled. This in turn can reduce over-etching and / or damage to the substrate on which the RF switching device is located, and can therefore reduce leakage, thereby further improving the overall switching performance of the RF switching device.

[0018] Figure 1 A cross-sectional view 100 of some embodiments of an RF switching device 102 including sidewall spacers 104 having a low dielectric constant is illustrated.

[0019] In some embodiments, the RF switching device 102 includes a gate electrode 106, a gate dielectric layer 108, a sidewall spacer 104, and a pair of source / drain regions 112. The gate dielectric layer 108 is located below the gate electrode 106 and separates the gate electrode 106 from a semiconductor layer 110 on which the RF switching device 102 is arranged. The semiconductor layer 110 may be, for example, or include silicon or some other suitable semiconductor material. The sidewall spacer 104 is disposed along the sidewalls of the gate electrode 106 and the sidewalls of the gate dielectric layer 108. The sidewall spacer 104 further overlies a pair of source / drain extensions 112e. The source / drain extensions 112e are portions of the pair of source / drain regions 112 that are respectively located on opposite sides of the gate electrode 106. The source / drain regions 112 and thus the source / drain extensions 112e are doped regions of the semiconductor layer 110 that have an opposite doping type than adjacent portions of the semiconductor layer 110. In some embodiments, the source / drain extensions 112e have a lower doping concentration than other portions of the source / drain regions 112.

[0020] In some embodiments, the sidewall spacers 104 include a sidewall spacer dielectric material with a low dielectric constant relative to silicon nitride. In yet other embodiments, the sidewall spacer dielectric material may be, for example, or include silicon oxycarbon nitride (SiOCN), silicon oxycarbon (SiOC), or some other suitable material. In other embodiments, the low dielectric constant is between about 4.2 to 5.5, about 4.2 to 4.5, about 4.5 to 5.0, about 5.0 to 5.5, or some other suitable value. In some embodiments, the low dielectric constant of the sidewall spacers 104 is less than about 6, less than about 7, or some other suitable value. In some embodiments, the sidewall spacers 104 include or consist essentially of silicon, carbon, nitrogen, and oxygen, wherein silicon is about 30 to 35 atomic percent of the sidewall spacers 104, carbon is about 3 to 10 atomic percent of the sidewall spacers 104, nitrogen is about 16 to 20 atomic percent of the sidewall spacers 104, and oxygen is about 40 to 45 atomic percent of the sidewall spacers 104. However, other atomic percentages and / or other materials are also suitable. In some embodiments, the gate dielectric layer 108 has a higher dielectric constant than the sidewall spacers 104.

[0021] In addition, the sidewall liner 114 lines the sidewall spacer 104 and separates the sidewall spacer 104 from the gate electrode 106, the gate dielectric layer 108, and the source / drain extensions 112e. The sidewall liner 114 may be, for example, or include silicon dioxide or some other suitable material, and / or may, for example, have a lower dielectric constant than the sidewall spacer 104 and / or the gate dielectric layer 108.

[0022] By adopting a relatively low dielectric constant for the sidewall spacer 104 (e.g., a dielectric constant less than or equal to 5.5), the parasitic capacitance from the gate electrode 106 to the drain region of the pair of source / drain regions 112 is low. This is because as the dielectric constant decreases, the capacitance between the gate electrode 106 and the drain region of the pair of source / drain regions 112 decreases. Therefore, leakage at this parasitic capacitance is low and isolation is high, so that the performance of the RF switching device 102 is high. In addition, reducing the parasitic capacitance from the gate electrode 106 to the drain region of the pair of source / drain regions 112 also reduces the insertion loss of the RF switching device 102. In some other embodiments, for example, if the dielectric constant of the sidewall spacer 104 is less than about 4.2, the etching rate of the sidewall spacer 104 can be increased (e.g., by a wet etching process). This may result in over-etching of the sidewall spacers 104 during fabrication, thereby reducing isolation between the RF switching device 102 and other semiconductor devices (not shown) disposed in / on the semiconductor layer 110 .

[0023] In some embodiments, for example, if the atomic percentage of carbon in the sidewall spacer 104 is less than about 3, the dielectric constant of the sidewall spacer 104 may be increased. This may increase the parasitic capacitance between the drain region of the pair of source / drain regions 112 and the gate electrode 106 of the RF switching device 102. In still other embodiments, for example, if the atomic percentage of nitrogen in the sidewall spacer 104 is greater than about 20, the dielectric constant of the sidewall spacer 104 may be increased. This may further increase the parasitic capacitance between the drain region of the pair of source / drain regions 112 and the gate electrode 106 of the RF switching device 102. In still other embodiments, for example, if the atomic percentage of oxygen in the sidewall spacer 104 is less than about 40, the dielectric constant of the sidewall spacer 104 may be increased. This may even further increase the parasitic capacitance between the drain region of the pair of source / drain regions 112 and the gate electrode 106 of the RF switching device 102. In an alternative embodiment, for example, if the atomic percentage of oxygen in the sidewall spacers 104 is greater than about 45, the sidewall spacers 104 (eg, Fig. 9 The rate at which the sidewall spacer layer 904 is etched (e.g., by wet etching) increases. This may result in the sidewall spacer 104 (e.g., Fig. 9 The sidewall spacer layer 904 is over-etched, thereby reducing the isolation between the RF switching device 102 and other semiconductor devices (not shown) disposed in / on the semiconductor layer 110.

[0024] Figure 2 Examples include Figure 1A cross-sectional view 200 of some embodiments of an integrated circuit (IC) in which an RF switching device 102 is located on a semiconductor-on-insulator (SOI) substrate 202 .

[0025] The SOI substrate 202 includes a high resistivity layer 204, a trap-rich layer 206 overlying the high resistivity layer 204, an insulator layer 208 overlying the trap-rich layer 206, and a device layer 210 overlying the insulator layer 208. The high resistivity layer 204 has a high resistance to reduce RF losses caused by the RF switching device 102, thereby improving the performance of the RF switching device 102. The high resistance may be, for example, between about 1,000 ohms and 10,000 ohms, about 1,000 ohms and 5,000 ohms, about 5,000 ohms and 10,000 ohms, or some other suitable value. The high resistivity layer 204 may be, for example, or include silicon or some other suitable semiconductor material.

[0026] The trap-rich layer 206 contains a high concentration of electron traps to reduce the parasitic surface conduction (PSC) effect along the top surface of the high-resistivity layer 204. The PSC effect may be caused, for example, by fixed charges in the insulator layer 208. The trap-rich layer 206 may be, for example, or include polysilicon or some other suitable material. In addition, the trap-rich layer 206 may have a thickness of, for example, about 1.0 micrometers to 2.0 micrometers, about 1.0 micrometers to 1.5 micrometers, about 1.5 micrometers to 2.0 micrometers, or some other suitable value.

[0027] The insulator layer 208 provides electrical isolation between the trap rich layer 206 and the device layer 210. In some embodiments, the insulator layer 208 has a lower dielectric constant than the sidewall spacers 104. In other embodiments, the insulator layer 208 has a higher dielectric constant than the sidewall spacers 104. The insulator layer 208 may, for example, be or include silicon dioxide and / or some other suitable dielectric material. The insulator layer 208 may, for example, have a thickness of about 1,000 angstroms to 4,000 angstroms, about 1,000 angstroms to 2,500 angstroms, about 2,500 angstroms to 4,000 angstroms, or some other suitable value.

[0028] The device layer 210 is a semiconductor layer in which the RF switching device 102 is formed. Figure 110 corresponds to the semiconductor layer 110 of the gate electrode 106. In addition, the device layer 210 is thin enough to promote full depletion of the RF switching device 102. That is, the depletion region of the RF switching device 102 extends through the entire thickness of the device layer 210. Since the gate electrode 106 is polysilicon having a doping type opposite to that of a portion of the device layer 210 located directly below the gate electrode 106, a depletion region may, for example, be formed in the device layer 210. The device layer 210 may, for example, have a thickness of about 50 nanometers to 100 nanometers, about 50 nanometers to 75 nanometers, about 75 nanometers to 100 nanometers, or some other suitable value. The device layer 210 may, for example, be or include silicon or some other suitable semiconductor material. In some embodiments, the device layer 210 is or includes the same semiconductor material as the high resistivity layer 204.

[0029] The isolation structure 212 extends into the device layer 210 to the insulator layer 208. In addition, the isolation structure surrounds the RF switching device 102. The isolation structure 212 provides electrical isolation between the RF switching device 102 and other devices (not shown) on the SOI substrate 202. The isolation structure 212 is or includes silicon dioxide and / or some other suitable dielectric material. The isolation structure 212 can be, for example, a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, and / or some other suitable isolation structure.

[0030] FIG. 3A to FIG. 3E exemplify Figure 2 Some alternative embodiments of the IC are shown in cross-sectional views 300a to 300e. Figure 3A As shown in the cross-sectional view 300a of FIG. 3 , the source / drain extension 112e is omitted. Figure 3B As shown in the cross-sectional view 300b of FIG. Figure 3C As illustrated in the cross-sectional view 300c of FIG. 1 , the device layer 210 is relatively thick, and thus the depletion region of the RF switching device 102 partially, but not completely, extends through the thickness of the device layer 210. Figure 3D As shown in the cross-sectional view 300d of FIG. 3 , the trap-rich layer 206 is omitted. Figure 3E As shown in the cross-sectional view 300e of FIG. 1 , a bulk semiconductor substrate 302 is used instead of the SOI substrate 202 and the bulk semiconductor substrate 302 is connected to the SOI substrate 202. Figure 1 Corresponding to the semiconductor layer 110.

[0031] although FIG. 3A to FIG. 3E Each illustrates Figure 2 Different variants of the IC, however Figure 2 Available FIG. 3A to FIG. 3E For example, the source / drain extension 112e (eg, Figure 3A ) and the trap-rich layer 206 may be omitted (as shown Figure 3D shown).

[0032] Figure 4 A cross-sectional view 400 of some embodiments of an IC having an interconnect structure 401 overlying an RF switching device 102 having sidewall spacers 104 having a low dielectric constant is illustrated.

[0033] In some embodiments, the IC includes the RF switching device 102 disposed in / on an SOI substrate 202. In yet other embodiments, the SOI substrate 202 includes a high resistivity layer 204, a trap-rich layer 206 overlying the high resistivity layer 204, an insulator layer 208 overlying the trap-rich layer 206, and a device layer 210 overlying the insulator layer 208. Figure 4 The SOI substrate 202 may be, for example, illustrated and / or described as Figure 2 In addition, the RF switching device 102 is disposed on and / or above the device layer 210 of the SOI substrate 202, and / or may be configured as Figures 1 to 3E The RF switching device 102 is provided.

[0034] In some embodiments, the device layer 210 may include a first doping type (e.g., p-type) having a first doping concentration, and the pair of source / drain regions 112 of the RF switching device 102 may include a second doping type (e.g., n-type) having a second doping concentration opposite to the first doping type. In some embodiments, the first doping type may be p-type and the second doping type may be n-type, or vice versa. In yet other embodiments, the first doping concentration of the device layer 210 is less than the second doping concentration of the pair of source / drain regions 112. In some embodiments, the gate electrode 106 may be, for example, or include polysilicon, doped polysilicon, or a metal (e.g., tungsten, titanium nitride, tantalum nitride, titanium, tantalum, silicide), another conductive material, or any combination of the foregoing materials. In some embodiments, the gate dielectric layer 108 may be, for example, or include an oxide (e.g., silicon dioxide), a high dielectric constant (high-k) dielectric material (e.g., silicon oxynitride, hafnium oxide, hafnium oxynitride, hafnium aluminum oxide, zirconium oxide), another suitable dielectric material, or any combination of the foregoing materials. As used herein, a high-k dielectric material is a dielectric material having a dielectric constant greater than 3.9.

[0035] The interconnect structure 401 overlies the SOI substrate 202. The interconnect structure 401 includes a plurality of vias 402, a plurality of conductive wires 404, and an interconnect dielectric structure. The plurality of vias 402 and the plurality of conductive wires 404 are disposed within the interconnect dielectric structure and are configured to electrically couple devices disposed within and / or on the SOI substrate 202 to each other and / or to another IC (not shown). The interconnect dielectric structure includes a plurality of inter-level dielectric (ILD) layers 406 and a plurality of dielectric protection layers 408. The bottommost via 402 extends from the bottommost conductive wire 404 to the pair of source / drain regions 112 and the gate electrode 106 of the RF switching device 102. The via 402 extends through the dielectric protection layer 408 (which may be made of a dielectric material and / or used as an etch stop layer during the manufacture of the IC). In some embodiments, the via 402 and / or the conductive wire 404 may be, for example, respectively or include aluminum, copper, tungsten, titanium nitride, tantalum nitride, another suitable conductive material, or any combination of the foregoing materials. In some embodiments, the ILD layer 406 may be, for example, or include an oxide (e.g., silicon dioxide), a low-k dielectric material, an extremely low-k dielectric material, another dielectric material, or any combination of the foregoing materials. As used herein, a low-k dielectric material is a dielectric material having a dielectric constant less than 3.9. Therefore, in some embodiments, the sidewall spacer 104 has a dielectric constant greater than that of the ILD layer 406. In yet other embodiments, the dielectric protection layer 408 may be, for example, or include silicon nitride, silicon carbide, silicon oxynitride, another suitable dielectric material, etc. Therefore, in some embodiments, the sidewall spacer 104 has a dielectric constant less than that of the dielectric protection layer 408.

[0036] Figures 5 to 12 Cross-sectional views 500 through 1200 illustrate some embodiments of methods of forming an RF switching device having a low dielectric constant sidewall spacer according to the present disclosure. Figures 5 to 12 The cross-sectional views 500 to 1200 shown in FIG. 1 are described with reference to one method, however, it should be understood that Figures 5 to 12 The structure shown in is not limited to the method, but can be independently independent of the method. Figures 5 to 12 It is described as a series of actions, but it should be understood that these actions are not restrictive, the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions illustrated and / or described can be omitted in whole or in part.

[0037] like Figure 5As illustrated in the cross-sectional view 500 of FIG. 5 , an SOI substrate 202 is provided. In some embodiments, the SOI substrate 202 includes a high resistivity layer 204, a trap-rich layer 206 overlying the high resistivity layer 204, an insulator layer 208 overlying the trap-rich layer 206, and a device layer 210 overlying the insulator layer 208. In such an embodiment, the SOI substrate 202 may be illustrated and / or described as Figure 2 In an alternative embodiment, a bulk semiconductor substrate is used instead of the SOI substrate 202, an example of which is shown in FIG. Figure 3E In an alternative embodiment, the trap-rich layer 206 is omitted, an example of which is Figure 3D middle.

[0038] like Figure 6 As illustrated in the cross-sectional view 600 of FIG. 2 , the isolation structure 212 is formed to extend from the top surface of the device layer 210 to the insulator layer 208. The isolation structure 212 surrounds the device region and divides the device region. For example, when viewed from top to bottom, the isolation structure 212 can extend laterally in a closed path along the boundary of the device region. In some embodiments, the process of forming the isolation structure 212 includes: depositing (e.g., by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, etc.) a pad oxide layer covering the SOI substrate 202; depositing (e.g., by a CVD process, a PVD process, an ALD process, etc.) a pad nitride layer covering the pad oxide layer; patterning the pad oxide layer and the pad nitride layer to form a trench having a layout of the isolation structure 212; with the pad oxide layer and the pad nitride layer in place, etching (e.g., wet etching and / or dry etching) into the SOI substrate 202 to extend the trench into the SOI substrate 202; depositing (e.g., by a CVD process, a PVD process, an ALD process, thermal oxidation, etc.) a dielectric layer filling the trench and covering the device layer 210; performing a planarization process (e.g., chemical mechanical planarization) on top of the dielectric layer; and removing the pad oxide layer and / or the pad nitride layer. However, other processes are also suitable for forming the isolation structure 212.

[0039] like Figure 7As illustrated in the cross-sectional view 700 of , a stacked gate electrode 106 and a gate dielectric layer 108 are formed on the device area. As described above, the device area is an area of ​​the device layer 210 that is surrounded and divided by the isolation structure 212. In some embodiments, the process of forming the gate electrode 106 and the gate dielectric layer 108 includes: depositing (for example, by a CVD process, a PVD process, an ALD process, thermal oxidation, etc.) a dielectric layer covering the device layer 210; depositing (for example, by a CVD process, a PVD process, an ALD process, sputtering, electroless plating, electroplating, etc.) a conductive layer covering the dielectric layer; and patterning the dielectric layer and the conductive layer, respectively, to define the gate dielectric layer 108 and the gate electrode 106. However, other processes are also applicable. For example, the gate electrode 106 and / or the gate dielectric layer 108 may be formed by a high-k metal gate (HKMG) replacement process. In such an embodiment, Fig.10 The sidewall spacers 104 may be formed before depositing the gate electrode 106 .

[0040] like Figure 8 As illustrated in the cross-sectional view 800 of , the top portion of the device layer 210 is lightly doped to reach the side of the gate electrode 106. The doping is formed into a pair of source / drain extensions 112e, which have a doping type opposite to the adjacent portion of the device layer 210. In an alternative embodiment, the light doping is omitted and the source / drain extensions 112e are not formed. In some other embodiments, the device layer 210 may include a first doping type (e.g., p-type), and the pair of source / drain extensions 112e may include a second doping type opposite to the first doping type (e.g., n-type). In an alternative embodiment, the light doping is omitted and the source / drain extensions 112e are not formed. The doping may, for example, use the gate electrode 106 (or a hard mask (not shown) on the gate electrode 106) as a mask. The doping may, for example, be performed by ion implantation and / or some other suitable doping process.

[0041] like Fig. 9 As illustrated in the cross-sectional view 900 of FIG. 1 , a sidewall liner layer 902 is deposited (e.g., by a CVD process, a PVD process, an ALD process, thermal oxidation, etc.) over the device layer 210 and the gate electrode 106, and the sidewall liner layer 902 further lines the sidewalls of the gate electrode 106. In an alternative embodiment, the deposition of the sidewall liner layer 902 is omitted (see, for example, FIG. 1 , in which the sidewall liner 114 is omitted). Figure 3B , Figure 3C and Figure 3E In some embodiments, the sidewall liner layer 902 may be or include, for example, silicon dioxide, another suitable dielectric material, or a combination of the foregoing materials.

[0042] Also by Fig. 9900 illustrates that a sidewall spacer layer 904 is deposited over the sidewall liner layer 902. In embodiments where the sidewall liner layer 902 is omitted, the sidewall spacer layer 904 further occupies the space currently occupied by the sidewall liner layer 902. In some embodiments, the sidewall spacer layer 904 comprises a sidewall spacer dielectric material having a low dielectric constant relative to silicon nitride. In still other embodiments, the sidewall spacer dielectric material may be, for example, or comprise silicon oxycarbon nitride (SiOCN), silicon oxycarbon (SiOC), or some other suitable material. In still other embodiments, the low dielectric constant is between about 4.2 to 5.5, about 4.2 to 4.5, about 4.5 to 5.0, about 5.0 to 5.5, or some other suitable value. In some embodiments, the low dielectric constant of the sidewall spacer layer 904 is less than about 6, less than about 7, or some other suitable value. In some embodiments, the sidewall spacer layer 904 includes or consists essentially of silicon, carbon, nitrogen, and oxygen, wherein silicon is approximately 30 to 35 atomic percent of the sidewall spacer layer 904, carbon is approximately 3 to 10 atomic percent of the sidewall spacer layer 904, nitrogen is approximately 16 to 20 atomic percent of the sidewall spacer layer 904, and oxygen is approximately 40 to 45 atomic percent of the sidewall spacer layer 904. However, other atomic percentages and / or other materials are also suitable. In some embodiments, the gate dielectric layer 108 has a higher dielectric constant than the sidewall spacer layer 904 and / or the sidewall liner layer 902 has a lower dielectric constant than the sidewall spacer layer 904. In addition, the dielectric constant of the sidewall spacer layer 904 may be, for example, less than 10% of the dielectric constant for the sidewall spacer layer 904. Figure 6 The dielectric constant of the pad nitride layer is described and / or is greater than that for Figure 6 The dielectric constant of the pad oxide layer is described.

[0043] In some embodiments, the sidewall spacer layer 904 is deposited by ALD, low pressure chemical vapor deposition (LPCVD), or some other suitable deposition. In yet other embodiments, the sidewall spacer layer 904 may be formed by only an ALD process or only an LPCVD process. In some embodiments in which the sidewall spacer layer 904 is deposited by a first ALD process, the deposition of the sidewall spacer layer 904 includes sequentially flowing the following gases over the device layer 210 in the following order: 1) hexachlorodisilane (e.g., Si2Cl6); 2) propylene (e.g., C3H6); 3) diatomic oxygen (e.g., O2); and 4) ammonia (e.g., NH3), thereby forming the sidewall spacer layer 904, such that the sidewall spacer layer 904 includes, for example, silicon oxycarbon nitride (SiOCN). In some embodiments, the aforementioned sequence is performed at an ambient temperature of about 580 to 650 degrees Celsius (°C), about 580 to 615°C, about 615 to 650°C, or some other suitable temperature. In some further embodiments, the hexachlorodisilane (HCD) in step 1) above is high purity hexachlorodisilane. By performing the first ALD process at ambient temperature, the sidewall spacer layer 904 includes or consists essentially of silicon, carbon, nitrogen, and oxygen (e.g., silicon oxycarbon nitride (SiOCN), wherein silicon is approximately 30 to 35 atomic percent of the sidewall spacer layer 904, carbon is approximately 3 to 10 atomic percent of the sidewall spacer layer 904, nitrogen is approximately 16 to 20 atomic percent of the sidewall spacer layer 904, and oxygen is approximately 40 to 45 atomic percent of the sidewall spacer layer 904. In some embodiments, this ensures that the sidewall spacer layer 904 includes silicon oxycarbon nitride (SiOCN) and / or has a low dielectric constant between approximately 4.5 and 5.5.

[0044] In some embodiments, for example, if the atomic percentage of carbon in the sidewall spacer layer 904 is less than about 3, the dielectric constant of the sidewall spacer layer 904 is increased. This may increase the distance between the drain region and the RF switching device ( Fig.11 In some embodiments, for example, if the atomic percentage of carbon in the sidewall spacer layer 904 is greater than about 10, the rate at which the sidewall spacer layer 904 is etched (e.g., by wet etching) may be increased during subsequent processing steps. For example, this may result in overetching of the sidewall spacer layer 904 during subsequent processing steps, thereby reducing the RF switching device ( Fig.11102) and other semiconductor devices (not shown) disposed in / on the SOI substrate 202. In some embodiments, for example, if the atomic percentage of nitrogen in the sidewall spacer layer 904 is greater than about 20, the dielectric constant of the sidewall spacer layer 904 can be increased. This can further increase the RF switching device ( Fig.11 In some other embodiments, for example, if the atomic percentage of oxygen in the sidewall spacer layer 904 is less than about 40, the dielectric constant of the sidewall spacer layer 904 is increased. This can further increase the RF switching device ( Fig.11 In an alternative embodiment, for example, if the atomic percentage of oxygen in the sidewall spacer layer 904 is greater than about 45, the rate at which the sidewall spacer layer 904 is etched (e.g., by wet etching) during subsequent processing steps is increased. This may result in over-etching of the sidewall spacer layer 904 during subsequent processing steps, thereby reducing the RF switching device ( Fig.11 102) and other semiconductor devices (not shown) disposed in / on the SOI substrate 202.

[0045] In an alternative embodiment, the sidewall spacer layer 904 is deposited by a second ALD process that includes sequentially flowing the following gases over the device layer 210 in the following order: 1) hexachlorodisilane (e.g., Si2Cl6); 2) propylene (e.g., C3H6); and 3) diatomic oxygen (e.g., O2) to form the sidewall spacer layer 904 such that the sidewall spacer layer 904 comprises, for example, silicon oxycarbide (SiOC). In some embodiments, the second ALD process sequence is performed at an ambient temperature of about 580 degrees Celsius to 650 degrees Celsius (°C), about 580°C to 615°C, about 615°C to 650°C, or some other suitable temperature. In some embodiments, this ensures that the sidewall spacer layer 904 comprises silicon oxycarbide (SiOC) and / or has a low dielectric constant between about 4.2 and 4.5. This can reduce the RF switching device ( Fig.11 The parasitic capacitance between the drain region of 102) and the gate electrode 106, thereby improving the RF switching device ( Fig.11 In yet other alternative embodiments, the sidewall spacer layer 904 may be or include, for example, silicon carbide (SiC) and / or another suitable dielectric material.

[0046] In still other embodiments, the second ALD process may omit the propylene flow of step 2, and may instead include performing a polishing process to remove impurities after performing the hexachlorodisilane flow. Thus, in such embodiments, the second ALD process may include: 1) flowing hexachlorodisilane (e.g., Si2Cl6) over the device layer 210; 2) performing a polishing process; and 3) flowing diatomic oxygen (e.g., O2) over the device layer 210 to form the sidewall spacer layer 904. In some embodiments, the polishing process may include flowing hexachlorodisilane (e.g., Si2Cl6) over the device layer 210 to form the sidewall spacer layer 904. Fig. 9 The structure is exposed to one or more etchants (eg, hydrofluoric acid, nitric acid, glacial acetic acid), another suitable etchant, or any combination of the foregoing.

[0047] like Fig.10 As shown in the cross-sectional view 1000, the side wall liner ( Fig. 9 902) and the sidewall spacer layer ( Fig. 9 The etching is performed in 904 of the sidewall spacer layer. Fig. 9 904) and side wall liner ( Fig. 9 902) to form a sidewall spacer layer 104 and a sidewall liner layer 114. In some embodiments, the back etching includes using an etchant solution to etch the sidewall liner layer ( Fig. 9 902) and the sidewall spacer layer ( Fig. 9 904) performs a wet etching process, the etchant solution comprising about 1 weight percent hydrogen fluoride. However, other percentages are also applicable to hydrogen fluoride. For example, the etchant solution can be about 0.001 to 1.0 weight percent hydrogen fluoride. In some embodiments, the etchant solution is an aqueous solution in which the solvent is deionized water or some other suitable solvent. In some embodiments, the etch back is performed at an ambient temperature of about 600° C. to 650° C., about 630° C., or some other suitable value.

[0048] In some embodiments, during the etch back, the sidewall spacer layer ( Fig. 9 904) is etched at a relatively low rate relative to the high rate of etching silicon nitride. In some other embodiments, silicon nitride may be etched at a high rate of about 8 angstroms per minute, for example, during the etch back, while the sidewall spacer layer ( Fig. 9 904) can be etched at a low rate of about 5 angstroms per minute, for example, during the etch back. Therefore, in some embodiments, the etch back is performed at a low rate of less than about 8 angstroms per minute, or some other suitable rate, on the sidewall spacer layer ( Fig. 9 904) is etched. For example, in at least one embodiment, the sidewall spacer layer ( Fig. 9 904) is or contains silicon oxycarbonitride and the etching back is performed by an aqueous solution containing about 1 weight percent hydrogen fluoride, and the etching back rate can be performed at a rate of about 5 angstroms per minute. By etching the sidewall spacer layer ( Fig. 9 The etch back can be better controlled by etching back the sidewall spacer 104, thereby controlling the shape and / or width of the sidewall spacer 104. This in turn can reduce overetching and / or damage to the device layer 210 and can therefore reduce leakage. In addition, this can increase the RF switching device ( Fig.11 102) and other semiconductor devices (not shown) disposed in / on the SOI substrate 202. In some other embodiments, during the etch-back, the sidewall liner layer ( Fig. 9 902) comparable sidewall spacer layer ( Fig. 9 In some embodiments, if the etchant solution contains more than about 1.0 weight percent hydrogen fluoride, for example, the sidewall spacer layer ( 904 ) may be overetched during the etch back. Fig. 9 904) and / or device layer 210, thereby making the RF switching device ( Fig.11 The performance of 102) is degraded.

[0049] like Fig.11 As illustrated in the cross-sectional view 1100 of , the device layer 210 is doped to form a pair of source / drain regions 112, thereby defining the RF switching device 102. The source / drain regions 112 overlap with the source / drain extensions 112e and have the same doping type (although at a higher doping concentration than the source / drain extensions 112e). In an alternative embodiment, Figure 8 Implementation Fig.11 The doping for forming the source / drain region 112 in the embodiment of the present invention is replaced by the light doping for forming the source / drain extension 112e, thereby omitting the source / drain extension. The doping may, for example, use the sidewall spacer 104 and the gate electrode 106 (or a hard mask (not shown) on the gate electrode 106) as a mask. The doping may, for example, be performed by ion implantation and / or some other suitable doping process.

[0050] By using a low dielectric constant for the sidewall spacers 104, the parasitic capacitance from the gate electrode 106 to the drain region of the pair of source / drain regions 112 is low. Therefore, leakage at this parasitic capacitance is low and isolation is high, so that the performance of the RF switching device 102 is high.

[0051] like Fig.12As illustrated in the cross-sectional view 1200 of FIG. 1 , an interconnect structure 401 is formed on the SOI substrate 202 and the RF switching device 102. The interconnect structure 401 includes a plurality of vias 402, a plurality of conductive wires 404, a plurality of interlayer dielectric (ILD) layers 406, and a plurality of dielectric protection layers 408. In some embodiments, the vias 402 and the conductive wires 404 may be formed by a single damascene process and / or a dual damascene process. In other embodiments, the ILD layer 406 and / or the dielectric protection layer 408 may be deposited, for example, by a CVD process, a PVD process, an ALD process, thermal oxidation, or other suitable growth or deposition process, respectively. In still other embodiments, the dielectric protection layer 408 may be configured to be used as an etch stop layer during the single damascene process and / or the dual damascene process, respectively.

[0052] In some embodiments, the ILD layer 406 may be, for example, or include an oxide (e.g., silicon dioxide), a low-k dielectric material, an extremely low-k dielectric material, another dielectric material, or any combination thereof. Therefore, in some embodiments, the sidewall spacer 104 has a dielectric constant greater than that of the ILD layer 406. In yet other embodiments, the dielectric cap layer 408 may be, for example, or include silicon nitride, silicon carbide, silicon oxynitride, another suitable dielectric material, etc. Therefore, in some embodiments, the sidewall spacer 104 has a dielectric constant less than that of the dielectric cap layer 408.

[0053] Fig.13 A flow chart illustrating some embodiments of a method 1300 of forming an RF switching device having a sidewall spacer with a low dielectric constant according to the present disclosure. Fig.13 The method 1300 is illustrated and described herein as a series of actions or events, but it should be understood that the illustrated order of these actions or events should not be interpreted as having a limiting meaning. For example, certain actions may occur in different orders and / or may occur simultaneously with other actions or events other than those illustrated and / or described herein. In addition, not all illustrated actions may be required when implementing one or more aspects or embodiments described herein, and one or more of the actions illustrated herein may be performed in one or more separate actions and / or stages.

[0054] A silicon-on-insulator (SOI) substrate is provided at act 1302. The SOI substrate includes a device layer overlying a high-resistivity layer. Figure 5 Cross-sectional view 500 of some embodiments corresponding to act 1302 is illustrated.

[0055] At act 1304, an isolation structure is formed in the device layer. The isolation structure surrounds and divides the device region in the device layer. Figure 6 Cross-sectional view 600 of some embodiments corresponding to act 1304 is illustrated.

[0056] At act 1306, a gate dielectric layer and a gate electrode are formed laterally over the device layer and within the device region. Figure 7 Cross-sectional view 700 of some embodiments corresponding to act 1306 is illustrated.

[0057] At act 1308, a sidewall liner layer is formed over the gate electrode and the device layer and a sidewall spacer layer is formed over the sidewall liner layer. The sidewall spacer layer has a low dielectric constant. Fig. 9 Cross-sectional view 900 of some embodiments corresponding to act 1308 is illustrated.

[0058] At act 1310, the sidewall liner layer and the sidewall spacer layer are etched to define a sidewall liner and a sidewall spacer, respectively. In some embodiments, the sidewall liner layer is etched faster than the sidewall spacer layer. Fig.10 Cross-sectional view 1000 of some embodiments corresponding to act 1310 is illustrated.

[0059] At act 1312, a pair of source / drain regions are formed within the device layer and on opposite sides of the gate electrode. Fig.11 Cross-sectional view 1100 of some embodiments corresponding to act 1312 is illustrated.

[0060] At act 1314, an interconnect structure is formed over the SOI substrate. Fig.12 Cross-sectional view 1200 of some embodiments corresponding to act 1314 is illustrated.

[0061] Therefore, in some embodiments, the present disclosure provides a radio frequency (RF) switching device disposed on / over a silicon-on-insulator (SOI) substrate, wherein the RF switching device includes a gate dielectric layer, a gate electrode, a source / drain region, and a sidewall spacer. The sidewall spacer laterally surrounds the sidewalls of the gate electrode and the gate dielectric layer, wherein the dielectric constant of the sidewall spacer is less than the dielectric constant of silicon nitride.

[0062] In some embodiments, the present application provides a method for forming an integrated circuit (IC), the method comprising: forming a stacked gate electrode and a gate dielectric on a substrate; depositing a sidewall spacer layer covering the substrate and the gate electrode and further lining the sidewalls of the gate electrode; etching back the sidewall spacer layer to form sidewall spacers on the sidewalls of the gate electrode, wherein the etching back is performed using an etchant containing hydrogen fluoride at an etching rate of less than about 8 angstroms per minute; and doping the substrate with the sidewall spacers and the gate electrode in place to form a pair of source / drain regions on opposite sides of the gate electrode, respectively.

[0063] In some embodiments, the sidewall spacer layer has a dielectric constant between about 4.2 and 5.5. In some embodiments, the etchant is a solution containing about 1 weight percent hydrogen fluoride. In some embodiments, the etch back is performed at an ambient temperature of about 630 degrees Celsius. In some embodiments, the sidewall spacer layer is deposited by an atomic layer deposition process. In some embodiments, the atomic layer deposition process includes flowing hexachlorodisilane, propylene, diatomic oxygen and ammonia over the substrate and the gate electrode. In some embodiments, the atomic layer deposition process includes flowing hexachlorodisilane and diatomic oxygen over the substrate and the gate electrode, wherein the atomic layer deposition process also includes performing a polishing process after flowing the hexachlorodisilane over the substrate and the gate electrode and before flowing the diatomic oxygen. In some embodiments, the method further includes: depositing a sidewall liner layer over the gate electrode and the substrate, wherein the sidewall liner layer is disposed between the sidewall spacer layer and the substrate, wherein the dielectric constant of the sidewall liner layer is less than the dielectric constant of the sidewall spacer layer. In some embodiments, the etch-back removes a portion of the sidewall liner layer to form a sidewall liner, wherein during the etch-back, the sidewall liner layer is etched faster than the sidewall spacer layer.

[0064] In some embodiments, the present application provides a method for forming an integrated circuit (IC), the method comprising: depositing a first pad layer covering a substrate; depositing a second pad layer covering the first pad layer; patterning the first pad layer and the second pad layer using a pattern of an isolation structure; etching into the substrate with the first pad layer and the second pad layer in place to form a groove located in the substrate and having the pattern, wherein the groove surrounds a device area and divides the device area; filling the groove with a dielectric material; forming a stacked gate electrode and a gate dielectric layer on the device area; depositing a first dielectric layer covering the substrate and the gate electrode and further lining the sidewalls of the gate electrode, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of the first pad layer and less than the dielectric constant of the second pad layer; etching back the first dielectric layer to form a sidewall spacer on the sidewall of the gate electrode; and doping the substrate with the sidewall spacer and the gate electrode in place to form a pair of source / drain regions on opposite sides of the gate electrode, respectively.

[0065] In some embodiments, the method further includes: removing the second liner layer before the forming of the gate electrode. In some embodiments, the first liner layer and the second liner layer include silicon oxide and silicon nitride, respectively. In some embodiments, the etching back includes applying an aqueous solution to the first dielectric layer, and wherein the aqueous solution includes hydrogen fluoride. In some embodiments, the substrate includes: a first silicon layer; a polysilicon layer overlying the first silicon layer; an insulator layer overlying the polysilicon layer; and a second silicon layer overlying the insulator layer. In some embodiments, the sidewall spacer includes carbon oxynitride silicon, wherein silicon is about 30 to 35 atomic percent of the sidewall spacer, carbon is about 3 to 10 atomic percent of the sidewall spacer, nitrogen is about 16 to 20 atomic percent of the sidewall spacer, and oxygen is about 40 to 45 atomic percent of the sidewall spacer. In some embodiments, the first dielectric layer is etched at a rate of about 5 angstroms per minute during the etching back.

[0066] In some embodiments, the present application provides an integrated circuit (IC), which includes: a semiconductor-on-insulator (SOI) substrate, including a device layer overlying an insulator layer and a high-resistivity layer located below the insulator layer; a pair of source / drain regions located in the device layer; a gate dielectric layer located on the device layer and laterally between the source / drain regions; a gate electrode overlying the gate dielectric layer; a sidewall liner disposed along a sidewall of the gate electrode and along an upper surface of the device layer; and a sidewall spacer overlying the device layer and located on a sidewall and an upper surface of the sidewall liner, wherein the sidewall spacer has a pair of sections respectively located on opposite sides of the gate electrode, wherein the sidewall spacer has a dielectric constant less than about 7, and wherein the dielectric constant of the sidewall spacer is greater than the dielectric constant of the sidewall liner and greater than the dielectric constant of the insulator layer.

[0067] In some embodiments, the sidewall spacer consists essentially of silicon oxycarbon nitride and has a dielectric constant of about 4.5 to 5.5. In some embodiments, the sidewall spacer consists essentially of silicon oxycarbide and has a dielectric constant of about 4.2 to 4.5. In some embodiments, the sidewall liner and the sidewall spacer directly overlie the pair of source / drain regions.

[0068] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming an integrated circuit, comprising: forming a stacked gate electrode and a gate dielectric on the substrate; depositing a sidewall spacer layer covering the substrate and the gate electrode and lining the sidewalls of the gate electrode; Etching back the sidewall spacer layer to form sidewall spacers on the sidewalls of the gate electrode, wherein the etching back is performed using an etchant containing hydrogen fluoride at an etching rate of 5 angstroms per minute; as well as The substrate is doped with the sidewall spacers and the gate electrode in place to form a pair of source / drain regions on opposite sides of the gate electrode, respectively.

2. The method of forming an integrated circuit of claim 1, wherein the sidewall spacer layer consists essentially of silicon oxycarbon nitride.

3. The method of forming an integrated circuit according to claim 1, wherein the etchant is a solution containing 1 weight percent hydrogen fluoride.

4. The method of forming an integrated circuit according to claim 1, wherein the etching back is performed at an ambient temperature of 630 degrees Celsius. 5 . The method of forming an integrated circuit according to claim 1 , wherein the sidewall spacer layer is deposited by an atomic layer deposition process.

6. The method of forming an integrated circuit of claim 5, wherein the atomic layer deposition process comprises flowing hexachlorodisilane, propylene, diatomic oxygen, and ammonia over the substrate and the gate electrode.

7. The method of forming an integrated circuit according to claim 5, wherein the atomic layer deposition process includes flowing hexachlorodisilane and diatomic oxygen over the substrate and the gate electrode, wherein the atomic layer deposition process also includes performing a polishing process after flowing the hexachlorodisilane over the substrate and the gate electrode and before flowing the diatomic oxygen.

8. The method of forming an integrated circuit according to claim 1, further comprising: A sidewall liner layer is deposited over the gate electrode and the substrate, wherein the sidewall liner layer is disposed between the sidewall spacer layer and the substrate, wherein a dielectric constant of the sidewall liner layer is less than a dielectric constant of the sidewall spacer layer.

9. The method of forming an integrated circuit according to claim 8, wherein the etch-back removes portions of the sidewall liner layer to form a sidewall liner, wherein during the etch-back, the sidewall liner layer is etched faster than the sidewall spacer layer.

10. A method of forming an integrated circuit, comprising: depositing a first pad layer covering the substrate; depositing a second cushion layer covering the first cushion layer; patterning the first pad layer and the second pad layer using a pattern of an isolation structure; With the first pad layer and the second pad layer in place, etching is performed into the substrate to form a groove in the substrate and having the pattern, wherein the groove surrounds a device area and divides the device area; filling the trench with a dielectric material; forming a stacked gate electrode and a gate dielectric layer on the device region; Depositing a first dielectric layer covering the substrate and the gate electrode and lining the sidewalls of the gate electrode, wherein the dielectric constant of the first dielectric layer is greater than the dielectric constant of the first pad layer and less than the dielectric constant of the second pad layer, wherein the first dielectric layer is substantially composed of silicon oxycarbon nitride; Etching back the first dielectric layer to form sidewall spacers on the sidewalls of the gate electrode; as well as The substrate is doped with the sidewall spacers and the gate electrode in place to form a pair of source / drain regions on opposite sides of the gate electrode, respectively.

11. The method of forming an integrated circuit according to claim 10, further comprising: The second pad layer is removed before forming the gate electrode. 12 . The method of forming an integrated circuit according to claim 10 , wherein the first pad layer and the second pad layer comprise silicon oxide and silicon nitride, respectively.

13. The method of forming an integrated circuit of claim 10, wherein the etching back comprises applying an aqueous solution to the first dielectric layer, and wherein the aqueous solution comprises hydrogen fluoride.

14. The method of forming an integrated circuit according to claim 13, wherein the substrate comprises: A first silicon layer; a polysilicon layer, covering the first silicon layer; an insulator layer overlying the polysilicon layer; as well as A second silicon layer overlies the insulator layer.

15. The method of forming an integrated circuit of claim 10 wherein the sidewall spacers consist essentially of silicon oxycarbon nitride, wherein silicon is 30 to 35 atomic percent of the sidewall spacers, carbon is 3 to 10 atomic percent of the sidewall spacers, nitrogen is 16 to 20 atomic percent of the sidewall spacers, and oxygen is 40 to 45 atomic percent of the sidewall spacers.

16. The method of forming an integrated circuit according to claim 10, wherein the first dielectric layer is etched at a rate of 5 angstroms per minute during the etch back.

17. An integrated circuit comprising: A semiconductor-on-insulator substrate comprising a device layer overlying an insulator layer and a high resistivity layer below the insulator layer; a pair of source / drain regions located in the device layer; a gate dielectric layer located on the device layer and laterally between the source / drain regions; a gate electrode overlying the gate dielectric layer; A sidewall liner is disposed along the sidewall of the gate electrode and along the upper surface of the device layer; as well as A sidewall spacer overlying the device layer and located on the sidewall and upper surface of the sidewall liner, wherein the sidewall spacer has a pair of segments respectively located on opposite sides of the gate electrode, wherein the sidewall spacer has a dielectric constant less than 7, and wherein the dielectric constant of the sidewall spacer is greater than the dielectric constant of the sidewall liner and greater than the dielectric constant of the insulator layer, wherein the sidewall spacer is substantially composed of silicon oxycarbon nitride.

18. The integrated circuit of claim 17, wherein the sidewall spacers have a dielectric constant of 4.5 to 5.

5.

19. The integrated circuit of claim 17, wherein the sidewall spacers have a dielectric constant of 4.2 to 4.

5.

20. The integrated circuit of claim 17, wherein the sidewall liner and the sidewall spacer directly overlie the pair of source / drain regions.

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