FINFET devices and methods

Abstract

The present application discloses a FINFET device and method. A device includes a fin extending from a semiconductor substrate; a gate stack on the fin; a first spacer on a sidewall of the gate stack; a source / drain region in the fin adjacent to the first spacer; an interlayer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source / drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source / drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends through the air gap and is in physical contact with the second spacer, wherein the first portion of the ILD seals the air gap.

Description

Technical Field

[0001] The present disclosure generally relates to FINFET devices and methods. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers of material over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a fin extending from a semiconductor substrate; a gate stack above the fin; a first spacer on a sidewall of the gate stack; a source / drain region adjacent to the first spacer in the fin; an interlayer dielectric layer (ILD) extending above the gate stack, the first spacer and the source / drain region, the ILD comprising a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source / drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends through the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

[0005] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a fin protruding from a substrate; a gate structure above a channel region of the fin; an epitaxial region adjacent to the channel region in the fin; a first dielectric layer above the gate structure, the first dielectric layer comprising a first region doped with a first dopant; a contact plug extending through the first dielectric layer and contacting the epitaxial region; a second dielectric layer above the first dielectric layer; and an air gap between the contact plug and the gate structure, wherein an upper region of the air gap is defined by the first region, and wherein the air gap is separated from the second dielectric layer by the first region.

[0006] According to another aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a gate stack above a semiconductor fin; forming an epitaxial source / drain region in the semiconductor fin adjacent to the gate stack; depositing a first dielectric layer above the gate stack and above the epitaxial source / drain region; forming an opening in the first dielectric layer to expose the epitaxial source / drain region; depositing a sacrificial material in the opening; depositing a conductive material on the sacrificial material in the opening; removing the sacrificial material to form a groove; and injecting a dopant into the first dielectric layer, wherein, after the first dielectric layer is injected, the groove is covered by the first dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity.

[0008] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A and Fig. 15B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 and Fig.23 is a cross-sectional view of an intermediate stage in the fabrication of a FinFET with an air gap, according to some embodiments.

[0011] Fig.24 Experimental data of dopant concentration profiles according to some embodiments are shown.

[0012] Fig.25 Experimental data showing the measured thickness of an interlayer dielectric with an overlying cap layer according to some embodiments is shown.

[0013] Fig.26 , Fig.27A , Fig.27B and Fig.28 is a cross-sectional view of an intermediate stage in the fabrication of a FinFET with an air gap, according to some embodiments.

[0014] Fig.29 Experimental data showing the measured thickness of an interlayer dielectric without an overlying capping layer according to some embodiments is shown.

[0015] Fig. 30A , Fig. 30B , Fig.31A , Fig.31B , Fig.32A , Fig.32B , Fig.33A and Fig.33B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET with an air gap, according to some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Additionally, for ease of description, spatially relative terms, such as "under," "beneath," "below," "on," "above," etc., may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0018] According to some embodiments, an air gap is formed around the contact of the source / drain epitaxial region of a FinFET device. The low dielectric constant (k value) of the air gap can reduce the capacitance between the gate stack and the contact of the FinFET device, which can improve the higher speed (e.g., "AC") operation of the FinFET. In some embodiments, an implantation process is performed to implant dopants into an adjacent interlayer dielectric (ILD) layer so that the ILD layer expands and seals the upper region of the air gap. In some embodiments, the presence of an additional dielectric layer (e.g., an etch stop layer) above the ILD layer during implantation can result in more lateral expansion of the ILD layer and less longitudinal expansion of the ILD layer. By sealing the air gap, the chance of subsequently deposited conductive material entering the air gap is reduced or eliminated. Therefore, the chance of an electrical short circuit being formed due to the presence of conductive material in the air gap is reduced or eliminated.

[0019] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view. The FinFET includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). An isolation region 56 is disposed in the substrate 50, and the fin 52 protrudes on and between adjacent isolation regions 56. Although the isolation region 56 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single continuous material like the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this article, the fin 52 refers to a portion extending between adjacent isolation regions 56.

[0020] A gate dielectric layer 92 is along the sidewalls and over the top surface of the fin 52, and a gate electrode 94 is over the gate dielectric layer 92. The source / drain regions 82 are disposed on opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross-sectional planes used in subsequent figures are further shown. Section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Section BB is perpendicular to section AA and along the longitudinal axis of the fin 52 and in a direction of current flow, for example, between the source / drain regions 82 of the FinFET. Section CC is parallel to section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0021] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0022] Figures 2 to 33B Included are cross-sectional views of intermediate stages in the fabrication of a FinFET according to some embodiments. Figures 2 to 7 Shows Figure 1 Reference cross section AA shown in FIG. , except for multiple fins / FinFETs. Fig. 8A , 9A , 10A, 11A, 12A, 13A, 14A, 15A, 30A, 31A, 32A and 33A are along Figure 1 The reference section AA is shown, and Figure 8B , 9B , 10B, 11B, 12B, 13B, 14B, 14C, 15B, 16, 17, 18, 19, 21, 22, 23, 26, 27A, 27B, 28, 30B, 31B, 32B and 33B are along Figure 1 A similar cross section BB as shown in FIG. 1 is shown, except with multiple fins / FinFETs. Fig. 10C and 10D It is along Figure 1 Reference cross section CC is shown, in addition to multiple fins / FinFETs.

[0023] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide); alloy semiconductors (including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide); or combinations thereof.

[0024] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type FinFET). The region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type FinFET). The region 50N can be physically separated from the region 50P (as shown by the separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be set between the region 50N and the region 50P.

[0025] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic.

[0026] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is less than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, a mask (or other layer) may remain on the fin 52.

[0027] exist Figure 4 In the embodiment, the insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 may be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it into another material, such as an oxide), etc., or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material such as the above-described filling material may be formed on the liner.

[0028] exist Figure 5 In the embodiment, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), a deep etching process, a combination thereof, etc. may be utilized. The planarization process exposes the fin 52 so that after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are level. In embodiments where the mask remains on the fin 52, the planarization process may expose the mask or remove the mask so that after the planarization process is completed, the top surface of the mask or the fin 52, respectively, is flush with the top surface of the insulating material 54.

[0029] exist Figure 6 Insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. Insulating material 54 is recessed so that the upper portions of fins 52 in regions 50N and 50P protrude from between adjacent STI regions 56. In addition, the top surface of STI region 56 may have a flat surface, a convex surface, a concave surface (e.g., a concave shape), or a combination thereof as shown. The top surface of STI region 56 may be formed to be flat, convex, and / or concave by appropriate etching. STI region 56 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of insulating material 54 (e.g., etching the material of insulating material 54 at a faster rate than the material of fin 52). For example, oxide removal using, for example, diluted hydrofluoric acid (dHF) may be used.

[0030] about Figures 2 to 6 The process described is only one example of how fin 52 may be formed. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over the top surface of substrate 50, and a trench may be etched through the dielectric layer to expose substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, a heteroepitaxial structure may be used for fin 52. For example, Figure 5 The fin 52 in the substrate 50 can be recessed, and a material different from the fin 52 can be epitaxially grown over the recessed fin 52. In these embodiments, the fin 52 includes a recessed material and an epitaxially grown material arranged over the recessed material. In yet another embodiment, a dielectric layer can be formed over the top surface of the substrate 50, and a trench can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trench using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments of epitaxial growth of homoepitaxial or heteroepitaxial structures, the epitaxially grown material can be doped in situ during growth, which can avoid previous and subsequent implantations, although in-situ and implantation doping can be used together.

[0031] In addition, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon-germanium (Si x Ge 1-x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, etc.

[0032] In addition, Figure 6 In the embodiment of the present invention, appropriate wells (not shown) may be formed in the fin 52 and / or the substrate 50. In some embodiments, a P well may be formed in the region 50N, and an N well may be formed in the region 50P. In some embodiments, a P well or an N well is formed in both the region 50N and the region 50P.

[0033] In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc., which is implanted into the region to a density equal to or less than 10 18 cm -3 The concentration, for example, is about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0034] After implanting region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist may be formed using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P, such as a PMOS region. The p-type impurity may be boron, boron fluoride, indium, etc., which is implanted into the region to a density equal to or less than 10 18 cm -3 The concentration, for example, is about 10 16 cm -3 and about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0035] After implantation of regions 50N and 50P, annealing may be performed to repair implant damage and activate implanted p-type and / or n-type impurities. In some embodiments, the grown material of the epitaxial fins may be in-situ doped during growth, which may eliminate implantation, although in-situ and implantation doping may be used together.

[0036] exist Figure 7 In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy dielectric layer 60 can be deposited on the dummy gate layer 62 and then planarized, for example, by CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), polycrystalline silicon germanium (poly-silicon germanium), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit selected materials. The dummy gate layer 62 can be made of other materials with high etching selectivity to the etching of the isolation region. Mask layer 64 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed across region 50N and region 50P. Note that for illustration purposes only, dummy dielectric layer 60 is shown covering only fin 52. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI region 56, extending between STI gate layer 62 and STI region 56.

[0037] Figures 8A to 15B Various additional steps in the fabrication of example devices are shown. Figures 8A to 15B Features in either region 50N or region 50P are shown. For example, Figures 8A to 15B The structure shown is applicable to both region 50N and region 50P. Differences in the structures of region 50N and region 50P, if any, are described in the text accompanying each figure.

[0038] exist Fig. 8A and 8B In the embodiment, the mask layer 64 (see Figure 7 ) is patterned to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching technique to form a dummy gate 72. The dummy gate 72 covers each channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from an adjacent dummy gate. The dummy gate 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of each epitaxial fin 52.

[0039] In addition, Fig. 8A and Figure 8B In the embodiment, the gate sealing spacer 80 can be formed on the exposed surface of the dummy gate 72, the mask 74 and / or the fin 52. Thermal oxidation or deposition followed by anisotropic etching can form the gate sealing spacer 80. The gate sealing spacer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0040] After forming the gate sealing spacer 80, an implant for a lightly doped source / drain (LDD) region (not explicitly shown) may be performed. In embodiments with different device types, similar to the above Figure 6 50P, and an appropriate type of impurity (e.g., p-type) can be implanted into the exposed fins 52 in the regions 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the regions 50P, while exposing the regions 50N, and an appropriate type of impurity (e.g., n-type) can be implanted into the exposed fins 52 in the regions 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. The lightly doped source / drain regions can have approximately 10 15 cm -3 to about 10 19 cm -3Annealing can be used to repair implant damage and activate implanted impurities.

[0041] exist Fig.9A and 9B In the embodiment, a gate spacer 86 is formed on the gate sealing isolation 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, etc.

[0042] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, steps in a different order may be used (e.g., the gate sealing spacer 80 may not be etched before the gate spacer 86 is formed, thereby producing an "L-shaped" gate sealing spacer), spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type and p-type devices. For example, the LDD region of an n-type device may be formed before the gate sealing spacer 80 is formed, and the LDD region of a p-type device may be formed after the gate sealing spacer 80 is formed.

[0043] exist Fig. 10A and Fig. 10B In accordance with some embodiments, epitaxial source / drain regions 82 are formed in the fins 52. In some cases, the epitaxial source / drain regions 82 may be formed to apply stress in the respective channel regions 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fins 52 such that each dummy gate 72 is disposed between respective adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend to the fins 52 and may also pass through the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the gate of the resulting FinFET that is subsequently formed.

[0044] The epitaxial source / drain regions 82 in the region 50N (e.g., NMOS region) can be formed by masking the region 50P, such as the PMOS region, and etching the source / drain regions of the fin 52 in the region 50N to form a recess in the fin 52. Then, the epitaxial source / drain regions 82 in the region 50N are epitaxially grown in the recess. The epitaxial source / drain regions 82 can include any acceptable material, such as suitable for n-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50N can include a material that applies tensile strain in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 82 in the region 50N can have a surface protruding from the corresponding surface of the fin 52 and can have a small facet.

[0045] The epitaxial source / drain regions 82 in the region 50P (e.g., a PMOS region) can be formed by masking the region 50N, such as an NMOS region, and etching the source / drain regions of the fin 52 in the region 50P to form a recess in the fin 52. Then, the epitaxial source / drain regions 82 in the region 50P are epitaxially grown in the recess. The epitaxial source / drain regions 82 can include any acceptable material, such as suitable for a p-type FinFET. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the region 50P can include a material that applies compressive strain in the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium tin, etc. The epitaxial source / drain regions 82 in the region 50P can also have a surface protruding from the corresponding surface of the fin 52 and can have a small facet.

[0046] The epitaxial source / drain regions 82 and / or the fins 52 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions followed by annealing. The impurity concentration of the source / drain regions may be about 10 19 cm -3 With about 10 21 cm -3 The n-type and / or p-type impurities of the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 may be doped in-situ during growth.

[0047] Due to the epitaxial process used to form epitaxial source / drain regions 82 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of fin 52. In some embodiments, these facets merge adjacent source / drain regions 82 of the same FinFET, such as Fig. 10C In other embodiments, as shown in Fig. 10DAs shown, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated. Fig. 10C and 10D In the illustrated embodiment, gate spacers 86 are formed covering a portion of the sidewalls of fin 52 that extend over STI regions 56, thereby preventing epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 86 can be adjusted to remove spacer material, thereby allowing the region of epitaxial growth to extend to the surface of STI regions 56.

[0048] exist Fig.11A and 11B In some embodiments, a first interlayer dielectric (ILD) 88 is deposited on Fig. 10A and 10B . The first ILD 88 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD) or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain region 82, the mask 74, and the gate spacer 86. The CESL 87 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., and may have an etching rate different from that of the material of the first ILD 88 above. In some embodiments, a CESL 87 having a thickness between about 2 nm and about 5 nm (e.g., about 3 mm) may be formed. In some cases, controlling the thickness of CESL 87 can control the size (eg, width or height) of source / drain contacts 118 and / or the size (eg, width or height) of subsequently formed air gaps 120 (see Fig.26 ).

[0049] exist Fig. 12A and 12B In the process of planarizing, a planarization process such as CMP may be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, and portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, the gate sealing spacer 80, the gate spacer 86, and the first ILD 88 are level. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may remain, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0050] exist Fig.13A and 13B In one embodiment, the dummy gate 72 and the mask 74 (if present) are removed in one or more etching steps, so that a recess 90 is formed. Portions of the dummy dielectric layer 60 in the recess 80 may also be removed. In some embodiments, only the dummy gate 72 is removed, and the dummy dielectric layer 60 remains and is exposed by the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and remains in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etches the dummy gate 72 without etching the first ILD 88, the gate spacer 86, or the CESL 87. Each recess 90 exposes and / or covers the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs 82 of epitaxial source / drain regions. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be optionally removed after the dummy gate 72 is removed.

[0051] exist Fig.14A and 14B In the embodiment, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Fig. 14C Shows Fig. 14B Detailed view of region 89 of . A gate dielectric layer 92 is conformally deposited in the recess 90, for example on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate seal spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. According to some embodiments, the gate dielectric layer 92 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 92 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy gate dielectric 60 remains in the recess 90, the gate dielectric layer 92 includes the material of the dummy gate dielectric 60 (e.g., silicon oxide).

[0052] The gate electrodes 94 are deposited on the gate dielectric layer 92 and fill the remaining portion of the recess 90. The gate electrodes 94 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig. 14B A single-layer gate electrode 94 is shown in FIG. 1 , but the gate electrode 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler materials 94C, such as Fig. 14C As shown. After filling the recess 90, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 92 and the material of the gate electrode 94, which are above the top surface of the ILD 88. The remaining portions of the gate electrode 94 and the material of the gate dielectric layer 92 thus form a replacement gate for the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 may be collectively referred to as a "gate stack". The gate and the gate stack may extend along the sidewalls of the channel region 58 of the fin 52.

[0053] The formation of gate dielectric layer 92 in region 50N and region 50P may occur simultaneously, such that gate dielectric layer 92 in each region is formed of the same material, and the formation of gate electrode 94 may occur simultaneously, such that gate electrode 94 in each region is formed of the same material. In some embodiments, gate dielectric layer 92 in each region may be formed by a different process, such that gate dielectric layer 92 may be a different material, and / or gate electrode 94 in each region may be formed by a different process, such that gate electrode 94 may be a different material. When different processes are used, various masking steps may be used to mask and expose appropriate regions.

[0054] exist Fig.15A and 15B In some embodiments, the second ILD 108 is deposited on the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, silicon oxide, etc., and can be deposited by any suitable method such as CVD, PECVD, etc. A planarization process such as CMP can be performed to planarize the surface of the second ILD 108. In some embodiments, the second ILD 108 can be formed to have a thickness between about 10nm and about 30nm, for example, about 15nm. Controlling the thickness and width of the second ILD 108 can also control the size of the expansion area 130 of the sealed air gap 120, as described below. Fig.26 describe.

[0055] According to some embodiments, before depositing the second ILD 108, a hard mask 96 is deposited over the structure. The hard mask 96 may include one or more dielectric material layers, such as silicon nitride, silicon oxynitride, etc., and may have a different etch rate than the material of the second ILD 108 above. In some embodiments, the hard mask 96 may be formed to have a thickness of about 2 nm to about 4 nm, such as about 3 nm. In some embodiments, the hard mask 96 is formed of the same material as the CESL 87, or is formed to have about the same thickness as the CESL 87. The subsequently formed source / drain contacts 118 (see Fig.26 ) through the hard mask 96 and the CESL 87 to contact the top surface of the epitaxial source / drain region 82, the gate contact 132 (see Fig.31A and 31B ) passes through the hard mask 96 to contact the top surface of the gate electrode 94.

[0056] Figures 16 to 26 The formation of source / drain contacts 118 with air gaps 120 is shown in accordance with some embodiments (see Fig.26 ). The source / drain contacts 118 physically and electrically contact the epitaxial source / drain regions 82. The source / drain contacts 118 may also be referred to as “contacts 118” or “contact plugs 118”. For clarity, Figures 16 to 24 is shown as Fig. 15B Detailed view of area 111. Fig.16 Shows Fig. 15B The same structure is shown in region 111.

[0057] exist Fig.17 In accordance with some embodiments, an opening 110 is formed in the first ILD 88 and the second ILD 108 to expose the epitaxial source / drain region 82. The opening 110 may be formed using appropriate photolithography and etching techniques. For example, a photoresist (e.g., a single-layer or multi-layer photoresist structure) may be formed over the second ILD 108. The photoresist may then be patterned to expose the second ILD 108 in an area corresponding to the opening 110. Then, using the patterned photoresist as an etching mask, an appropriate etching process may be performed to etch the opening 110. The one or more etching processes may include a wet etching process and / or a dry etching process. In some embodiments, when forming the opening 110, the CESL 87 and / or the hard mask 96 may be used as an etching stop layer. As shown in FIG. Fig.17As shown, the portion of CESL 87 that extends above epitaxial source / drain regions 82 may also be removed. In some embodiments, opening 110 may extend below the top surface of epitaxial source / drain regions 82 and into epitaxial source / drain regions 82. In some embodiments, one or more etching processes may remove material of first ILD 88 to expose CESL 87. Opening 110 may have a thickness such as Fig.17 10. In some embodiments, opening 110 may have a width W1 between about 10 nm and about 30 nm. Width W1 may be measured across the top of opening 110, across the bottom of opening 110, or across any other location of opening 110. In some cases, controlling width W1 may control the size of source / drain contacts 118 and / or the size of subsequently formed air gaps 120 (see FIG. 10A ). Fig.26 ).

[0058] exist Fig.18 In some embodiments, a dummy spacer layer 112 is formed over the opening 110. In some embodiments, the dummy spacer layer 112 may be formed as a capping layer that extends over the second ILD 108, the CESL 87, and the epitaxial source / drain regions 82. The dummy spacer layer 112 may include a material such as silicon, polysilicon, amorphous silicon, or the like, or a combination thereof. In some embodiments, the dummy spacer layer 112 is a material that may be etched with high selectivity relative to other layers such as the second ILD 108, the CESL 87, or the contact spacer layer 114 (described below). The dummy spacer layer 112 may be deposited by PVD, CVD, ALD, or the like. In some embodiments, the dummy spacer layer 112 may be formed to have a thickness between about 3 nm and about 9 nm, for example, about 6 nm. In some embodiments, the thickness of the dummy spacer layer 112 is approximately equal to the width W2 of the subsequently formed air gap 120 (see Fig.21 ).

[0059] exist Fig.19 In some embodiments, a contact spacer layer 114 is formed on the dummy spacer layer 112. Before forming the contact spacer layer 114, a suitable anisotropic dry etching process may be performed to remove regions of the dummy spacer layer 112 that extend laterally over the second ILD 108 and the epitaxial source / drain regions 82. Due to the anisotropy of the dry etching process, regions of the dummy spacer layer 112 that extend along the sidewalls of the opening 110 remain. In some embodiments, the anisotropic dry etching process may also etch material of the epitaxial source / drain regions 82 and thus extend the opening 110 further into the epitaxial source / drain regions 82.

[0060] In some embodiments, the contact isolation layer 114 may be formed as a blanket layer extending over the second ILD 108, the dummy spacer layer 112, and the epitaxial source / drain regions 82. The contact spacer layer 114 may include one or more material layers, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof. The contact spacer layer 114 may be deposited by PVD, CVD, ALD, etc. In some embodiments, the contact spacer layer 114 may be formed to have a thickness between about 2 nm and about 5 nm, such as about 3 nm. After forming the contact spacer layer 114, a suitable anisotropic dry etching process may be performed to remove the region of the contact spacer layer 114 extending laterally over the second ILD 108, the dummy spacer layer 112, and the epitaxial source / drain regions 82. Due to the anisotropy of the dry etching process, the region of the contact spacer layer 114 extending along the sidewall of the opening 110 (e.g., extending along the dummy spacer layer 112) remains. In some cases, controlling the thickness of the contact spacer layer 114 can control the size of the source / logic contact 118 and / or the size of the subsequently formed air gap 120 (see Fig.26 ).

[0061] Steering Fig. 20 According to some embodiments, one or more conductive materials are deposited in the opening 110 to form a source / drain contact 118. In some embodiments, the conductive material 118 of the source / drain contact includes a liner (not shown separately) conformally deposited on the surface of the opening 110 (e.g., on the contact spacer layer 114), and a conductive filling material deposited on the liner to fill the opening 110. In some embodiments, the liner includes titanium, cobalt, nickel, titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, etc. or a combination thereof. In some embodiments, the conductive filling material includes cobalt, tungsten, copper, aluminum, gold, silver, alloys thereof, etc., or a combination thereof. The liner or conductive filling material can be deposited using one or more suitable processes (such as CVD, PVD, ALD, sputtering, plating, etc.).

[0062] In some embodiments, silicide regions 116 may also be formed on the upper portion of the epitaxial source / drain regions 82 to improve the electrical connection between the epitaxial source / drain regions 82 and the source / drain contacts 118. The silicide regions 116 may be formed by reacting the upper portion of the epitaxial source / drain regions 82 with the liner. In some embodiments, a separate material may be deposited on the epitaxial source / drain regions 82 to react with the epitaxial source / drain regions 82 to form the silicide regions 116. The silicide regions 116 may include titanium silicide, nickel silicide, etc., or a combination thereof. In some embodiments, one or more annealing processes are performed to promote the silicide formation reaction. After depositing the conductive fill material for the source / drain contacts 118, excess material may be removed by using a planarization process such as CMP to form a top surface of the source / drain contacts 118 coplanar with the top surface of the second ILD 108.

[0063] Steering Fig.21 , according to some embodiments, the material of the dummy spacer layer 112 is removed to form the air gap 120. The material of the dummy spacer layer 112 may be removed using a suitable etching process (e.g., a dry etching process). The etching process may be selective to the material of the dummy spacer layer 112 over the material of the second ILD 108, the CESL 87, or the contact spacer layer 114. For example, in an embodiment where the dummy spacer layer 112 includes silicon and the contact spacer layer 114 includes silicon nitride, the etching process may include using HBr, O2, He, CH3F, H2, etc., or a combination thereof as a process gas in a plasma etching process that selectively etches the silicon of the dummy spacer layer 112. Other materials or etching processes are also possible.

[0064] In some embodiments, the air gap 120 can be formed to have a width W2 between about 0.5 nm and about 4 nm, such as about 2.5 nm. In some cases, forming the air gap 120 with a larger width W2 can result in reduced capacitance and improved device performance, which will be described in more detail below. The air gap 120 can have a substantially uniform width, or the width can vary along its vertical length (e.g., the length extending away from the substrate 50). For example, the width of the air gap 120 can be smaller near the bottom (e.g., near the epitaxial source / drain region 82) than near the top (e.g., near the second ILD 108). In some embodiments, the bottom of the air gap 120 can extend into the epitaxial source / drain region 82 (e.g., near the epitaxial source / drain region 82). Fig.21 ), or the air gap 120 may have a bottom at or above the top surface of the epitaxial source / drain. The air gap 120 may extend at an angle relative to the vertical axis, such as Fig.21 as shown, or may extend substantially along a vertical axis.

[0065] In some cases, the capacitance between the source / drain contact 118 and the gate stack 92 / 94 can be reduced by forming an air gap 120 between the source / drain contact 118 and the gate stack 92 / 94. The capacitance can be reduced in this manner because the dielectric constant (k value) of air is lower, approximately k=1, relative to other spacer materials such as silicon oxide, silicon nitride, etc. By reducing the capacitance using the air gap 120, the FinFET device can have faster response speed and improved performance at faster frequency operation.

[0066] Go to Fig. 22 , a capping layer 122 is formed over the second ILD 108, the source / drain contacts 118, and the air gap 120. The capping layer 122 may be formed as a masking layer extending over the entire air gap 120, such that the air gap 120 is closed. In some embodiments, some material of the capping layer 122 may partially extend into the air gap 120 (e.g., Fig. 22 ), but in other embodiments, the air gap 120 remains free of the material of the capping layer 122. In this way, the air gap 120 is not filled with the capping layer 122, but is surrounded by air in a closed area adjacent to the source / drain contact 118. In some embodiments, the capping layer 122 is subsequently used as an etch stop layer for forming a conductive feature 136 on the source / drain contact 118, as shown below Fig.32A and 32B Described in .

[0067] The capping layer 122 may include one or more material layers, such as silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride, etc., or a combination thereof. The capping layer 122 may be deposited by PVD, CVD, ALD, etc. In some embodiments, the capping layer 122 may be formed to have a thickness between about 6 nm and about 16 nm, such as about 11 nm. In some cases, a thicker capping layer 122 may reduce the vertical expansion of the second ILD 108 during the implantation process 124, as follows Fig.23 In some cases, the implantation depth of the implanted dopant can be controlled by controlling the thickness of the capping layer, as follows Fig.23 As described in.

[0068] exist Fig.23In some embodiments, an implantation process 124 is performed through the capping layer 122 to implant the second ILD 108 with a dopant to seal the air gap 120. In some embodiments, the implanted dopant increases the volume of the implanted region 126 of the second ILD 108 relative to the non-implanted region of the second ILD 108. The air gap 120 provides a volume in which the adjacent implanted region 126 can expand. The portion of the implanted region 126 that has expanded into the air gap 120 is referred to herein as the expansion region 130. In some embodiments, the implantation process 124 can be controlled so that the expansion region 130 extends completely over the entire width of the air gap 120. The air gap 120 is thereby sealed. For example, the dose, implantation depth, dopant type, angle, implantation energy, or other characteristics of the implantation process 124 can be controlled to control the expansion of the implanted region 126, which will be described in more detail below. The upper region of the air gap 120 can be bounded by the expansion region 130, and / or the lower region of the air gap 120 can be bounded by the source / drain region 82.

[0069] By forming the extended region 130 in this manner to seal the air gap 120, subsequently deposited materials may be prevented from entering the air gap 120. In some cases, the entry of subsequently deposited materials into the air gap 120 may cause process defects or device failure. For example, the capping layer 122 may be subsequently etched and a conductive material may be deposited to form the conductive feature 136 (see Fig.32B ), and the extension region 130 prevents conductive material from being deposited within the air gap 120 and possibly causing an electrical short. Additionally, in some cases, the material of the second ILD 108 may be silicon oxide having a lower k value than other materials, such as silicon nitride, which may be used to seal the air gap 120. In this way, sealing the air gap 120 with the material of the second ILD 108 may reduce capacitance relative to sealing the air gap 120 with another material.

[0070] In some embodiments, the dopant species implanted by the implantation process 124 includes Ge, Ar, Xe, Si, etc., or a combination thereof. In some embodiments, the implanted dopant is an atomic species having a larger atomic radius than silicon. For example, when implanted into the second ILD 108 including silicon, the larger size of the implanted dopant can cause the volume of the implantation region 126 of the second ILD 108 to increase, thereby forming the extension region 130. In some embodiments, the implantation process 124 includes implanting the dopant at an angle of about 0 degrees to about 60 degrees from the vertical axis. In some cases, depending on the application or device geometry, it may be beneficial to control the implantation angle. For example, the implantation process 124 may be performed at a certain angle to reduce the spreading effect. In some embodiments, the implantation dose of the dopant may be about 10 14 Atom / cm 2 to about 10 16Atom / cm 2 In some embodiments, the 22 cm -3 (For example, at about 10 19 cm -3 With about 10 22 cm -3 Increasing the implanted dose or increasing the concentration of the dopant within the implanted region 126 may increase the extension of the implanted region 126. In some embodiments, the implantation temperature is in the range of about -100°C to about 450°C.

[0071] Still refer to Fig.23 , the implantation depth D1 indicates the depth at which the dopant concentration in the second ILD 108 is the maximum, measured from the top of the second ILD 108. In some embodiments, the implantation depth D1 may be between about 0 nm and about 20 nm, for example, about 5 nm. In some cases, the implantation depth D1 corresponds approximately to the location of the implantation region 126 having the maximum amount of expansion. Therefore, by controlling the implantation depth D1, the location of the expansion region 130 may be controlled. It has been observed that the implantation depth D1 above the second ILD 108 may result in an incomplete sealing of the air gap 120. It has been observed that an implantation depth D1 greater than about 10 nm may result in a larger dopant region 128, which will be described in detail below. In some embodiments, the implantation depth D1 may be determined by the parameters of the implantation process 124 and the thickness of the capping layer 122. For example, the implantation depth D1 may be increased by increasing the implantation energy. In some embodiments, the dopant is implanted at an implantation energy of about 2 keV to about 30 keV (e.g., about 20 keV). As another example, by increasing the thickness of the capping layer 122 , dopants must travel a longer distance through the capping layer 122 before reaching the second ILD 108 , thus reducing the implant depth D1 . In this way, the implant depth D1 may be controlled by controlling the implant energy and / or the thickness of the capping layer 122 .

[0072] Go to Fig.24, shows an example dopant concentration profile 200 according to some embodiments. Profile 200 shows experimental data of implanted dopant concentration measured from the surface of cap layer 122. Curve 202A shows a first concentration curve resulting from a first implant dose, and curve 202B shows a second concentration curve resulting from a second implant dose greater than the first implant dose. Curves 202A and 202B both correspond to implants having approximately the same implant energy. Curve 202B corresponding to the second implant dose shows curve 202A having a greater dopant concentration within the second ILD 108 than curve 202A corresponding to the first implant dose. As shown in profile 200, the maximum concentration of implanted dopants is at an implant depth D1 in the second ILD 108. For profile 200, the implant depth D1 is approximately 5 nm, although the implant depth D1 may be different in other cases. Because curves 202A and 202B correspond to implants having approximately the same implant energy, the implant depth D1 is approximately the same for curves 202A and 202B.

[0073] In some embodiments, before performing the implantation process 124, a capping layer 122 is formed over the second ILD 108 to promote lateral expansion of the implantation region 126 and inhibit vertical expansion of the implantation region 126. For example, the presence of the capping layer 122 over the second ILD 108 can prevent the second ILD 108 from expanding in the vertical direction. In this way, the expansion of the second ILD 108 can be limited to lateral expansion toward the air gap 120. By forming the capping layer 122 before the implantation process 124 to promote the lateral expansion of the ILD 108, the expansion region 130 can be formed more uniformly and more completely seal the air gap 120. In addition, the air gap 120 can be sealed by the expansion region 130 using an implantation process 124 with a smaller implantation dose, which can reduce implantation damage.

[0074] In some cases, the capping layer 122 can reduce the vertical expansion of the second ILD 108. For example, Fig.25 1 shows experimental data 300 of the measured thickness of the second ILD 108 having the overlying cap layer 122. The data 300 shows the thickness of the second ILD before and after the implantation process 124 is performed. The points indicated at "Ref" represent the thickness of the second ILD 108 before the implantation process 124, and the remaining points represent the thickness of the second ILD 108 after the implantation process 124. Fig.25As shown, the overlying capping layer 122 may cause little or no vertical expansion of the second ILD 108, and the thickness of the second ILD 108 may remain substantially uniform. In this way, the use of the capping layer 122 may allow for a flatter top surface of the second ILD 108 and / or the capping layer 122 after the implantation process 124 is performed. A flatter second ILD 108 or capping layer 122 may improve uniformity and alignment of subsequent processing steps. In some embodiments, a thicker capping layer 122 may suppress more vertical expansion than a thinner capping layer 122. In some embodiments, a thinner capping layer 122 (e.g., less than about 6 nm) may partially suppress vertical expansion such that the vertical expansion is less than without the capping layer 122. Fig.28 and 29 An embodiment is described in which the cover layer 122 does not exist.

[0075] In some embodiments, the implantation process 124 may be controlled to control the size of the implanted region 126 and, therefore, the size of the extension region 130. For example, Fig.26 An embodiment is shown in which the extension region 130 extends along the length L1 of the air gap 120 that is approximately equal to the thickness of the second ILD 108. In some embodiments, dopants are implanted throughout the thickness of the second ILD 108, and all of the second ILD 108 exposed to the air gap 120 is extended into the air gap 120 as the extension region 130. In this manner, the thickness of the second ILD 108 can determine the length L1 of the extension region 130. In some embodiments, the length L1 of the extension region 130 can be between about 10% and about 105% of the thickness of the second ILD 108, depending on the thickness of the ILD 108 and the implantation conditions. In some embodiments, the implantation depth D1 can determine the length L1 of the extension region 130, because a larger implantation depth D1 can form an extension region 130 with a larger L1. By controlling the size of the extension region 130, the vertical length (e.g., the distance between the top and the bottom) of the air gap 120 can also be controlled. In some embodiments, the vertical length of the air gap 120 can be between about 12 nm and about 25 nm, for example, about 16 nm.

[0076] Fig.27A and 27B An embodiment is shown in which a two-step implantation process 124A-B is used to form the extension region 130. See above Fig.23 and 26In some cases, some of the dopants implanted during implant process 124 migrate through air gap 120 and into dopant region 128 near the bottom of air gap 120. In some cases, dopant region 128 can be located near channel region 58 of fin 52. In some cases, dopants within dopant region 128 can cause an increase in channel resistance or can cause other undesirable effects (e.g., implant damage). Fig.27A and 27B The two-step implantation process 124A-B shown can reduce the amount of dopant that migrates into the air gap 120, thereby reducing the size or dopant concentration of the dopant region 128. In some cases, the two-step implantation process 124A-B can prevent the dopant from forming the dopant region 128. In some embodiments, the two-step implantation process 124A-B includes a first implantation process 124A and a second implantation process 124B, the first implantation process 124A includes a relatively small implantation energy or dose, and the second implantation process 124B includes a relatively large implantation energy or dose. In some embodiments, the implantation angle, dopant type, temperature or other parameters of the first implantation process 124A can be different from the implantation angle, dopant type, temperature or other parameters of the second implantation process 124B.

[0077] Go to Fig.27A , similar to Fig.23 , a first implantation process 124A is performed after forming the capping layer 122. In some embodiments, the first implantation process 124A uses a relatively small first implantation energy, so the first implantation depth D2 is relatively shallow. For example, the first implantation depth D2 may be between about 0 nm (e.g., at or near the top of the second ILD 108) and about 5 nm, such as about 1 nm. Fig.27A As shown, the first implantation process 124A forms a first extended region 130A that seals the air gap 120. The first extended region 130A prevents the dopant implanted by the second implantation process 124B from migrating into the air gap 120. Due to the lower first implantation energy, less dopant enters the air gap 120, so the dopant region 128 is smaller and / or has a lower dopant concentration. For example, the dopant region 128 formed by the first implantation process 124A can be smaller than the dopant region 128 formed by the second implantation process 124B. Fig.23 or Fig.26 The dopant regions are formed by the implantation process 124 described in .

[0078] Go to Fig.27B , the second implantation process 124B is performed after the first implantation process 124A. In some embodiments, the second implantation process 124B uses a relatively large second implantation energy, so the second implantation depth D3 is greater than the first implantation depth D2. For example, the second implantation depth D3 may be between about 1 nm and about 10 nm, such as about 5 nm. Fig.27BAs shown, the second implantation process 124B increases the size of the first extension region 130A to form the second extension region 130B that further seals the air gap 120. The second extension region 130B is larger than the first extension region 130A and seals the air gap 120 more completely than the first extension region 130A. Due to the presence of the first extension region 130A, the dopant implanted by the second implantation process 124B is prevented from migrating into the air gap 120. Therefore, the dopant from the second implantation process 124B is prevented from reaching the dopant region 128. In this case, the dopant region 128 formed by the total two-step implantation process 124A-B can be smaller than the dopant region 128 formed by the above two-step implantation process 124A-B. Fig.23 or Fig.26 In this manner, undesirable effects due to the dopant region 128 may be reduced or eliminated by using the two-step implantation process 124A-B as described herein.

[0079] Go to Fig.28 and 29 , shows an embodiment in which the implantation process 124 is performed before forming the capping layer 122. Fig.28 As shown, the implantation process 124 expands the second ILD 108 in both the horizontal and vertical directions without being constrained by the vertical expansion provided by the capping layer 122. In addition to the lateral expansion forming the expansion region 130, the vertical expansion also results in an increase in the thickness of the second ILD 108. In some embodiments, the thickness of the second ILD 108 can be increased by a distance D4, which is between about 0.5 nm and about 3 nm. For example, Fig.29 Experimental data 400 showing the measured thickness of the second ILD 108 without the capping layer 122 is shown. The data 400 shows the thickness of the second ILD before and after the implantation process 124 is performed. The points indicated at "Ref" show the thickness of the second ILD 108 before the implantation process 124, and the remaining points show the thickness of the second ILD 108 after the implantation process 124 using two different implantation doses. Fig.29 As shown, the thickness of the second ILD 108 increases due to the vertical expansion without the capping layer 122. The data 400 also shows that a higher implant dose may cause a greater vertical expansion of the second ILD 108.

[0080] Figures 30A to 32B is a cross-sectional view of an additional stage in fabricating a FinFET according to some embodiments. Figures 30A to 32B Shows Fig.14A and 14B Same cross-sectional view of the structure shown. Fig. 30A and 30BThe structure after forming the extension region 130 is shown, for example, Fig.26 After the implantation process 124 described in Fig.27A and 27B After the two-step implantation process 124A-B described in .

[0081] exist Fig.31A and 31B In the embodiment of the present invention, a gate contact 132 is formed by the capping layer 122, the second ILD 108 and the hard mask 96. An opening of the gate contact 132 may be first formed by the capping layer 122, the second ILD 108 and the hard mask 96. The opening may be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc., or a combination thereof. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc., or a combination thereof. A planarization process such as CMP may be performed to remove excess material from the surface of the capping layer 122. The remaining liner and conductive material form the gate contact 132 in the opening. The gate contact 132 is physically and electrically coupled to the gate electrode 94. The source / drain contact 118 and the gate contact 132 may be formed in different processes, or may be formed in the same process. Although shown as being formed with the same cross-section, it is understood that each of the source / drain contacts 118 and the gate contact 132 may be formed with different cross-sections, which may avoid shorting of the contacts.

[0082] exist Fig.32A and 32B In some embodiments, conductive features 136 are formed to contact source / drain contacts 118. Conductive features 136 may include one or more metal lines and / or vias that make physical and electrical contact with source / drain contacts 118. In some embodiments, some conductive features 136 may also be formed that contact gate contact 132 (at Fig.32A and 32B 1 . The conductive feature 136 may be, for example, a redistribution layer. The conductive feature 136 may be formed using any suitable technique.

[0083] In some embodiments, a dielectric layer 134 may be first formed over the capping layer 122, and a conductive feature 136 may be formed within the dielectric layer 134. The dielectric layer 134 may be formed of a dielectric material (such as a low-k dielectric material), a polymer (e.g., polyimide), silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, etc., or a combination thereof. The dielectric layer 134 may be formed using a suitable process such as spin coating, CVD, PVD, ALD, etc. An opening for the conductive feature 136 (not shown) may then be formed through the dielectric layer 134 and the capping layer 122 to expose the source / drain contact 118. The opening may be formed using acceptable photolithography and etching techniques. In some cases, sealing the air gap 120 using the extension region 130 may prevent the air gap 120 from being exposed when the opening is formed. For example, due to, for example, photolithography misalignment, the opening may be formed to extend over the air gap 120. In this manner, subsequently deposited materials are prevented from entering the air gap 120.

[0084] In some embodiments, the material of the conductive feature 136 may be formed using a single and / or dual metal damascene process, a via first process, or a metal first process. A liner such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc., which may be formed using a deposition process such as CVD, ALD, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc., or a combination thereof. The conductive material may be formed on top of the diffusion barrier layer in the opening by an electrochemical plating process, CVD, ALD, PVD, etc., or a combination thereof. The material of the liner and / or the conductive material is blocked from entering the air gap 120 by the extension region 130. A planarization process such as CMP may be performed to remove excess material from the surface of the dielectric layer 134. The remaining liner and conductive material form a conductive feature 136. In other embodiments, other techniques may be used to form the conductive feature 136.

[0085] Fig.33A and 33B The formation of the conductive features 136 is shown for embodiments where the implant process 124 is performed prior to forming the capping layer 124 . Fig.33A -B is similar to the embodiment shown in the previous embodiment Fig.28 and 29 The embodiments described. Fig.33A As shown in FIG. 1-B, the implant process 124 increases the thickness of the second ILD 108 without being constrained by the vertical extension provided by the capping layer 122. The planarity of the second ILD 108 may also be reduced. The conductive feature 136 is formed to contact the source / drain contacts 118 and may be similar to the above for Fig.32A -B describes the conductive characteristics.

[0086] Embodiments can achieve advantages. By forming an air gap between the source / drain contacts and the gate stack of a FinFET device, the capacitance between the source / drain contacts and the gate stack can be reduced. Reducing this capacitance can increase the speed or high-frequency operation of the FinFET device. In addition, the top of the air gap is sealed by injecting an interlayer dielectric layer (ILD) with a dopant. The injected dopant causes the ILD to expand and extend through the air gap, thereby sealing the air gap. By sealing the air gap, unwanted materials can be prevented from entering the air gap and reducing device performance or causing process defects. In some cases, the use of two separate implantation steps can reduce the amount of dopants implanted near the channel region of the FinFET device. In addition, by forming a capping layer before injecting the dopant, the vertical expansion of the ILD can be suppressed, resulting in a more uniform top surface.

[0087] In some embodiments, a device includes: a fin extending from a semiconductor substrate; a gate stack on the fin; a first spacer on a sidewall of the gate stack; a source / drain region in the fin adjacent to the first spacer; an interlayer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source / drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source / drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends through the air gap and is in physical contact with the second spacer, wherein the first portion of the ILD seals the air gap. In an embodiment, the ILD has a first thickness, and wherein the first portion of the ILD has a second thickness, the second thickness being between 10% and 105% of the first thickness. In an embodiment, the device includes an etch stop layer on the gate stack and on the first spacer, wherein a portion of the etch stop layer is exposed to the air gap. In an embodiment, wherein the first portion of the ILD has a first concentration of dopant, and wherein the second portion of the ILD has a second concentration of dopant, the second concentration being less than the first concentration. In an embodiment, the dopant comprises Ge, Ar, Si, or Xe. In an embodiment, the second spacer extends closer to the semiconductor substrate than the air gap. In an embodiment, the contact plug extends closer to the semiconductor substrate than the air gap. In an embodiment, the second spacer comprises silicon nitride. In an embodiment, the device comprises a capping layer on the ILD. In an embodiment, a first region of the capping layer on the first portion of the ILD extends closer to the semiconductor substrate than a second region of the capping layer on the second portion of the ILD.

[0088] In some embodiments, a semiconductor device includes: a fin protruding from a substrate; a gate structure over a channel region of the fin; an epitaxial region in the fin adjacent to the channel region; a first dielectric layer over the gate structure, the first dielectric layer including a first region doped with a first dopant; a contact plug extending through the first dielectric layer and contacting the epitaxial region; a second dielectric layer over the first dielectric layer; and an air gap between the contact plug and the gate structure, wherein an upper region of the air gap is defined by the first region, and wherein the air gap is separated from the second dielectric layer by the first region. In an embodiment, a lower region of the air gap is defined by the epitaxial region. In an embodiment, a region in the epitaxial region adjacent to the air gap is doped with the first dopant. In an embodiment, a maximum concentration of the first dopant in the first region is between 1 nm and 5 nm below a top surface of the first dielectric layer. In an embodiment, a concentration of the first dopant in the first region is between 10 19 cm -3 and 10 22 cm -3 In an embodiment, a portion of the second dielectric layer protrudes into the first region.

[0089] In some embodiments, a method includes: forming a gate stack above a semiconductor fin; forming an epitaxial source / drain region in the semiconductor fin adjacent to the gate stack; depositing a first dielectric layer above the gate stack and above the epitaxial source / drain region; forming an opening in the first dielectric layer to expose the epitaxial source / drain region; depositing a sacrificial material in the opening; depositing a conductive material over the sacrificial material in the opening; removing the sacrificial material to form a recess; and implanting the first dielectric layer with a dopant, wherein after implanting the first dielectric layer, the recess is covered by the first dielectric layer. In an embodiment, the sacrificial material is silicon. In an embodiment, the method includes depositing a second dielectric layer on the sacrificial material in the opening. In an embodiment, the method includes depositing a third dielectric layer over the first dielectric layer before implanting the first dielectric layer.

[0090] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0091] Example 1. A semiconductor device comprising: a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source / drain region adjacent to the first spacer in the fin; an interlayer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source / drain region, the ILD comprising a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source / drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends through the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

[0092] Example 2. The device of Example 1, wherein the ILD has a first thickness, and wherein the first portion of the ILD has a second thickness between 10% and 105% of the first thickness.

[0093] Example 3. The device of Example 1, further comprising an etch stop layer on the gate stack and on the first spacer, wherein a portion of the etch stop layer is exposed to the air gap.

[0094] Example 4. The device of Example 1, wherein the first portion of the ILD has a first concentration of a dopant, and wherein the second portion of the ILD has a second concentration of a dopant, the second concentration being less than the first concentration.

[0095] Example 5. The device of Example 4, wherein the dopant comprises Ge, Ar, Si, or Xe.

[0096] Example 6. The device of Example 1, wherein the second spacer extends closer to the semiconductor substrate than the air gap.

[0097] Example 7. The device of Example 1, wherein the contact plug extends closer to the semiconductor substrate than the air gap.

[0098] Example 8. The device of Example 1, wherein the second spacer comprises silicon nitride.

[0099] Example 9. The device of Example 1, further comprising a capping layer on the ILD.

[0100] Example 10. The device of Example 9, wherein a first region of the capping layer on the first portion of the ILD extends closer to the semiconductor substrate than a second region of the capping layer on the second portion of the ILD.

[0101] Example 11. A semiconductor device comprising: a fin protruding from a substrate; a gate structure above a channel region of the fin; an epitaxial region adjacent to the channel region in the fin; a first dielectric layer above the gate structure, the first dielectric layer comprising a first region doped with a first dopant; a contact plug extending through the first dielectric layer and contacting the epitaxial region; a second dielectric layer above the first dielectric layer; and an air gap between the contact plug and the gate structure, wherein an upper region of the air gap is defined by the first region, and wherein the air gap is separated from the second dielectric layer by the first region.

[0102] Example 12. The semiconductor device of Example 11, wherein a lower region of the air gap is defined by the epitaxial region.

[0103] Example 13. The semiconductor device of Example 11, wherein a region of the epitaxial region adjacent to the air gap is doped with the first dopant.

[0104] Example 14. The semiconductor device of Example 11, wherein a maximum concentration of the first dopant within the first region is between 1 nm and 5 nm below a top surface of the first dielectric layer.

[0105] Example 15. The semiconductor device according to Example 11, wherein the first region is included in 10 19 cm -3 with 10 22 cm -3 The concentration of the first dopant is between .

[0106] Example 16. The semiconductor device of Example 11, wherein a portion of the second dielectric layer protrudes into the first region.

[0107] Example 17. A method for manufacturing a semiconductor device, comprising: forming a gate stack above a semiconductor fin; forming an epitaxial source / drain region in the semiconductor fin adjacent to the gate stack; depositing a first dielectric layer above the gate stack and above the epitaxial source / drain region; forming an opening in the first dielectric layer to expose the epitaxial source / drain region; depositing a sacrificial material in the opening; depositing a conductive material over the sacrificial material in the opening; removing the sacrificial material to form a groove; and injecting a dopant into the first dielectric layer, wherein, after the first dielectric layer is injected, the groove is covered by the first dielectric layer.

[0108] Example 18. The method of Example 17, wherein the sacrificial material is silicon.

[0109] Example 19. The method of Example 17, further comprising: depositing a second dielectric layer on the sacrificial material within the opening.

[0110] Example 20. The method of Example 17, further comprising depositing a third dielectric layer over the first dielectric layer before implanting the first dielectric layer.

Claims

1. A semiconductor device, comprising: a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source / drain region in the fin adjacent to the first spacer; an interlayer dielectric layer ILD extending over the gate stack, the first spacer, and the source / drain regions, the ILD comprising a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD, wherein the first portion of the ILD has a first concentration of dopants, and wherein the second portion of the ILD has a second concentration of dopants, the second concentration being less than the first concentration; a contact plug extending through the ILD and contacting the source / drain region; a second spacer on a sidewall of the contact plug; and An air gap is between the first spacer and the second spacer, wherein the first portion of the ILD extends through the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

2. The device according to claim 1, wherein The ILD has a first thickness, and wherein the first portion of the ILD has a second thickness between 10% and 105% of the first thickness.

3. The device of claim 1 , further comprising an etch stop layer on the gate stack and on the first spacer, wherein: A portion of the etch stop layer is exposed to the air gap.

4. The device according to claim 1, wherein The dopant includes Ge, Ar, Si or Xe.

5. The device according to any one of claims 1 to 3, wherein: The second spacer extends closer to the semiconductor substrate than the air gap.

6. The device according to any one of claims 1 to 3, wherein: The contact plug extends closer to the semiconductor substrate than the air gap.

7. The device according to claim 1, wherein The second spacer includes silicon nitride.

8. The device according to any one of claims 1 to 3, further comprising a capping layer on the ILD.

9. The device according to claim 8, wherein A first region of the capping layer on the first portion of the ILD extends closer to the semiconductor substrate than a second region of the capping layer on the second portion of the ILD.

10. A semiconductor device comprising: fins, protruding from the substrate; a gate structure over the channel region of the fin; an epitaxial region adjacent to the channel region in the fin; a first dielectric layer, over the gate structure, the first dielectric layer comprising a first region doped with a first dopant, wherein the first dielectric layer comprises a first portion and a second portion, wherein the second portion of the first dielectric layer is closer to the gate structure than the first portion of the first dielectric layer, wherein the first portion of the first dielectric layer has a first concentration of the first dopant, and wherein the second portion of the first dielectric layer has a second concentration of the first dopant, the second concentration being less than the first concentration; a contact plug extending through the first dielectric layer and contacting the epitaxial region; a second dielectric layer on the first dielectric layer; and An air gap is between the contact plug and the gate structure, wherein an upper region of the air gap is defined by the first region, and wherein the air gap is separated from the second dielectric layer by the first region.

11. The semiconductor device according to claim 10, wherein: A lower region of the air gap is defined by the epitaxial region.

12. The semiconductor device according to claim 10, wherein: A region of the epitaxial region adjacent to the air gap is doped with the first dopant.

13. The semiconductor device according to claim 10, wherein: A maximum concentration of the first dopant in the first region is between 1 nm and 5 nm below a top surface of the first dielectric layer.

14. The semiconductor device according to claim 10, wherein: The first area includes 10 19 cm -3 with 10 22 cm -3 The concentration of the first dopant is between .

15. The semiconductor device according to claim 10, wherein A portion of the second dielectric layer protrudes into the first region.

16. A method for manufacturing a semiconductor device, comprising: forming a gate stack over the semiconductor fin; forming an epitaxial source / drain region in the semiconductor fin adjacent to the gate stack; depositing a first dielectric layer over the gate stack and over the epitaxial source / drain regions; forming an opening in the first dielectric layer to expose the epitaxial source / drain region; depositing a sacrificial material within the opening; depositing a conductive material over the sacrificial material within the opening; removing the sacrificial material to form a recess; as well as The first dielectric layer is injected with a dopant, wherein, after the first dielectric layer is injected, the groove is covered by the first dielectric layer, wherein the first dielectric layer includes a first portion and a second portion, wherein the second portion of the first dielectric layer is closer to the gate stack than the first portion of the first dielectric layer, wherein the first portion of the first dielectric layer has a first concentration of the dopant, and wherein the second portion of the first dielectric layer has a second concentration of the dopant, the second concentration being less than the first concentration.

17. The method according to claim 16, wherein: The sacrificial material is silicon.

18. The method according to claim 16, further comprising: A second dielectric layer is deposited over the sacrificial material within the opening.

19. The method according to claim 16, further comprising: A third dielectric layer is deposited over the first dielectric layer prior to implanting the first dielectric layer.

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