Antifuse devices, antifuse cell structures, and methods of making the same

Abstract

The application provides a kind of antifuse device, antifuse unit structure and its preparation method, belong to semiconductor technical field.Antifuse device includes first doped region, second doped region, first gate dielectric layer and first gate conductive layer, wherein, first gate dielectric layer includes recess filled with conductive material, recess maximum depth in perpendicular to substrate direction is less than the thickness of first gate dielectric layer;First gate conductive layer covers recess and is connected with conductive material in recess.First gate dielectric layer is more easily broken down by high electric field, so as to reduce the voltage applied to antifuse device.For a plurality of antifuse devices, it can be ensured that breakdown voltage and breakdown position are relatively consistent.By adjusting the structure, position and size of each part of antifuse device, the device size can be reduced, and compatibility with other semiconductor processes can also be achieved, simplifying the entire preparation process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to an antifuse device and its fabrication method, as well as to an antifuse unit structure and its fabrication method. Background Technology

[0002] Anti-fuse devices are one-time programmable devices (OTPs) and are widely used in DRAM, NAND and other memory devices.

[0003] An antifuse device is a semiconductor device consisting of two conductive layers and a dielectric layer between them. When unprogrammed, the conductive layers are separated by the dielectric layer, and the antifuse is open-circuited. During programming (with an applied high voltage), the dielectric layer is broken down by the high electric field, forming an electrical connection between the two conductive layers, and the antifuse is short-circuited (melted). This melting process is physically one-time, permanent, and irreversible. The on and off states of the antifuse can represent logic "0" and logic "1," respectively.

[0004] In related technologies, patent US5909049 discloses an antifuse device with N+ and N- regions. The antifuse layer of the antifuse device is entirely located on the N- region, and the antifuse layer is thinner than the gate dielectric layer of the select transistor. This technical solution, by forming the N+ region of the antifuse device, does not affect the performance of the antifuse device but increases its area. However, the oxide layer and the antifuse layer in this solution are made of different materials, making defects more likely to occur at the edge of the antifuse layer due to stress variations, resulting in poor consistency in the breakdown voltage of the antifuse device.

[0005] The antifuse device disclosed in patent US7402855 has a variable thickness gate oxide layer, with the thinner gate oxide layer serving as the breakdown region. The antifuse device has a lightly doped drain (LDD) structure and source / drain regions. This technology utilizes standard CMOS technology to fabricate the antifuse device. However, due to material differences, defects are more likely to occur at the interface between the thin gate oxide layer and the sidewalls, making the antifuse device more susceptible to breakdown at this interface. This results in poor consistency in the breakdown voltage of the antifuse device. Furthermore, the inclusion of source / drain regions in this technology leads to a larger antifuse device area.

[0006] US6130469 discloses an antifuse device in which the thickness of the gate dielectric layer at the corner is difficult to control, resulting in poor consistency of the breakdown voltage.

[0007] US6956258 discloses an antifuse device in which the gate dielectric layer is very thin and uniform in thickness. When voltage is applied to the antifuse gate, the gate dielectric layer will be broken down at the defective or thinnest position. However, the defective or thinnest position of the gate dielectric layer is random, which means that the breakdown position of this technical solution is also random.

[0008] US Patent 8026574B2 discloses an antifuse device with a variable thickness gate oxide. The thin gate oxide is the breakdown region and can be rectangular or triangular. The thick gate oxide has the same thickness as the gate oxide of the select transistor. The antifuse device also has a lightly doped drain region and a channel region. In normal operation (assuming the thin gate oxide layer is not programmed to break down), the thick gate oxide prevents the thin gate oxide from breaking down, and the lightly doped drain region further reduces the risk of the thin gate oxide breaking down. The device corresponding to the thick gate oxide and the lightly doped drain is essentially equivalent to a select transistor.

[0009] Therefore, existing antifuse devices still have certain defects in structure and fabrication, such as excessively high breakdown voltage, poor consistency of breakdown voltage magnitude, large size, and incompatibility with CMOS processes, which affect the performance and mass production of semiconductor devices.

[0010] It should be noted that the information in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0011] The purpose of this invention is to provide an antifuse device and its preparation method, an antifuse unit structure and its preparation method, to solve one or more problems existing in the prior art.

[0012] According to a first aspect of the present invention, an antifuse device is provided, comprising:

[0013] The first doped region is formed on a substrate;

[0014] A second doped region is disposed within the first doped region and has the same doping type as the first doped region, and the doping concentration of the second doped region is greater than that of the first doped region;

[0015] A first gate dielectric layer is at least partially disposed on the first doped region; the first gate dielectric layer includes a groove filled with a conductive material, and the maximum depth of the groove in the direction perpendicular to the substrate is less than the thickness of the first gate dielectric layer.

[0016] A first gate conductive layer is disposed on the first gate dielectric layer, covers the groove, and is connected to the conductive material in the groove.

[0017] In one exemplary embodiment of the present invention, the antifuse device further includes:

[0018] The first well is a deep well and is disposed on the substrate;

[0019] The second well is disposed in the first well, and the second well and the first well have different doping types, and the second well and the first doped region have different doping types;

[0020] The first doped region is located in the second well.

[0021] In an exemplary embodiment of the present invention, the substrate is a P-type substrate, and the first doped region is N-type doped.

[0022] In one exemplary embodiment of the present invention, the number of grooves is multiple.

[0023] In one exemplary embodiment of the present invention, each of the grooves has the same maximum depth in the direction perpendicular to the substrate.

[0024] In an exemplary embodiment of the present invention, the distance from the bottom of the groove to the bottom of the first gate dielectric layer is 2nm to 3nm.

[0025] In an exemplary embodiment of the present invention, the conductive material filled in the groove is polycrystalline silicon, and the polycrystalline silicon has a gap chamber.

[0026] In an exemplary embodiment of the present invention, the antifuse device further includes a sidewall, wherein the projection of the first gate conductive layer on the substrate is located within the projection of the first gate dielectric layer, and the sidewall is disposed on the first gate dielectric layer and covers both sides of the first gate conductive layer.

[0027] In an exemplary embodiment of the present invention, the antifuse device further includes a sidewall, wherein the projections of the first gate dielectric layer and the first gate conductive layer on the substrate completely overlap, and the sidewall simultaneously covers both sides of the first gate dielectric layer and the first gate conductive layer.

[0028] In an exemplary embodiment of the present invention, the antifuse device further includes an isolation region located on the substrate and at least on the side of the first doped region away from the second doped region;

[0029] In this configuration, a portion of the first gate dielectric layer is located on the isolation region, and another portion is located on the first doped region.

[0030] In an exemplary embodiment of the present invention, the projection of the first gate dielectric layer on the substrate is entirely within the projection of the first doped region.

[0031] In an exemplary embodiment of the present invention, the material of the first gate conductive layer is one or more of polycrystalline silicon, titanium nitride, and tungsten.

[0032] In an exemplary embodiment of the present invention, the first gate dielectric layer is silicon dioxide.

[0033] In one exemplary embodiment of the present invention, the antifuse device further includes:

[0034] A barrier layer covers the first gate conductive layer;

[0035] A metal layer covers the barrier layer.

[0036] According to a second aspect of the present invention, an antifuse unit structure is provided, comprising:

[0037] The antifuse device described in any of the above items;

[0038] The selected transistor is disposed on the substrate and includes at least a second gate dielectric layer, a second gate conductive layer, a third doped region, and a fourth doped region; the doping types of the third doped region and the fourth doped region are the same as those of the first doped region, and the doping concentrations of the third doped region and the fourth doped region are greater than those of the first doped region.

[0039] The third doped region is electrically connected to the second doped region.

[0040] In an exemplary embodiment of the present invention, the first gate dielectric layer and the second gate dielectric layer have equal thicknesses and their upper surfaces are flush; and / or, the first gate conductive layer and the second gate conductive layer have equal thicknesses and their upper surfaces are flush.

[0041] In one exemplary embodiment of the present invention, the third doped region and the second doped region share the same doped region.

[0042] In an exemplary embodiment of the present invention, the antifuse device includes a first well and a second well; the first well is a deep well disposed on the substrate; the second well is disposed in the first well and has a different doping type from the first well; wherein the first doped region, the third doped region and the fourth doped region are all disposed in the second well, and the first doped region, the third doped region and the fourth doped region all have a different doping type from the second well.

[0043] In one exemplary embodiment of the present invention, the third doped region and the fourth doped region have the same doping concentration as the second doped region.

[0044] In one exemplary embodiment of the present invention, an isolation region is provided between the third doped region and the second doped region.

[0045] According to a third aspect of the present invention, a method for manufacturing the antifuse device according to any one of the above claims is provided, comprising:

[0046] Provide the substrate;

[0047] The first doped region is formed on the substrate;

[0048] A first gate dielectric layer having the groove is formed on the first doped region;

[0049] The conductive material is filled into the groove;

[0050] A first gate conductive layer is formed on the first gate dielectric layer, and the first gate conductive layer covers the groove; a second doped region is formed in the first doped region.

[0051] In one exemplary embodiment of the present invention, the method further includes: after filling the groove with the conductive material, performing a planarization process on the first gate dielectric layer.

[0052] In an exemplary embodiment of the present invention, forming a first gate dielectric layer having the groove includes:

[0053] A first gate dielectric layer of a certain thickness is formed;

[0054] A trench is formed on the already formed first gate dielectric layer, penetrating the gate dielectric layer;

[0055] The remaining thickness of the first gate dielectric layer continues to be deposited within the trench and on the already formed first gate dielectric layer.

[0056] According to a fourth aspect of the present invention, a method for preparing an antifuse unit structure as described in any one of the preceding claims is provided, comprising:

[0057] Provide the substrate;

[0058] The first doped region is formed on the substrate;

[0059] The second gate dielectric layer and the first gate dielectric layer having the groove are formed;

[0060] The groove is filled with a conductive material;

[0061] A first gate conductive layer is formed on the first gate dielectric layer, and a second gate conductive layer is formed on the second gate dielectric layer;

[0062] The second doped region, the third doped region, and the fourth doped region are formed.

[0063] In an exemplary embodiment of the present invention, the first gate dielectric layer and the second gate dielectric layer are formed using the same mask; and / or, the first gate conductive layer and the first gate conductive layer are formed using the same mask.

[0064] In an exemplary embodiment of the present invention, forming the first gate dielectric layer and the second gate dielectric layer having the groove includes:

[0065] A first gate dielectric layer and a second gate dielectric layer of a certain thickness are formed;

[0066] A trench is formed on the already formed first gate dielectric layer, penetrating the first gate dielectric layer;

[0067] The remaining thickness of the first and second gate dielectric layers continues to be deposited within the trench and on the already formed first and second gate dielectric layers.

[0068] In one exemplary embodiment of the present invention, the method further includes: after filling the groove with the conductive material, performing a planarization process on the first gate dielectric layer.

[0069] The antifuse device of this invention features a groove in the gate dielectric layer, filled with a conductive material that connects to the gate conductive layer. The groove reduces the thickness of the dielectric layer and shortens the distance between the gate conductive layer and the doped region, making the gate dielectric layer more susceptible to breakdown by a high electric field, thereby reducing the voltage applied to the antifuse device. For an array structure with multiple antifuse devices, the breakdown voltage and breakdown location of each antifuse device are relatively consistent, ensuring consistent overall performance and ideal switching characteristics for the antifuse unit structure composed of the antifuse device and the selection transistor. Furthermore, by adjusting the structure, position, and size of each part of the antifuse device, the device size can be reduced, and compatibility with CMOS processes can be achieved, simplifying the entire fabrication process.

[0070] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0071] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0072] Figure 1 This is a schematic diagram of the first structure of the antifuse device of the present invention;

[0073] Figure 2 This is a schematic diagram of a second structure of the antifuse device of the present invention;

[0074] Figure 3 for Figure 2 Top view;

[0075] Figure 4 This is a schematic diagram of the third structure of the antifuse device of the present invention;

[0076] Figure 5 This is a schematic diagram of the fourth structure of the antifuse device of the present invention;

[0077] Figure 6 This is a schematic diagram of the fifth structure of the antifuse device of the present invention;

[0078] Figure 7 This is a schematic diagram of the sixth structure of the antifuse device of the present invention;

[0079] Figure 8 This is a schematic diagram of the seventh structure of the antifuse device of the present invention;

[0080] Figure 9 This is a schematic diagram of the eighth structure of the antifuse device of the present invention;

[0081] Figure 10 This is a schematic diagram of a spacer compartment for conductive materials.

[0082] Figure 11 This is a schematic diagram of the first structure of the antifuse unit of the present invention;

[0083] Figure 12 for Figure 10 Top view;

[0084] Figure 13 This is a schematic diagram of the second structure of the antifuse unit of the present invention;

[0085] Figure 14 This is a schematic diagram of the third structure of the antifuse unit of the present invention;

[0086] Figure 15 This is a schematic diagram of the fourth structure of the antifuse unit structure of the present invention;

[0087] Figure 16 This is a schematic diagram of the fifth structure of the antifuse unit of the present invention;

[0088] Figure 17 This is a schematic diagram of the sixth structure of the antifuse unit structure of the present invention;

[0089] In the figure: 100, substrate; 200, antifuse device; 300, select transistor; 201, first N-doped region; 202, second N+ doped region; 203, first gate dielectric layer; 204, trench; 205, first gate conductive layer; 206, deep N-well; 207, P-well; 208, sidewall; 209, isolation region; 222, tip; 301, third N+ doped region; 302, fourth N+ doped region; 303, second gate dielectric layer; 304, second gate conductive layer. Detailed Implementation

[0090] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0091] To address the problems of excessively high breakdown voltage and poor consistency in breakdown voltage that are common in existing antifuse devices, this invention provides an antifuse device that solves the problems of excessively high and inconsistent breakdown voltage. This antifuse device can be a P-type device or an N-type device depending on the doping type; the following description uses an N-type device as an example.

[0092] like Figure 1 As shown, the antifuse device 200 of this embodiment includes a first N-doped region 201 formed on a P-type substrate 100, and a second N+ doped region 202 disposed within the first doped region. A first gate dielectric layer 203 is disposed on the first doped region, and at least a portion of the first gate dielectric layer 203 is located above the first doped region; the first gate dielectric layer 203 includes a groove 204, which is filled with a conductive material, and the maximum depth of the groove 204 in the direction perpendicular to the substrate 100 is less than the thickness of the first gate dielectric layer 203; a first gate conductive layer 205 is disposed on the first gate dielectric layer 203, which covers the groove 204 and is connected to the conductive material within the groove 204.

[0093] In the antifuse device 200, the first N-doped region 201 and the second N+ doped region 202 are conductive, while the first gate dielectric layer 203 acts as an insulator, separating the doped regions from the first gate conductive layer 205. A groove 204 is formed within the first gate dielectric layer 203, and the groove 204 is filled with conductive material. The conductive material within the groove 204 can be considered as part of the first gate conductive layer 205. When no high voltage is applied to the antifuse device, the doped regions and the first gate conductive layer 205 are separated by the first gate dielectric layer 203, and the antifuse is open-circuited at both ends. When a high voltage is applied to the antifuse device, because the first gate dielectric layer 203 at the groove is relatively thin, it is easily broken down by the high electric field, forming an electrical connection between the first gate conductive layer 205 and the doped regions, and the antifuse melts.

[0094] The presence of the groove 204 reduces the thickness of the dielectric layer and brings the first gate conductive layer 205 closer to the doped region, making the first gate dielectric layer 203 more susceptible to breakdown by a high electric field. This reduces the voltage applied to the antifuse device. Furthermore, since the fabrication of the groove 204 structure is controllable, for an array structure with multiple antifuse devices, adjusting the depth of the groove 204 ensures consistent breakdown voltages for each antifuse device. Simultaneously, since breakdown is most likely to occur in the thinner region of the first gate dielectric layer 203, specifically on the side of the groove 204 near the second N+ doped region—specifically, at the tip 222 of the groove 204 near the first gate dielectric layer 203—the first gate dielectric layer 203 is thinnest at this location. This tip 222 also creates a tip discharge effect, further fixing the breakdown location of the antifuse device. This facilitates rapid fault location and targeted analysis when the antifuse device malfunctions. Thus, the breakdown location of the antifuse device is fixed, making it easier to control its performance during manufacturing. Therefore, by adjusting the position of the groove, the breakdown position of each antifuse device can be ensured to be relatively consistent, thereby ensuring the overall performance of each antifuse device is consistent.

[0095] The antifuse device 200 of this embodiment will now be described in detail:

[0096] The second N+ doped region 202 is set as a heavily doped region, which can reduce the surface contact resistance. The doping concentration of the first N-doped region 201 and the second N+ doped region 202 will affect the breakdown voltage of the antifuse device and the on-resistance of the antifuse device after breakdown, and can be set as needed.

[0097] In this embodiment, the doped region of the antifuse device 200 is directly disposed on the substrate 100, thereby minimizing the device area. In other embodiments, such as... Figure 2 and Figure 3As shown, the antifuse device 200 may further include a deep N-well 206 disposed on the substrate 100, and a P-well 207 disposed in the first deep N-well 206. A first N-doped region 201 is disposed in the P-well 207 to form an N-type device. The deep N-well 206 can isolate the antifuse device 200 from other devices, reducing mutual electrical interference. This structure can omit the isolation region 209 and reduce the device area.

[0098] The cross-sectional shape of the groove 204 in the direction perpendicular to the substrate 100 can be as follows: Figure 2 The rectangle shown Figure 4 The semi-ellipse shown Figure 5 The triangle shown can also be in many other shapes, which will not be listed here. Different groove shapes are mainly due to effects of the actual process, such as suboptimal etching selectivity or step effects in the deposition process. Specifically, Figure 2 The rectangle is formed under ideal process conditions. When etching to form grooves, due to the non-ideality of etching selectivity... Figure 2 The grooves formed by etching will be inverted trapezoidal, or... Figure 4 The semi-ellipse shape, even for Figure 5 A triangle. Still based on Figure 2 For example, even if the etched grooves are ideally rectangular, the step effect of the deposition process can still cause them to become... Figure 4 The semi-ellipse, even Figure 5 The groove 204 is an inverted triangle. However, regardless of its specific shape, it does not affect its ability to reduce breakdown voltage. The projection shape of the groove 204 onto the substrate 100 can also be various, and this invention does not specifically limit this. The depth of the groove 204 in the direction perpendicular to the substrate 100 determines the distance between the conductive material and the doped region, affecting the magnitude of the breakdown voltage, and can be set as needed. Preferably, the distance between the bottom of the groove 204 and the bottom of the first gate dielectric layer 203 is 2nm to 3nm. This depth ensures that the dielectric layer can be broken down without affecting other devices.

[0099] The number of grooves 204 can be one or more. The "multiple" mentioned in this invention refers to at least two. For example, as... Figure 6 In the illustrated embodiment, there are two grooves 204. At the same breakdown voltage, providing multiple grooves 204 increases the probability of the antifuse device being broken down, ensuring that it can be broken down. The multiple grooves 204 can be uniformly distributed within the first gate dielectric layer 203, or they can be positioned at appropriate locations as needed. Preferably, when the maximum depth of each groove 204 in the direction perpendicular to the substrate 100 is the same, it can be ensured that the device breaks down at the same breakdown voltage regardless of which groove 204 it is broken down from, thereby ensuring the consistency of the breakdown voltage.

[0100] The conductive material filling the groove 204 is polycrystalline silicon (Poly-Si), which has the following properties: Figure 10 The gap chambers shown serve to adjust for the thermal expansion and stress of the polysilicon. Because the thermal expansion coefficients of polysilicon and the first gate dielectric layer 203 are different, temperature changes during breakdown can cause defects in the first gate dielectric layer 203. The gap chambers can counteract the effects of thermal expansion and stress on the first gate dielectric layer 203. For example, in one embodiment, the groove 204 is filled with germanium silicon with the largest possible crystal grain size. Since the germanium silicon particles are relatively large, for example, when the particle diameter reaches 1000 angstroms or even larger, gap chambers are formed between the particles. This structure counteracts the effects of thermal expansion and stress on the first gate dielectric layer 203.

[0101] Accordingly, the material of the first gate conductive layer 205 can be one or more of polysilicon (Poly-Si), titanium nitride, and tungsten. For example, in one embodiment, the material of the first gate conductive layer 205 is polysilicon; in another embodiment, the material of the first gate conductive layer 205 is tungsten; or, in yet another embodiment, the material of the first gate conductive layer 205 includes two layers, with the upper layer being tungsten and the lower layer being titanium nitride; or, in yet another embodiment, the material of the first gate conductive layer 205 includes three layers, with the upper layer being tungsten, the middle layer being titanium nitride, and the lower layer being polysilicon. In short, the material of the first gate conductive layer 205 can be various combinations of the above materials, which will not be listed here. The conductive material in the groove 204 and the material of the first gate conductive layer 205 can be the same or different. When they are the same, it is convenient to simplify the fabrication process.

[0102] The first gate dielectric layer 203 is made of an insulating material, specifically silicon dioxide. In some embodiments, such as... Figure 6 As shown, the projection of the first gate dielectric layer 203 onto the substrate 100 is entirely within the projection of the first doped region, which can reduce the device area.

[0103] The antifuse device 200 may also include a sidewall 208 (spacer) for protecting the functional layer of the device and preventing defects from occurring at the contact point between the first gate dielectric layer 203 and the sidewall 208, thereby affecting the breakdown voltage. In some specific embodiments, such as Figure 7As shown, the projection of the first gate conductive layer 205 onto the substrate 100 lies within the projection of the first gate dielectric layer 203, meaning the area of ​​the first gate conductive layer 205 is smaller than that of the first gate dielectric layer 203. The sidewalls 208 are disposed on the first gate dielectric layer 203 and cover both sides of the first gate conductive layer 205, preventing defects from occurring at the contact points between the first gate dielectric layer 203 and the sidewalls 208, thereby avoiding defects affecting the breakdown voltage. In other embodiments, such as... Figure 1 and Figure 8 As shown, the projections of the first gate dielectric layer 203 and the first gate conductive layer 205 on the substrate 100 completely overlap, that is, the areas of the first gate conductive layer 205 and the first gate dielectric layer 203 are equal, and the sidewall 208 covers both sides of the first gate dielectric layer 203 and the first gate conductive layer 205.

[0104] The antifuse device 200 may also include an isolation region 209, which is located at least on the side of the first doped region away from the second doped region, for further isolation from other devices to prevent electrical interference. The isolation region 209 can be a shallow trench isolation structure to achieve effective device isolation with a smaller area. In such cases... Figure 8 In some embodiments shown, the antifuse device 200 includes a P-well 207, and the isolation region 209 is disposed within the P-well 207. In such... Figure 9 In other embodiments shown, the doped region of the antifuse device is disposed directly on the substrate 100, and therefore the isolation region 209 is also disposed on the substrate 100. For device structures including the isolation region 209, such as... Figure 8 , 9 As shown, a portion of the first gate dielectric layer 203 can be located on the shallow trench isolation structure, and another portion can be located on the first doped region, which can minimize the effective area occupied by the device.

[0105] In this embodiment, the antifuse device 200 may further include a barrier layer and a metal layer (not shown) disposed from bottom to top on the first gate conductive layer 205. The metal layer can reduce the resistance and capacitance of the gate, and the barrier layer can prevent the upper metal layer from diffusing into the polysilicon. In this structure, the sidewall 208 can simultaneously cover the first gate conductive layer 205, the barrier layer, and the sidewall 208 of the metal layer. The material of the barrier layer can be titanium nitride, etc., and the material of the metal layer can be tungsten.

[0106] This invention also provides a method for preparing an antifuse device 200, the method comprising:

[0107] Step S100: Provide a substrate 100;

[0108] Step S200: A first N-doped region 201 is formed on the substrate 100;

[0109] Step S300: A first gate dielectric layer 203 with a groove 204 is formed on the first N-doped region 201;

[0110] Step S400: Fill the groove 204 with conductive material;

[0111] In step S500, a first gate conductive layer 205 is formed on the first gate dielectric layer 203, and the first gate conductive layer 205 covers the groove 204.

[0112] In step S600, a second N+ doped region 202 is formed in the first N-doped region 201.

[0113] In steps S200 and S600 above, both doped regions can be formed using methods such as high-temperature diffusion or ion implantation. In steps S300 and S500, the formation of the first gate dielectric layer 203 and the first gate conductive layer 205 can be achieved using various thin-film forming methods such as chemical vapor deposition, thermal oxidation, epitaxy, vacuum evaporation, magnetron sputtering, and plasma deposition. Similarly, the conductive material within the groove 204 can also be formed using various methods described above for the first gate conductive layer 205. When the conductive material within the groove 204 and the material of the first gate conductive layer 205 are the same, the fabrication process can be simplified.

[0114] In step S300, the groove 204 can be prepared by etching, i.e., selectively etching or stripping the surface of the substrate 100 or the surface-covering thin film according to the mask pattern, which can be wet etching or dry etching. When etching the groove 204, a first gate dielectric layer of the required thickness can be formed directly, and then the groove 204 of the required depth can be etched. Alternatively, a portion of the first gate dielectric layer of thickness can be formed first, and then the groove location can be directly etched to the bottom, exposing the underlying first N-doped region 201, forming a trench. Then, the remaining thickness of the first gate dielectric layer 203 is formed on the already formed first gate dielectric layer and within the trench, thereby forming the groove 204 of the required depth. The latter method allows for better control of the groove 204 depth. Furthermore, since the size of the groove 204 meets the minimum design rule, in DRAM technology, the mask used to generate the groove 204 and the mask used to manufacture the buried gate of the cell region can be the same mask layer, thus avoiding the use of redundant masks in the fabrication of the groove 204. The distance from the bottom of the groove 204 to the bottom of the first gate dielectric layer 203 can be 2nm to 3nm, that is, the thickness of the first gate dielectric layer 203 at the bottom of the groove 204 is 2nm to 3nm. This thickness can reduce the breakdown voltage, ensure the structural stability when not broken down, and facilitate fabrication.

[0115] Preferably, in step S400, after filling the groove 204 with conductive material, the entire first gate dielectric layer 203 can be planarized so that the upper surface of the conductive material is flush with the first gate dielectric layer 203, so as to facilitate the subsequent preparation of the first gate conductive layer 205.

[0116] The method in this embodiment may also include methods for forming other structures such as isolation region 209, barrier layer, and metal layer. Isolation region 209 may be formed by etching, and thin film structures such as barrier layer and metal layer may be formed by thin film forming method as described above.

[0117] The following is an example Figure 3 Taking the N-type antifuse device 200 shown as an example, its fabrication process will be specifically explained:

[0118] In step S200, a deep N-well 206 is formed on the P-type substrate 100, a P-well 207 is formed in the deep N-well 206, a shallow trench isolation (STI) is formed in the P-well 207 by etching and deposition, and a first N-doped region 201 is formed in the P-well 207 by ion implantation.

[0119] In step S300, a first gate dielectric layer 203 of the antifuse device 200 is deposited and formed over the STI and the first N-doped region 201. A portion of the first gate dielectric layer 203 may be located on the STI and another portion may be located on the first N-doped region 201.

[0120] A groove 204 is formed on the first gate dielectric layer 203 of the antifuse device by etching. The maximum depth of the groove 204 in the direction perpendicular to the substrate 100 is less than the thickness of the first gate dielectric layer 203. The distance from the bottom of the groove 204 to the bottom of the first gate dielectric layer 203 is 2nm to 3nm. Figure 2 The rectangle of the central groove 204 is formed under ideal process conditions. However, when etching to form the groove, due to the non-ideal nature of the etching selectivity, Figure 2 The grooves formed by etching will be inverted trapezoidal, or... Figure 4 The semi-ellipse shape, even for Figure 5 A triangle.

[0121] During the deposition of the first gate dielectric layer 203, a trench 204 is formed using the aforementioned two-step deposition process and one etching process. Specifically, the first gate dielectric of the antifuse device (which can be silicon dioxide) is first deposited, then an etching process is used to form a trench (located below the trench 204), and then the first gate dielectric is deposited again, ultimately forming the structure of the trench 204. The thickness of the first gate dielectric deposited in the second step is 2nm to 3nm, so that the thickness from the bottom of the trench to the surface of the first doped region is 2nm to 3nm. In actual processes, even if the trench formed by etching is a relatively ideal rectangle, the step effect in the second deposition process will result in the final trench 204 being... Figure 4 The semi-ellipse shape, even for Figure 5 An inverted triangle.

[0122] In step S500, polysilicon is filled into the groove 204, completely filling the groove 204. For example, germanium-silicon with a grain size greater than 1000 angstroms can be used to fill the groove 204, creating gaps between the grains to counteract the effects of thermal expansion and stress on the first gate dielectric layer 203. After filling, the first gate dielectric layer 203 of the antifuse device 200 is planarized, making the upper surface of the polysilicon flush with the first gate dielectric layer 203.

[0123] In step S500, polysilicon (first gate conductive layer 205) is deposited on the first gate dielectric layer 203 to completely cover the first gate dielectric layer 203. Then, a barrier layer and a metal layer are deposited sequentially on the polysilicon. Then, sidewalls 208 of the antifuse device 200 are formed on both sides of the polysilicon, the barrier layer, and the metal layer.

[0124] In step S600, a second N+ doped region 202 is formed in the first N-doped region 201 next to the sidewall 208 by ion implantation.

[0125] This invention also provides an antifuse unit structure, which includes the antifuse device 200 and a selection transistor 300 as described in the above embodiments, with the selection transistor 300 adjacent to the antifuse device 200. Since this embodiment includes the antifuse device of this invention, it also has the same technical effects as the antifuse device.

[0126] In one embodiment, such as Figures 11-12As shown, the select transistor 300 is also disposed on the substrate 100, including a second gate dielectric layer 303, a second gate conductive layer 304, a third N+ doped region 301, and a fourth N+ doped region 302; the third N+ doped region 301 is electrically connected to the second N+ doped region 202 of the antifuse device 200. The first gate conductive layer 205 of the antifuse device 200 is connected to the word line, the second gate conductive layer 304 of the select transistor 300 is connected to the select line, and the fourth N+ doped region 302 is connected to the bit line. Preferably, an isolation region (STI) is also provided between the second N+ doped region 202 and the third N+ doped region 301 to separate the antifuse device and the select transistor, allowing for more flexible control of the programming process.

[0127] In this embodiment, the first gate dielectric layer 203 of the antifuse device and the second gate dielectric layer 303 of the select transistor 300 have equal thicknesses and flush upper surfaces. Therefore, the first gate dielectric layer 203 of the antifuse device and the second gate dielectric layer 303 of the select transistor can be fabricated using the same mask layer, simplifying the fabrication process and facilitating compatibility with subsequent processes. Similarly, the first gate conductive layer 205 of the antifuse device and the second gate conductive layer 304 of the select transistor have equal thicknesses and flush upper surfaces. Therefore, the first gate conductive layer 205 of the antifuse device and the second gate conductive layer 304 of the select transistor can be fabricated using the same mask layer, also facilitating compatibility with subsequent processes. Furthermore, the third N+ doped region 301 and the fourth N+ doped region 302 of the select transistor 300 have the same doping concentration as the second N+ doped region 202 of the antifuse device, thus ensuring compatibility of the doping processes for the two devices. This simplifies the fabrication of the entire antifuse unit structure.

[0128] To reduce the device area, the present invention can be implemented in various ways. For example, in one embodiment, when the antifuse device 200 includes the first deep N-well 206 and P-well 207 as described above, such as... Figure 13 As shown, the third N+ doped region 301 and the fourth N+ doped region 302 of the selector transistor 300 can both be disposed in the P-well 207. In another embodiment, as... Figure 14 As shown, further, by selecting the third N+ doped region 301 of the transistor and the second N+ doped region 202 of the antifuse device to share the same N+ doped region, the connecting wires can be omitted, which can reduce the area of ​​the doped region.

[0129] In this embodiment, the selection transistor 300 may further include a lightly doped drain (LDD) to improve the breakdown voltage performance of the selection transistor 300. Those skilled in the art will understand that the selection transistor 300 of the present invention may also include other structures, which will not be described in detail here.

[0130] In the above embodiments, the antifuse unit structure may further include isolation region 209, sidewall 208, and other structures, as described above, see reference. Figures 15-17 Further details will not be elaborated here. In summary, the antifuse device in the antifuse unit structure of the present invention can be any of the aforementioned structures.

[0131] The present invention also provides a method for preparing an antifuse unit structure, the method comprising:

[0132] Step S100: Provide a substrate 100;

[0133] Step S200: A first N-doped region 201 is formed on the substrate 100;

[0134] Step S300: Form the first gate dielectric layer 203 with groove 204 and the second gate dielectric layer 303 of the selection transistor for the antifuse device;

[0135] Step S400: Fill the groove 204 with conductive material;

[0136] In step S500, a first gate conductive layer 205 of the antifuse device is formed on the first gate dielectric layer 203 of the antifuse device, and a second gate conductive layer 304 of the selection transistor is formed on the second gate dielectric layer 303 of the selection transistor.

[0137] Step S600: Form the second N+ doped region of the antifuse device and the third and fourth N+ doped regions of the selection transistor.

[0138] In step S300 above, if the first gate dielectric layer 203 of the antifuse device and the gate dielectric layer of the select transistor have the same thickness, they can be fabricated using the same mask layer, simplifying the fabrication process. Similarly, in step S500, when forming the gate conductive layers of the antifuse device and the select transistor, since their gate conductive layers have the same thickness, they can also be fabricated using the same mask layer. When both the antifuse device 200 and the select transistor 300 include a barrier layer and a metal layer, they can also be fabricated using the same mask layer. Therefore, the fabrication processes of the antifuse device 200 and the select transistor 300 are compatible, greatly simplifying the fabrication process of the entire antifuse unit structure.

[0139] The following is an example Figure 12 Taking the N-type antifuse unit structure shown as an example, its preparation process will be explained in detail:

[0140] In step S200, a deep N-well 206 is formed on the P-type substrate 100, and a P-well 207 is formed in the deep N-well 206. Shallow trench isolation (STI) is formed in the P-well 207 by etching and deposition. Shallow trench isolation (STI) is also formed in the region between the antifuse device 200 and the select transistor 300. A first N-doped region 201 is formed in the P-well 207 by ion implantation.

[0141] In step S300, a first gate dielectric layer 203 of the antifuse device and a second gate dielectric layer 303 of the select transistor are formed using the same mask, and the first gate dielectric layer 203 of the antifuse device and the second gate dielectric layer 303 of the select transistor have the same thickness. The first gate dielectric layer 203 of the antifuse device is located above the first N-doped region 201, and the second gate dielectric layer 303 of the select transistor is located on the substrate 100. A portion of the first gate dielectric layer 203 of the antifuse device may be located on the STI, and another portion may be located on the first N-doped region 201.

[0142] During the deposition of the first gate dielectric layer 203, a trench 204 is formed using the aforementioned two-step deposition process and one etching process. Specifically, the first gate dielectric (which can be silicon dioxide) of the antifuse device is first deposited, then an etching process is used to form a trench, and then the first gate dielectric is deposited again, ultimately forming the trench 204 structure. The thickness of the first gate dielectric deposited in the second step is 2nm to 3nm. In actual processes, even if the trench formed by etching is a relatively ideal rectangle, the step effect in the second deposition process will cause the final trench 204 to be... Figure 4 The semi-ellipse shape, even for Figure 5 An inverted triangle.

[0143] In step S500, polysilicon is filled into the groove 204, completely filling the groove 204. For example, germanium-silicon with a grain size greater than 1000 angstroms can be used to fill the groove 204, creating gaps between the grains to counteract the effects of thermal expansion and stress on the first gate dielectric layer 203. After filling, the first gate dielectric layer 203 of the antifuse device is planarized, making the upper surface of the polysilicon flush with the first gate dielectric layer 203. The processed antifuse device 200 and the select transistor 300 have gate dielectric layers of the same thickness.

[0144] In step S500, polysilicon is deposited on the first gate dielectric layer 203 of the antifuse device 200 and the second gate dielectric layer 303 of the select transistor 300, so that the polysilicon completely covers the gate dielectric layer. Then, a barrier layer and a metal layer are deposited sequentially on the polysilicon. A lightly doped drain (LDD) of the select transistor 300 is formed by ion implantation. Then, sidewalls 208 are formed on the outer sides of both the antifuse device 200 and the select transistor 300.

[0145] In step S600, a second N+ doped region 202 is formed in the first N-doped region 201 next to the sidewall 208 of the antifuse device 200 by ion implantation. At the same time, a third N+ doped region 301 and a fourth N+ doped region 302 of the select transistor 300 are formed next to the sidewall 208 of the select transistor 300 by ion implantation.

[0146] The above only provides examples of N-type doped structures. The same applies to P-type structures, so they will not be elaborated here.

[0147] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0148] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion meaning and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0149] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims.

Claims

1. An antifuse device, characterized in that, include: The first doped region is formed on a substrate; A second doped region is disposed within the first doped region and has the same doping type as the first doped region, and the doping concentration of the second doped region is greater than that of the first doped region; A first gate dielectric layer is at least partially disposed on the first doped region; the first gate dielectric layer includes a groove filled with a conductive material, and the maximum depth of the groove in the direction perpendicular to the substrate is less than the thickness of the first gate dielectric layer. A first gate conductive layer is disposed on the first gate dielectric layer, covers the groove, and is connected to the conductive material in the groove.

2. The antifuse device according to claim 1, characterized in that, The antifuse device also includes: The first well is a deep well and is disposed on the substrate; The second well is disposed in the first well, and the second well and the first well have different doping types, and the second well and the first doped region have different doping types; The first doped region is located in the second well.

3. The antifuse device according to claim 2, characterized in that, The substrate is a P-type substrate, and the first doped region is N-type doped.

4. The antifuse device according to claim 1, characterized in that, The number of grooves is multiple.

5. The antifuse device according to claim 4, characterized in that, The grooves have the same maximum depth in the direction perpendicular to the substrate.

6. The antifuse device according to claim 1, characterized in that, The distance from the bottom of the groove to the bottom of the first gate dielectric layer is 2nm~3nm.

7. The antifuse device according to claim 1, characterized in that, The conductive material filled in the groove is polycrystalline silicon, and the polycrystalline silicon has a gap chamber.

8. The antifuse device according to claim 1, characterized in that, The antifuse device further includes a sidewall, wherein the projection of the first gate conductive layer on the substrate is located within the projection of the first gate dielectric layer, and the sidewall is disposed on the first gate dielectric layer and covers both sides of the first gate conductive layer.

9. The antifuse device according to claim 1, characterized in that, The antifuse device further includes a sidewall, wherein the projections of the first gate dielectric layer and the first gate conductive layer on the substrate completely overlap, and the sidewall simultaneously covers both sides of the first gate dielectric layer and the first gate conductive layer.

10. The antifuse device according to claim 1, characterized in that, The antifuse device further includes an isolation region located on the substrate, and at least on the side of the first doped region away from the second doped region; In this configuration, a portion of the first gate dielectric layer is located on the isolation region, and another portion is located on the first doped region.

11. The antifuse device according to claim 1, characterized in that, The projection of the first gate dielectric layer on the substrate is entirely within the projection of the first doped region.

12. The antifuse device according to claim 1, characterized in that, The material of the first gate conductive layer is one or more of polycrystalline silicon, titanium nitride, and tungsten.

13. The antifuse device according to claim 1, characterized in that, The first gate dielectric layer is silicon dioxide.

14. The antifuse device according to claim 1, characterized in that, The antifuse device also includes: A barrier layer covers the first gate conductive layer; A metal layer covers the barrier layer.

15. An antifuse unit structure, characterized in that, include: The antifuse device according to any one of claims 1-14; The selected transistor is disposed on the substrate and includes at least a second gate dielectric layer, a second gate conductive layer, a third doped region, and a fourth doped region; the doping types of the third doped region and the fourth doped region are the same as those of the first doped region, and the doping concentrations of the third doped region and the fourth doped region are greater than those of the first doped region. The third doped region is electrically connected to the second doped region.

16. The antifuse unit structure according to claim 15, characterized in that, The first gate dielectric layer and the second gate dielectric layer have the same thickness and their upper surfaces are flush. And / or, the first gate conductive layer and the second gate conductive layer have the same thickness and their upper surfaces are flush.

17. The antifuse unit structure according to claim 16, characterized in that, The third doped region and the second doped region share the same doped region.

18. The antifuse unit structure according to claim 16, characterized in that, The antifuse device includes a first well and a second well; the first well is a deep well disposed on the substrate; the second well is disposed in the first well and has a different doping type from the first well. The first doped region, the third doped region, and the fourth doped region are all located in the second well, and the first doped region, the third doped region, and the fourth doped region have different doping types from the second well.

19. The antifuse unit structure according to claim 16, characterized in that, The third and fourth doped regions have the same doping concentration as the second doped region.

20. The antifuse unit structure according to claim 16, characterized in that, An isolation region exists between the third doped region and the second doped region.

21. A method for preparing an antifuse device according to any one of claims 1-14, characterized in that, include: Provide the substrate; The first doped region is formed on the substrate; A first gate dielectric layer having the groove is formed on the first doped region; The conductive material is filled into the groove; A first gate conductive layer is formed on the first gate dielectric layer, and the first gate conductive layer covers the groove; a second doped region is formed in the first doped region.

22. The method for preparing the antifuse device according to claim 21, characterized in that, Also includes: After the conductive material is filled into the groove, the first gate dielectric layer is planarized.

23. The method for preparing the antifuse device according to claim 22, characterized in that, Forming a first gate dielectric layer having the aforementioned groove includes: A first gate dielectric layer of a certain thickness is formed; A trench is formed on the already formed first gate dielectric layer, penetrating the gate dielectric layer; The remaining thickness of the first gate dielectric layer continues to be deposited within the trench and on the already formed first gate dielectric layer.

24. A method for preparing the antifuse unit structure as described in claim 15, characterized in that, include: Provide the substrate; The first doped region is formed on the substrate; The second gate dielectric layer and the first gate dielectric layer having the groove are formed; The groove is filled with a conductive material; A first gate conductive layer is formed on the first gate dielectric layer, and a second gate conductive layer is formed on the second gate dielectric layer; The second doped region, the third doped region, and the fourth doped region are formed.

25. The method for preparing the antifuse unit structure according to claim 24, characterized in that, The first gate dielectric layer and the second gate dielectric layer are formed using the same mask; And / or, the first gate conductive layer and the first gate conductive layer are formed using the same mask.

26. The method for preparing the antifuse unit structure according to claim 24, characterized in that, Forming the second gate dielectric layer and the first gate dielectric layer having the groove includes: A first gate dielectric layer and a second gate dielectric layer of a certain thickness are formed; A trench is formed on the already formed first gate dielectric layer, penetrating the first gate dielectric layer; The remaining thickness of the first and second gate dielectric layers continues to be deposited within the trench and on the already formed first and second gate dielectric layers.

27. The method for preparing the antifuse unit structure according to claim 24, characterized in that, Also includes: After the conductive material is filled into the groove, the first gate dielectric layer is planarized.

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