Display device and method of manufacturing a display device

Abstract

The present disclosure relates to a display device and a method of manufacturing a display device, the display device including: a substrate; a first semiconductor layer over the substrate; a first gate insulating film over the first semiconductor layer; a first conductive layer over the first gate insulating film, and the first conductive layer including a first gate electrode and a first electrode of a capacitor connected to the first gate electrode; a second semiconductor layer over the first gate insulating film, and the second semiconductor layer being at a different layer from the first semiconductor layer; a second gate insulating film over the first conductive layer and the second semiconductor layer; a second conductive layer over the second gate insulating film, and the second conductive layer including a second gate electrode and a second electrode of the capacitor; a second interlayer insulating film over the second conductive layer; and a third conductive layer over the second interlayer insulating film, and the third conductive layer including a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2019-0107175, filed on August 30, 2019, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments of this disclosure relate to a display device and a method of manufacturing a display device. Background Technology

[0004] With the development of multimedia, display devices are becoming increasingly important. In response, various types of display devices, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, are being used. In display devices, OLED displays use OLEDs to display images by causing electrons and holes to recombine and generate light. OLED displays include multiple transistors that provide driving current to the OLEDs. Summary of the Invention

[0005] One or more aspects of embodiments of this disclosure relate to display devices in which the number of masks used in the manufacturing process is reduced.

[0006] One or more aspects of embodiments of this disclosure relate to a method of manufacturing a display device in which the number of masks used in the manufacturing process is reduced.

[0007] The scope of this disclosure is not limited to the foregoing purposes, and other unmentioned purposes will be readily apparent to those skilled in the art from the following description.

[0008] One or more exemplary embodiments of this disclosure provide a display device, the display device comprising: a substrate; a first semiconductor layer located on the substrate; a first gate insulating film located on the first semiconductor layer; a first conductive layer located on the first gate insulating film, and the first conductive layer including a first gate electrode and a first electrode of a capacitor connected to the first gate electrode; a second semiconductor layer located on the first gate insulating film, and the second semiconductor layer being located at a different layer from the first semiconductor layer; a second gate insulating film located on the first conductive layer and the second semiconductor layer; a second conductive layer located on the second gate insulating film, and the second conductive layer including a second gate electrode and a second electrode of the capacitor; a second interlayer insulating film located on the second conductive layer; and a third conductive layer located on the second interlayer insulating film, and the third conductive layer including a first source electrode and a first drain electrode connected to the first semiconductor layer and a second source electrode and a second drain electrode connected to the second semiconductor layer.

[0009] In one or more example embodiments of this disclosure, the first gate electrode and the second semiconductor layer are coplanar.

[0010] In one or more exemplary embodiments of this disclosure, the second gate insulating film is located between the first gate electrode and the second electrode of the capacitor, and the second gate insulating film is located between the second semiconductor layer and the second gate electrode.

[0011] In one or more example embodiments of this disclosure, the display device further includes a lower light-shielding pattern that overlaps with at least a portion of the second semiconductor layer, the lower light-shielding pattern being located below the second semiconductor layer.

[0012] In one or more example embodiments of this disclosure, the lower light-shielding pattern is coplanar with the first semiconductor layer and comprises the same material as the first semiconductor layer.

[0013] In one or more exemplary embodiments of this disclosure, the display device further includes a first interlayer insulating film, wherein the first interlayer insulating film is located between the lower light-shielding pattern and the second semiconductor layer.

[0014] In one or more example embodiments of this disclosure, the lower light-shielding pattern is coplanar with the first gate electrode and comprises the same material as the first gate electrode.

[0015] In one or more example embodiments of this disclosure, the first interlayer insulating film is located between the first conductive layer and the second semiconductor layer, and the second semiconductor layer is located above the first conductive layer.

[0016] In one or more exemplary embodiments of this disclosure, a plurality of insulating films are located between the first gate electrode and the second electrode of the capacitor, and at least one of the plurality of insulating films is located between the second semiconductor layer and the second gate electrode.

[0017] In one or more exemplary embodiments of this disclosure, the lower light-shielding pattern is connected to the second gate electrode, or to any one of the second source electrode and the second drain electrode.

[0018] One or more exemplary embodiments of this disclosure provide a display device comprising: a first transistor including a non-oxide semiconductor on a first layer; a second transistor including an oxide semiconductor on a second layer, the second layer being different from the first layer on which the non-oxide semiconductor is located; and a capacitor, wherein a first electrode of the capacitor and a gate electrode of the first transistor are formed by a first conductive layer, a gate electrode of the second transistor and a second electrode of the capacitor are formed by a second conductive layer different from the first conductive layer, a source / drain electrode of the first transistor and a source / drain electrode of the second transistor are formed by a third conductive layer different from the first and second conductive layers, and the gate electrode of the second transistor and the second electrode of the capacitor are coplanar.

[0019] In one or more exemplary embodiments of this disclosure, the first transistor is a p-type metal-oxide-semiconductor transistor and the second transistor is an n-type metal-oxide-semiconductor transistor, or wherein the first transistor is an n-type metal-oxide-semiconductor transistor and the second transistor is a p-type metal-oxide-semiconductor transistor.

[0020] In one or more exemplary embodiments of this disclosure, the display device further includes a lower light-shielding pattern that overlaps with at least a portion of the non-oxide semiconductor of the second transistor, the lower light-shielding pattern being located below the second transistor.

[0021] In one or more exemplary embodiments of this disclosure, the lower light-shielding pattern is coplanar with the non-oxide semiconductor of the first transistor and comprises the same material as the non-oxide semiconductor of the first transistor.

[0022] In one or more example embodiments of this disclosure, the oxide semiconductor of the second transistor is coplanar with the gate electrode of the first transistor.

[0023] One or more exemplary embodiments of this disclosure provide a method for manufacturing a display device, the method comprising: forming a first semiconductor layer of a first transistor on a substrate; forming a first gate insulating film on the first semiconductor layer; forming a first gate electrode and a first electrode of a capacitor connected to the first gate electrode on the first gate insulating film, wherein each of the first gate electrode and the first electrode of the capacitor is formed by a first conductive layer; forming a second semiconductor layer of a second transistor on the first gate insulating film, the second semiconductor layer being located at a different layer from the first semiconductor layer; forming a second gate insulating film on the second semiconductor layer of the second transistor; and forming a second conductive layer on the second gate insulating film, wherein the second conductive layer includes a second electrode of the capacitor and a second gate electrode.

[0024] In one or more example embodiments of this disclosure, the first gate electrode and the second semiconductor layer are coplanar.

[0025] In one or more example embodiments of this disclosure, the method further includes: forming a lower light-shielding pattern that overlaps with at least a portion of the second semiconductor layer.

[0026] In one or more example embodiments of this disclosure, the lower light-shielding pattern is coplanar with the first semiconductor layer and comprises the same material as the first semiconductor layer.

[0027] In one or more example embodiments of this disclosure, the method further includes: forming a first interlayer insulating film after forming the first conductive layer, the first interlayer insulating film being located between the first conductive layer and the second semiconductor layer, wherein the second semiconductor layer is disposed above the first conductive layer.

[0028] According to one or more embodiments of the display device and one or more embodiments of the method for manufacturing the display device, the number of masks can be reduced, thereby reducing process costs and improving process efficiency.

[0029] The effects of one or more embodiments of this disclosure are not limited to the descriptions above, and various other effects are described in the specification. Attached Figure Description

[0030] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 This is a plan view of the display device according to an embodiment;

[0032] Figure 2 yes Figure 1A side view of the display device;

[0033] Figure 3 This is an equivalent circuit diagram of a pixel of a display device according to an embodiment;

[0034] Figure 4 This is a cross-sectional view showing an exemplary cross-section of the periphery of a curved region of a pixel and a non-display area according to an embodiment;

[0035] Figure 5 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment;

[0036] Figures 6 to 17 This is a cross-sectional view illustrating the process operations of a method for manufacturing a display device according to an embodiment;

[0037] Figure 18 This is a cross-sectional view of a display device according to another embodiment;

[0038] Figure 19 This is a cross-sectional view of a display device according to yet another embodiment;

[0039] Figure 20 This is a cross-sectional view of a display device according to another embodiment;

[0040] Figure 21 This is a cross-sectional view of a display device according to another embodiment;

[0041] Figure 22 It shows the manufacturing basis Figure 21 A partial flowchart of the method of the display device in an embodiment; and

[0042] Figures 23 to 25 It shows the manufacturing basis Figure 21 A cross-sectional view of the process operation of the method for displaying the device according to an embodiment. Detailed Implementation

[0043] Embodiments of the invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are illustrated. However, the invention may be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0044] It will also be understood that when a layer is referred to as being "on" another layer or substrate, the layer may be directly on said other layer or substrate, or there may be an intermediate layer. Throughout the specification, the same reference numerals indicate the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0045] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, a first element discussed below may be designated a second element without departing from the teachings of one or more embodiments. Describing an element as a “first” element may not require or imply the existence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0046] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms.

[0047] It will also be understood that, when used in this specification, the terms “comprising,” “including,” “containing,” and / or “having” indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0048] As used herein, when expressions such as “at least one of…”, “one of…” and “selected from…” precede or follow a column of elements, they modify the entire column of elements but not the individual elements of that column.

[0049] As used herein, the term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0050] Furthermore, when describing embodiments of this disclosure, the term "may" refers to "one or more embodiments of this disclosure".

[0051] As used herein, phrases such as “plan view” may refer to a view viewed from the top of the display device or from a direction perpendicular to the display area (or display plane) of the display device.

[0052] It will be understood that when an element is referred to as being "on" another element, "connected to" or "coupled to" another element, the element may be directly on, directly connected to or directly coupled to the other element, or one or more intermediate elements may also be present. When an element is referred to as being "directly on" another element, "directly connected to" or "directly coupled to" another element, no intermediate elements are present.

[0053] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” “bottom,” and “top” are used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device is flipped in the drawings, an element described as “below” or “under” other elements or features will subsequently be oriented as “above” or “on” other elements or features. Thus, the term “below” can cover both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Furthermore, when an element is described as “above” another element, that element may be further away from the substrate of the display device than other elements in a direction perpendicular to the substrate. When an element is described as being "below" another element, that element may be closer to the substrate of the display device than other elements in a direction perpendicular to the substrate.

[0054] As used herein, the terms “substantially” and similar terms are used as approximations rather than terms of degree, and are intended to account for inherent biases in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0055] As used in this article, the term “use” can be considered synonymous with the term “utilize”.

[0056] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense.

[0057] In the detailed description, those skilled in the art will understand that many changes and modifications can be made to the disclosed embodiments without substantially departing from the principles of the invention. Therefore, the disclosed embodiments of the invention are used in a general and descriptive sense only and not for limiting purposes.

[0058] In the following description, specific embodiments will be described with reference to the accompanying drawings.

[0059] Figure 1 This is a plan view of a display device according to an embodiment. Figure 2 yes Figure 1A side view of the display device. Figure 2 The shape of the side surface of the display device, which is curved in the thickness direction of the display device, is shown.

[0060] Display device 1 can be a device for displaying moving or still images, and display device 1 can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs), and can also be used as a display screen for various products such as televisions, laptops, monitors, billboards, and Internet of Things devices.

[0061] The display device 1 according to one or more embodiments may have a generally rectangular shape in a plan view. The display device 1 may have a rectangular shape in a plan view, wherein the angles at the corners of the rectangular shape are right angles. However, this disclosure is not limited thereto, and the display device 1 may have a rectangular shape in a plan view whose corners are rounded or curved.

[0062] In the accompanying drawings, the first direction DR1 represents the lateral direction of the display device 1 in a plan view, and the second direction DR2 represents the longitudinal direction of the display device 1 in a plan view. Additionally, the third direction DR3 represents the thickness direction of the display device 1. The first direction DR1 and the second direction DR2 intersect each other perpendicularly, and the third direction DR3 is a direction that intersects the plane containing the first direction DR1 and the second direction DR2, and the third direction DR3 intersects both the first direction DR1 and the second direction DR2 perpendicularly. However, the directions described in the embodiments should be understood as relative directions, and the embodiments are not limited to the described directions.

[0063] Unless otherwise defined, in this specification, the terms “upper,” “upper surface,” or “upper side,” as used relative to a third party to DR3, refer to the direction relative to the display surface of the display panel 100 (e.g., the surface of the display panel 100 through which the display panel 100 emits light to display an image), and the terms “lower,” “lower surface,” or “lower side” refer to the direction opposite to the display surface relative to the display panel 100.

[0064] Reference Figure 1 and Figure 2 The display device 1 may include a display panel 100. The display panel 100 may be a flexible substrate comprising a flexible polymer material such as polyimide. Therefore, the display panel 100 may be flexible, bendable, foldable, or rollable.

[0065] Display panel 100 may be an organic light-emitting display panel. In one or more embodiments, an organic light-emitting display panel is shown as display panel 100, but this disclosure is not limited thereto, and other types of display panels such as liquid crystal display (LCD) panels, quantum dot organic light-emitting display (QD-OLED) panels, quantum dot LCD (QD-LCD) panels, quantum nano-light-emitting display panels (nano-emission display (NED) panels), and micro LED panels may be used as display panel 100.

[0066] Display panel 100 may include a display area DA in which a screen (e.g., an image is displayed) is shown, and a non-display area NDA in which no screen is shown (e.g., no image is displayed). In a plan view, display panel 100 may be divided into display area DA and non-display area NDA. Non-display area NDA may be configured to surround display area DA. Non-display area NDA may form a border.

[0067] The display area DA may have a rectangular shape in a planar view, with right angles at its corners. In one or more embodiments, the display area DA may have a rectangular shape in a planar view, with rounded or curved corners. The display area DA may have a short side and a long side. Each long side may be longer than each short side. The short side of the display area DA may be a side extending in a first direction DR1. The long side of the display area DA may be a side extending in a second direction DR2. However, the planar shape of the display area DA is not limited to a rectangular shape, and the display area DA may be circular, elliptical, or various other suitable shapes.

[0068] The display area DA may include multiple pixels. The pixels may be arranged in a rectangular shape. Each pixel may include a light-emitting layer and a circuit layer that controls the amount of light emitted by the light-emitting layer. The circuit layer may include lines, electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting material. The light-emitting layer may be sealed with an encapsulation film. The detailed configuration of the pixels will be described in more detail below.

[0069] The non-display area NDA can be configured to be adjacent to the two short sides and two long sides of the display area DA. In this case, the non-display area NDA can surround all the sides of the display area DA and form the edge (e.g., the outer edge) of the display area DA. However, this disclosure is not limited thereto, and the non-display area NDA can be configured to be adjacent to only the two short sides or the two long sides of the display area DA.

[0070] The display panel 100 may include a main region MA and a curved region BA connected to one side of the main region MA in a second direction DR2. The display panel 100 may also include a sub-region SA, one side of which is connected to the curved region BA in the second direction DR2, and the sub-region SA is curved in its thickness direction to overlap with the main region MA in the thickness direction.

[0071] The display area DA can be located within the main area MA. The non-display area NDA can be located at the outer edge of the display area DA within the main area MA.

[0072] The main area MA can have a shape similar to the exterior of the display device 1 in a plan view. The main area MA can be a flat area positioned within a surface. In other words, the main area MA can be positioned on, for example... Figure 1 The area in the generally flat planar surface of the display device 1 shown. However, the present disclosure is not limited thereto, and at least one of the remaining edges of the main region MA, other than the edge (side) connected to the curved region BA, can be bent to form a curved surface, or can be bent in the vertical direction.

[0073] When at least one of the remaining edges of the main area MA, other than the edge (side) connecting to the curved area BA, is curved or bent, the display area DA may also be located at the corresponding edge. However, this disclosure is not limited thereto, and the non-display area NDA, which does not display a screen, may be located at the curved or bent edge, or the display area DA and the non-display area NDA may be located together at the curved or bent edge.

[0074] The non-display area NDA of the main area MA can be located in the area extending from the outer boundary of the display area DA to the edge of the display panel 100. Signal lines or drive circuits for applying signals to the display area DA can be provided in the non-display area NDA of the main area MA.

[0075] The curved region BA can be connected to a short side of the main region MA. The width of the curved region BA (width in the first direction DR1) can be smaller than (or less than) the width of the main region MA (width of the short side). The connection between the main region MA and the curved region BA can have an L-shaped cutout to reduce the width of the border.

[0076] In the bending region BA, the display panel 100 can be bent with curvature in a direction opposite to the direction of its display surface (e.g., the direction in which the display surface faces). Because the display panel 100 is bent in the bending region BA, the surface of the display panel 100 (e.g., the sub-region SA) can be reversed. That is, an upward-facing surface of the display panel 100 can be turned to face downwards by passing through the bending region BA to the outside of the side surface of the display panel 100.

[0077] Sub-region SA extends from curved region BA. Sub-region SA may extend from the curved end in a direction parallel to the main region MA. Sub-region SA may overlap with the main region MA in the thickness direction of the display panel 100. Sub-region SA may overlap with non-display region NDA at the edge of the main region MA, and may further overlap with the display region DA of the main region MA. The width of sub-region SA may be the same as, equal to, or substantially equal to the width of curved region BA, but this disclosure is not limited thereto. For example, in one or more embodiments, sub-region SA and curved region BA may have different widths.

[0078] The pad portion can be disposed on a sub-region SA of the display panel 100. External devices can be mounted on (or attached to) the pad portion. Examples of external devices may include a driver chip 200 and a driver substrate 300 formed as a flexible or rigid printed circuit board. Additionally, wire connection films and connectors may be mounted on the pad portion as external devices. One or more external devices may be mounted in the sub-region SA. For example, such as... Figure 1 and Figure 2 As shown, the driver chip 200 can be disposed in a sub-region SA of the display panel 100, and the driver substrate 300 can be attached to the end of the sub-region SA. In this case, the display panel 100 can include both a pad portion connected to the driver chip 200 and a pad portion connected to the driver substrate 300. As another example, the driver chip can be mounted on a film, and the film can be attached to the sub-region SA of the display panel 100.

[0079] The driver chip 200 can be mounted on one surface of the display panel 100. In one or more embodiments, said one surface of the display panel 100 is coplanar with the display surface of the display panel 100 (e.g., the driver chip 200 is mounted on the same surface of the display panel 100 as said display surface). As described above, since the curved region BA is bent and reversed, the driver chip 200 can be mounted on the surface of the display panel 100 that faces downward in the thickness direction (or away from the display region DA), and therefore, the upper surface of the driver chip 200 can face downward.

[0080] The driver chip 200 can be attached to the display panel 100 using an anisotropic conductive film, or it can be attached to the display panel 100 by ultrasonic welding. The lateral width of the driver chip 200 can be smaller than (or less than) the lateral width of the display panel 100. The driver chip 200 can be disposed in the center of the sub-region SA in the lateral direction (first direction DR1), and the left and right edges of the driver chip 200 can be spaced apart from the left and right edges of the sub-region SA, respectively.

[0081] The driver chip 200 may include an integrated circuit that drives the display panel 100. In one or more embodiments, the integrated circuit may be a data driver integrated circuit that generates and provides data signals, but this disclosure is not limited thereto. The driver chip 200 is connected to line pads disposed on a pad portion of the display panel 100 to provide data signals to the line pads. Lines connected to the line pads extend to pixels to apply data signals to the corresponding pixels.

[0082] Figure 3 This is an equivalent circuit diagram of a display device according to an embodiment.

[0083] Reference Figure 3 The circuitry for one pixel of an organic light-emitting display device includes an organic light-emitting diode (OLED), multiple transistors T1 to T7 (T1, T2, T3, T4, T5, T6, and T7), and a capacitor Cst. Data signals DATA, a first scan signal Gw-p, a second scan signal Gw-n, a third scan signal GI, a light emission control signal EM, a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage VINT are applied to the pixel's circuitry.

[0084] An organic light-emitting diode (OLED) includes an anode electrode and a cathode electrode. A capacitor Cst includes a first electrode and a second electrode.

[0085] The plurality of transistors may include transistors T1 through T7 (transistor T1, transistor T2, transistor T3, transistor T4, transistor T5, transistor T6, and transistor T7). Each of transistors T1 through T7 includes a gate electrode, a first source / drain electrode, and a second source / drain electrode. Either the first source / drain electrode or the second source / drain electrode of each of transistors T1 through T7 may be a source electrode, and the other source / drain electrode may be a drain electrode.

[0086] Each of transistors T1 to T7 can be a thin-film transistor. Each of transistors T1 to T7 can be either a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In one or more embodiments, the first transistor T1, used as a driving transistor, the second transistor T2, used as a data transmission transistor, the fifth transistor T5, used as a first light-emitting control transistor, and the sixth transistor T6, used as a second light-emitting control transistor, can be PMOS transistors (e.g., in...). Figure 3 (In the embodiment shown). On the other hand, the third transistor T3, used as a compensation transistor, the fourth transistor T4, used as a first initialization transistor, and the seventh transistor T7, used as a second initialization transistor, can be NMOS transistors (e.g., in...). Figure 3 (As shown in the embodiment). PMOS transistors and NMOS transistors have different characteristics. The third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be formed as NMOS transistors with relatively high cutoff characteristics, and therefore, leakage of drive current during the emission period of the organic light-emitting diode (OLED) can be reduced.

[0087] In the following description, each component will be described in more detail according to one or more embodiments.

[0088] The gate electrode of the first transistor T1 is connected to the first electrode of the capacitor Cst. The first source / drain electrode of the first transistor T1 is connected to the terminal of the first power supply voltage ELVDD via the fifth transistor T5. The second source / drain electrode of the first transistor T1 is connected to the anode electrode of the organic light-emitting diode (OLED) via the sixth transistor T6. The first transistor T1 receives the data signal DATA according to the switching operation of the second transistor T2 and supplies the driving current corresponding to the data signal DATA to the OLED.

[0089] The gate electrode of the second transistor T2 is connected to the terminal of the first scan signal Gw-p. The first source / drain electrode of the second transistor T2 is connected to the terminal of the data signal DATA. The second source / drain electrode of the second transistor T2 is connected to the terminal of the first power supply voltage ELVDD via the fifth transistor T5 while being connected to the first source / drain electrode of the first transistor T1. The second transistor T2 is turned on according to the first scan signal Gw-p to perform the switching operation in which the data signal DATA is transmitted to the first source / drain electrode of the first transistor T1.

[0090] The gate electrode of the third transistor T3 is connected to the terminal of the second scan signal Gw-n. The first source / drain electrode of the third transistor T3 is connected to the second source / drain electrode of the first transistor T1, and simultaneously connected to the anode electrode of the organic light-emitting diode (OLED) via the sixth transistor T6. The second source / drain electrode of the third transistor T3 is connected to the first electrode of the capacitor Cst, the first source / drain electrode of the fourth transistor T4, and the gate electrode of the first transistor T1. The third transistor T3 is turned on according to the second scan signal Gw-p to connect the gate electrode of the first transistor T1 to the second source / drain electrode, and is connected to the first transistor T1 in a diode manner. Therefore, due to the threshold voltage of the first transistor T1, a voltage difference is generated between the first source / drain electrode and the gate electrode of the first transistor T1. Therefore, the data signal DATA can be supplied to the gate electrode of the first transistor T1 in a manner that compensates for the deviation of the threshold voltage of the first transistor T1.

[0091] The gate electrode of the fourth transistor T4 is connected to the terminal of the third scan signal GI. The second source / drain electrode of the fourth transistor T4 is connected to the terminal of the initialization voltage VINT. The first source / drain electrode of the fourth transistor T4 is connected to the first electrode of capacitor Cst, the second source / drain electrode of the third transistor T3, and the gate electrode of the first transistor T1. The fourth transistor T4 is turned on according to the third scan signal GI to perform the operation in which the initialization voltage VINT is transferred to the gate electrode of the first transistor T1, such that the voltage of the gate electrode of the first transistor T1 is initialized.

[0092] The gate electrode of the fifth transistor T5 is connected to the terminal of the light emission control signal EM. The first source / drain electrode of the fifth transistor T5 is connected to the terminal of the first power supply voltage ELVDD. The second source / drain electrode of the fifth transistor T5 is connected to the first source / drain electrode of the first transistor T1 and the second source / drain electrode of the second transistor T2.

[0093] The gate electrode of the sixth transistor T6 is connected to the terminal of the light emission control signal EM. The first source / drain electrode of the sixth transistor T6 is connected to the second source / drain electrode of the first transistor T1 and the first source / drain electrode of the third transistor T3. The second source / drain electrode of the sixth transistor T6 is connected to the anode electrode of the organic light-emitting diode (OLED).

[0094] The fifth transistor T5 and the sixth transistor T6 are turned on concurrently (e.g., simultaneously) according to the light emission control signal EM so as to drive current to flow into (or through) the organic light emission diode OLED.

[0095] The gate electrode of the seventh transistor T7 is connected to the terminal of the light emission control signal EM. The first source / drain electrode of the seventh transistor T7 is connected to the anode electrode of the organic light-emitting diode (OLED). The second source / drain electrode of the seventh transistor T7 is connected to the terminal of the initialization voltage VINT. The seventh transistor T7 is turned on according to the light emission control signal EM to initialize the anode electrode of the OLED.

[0096] The seventh transistor T7 receives the same emission control signal EM as the fifth transistor T5 and the sixth transistor T6. However, because the seventh transistor T7 is an NMOS transistor, and the fifth and sixth transistors T6 are PMOS transistors, the seventh transistor T7 can be turned on at different timings than the fifth and sixth transistors T6. That is, when the emission control signal EM is high, the seventh transistor T7 is on, and the fifth and sixth transistors T6 are off. When the emission control signal EM is low, the seventh transistor T7 is off, and the fifth and sixth transistors T6 are on. Therefore, the initialization operation of the seventh transistor T7 can be performed outside the emission time when the fifth transistor T5 and the sixth transistor T6 are on, and can also be performed outside the emission time when the fifth transistor T5 and the sixth transistor T6 are off.

[0097] exist Figure 3 The illustrated embodiment shows an example in which the gate electrode of the seventh transistor T7 receives the light emission control signal EM. However, in one or more embodiments, the pixel circuitry may be configured such that the gate electrode of the seventh transistor T7 receives the third scan signal GI.

[0098] The second electrode of capacitor Cst is connected to the terminal of the first power supply voltage ELVDD. The first electrode of capacitor Cst is connected to the gate electrode of the first transistor T1, the second source / drain electrode of the third transistor T3, and the first source / drain electrode of the fourth transistor T4. The cathode electrode of the organic light-emitting diode (OLED) is connected to the terminal of the second power supply voltage ELVSS. The OLED receives drive current from the first transistor T1 and emits light to display an image.

[0099] In the following text, reference will be made to Figure 4 The cross-sectional structure of the display panel 100 is described in detail. Figure 4 An example of the cross-sectional structure of a pixel of the display area DA of the display panel 100 and the non-display area NDA including the curved area BA is shown.

[0100] Figure 4 This is a cross-sectional view showing an example cross-section of the periphery of the pixels of the display area and the curved area of ​​the non-display area according to an embodiment.

[0101] First, refer to Figure 4 Describes the display area DA of the display panel 100.

[0102] The display area DA may include a silicon transistor area AR1 and an oxide transistor area AR2. The silicon transistor area AR1 contains a non-oxide inorganic semiconductor transistor (hereinafter referred to as a "silicon transistor") comprising polycrystalline silicon used as a channel, and the oxide transistor area AR2 contains an oxide semiconductor transistor (hereinafter referred to as a "oxide transistor") comprising an oxide semiconductor used as a channel. The silicon transistor in the silicon transistor area AR1 may be a PMOS transistor, and... Figure 4 In the example, a first transistor T1 is shown as a silicon transistor, used as a driving transistor. The oxide transistor disposed in the oxide transistor region AR2 can be an NMOS transistor, and... Figure 4 In the example shown, a third transistor T3 is illustrated as a compensation transistor, serving as an example of an oxide transistor. In one or more embodiments, the second transistor T2, the fifth transistor T5, and the sixth transistor T6, which are other silicon transistors disposed in the silicon transistor region AR1, may have substantially the same stacking structure as the first transistor T1, and the fourth transistor T4 and the seventh transistor T7, which are other oxide transistors disposed in the oxide transistor region AR2, may have substantially the same stacking structure as the third transistor T3. Silicon transistors and oxide transistors will be described in more detail below.

[0103] A substrate 101, a barrier layer 102, a buffer layer 103, a silicon semiconductor pattern PS including a silicon underside light-shielding pattern 104 and a silicon semiconductor layer 105, a first gate insulating film GI1, a first conductive layer 110, a first interlayer insulating film ILD1, an oxide semiconductor layer 135, a second gate insulating film GI2, a second conductive layer 140, a second interlayer insulating film ILD2, a third conductive layer 150, a first via layer VIA1, a fourth conductive layer 160, a second via layer VIA2, an anode electrode ANO, and a pixel defining film PDL can be sequentially disposed or stacked in the display area DA of the display panel 100. Each of the layers described above can be formed as a single film or can be formed as a stacked film including multiple films. In one or more embodiments, another layer may also be disposed between these layers.

[0104] The substrate 101 supports the various layers disposed thereon. The substrate 101 may be made of an insulating material, such as a polymer resin. Examples of polymer materials may include polyethersulfone (PES), polyacrylate (PA), polyaryl compound (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. The substrate 101 may also include a metallic material.

[0105] The substrate 101 may be a flexible substrate that is bendable, foldable, or rollable. Examples of materials forming the flexible substrate may include PI, but this disclosure is not limited thereto.

[0106] When the organic light-emitting display device is a back-emitting or double-emitting type, a transparent substrate can be used. When the organic light-emitting display device is a top-emitting type, transparent, translucent, and / or opaque substrates can be used.

[0107] A barrier layer 102 may be disposed on the substrate 101. The barrier layer 102 can prevent or reduce the diffusion of impurity ions, prevent or reduce the penetration of moisture or external air, and perform surface planarization. The barrier layer 102 may include silicon nitride, silicon oxide, or silicon oxynitride, etc. Depending on the type of substrate 101 or process conditions, the barrier layer 102 may be omitted.

[0108] A buffer layer 103 may be disposed on the barrier layer 102. The buffer layer 103 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. In one or more embodiments, the buffer layer 103 may be omitted depending on the type of the substrate 101 or the process conditions.

[0109] A silicon semiconductor pattern PS can be disposed on the buffer layer 103. The silicon semiconductor pattern PS can be made of polycrystalline silicon, monocrystalline silicon, or amorphous silicon, etc. The silicon semiconductor pattern PS may include a silicon under-shielding pattern 104 and a silicon semiconductor layer 105. The silicon under-shielding pattern 104 and the silicon semiconductor layer 105 can be made of the same material and can be formed as coplanar. In other words, the silicon under-shielding pattern 104 and the silicon semiconductor layer 105 can be configured to be coplanar (e.g., disposed on the buffer layer 103). The silicon under-shielding pattern 104 can be disposed in the oxide transistor region AR2, and the silicon semiconductor layer 105 can be disposed in the silicon transistor region AR1. For example, in one or more embodiments, the silicon under-shielding pattern 104 is not disposed in the silicon transistor region AR1.

[0110] The silicon under-shielding pattern 104 can be positioned below the oxide semiconductor layer 135 to prevent or substantially prevent downward-incident light from the display panel 100 from entering the oxide semiconductor layer 135 disposed above the silicon under-shielding pattern 104. The silicon under-shielding pattern 104 can (e.g., in the thickness direction) at least overlap with the channel region 135c of the oxide semiconductor layer 135. In one or more embodiments, in Figure 4 In the cross-sectional view shown, the silicon lower light-shielding pattern 104 may (e.g., in the thickness direction) overlap with the entire oxide semiconductor layer 135.

[0111] In one or more embodiments, the silicon under-shielding pattern 104 can be used as another gate electrode of the oxide transistor. In this case, the silicon under-shielding pattern 104 can be connected to the second gate electrode 142. In one or more embodiments, the silicon under-shielding pattern 104 can be connected (e.g., electrically connected) to either the first source / drain electrode 153 or the second source / drain electrode 154 of the transistor disposed in the oxide transistor region AR2.

[0112] The silicon semiconductor layer 105 can be made of polycrystalline silicon. In this case, polycrystalline silicon can be formed by crystallizing amorphous silicon using crystallization methods such as rapid thermal annealing (RTA), solid-state crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), or sequential lateral curing (SLS).

[0113] The silicon semiconductor layer 105 may include a channel region 105c that overlaps with the first gate electrode 111 above it in its thickness direction, and a first source / drain region 105a and a second source / drain region 105b of the silicon semiconductor layer 105 respectively located on one side and the other side of the channel region 105c. The first source / drain region 105a and the second source / drain region 105b of the silicon semiconductor layer 105 may include a plurality of charge carrier ions, and therefore may have higher conductivity and lower resistance than the channel region 105c.

[0114] The silicon semiconductor layer 105 can be the semiconductor layer of each of the first transistor T1, the second transistor T2, the fifth transistor T5 and the sixth transistor T6 described above, and can form the channel of the corresponding transistor.

[0115] The first gate insulating film GI1 can be disposed on a silicon semiconductor pattern PS. The first gate insulating film GI1 may include silicon compounds or metal oxides, etc. For example, the first gate insulating film GI1 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide, etc. The above materials may be used alone or in combination.

[0116] The first gate insulating film GI1 may cover the upper surface of the silicon semiconductor layer 105 except for the portion in which contact holes CNT1 and CNT2 are formed, and in one or more embodiments, the first gate insulating film GI1 may also cover the side surfaces of the silicon semiconductor layer 105. Furthermore, the first gate insulating film GI1 may cover the upper and side surfaces of the silicon under-shielding pattern 104. In one or more embodiments, the first gate insulating film GI1 may be disposed substantially or essentially above the entire surface of the substrate 101.

[0117] A first conductive layer 110 is disposed on a first gate insulating film GI1. The first conductive layer 110 may comprise one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a single film or a multilayer film.

[0118] The first conductive layer 110 may include a first gate electrode 111 disposed in the silicon transistor region AR1.

[0119] The first gate electrode 111 may be the gate electrode of a silicon transistor. The first gate electrode 111 may be connected to the first electrode of a capacitor Cst. The first electrode of the capacitor Cst may be formed using the first gate electrode 111 itself, or using a portion extending from the first gate electrode 111. Therefore, a portion of the pattern of the integrated first conductive layer 110 may include the first gate electrode 111 and the first electrode of the capacitor Cst. For example, a portion of the pattern of the integrated first conductive layer 110 may overlap with the silicon semiconductor layer 105 to serve as the first gate electrode 111 at a corresponding portion, and another portion of the pattern may not overlap with the silicon semiconductor layer 105 to serve as the first electrode of the capacitor Cst, which overlaps with the second electrode 141 of the capacitor Cst above it. As another example, a portion of the pattern of the integrated first conductive layer 110 may overlap with the silicon semiconductor layer 105 to serve as both the first gate electrode 111 and the first electrode of the capacitor Cst.

[0120] A first interlayer insulating film (ILD1) is disposed on the first conductive layer 110. The first interlayer insulating film (ILD1) may include silicon compounds and / or metal oxides, etc. For example, the first interlayer insulating film (ILD1) may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and / or titanium oxide, etc. The above materials may be used alone or in combination.

[0121] The first interlayer insulating film ILD1 may be disposed on the first conductive layer 110 including the first gate electrode 111 to prevent or substantially prevent the first conductive layer 110 from being oxidized by subsequent processes (e.g., high-temperature activation of the silicon semiconductor layer 105). The thickness of the first interlayer insulating film ILD1 may be less than (or less than) the thickness of each of the first gate insulating film GI1 and the second gate insulating film GI2.

[0122] An oxide semiconductor layer 135 is disposed on the first interlayer insulating film ILD1. The oxide semiconductor layer 135 may be disposed in the oxide transistor region AR2. The oxide semiconductor layer 135 may include an oxide semiconductor. The oxide semiconductor may include one or more oxides selected from gallium indium zinc oxide (GIZO), zinc (Zn), indium (In), gallium (Ga), tin (Sn), cadmium (Cd), germanium (Ge), hafnium (Hf), and combinations thereof. The oxide semiconductor may include at least one selected from indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin oxide (IZO).

[0123] The oxide semiconductor layer 135 may include a channel region 135c that overlaps with the second gate electrode 142 above it in its thickness direction, and a first source / drain region 135a and a second source / drain region 135b of the oxide semiconductor layer 135 respectively located on one side and the other side of the channel region 135c. The first source / drain region 135a and the second source / drain region 135b of the oxide semiconductor layer 135 may be conductive regions and may have higher conductivity and lower resistance than the channel region 135c.

[0124] The oxide semiconductor layer 135 can be the semiconductor layer of each of the third transistor T3, the fourth transistor T4 and the seventh transistor T7 described above, and can form the channel of the corresponding transistor.

[0125] A second gate insulating film GI2 is disposed on the oxide semiconductor layer 135. The second gate insulating film GI2 may include silicon compounds or metal oxides, etc. For example, the second gate insulating film GI2 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, or titanium oxide, etc. The above materials may be used alone or in combination.

[0126] The second gate insulating film GI2 can cover the upper surface of the oxide semiconductor layer 135 except for the portion in which contact holes CNT3 and CNT4 are formed, and the second gate insulating film GI2 can also cover the side surface of the oxide semiconductor layer 135. The second gate insulating film GI2 can be disposed substantially above the entire surface of the substrate 101 or extend substantially above the entire surface of the substrate 101.

[0127] In one or more embodiments, the second gate insulating film GI2 may perform different functions depending on its location. For example, a portion of the second gate insulating film GI2 located in the oxide transistor region AR2 may be disposed between the oxide semiconductor layer 135 and the second gate electrode 142 to serve as the gate insulating film of the oxide transistor. In one or more embodiments, a portion of the second gate insulating film GI2 located (e.g., in the thickness direction) in the region (of the silicon transistor region AR1) overlapping with the second electrode 141 of the capacitor Cst and the first electrode of the capacitor Cst connected to the first gate electrode 111 may serve as the dielectric of the capacitor Cst, with another insulating layer (e.g., a first interlayer insulating film ILD1) located between the second electrode 141 of the capacitor Cst and the first electrode of the capacitor Cst connected to the first gate electrode 111. That is, the second electrode 141 of the capacitor Cst and the first electrode of the capacitor Cst connected to the first gate electrode 111 may form the capacitor Cst while facing each other in the overlapping region, with the second gate insulating film GI2 between them. In one or more embodiments, the oxide semiconductor layer 135 of the transistor disposed in the oxide transistor region AR2 may be positioned below a portion of the second gate insulating film GI2, and another portion of the second gate insulating film GI2 may be located on the first interlayer insulating film ILD1, which is located on the gate electrode 111 disposed in the silicon transistor region AR1. In one or more embodiments, in the oxide transistor region AR2, the oxide semiconductor layer 135 is located between the first interlayer insulating film ILD1 and the second gate insulating film GI2, and in the silicon transistor region AR1, the first interlayer insulating film ILD1 and the second gate insulating film GI2 are located between the second electrode 141 of the capacitor Cst and the first electrode of the capacitor Cst connected to the first gate electrode 111.

[0128] As described above, the second gate insulating film GI2 can be used as a gate insulating film in the region overlapping with the oxide semiconductor layer 135 and the second gate electrode 142 of the transistor disposed in the oxide transistor region AR2, and the second gate insulating film GI2 can be used as a dielectric of capacitor Cst in the region overlapping with the second electrode 141 and the first electrode of capacitor Cst. As described above, an insulating film (e.g., the second gate insulating film GI2) can be used as the gate insulating film of the transistor included in the oxide transistor region AR2, and can also be used in another region (e.g., as...) Figure 4 The dielectric of the capacitor Cst in the silicon transistor region AR1 shown is incorporated, and therefore, the manufacturing or fabrication process can be simplified compared to forming individual insulating films separately. Furthermore, the number of insulating films included in the display device 1 is reduced, and thus, the thickness of the display device 1 can be reduced.

[0129] The second conductive layer 140 is disposed on the second gate insulating film GI2. The second conductive layer 140 may include the second electrode 141 of the capacitor Cst disposed in the silicon transistor region AR1 and the second gate electrode 142 of the transistor disposed in the oxide transistor region AR2. The second conductive layer 140 may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a single film or a multilayer film.

[0130] The oxide semiconductor layer 135 of the transistor disposed in the oxide transistor region AR2 may be disposed above the first gate electrode 111 of the transistor disposed in the silicon transistor region AR1, or may be disposed in a layer located above the first gate electrode 111. In one or more embodiments, a portion of the first interlayer insulating film ILD1 is located below the oxide semiconductor layer 135 of the transistor in the oxide transistor region AR2, and another portion of the first interlayer insulating film ILD1 is located above the gate electrode 111 of the transistor in the silicon transistor region AR1. For example, the first interlayer insulating film ILD1 may be stacked on the first gate electrode 111, and the oxide semiconductor layer 135 may be disposed on the first interlayer insulating film ILD1.

[0131] The oxide semiconductor layer 135 of the transistor disposed in the oxide transistor region AR2 may be located below the second electrode 141 of the capacitor Cst disposed in the silicon transistor region AR1, or may be located in a layer below the second electrode 141. In one or more embodiments, a portion of the second gate insulating film GI2 is located above the oxide semiconductor layer 135 of the transistor in the oxide transistor region AR2, and another portion of the second gate insulating film GI2 is located below the second electrode 141 of the capacitor Cst in the silicon transistor region AR1. For example, the second gate insulating film GI2 may be disposed on the oxide semiconductor layer 135 of the transistor disposed in the oxide transistor region AR2 (e.g., on the upper surface and / or on the side surface of the oxide semiconductor layer 135), and the second conductive layer 140 including the second electrode 141 of the capacitor Cst and the second gate electrode 142 of the transistor disposed in the oxide transistor region AR2 may be disposed on the second gate insulating film GI2.

[0132] The second electrode 141 of the capacitor Cst disposed in the silicon transistor region AR1 and the second gate electrode 142 of the transistor disposed in the oxide transistor region AR2, forming the second conductive layer 140, can be made of the same material or comprise the same material. Furthermore, the second electrode 141 and the second gate electrode 142 of the capacitor Cst can be formed as coplanar (e.g., as shown in the image). Figure 4 As shown in the diagram, (shared plane).

[0133] Specifically, the second electrode 141 of the capacitor Cst disposed in the silicon transistor region AR1 and the second gate electrode 142 of the transistor disposed in the oxide transistor region AR2 can both be disposed on the same insulating film (e.g., the second gate insulating film GI2).

[0134] Furthermore, the second electrode 141 of the capacitor Cst disposed in the silicon transistor region AR1 and the second gate electrode 142 of the transistor disposed in the oxide transistor region AR2 can be formed concurrently (e.g., simultaneously) using a single mask. As described above, the second gate electrode 142 of the transistor disposed in the oxide transistor region AR2 is not formed using a separate conductive layer through a separate mask process, but is formed concurrently (e.g., simultaneously) with the second electrode 141 of the capacitor Cst disposed in the silicon transistor region AR1 using the same mask, and therefore, the number of mask processes can be reduced.

[0135] The second interlayer insulating film ILD2 is disposed on the second conductive layer 140. The second interlayer insulating film ILD2 may include silicon compounds or metal oxides, etc. For example, the second interlayer insulating film ILD2 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide and / or titanium oxide, etc. The above materials may be used alone or in combination.

[0136] The thickness of the second interlayer insulating film ILD2 can be greater than the thickness of each of the first gate insulating film GI1, the second gate insulating film GI2, and the first interlayer insulating film ILD1 described above. Furthermore, the second interlayer insulating film ILD2 can be formed of the same material as the first interlayer insulating film ILD1, but this disclosure is not limited thereto.

[0137] The third conductive layer 150 is disposed on the second interlayer insulating film ILD2. The third conductive layer 150 may include one or more metals selected from aluminum (Al), molybdenum (Mo), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0138] The third conductive layer 150 may include a first source / drain electrode 151 and a second source / drain electrode 152 of a transistor disposed in the silicon transistor region AR1, and a first source / drain electrode 153 and a second source / drain electrode 154 of a transistor disposed in the oxide transistor region AR2.

[0139] In the transistor disposed in the silicon transistor region AR1, the first source / drain electrode 151 can be connected to the first source / drain region 105a of the silicon semiconductor layer 105 through the first contact hole CNT1. The first contact hole CNT1 passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, the first interlayer insulating film ILD1, and the first gate insulating film GI1 and exposes the first source / drain region 105a of the silicon semiconductor layer 105. The second source / drain electrode 152 can be connected to the second source / drain region 105b of the silicon semiconductor layer 105 through the second contact hole CNT2. The second contact hole CNT2 passes through the second interlayer insulating film ILD2, the second gate insulating film GI2, the first interlayer insulating film ILD1, and the first gate insulating film GI1 and exposes the second source / drain region 105b of the silicon semiconductor layer 105.

[0140] In the transistor disposed in the oxide transistor region AR2, the first source / drain electrode 153 can be connected to the first source / drain region 135a of the oxide semiconductor layer 135 through the third contact hole CNT3. The third contact hole CNT3 passes through the second interlayer insulating film ILD2 and the second gate insulating film GI2 and exposes the first source / drain region 135a of the oxide semiconductor layer 135. The second source / drain electrode 154 can be connected to the second source / drain region 135b of the oxide semiconductor layer 135 through the fourth contact hole CNT4. The fourth contact hole CNT4 passes through the second interlayer insulating film ILD2 and the second gate insulating film GI2 and exposes the second source / drain region 135b of the oxide semiconductor layer 135.

[0141] The first via layer VIA1 is disposed on the third conductive layer 150. The first via layer VIA1 may include inorganic or organic insulating materials, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and / or benzocyclobutene (BCB), etc.

[0142] A fourth conductive layer 160 is disposed on the first via layer VIA1. The fourth conductive layer 160 may comprise one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer 110 may be a single film or a multilayer film.

[0143] The fourth conductive layer 160 may include a connection electrode 161 and an upper light-shielding pattern 163. The fifth contact hole CNT5, which exposes the second source / drain electrode 152 of the transistor disposed in the silicon transistor region AR1, may be disposed in the first via layer VIA1, and the connection electrode 161 may be connected to the second source / drain electrode 152 through the fifth contact hole CNT5.

[0144] The upper light-shielding pattern 163 can be used to prevent or substantially prevent light incident from the display panel 100 in the upward direction (e.g., the thickness direction) from entering the oxide semiconductor layer 135 positioned below the upper light-shielding pattern 163. The upper light-shielding pattern 163 can be configured to at least overlap with the channel region 135c of the oxide semiconductor layer 135. In one or more embodiments, the upper light-shielding pattern 163 can be configured such that... Figure 4 The cross-sectional view shown overlaps with the entire oxide semiconductor layer 135.

[0145] The second via layer VIA2 is disposed on the connecting electrode 161. The second via layer VIA2 may include inorganic insulating materials and / or organic insulating materials, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin and / or BCB, etc.

[0146] An anode electrode ANO is disposed on the second via layer VIA2. The anode electrode ANO can be an anode electrode. For each pixel, the anode electrodes ANO can be disposed separately from each other. The anode electrode ANO can be connected (e.g., electrically connected) to the connection electrode 161 through a sixth contact hole CNT6, which passes through the second via layer VIA2 and exposes a portion of the connection electrode 161.

[0147] The anode electrode (ANO) is not limited to this and may have a stacked film structure in which layers of materials with high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3), and reflective material layers, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or mixtures thereof, are stacked. The layer with high work function may be disposed above the reflective material layer and may be disposed close to the light-emitting layer (EL). The anode electrode (ANO) may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, and ITO / Ag / ITO, but this disclosure is not limited thereto.

[0148] A pixel-defining film (PDL) can be disposed on the anode electrode (ANO). The PDL may include openings that partially expose the anode electrode (ANO). The PDL may be made of organic or inorganic insulating materials. For example, the PDL may include at least one of polyimide resin, acrylic resin, silicone compound, and polyacrylic resin.

[0149] The light-emitting layer EL is disposed on the anode electrode ANO exposed by the pixel-defined film PDL. The light-emitting layer EL may include an organic material layer. The organic material layer of the light-emitting layer may include an organic light-emitting layer, and may also include a hole injection / transport layer and / or an electron injection / transport layer.

[0150] The cathode electrode CAT can be disposed on the light-emitting layer EL. The cathode electrode CAT can be a common electrode disposed above all pixels PX without distinguishing between pixels PX. Each of the anode electrode ANO, the light-emitting layer EL, and the cathode electrode CAT can form an organic light-emitting element.

[0151] The cathode electrode CAT may include a material layer having a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, compounds thereof, or mixtures thereof (e.g., mixtures of Ag and Mg). The cathode electrode CAT may also include a transparent metal oxide layer disposed on the material layer having a low work function.

[0152] An anode (ANO), a light-emitting layer (EL), and a cathode (CAT) can constitute an organic light-emitting element.

[0153] A thin-film encapsulation layer 170, comprising a first inorganic film 171, a first organic film 172, and a second inorganic film 173, is disposed above the cathode electrode CAT. The first inorganic film 171 and the second inorganic film 173 may contact each other at their ends. The first organic film 172 may be sealed by the first inorganic film 171 and the second inorganic film 173.

[0154] Each of the first inorganic membrane 171 and the second inorganic membrane 173 may include silicon nitride, silicon oxide, and / or silicon oxynitride, etc. The first organic membrane 172 may include an organic insulating material.

[0155] The non-display area NDA will be described below.

[0156] In the non-display area NDA of the display panel 100, the substrate 101, barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, second gate insulating film GI2, second interlayer insulating film ILD2, first via layer VIA1, fourth conductive layer 160, second via layer VIA2 and pixel limiting film PDL can be sequentially arranged or stacked.

[0157] The non-display area NDA may include the curved area BA and the curved opening OP1.

[0158] In the non-display area NDA, the curved region BA can be a region in which the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, second gate insulating film GI2, and second interlayer insulating film ILD2 are not disposed, and where the upper surface of the substrate 101 is exposed. In one or more embodiments, the side portions of the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, second gate insulating film GI2, and / or second interlayer insulating film ILD2 define a curved opening OP1 that exposes the upper surface of the substrate 101 located in the curved region BA. In one or more embodiments, as Figure 4 As shown, the curved opening OP1 can be conical and / or stepped.

[0159] In the non-display area NDA, the bent opening OP1 can pass through the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, second gate insulating film GI2 and / or second interlayer insulating film ILD2, and expose a portion of the substrate 101. In the bent opening OP1, the side surfaces of the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, second gate insulating film GI2 and second interlayer insulating film ILD2 can be exposed. The exposed side surfaces of the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, second gate insulating film GI2 and second interlayer insulating film ILD2 can be arranged relative to each other, but this disclosure is not limited thereto.

[0160] The curved opening OP1 can be formed by the process operations of forming the first contact hole CNT1 to the fourth contact hole CNT4, which will be described in more detail below. By forming the curved opening OP1, bending stress that may occur when the display device 1 described above is bent in the curved region BA can be prevented or reduced.

[0161] The curved opening OP1 can be filled with a first via layer VIA1. The first via layer VIA1 can be disposed on the second interlayer insulating film ILD2 located in the non-display area NDA, and can be disposed on the exposed side surfaces of the barrier layer 102, buffer layer 103, first gate insulating film GI1, first interlayer insulating film ILD1, second gate insulating film GI2, and second interlayer insulating film ILD2 located in the curved area BA. The first via layer VIA1 can contact (e.g., in direct contact) the exposed upper surface of the substrate 101.

[0162] In the non-display area NDA and the curved area BA, a connecting line 165 may be disposed on the first via layer VIA1. The connecting line 165 may be formed by a fourth conductive layer 160. The connecting line 165 may be formed concurrently (e.g., simultaneously) with the connecting electrode 161 and / or the upper light-shielding pattern 163 described above, and may be made of the same material as the material forming the connecting electrode 161 and / or the upper light-shielding pattern 163.

[0163] like Figure 4 As shown, the second via layer VIA2 and the pixel defining film PDL can be disposed on the connecting line 165. However, in one or more embodiments, at least one of the second via layer VIA2 and the pixel defining film PDL can be omitted in the non-display area NDA.

[0164] Hereinafter, a method for manufacturing a display device according to an embodiment will be described.

[0165] Figure 5This is a flowchart illustrating a method for manufacturing a display device according to an embodiment, and Figures 6 to 17 This is a cross-sectional view illustrating the process operation of a method for manufacturing a display device according to one or more embodiments.

[0166] Reference Figure 5 and Figure 6 A substrate 101 is provided, in which a display area DA (including a silicon transistor area AR1 and an oxide transistor area AR2) and a non-display area NDA disposed around the display area DA are defined, and a silicon semiconductor pattern PS (S01) including a silicon semiconductor layer 105 disposed in the silicon transistor area AR1 and a silicon lower light-shielding pattern 104 disposed in the oxide transistor area AR2 is disposed on the substrate 101.

[0167] In one or more embodiments, a barrier layer 102 and a buffer layer 103 are sequentially stacked on a substrate 101, and a silicon semiconductor layer 105 and a silicon under-mask pattern 104 are concurrently (e.g., simultaneously) formed on the buffer layer 103. The patterned silicon semiconductor layer 105 and the patterned silicon under-mask pattern 104 can be formed using a single masking process (e.g., the same mask). That is, material for the silicon semiconductor layer can be deposited across the entire surface of the buffer layer 103, and then the material for the silicon semiconductor layer can be patterned using a photolithography process, such that... Figure 6 As shown, a silicon semiconductor pattern PS comprising a silicon semiconductor layer 105 and a silicon underside light-shielding pattern 104 can be formed (e.g., concurrently formed).

[0168] Subsequently, referring to Figure 7 A first gate insulating film GI1 is formed on a silicon semiconductor pattern PS, and a first conductive layer 110 (S02) including a first gate electrode 111 is formed on the first gate insulating film GI1.

[0169] In one or more embodiments, a first gate insulating film GI1 is formed on the entire surface (e.g., the entire exposed surface) of a buffer layer 103 on which a silicon semiconductor layer 105 is formed. Subsequently, a first gate electrode 111 is formed on the first gate insulating film GI1. That is, a material layer for the first conductive layer 110 can be deposited on the entire surface of the first gate insulating film GI1, and the material layer for the first conductive layer 110 can be patterned by a photolithography process, such that... Figure 7 As shown, a first gate electrode 111 can be formed.

[0170] Subsequently, referring to Figure 8 A first interlayer insulating film ILD1 is formed on the first gate electrode 111, and an oxide semiconductor layer 135 (S03) is formed on the first interlayer insulating film ILD1.

[0171] In one or more embodiments, a first interlayer insulating film ILD1 is formed on the entire surface (e.g., the entire exposed surface) of a first gate insulating film GI1 on which a first gate electrode 111 is formed. Subsequently, an oxide semiconductor layer 135 is formed on the first interlayer insulating film ILD1. The oxide semiconductor layer 135 can be formed by a mask process. For example, material for the oxide semiconductor layer can be deposited on the entire surface of the first interlayer insulating film ILD1, and then the material for the oxide semiconductor layer can be patterned by a photolithography process, such that... Figure 8 As shown, an oxide semiconductor layer 135 can be formed.

[0172] Subsequently, referring to Figure 9 A second gate insulating film GI2 is formed on the oxide semiconductor layer 135, and a second conductive layer 140 (S04) including a second electrode 141 and a second gate electrode 142 of a capacitor Cst is formed on the second gate insulating film GI2.

[0173] In one or more embodiments, a second gate insulating film GI2 is deposited on the entire surface (e.g., the entire exposed surface) of a first interlayer insulating film ILD1 on which an oxide semiconductor layer 135 is disposed, and a patterned second electrode 141 and a patterned second gate electrode 142 of a capacitor Cst are concurrently (e.g., simultaneously) formed on the second gate insulating film GI2. The patterned second electrode 141 and the patterned second gate electrode 142 of the capacitor Cst can be formed by a single mask process (e.g., the same mask). That is, material for the second conductive layer can be deposited on the entire surface of the second gate insulating film GI2, and the material for the second conductive layer can be patterned by a photolithography process, such that... Figure 9 As shown, a second conductive layer 140 can be formed, including a second electrode 141 and a second gate electrode 142 of a capacitor Cst.

[0174] Subsequently, referring to Figure 10 A second interlayer insulating film ILD2 is stacked on a second conductive layer 140 including a second electrode 141 and a second gate electrode 142 of a capacitor Cst, and a first contact hole CNT1 and a second contact hole CNT2 (S05) are formed in the display area DA to expose a portion of the silicon semiconductor layer 105.

[0175] Contact holes CNT1 and CNT2 can be formed using a single mask process (e.g., the same mask). The first contact hole CNT1 and the second contact hole CNT2 can be formed concurrently (e.g., simultaneously) using the same mask. For example, an insulating layer for the second interlayer insulating film is deposited on the entire surface of the first interlayer insulating film ILD1, on which the oxide semiconductor layer 135, the second gate insulating film GI2, and the second gate electrode 142 are formed. Subsequently, a first photoresist pattern PR1 exposing a portion of the silicon semiconductor layer 105 is formed on the insulating layer for the second interlayer insulating film, and the first photoresist pattern PR1 is used as an etching mask to etch the insulating layer for the second interlayer insulating film, the first interlayer insulating film ILD1, and the first gate insulating film GI1, thereby forming the first contact hole CNT1 and the second contact hole CNT2 exposing a portion of the silicon semiconductor layer 105.

[0176] Additionally, in the non-display area NDA, the curved opening OP1 can be formed without any additional processes by forming the first contact hole CNT1 and the second contact hole CNT2 in operation S05 and the third contact hole CNT3 and the fourth contact hole CNT4 in operation S06, which will be described in more detail below. A portion of the curved opening OP1 can also be formed by forming the first contact hole CNT1 and the second contact hole CNT2 in operation S05.

[0177] Specifically, the first photoresist pattern PR1 can be formed to expose a portion of the silicon semiconductor layer 105 (e.g., the upper surface) and the curved opening OP1 of the curved region BA. When etching is performed using the first photoresist pattern PR1, the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the first gate insulating film GI1 located in the curved region BA can be etched concurrently (e.g., simultaneously) in operation S05, which forms the first contact hole CNT1 and the second contact hole CNT2, and thus a portion of the buffer layer 103 in the corresponding region can be exposed. In operation S05, the first contact hole CNT1 and the second contact hole CNT2 are etched to expose a portion of the silicon semiconductor layer 105, and therefore, the silicon semiconductor layer 105 may also be partially etched or damaged during the etching process. To minimize or reduce damage to the silicon semiconductor layer 105, operation S05 can be performed to etch only the second interlayer insulating film ILD2, the first interlayer insulating film ILD1, and the first gate insulating film GI1 located in the curved region BA. Therefore, in operation S05, the buffer layer 103 located in the non-display area NDA can be retained instead of being removed. The curved opening OP1, which exposes the surface of the substrate 101, can be formed (e.g., fully formed) by operation S06, which forms the third contact hole CNT3, the fourth contact hole CNT4, and the curved opening OP1, as will be described in more detail below.

[0178] Subsequently, referring to Figure 11 The third contact hole CNT3 and the fourth contact hole CNT4 (S06) are formed to expose a portion of the oxide semiconductor layer 135.

[0179] Contact holes CNT3 and CNT4 can be formed using a mask process. The third contact hole CNT3 and the fourth contact hole CNT4 can be formed concurrently (e.g., simultaneously) using the same mask. For example, a second photoresist pattern PR2 is formed on a second interlayer insulating film ILD2 in which the first contact hole CNT1 and the second contact hole CNT2 are formed, exposing a portion of the oxide semiconductor layer 135, and the second photoresist pattern PR2 is used as an etching mask to etch the second interlayer insulating film ILD2 to form the third contact hole CNT3 and the fourth contact hole CNT4 exposing a portion of the oxide semiconductor layer 135.

[0180] Additionally, the process of forming a curved opening OP1 in the non-display area NDA can be completed through operation S06. The buffer layer 103 and the barrier layer 102, which were not etched in operation S05 when forming the first contact hole CNT1 and the second contact hole CNT2, can be etched in operation S06, and thus the process of forming a curved opening OP1 that exposes a portion of the substrate 101 (e.g., the upper surface) can be completed.

[0181] Specifically, the thickness of each of the buffer layer 103 and the barrier layer 102 can be similar to the thickness of each of the second interlayer insulating film ILD2 and the second gate insulating film GI2. That is, when etching the buffer layer 103 and the barrier layer 102, the method of etching the above components can be substantially the same as the method of etching the second interlayer insulating film ILD2 and the second gate insulating film GI2, and no separate process is required. Therefore, the process operation of forming the curved opening OP1 can be completed by etching the buffer layer 103 and the barrier layer 102 in operation S06.

[0182] Subsequently, referring to Figure 12A patterned third conductive layer 150 is formed on the second interlayer insulating film ILD2 (S07). The patterned third conductive layer 150 can be formed by a mask process. For example, a material layer for the third conductive layer is deposited on the entire surface of the second interlayer insulating film ILD2. In the deposition process, the material layer for the third conductive layer can be deposited on the inside of the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4. Therefore, the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor disposed in the silicon transistor region AR1, and the first source / drain electrode 153 and the second source / drain electrode 154 of the transistor disposed in the oxide transistor region AR2 can be connected to the silicon semiconductor layer 105 and the oxide semiconductor layer 135, respectively. Subsequently, a photoresist layer is deposited on the material layer for the third conductive layer, a photoresist pattern is formed by exposure and development, and then the photoresist pattern is used as an etching mask to etch the material layer for the third conductive layer. Subsequently, the photoresist pattern is removed by a stripping or ashing process, and thus, as Figure 12 As shown, a fully patterned third conductive layer 150 is formed.

[0183] Subsequently, referring to Figure 13 A first via layer VIA1 is formed on the third conductive layer 150, and a fifth contact hole CNT5 (S08) is formed to expose a portion of the first source / drain electrode 151 and a portion of the second source / drain electrode 152 of the transistor disposed in the silicon transistor region AR1.

[0184] The first via layer VIA1 may include, for example, an organic material, including a photosensitive material. The first via layer VIA1 may be stacked over the display area DA and the non-display area NDA and may have a generally flat surface. In this case, the curved opening OP1 of the curved region BA of the non-display area NDA may also be filled with the first via layer VIA1. After depositing the organic material layer for the via layer, a fifth contact hole CNT5, exposing a portion of the first source / drain electrode 151 and a portion of the second source / drain electrode 152 of the transistor disposed in the silicon transistor region AR1, can be formed in the first via layer VIA1 by exposure and development.

[0185] Subsequently, referring to Figure 14 A fourth conductive layer 160 (S09) is formed on the first via layer VIA1.

[0186] The fourth conductive layer 160 may include a connection electrode 161 disposed in the display area DA, an upper light-shielding pattern 163, and a connection line 165 disposed in the non-display area NDA. The patterned fourth conductive layer 160 can be formed by a masking process. For example, a material layer for the fourth conductive layer is deposited on the entire surface of the first via layer VIA1. In the deposition process, the material layer for the fourth conductive layer may be deposited on the inside of the fifth contact hole CNT5. In one or more embodiments, the connection electrode 161 may be formed such that the connection electrode 161 contacts the second source / drain electrode 152. Therefore, the connection electrode 161 can be connected (e.g., electrically connected) to the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor disposed in the silicon transistor region AR1. Subsequently, a photoresist layer is deposited on the material layer for the fourth conductive layer, a photoresist pattern is formed by exposure and development, and then the photoresist pattern is used as an etching mask to etch the material layer for the fourth conductive layer. Thereafter, the photoresist pattern is removed by a stripping or ashing process, and thus, as... Figure 14 As shown, a patterned fourth conductive layer 160 is formed (e.g., fully formed).

[0187] Subsequently, referring to Figure 15 A second via layer VIA2 is formed on the fourth conductive layer 160, and a sixth contact hole CNT6 (S10) is formed to expose a portion of the connecting electrode 161.

[0188] The second via layer VIA2 may include, for example, an organic material, including a photosensitive material. The second via layer VIA2 may be stacked only in the display area DA and may have a generally or substantially flat surface. After depositing the organic material layer for the via layer, a sixth contact hole CNT6 exposing a portion of the connection electrode 161 can be formed in the second via layer VIA2 by exposure and development.

[0189] Subsequently, referring to Figure 16 An anode electrode ANO(S11) is formed on the second via layer VIA2.

[0190] A patterned anode electrode ANO can be formed using a masking process. Specifically, a material layer for the anode electrode is deposited on the entire surface of the second via layer VIA2. In the deposition process, the material layer for the anode electrode can be deposited on the inside of the sixth contact hole CNT6 and connected (e.g., electrically connected) to the connection electrode 161.

[0191] Subsequently, referring to Figure 17 A patterned pixel-defining film PDL (S12) is formed on a second via layer VIA2 in which an anode electrode ANO is formed.

[0192] Pixel-defined films (PDLs) can include, for example, organic materials, including photosensitive materials. In this case, a patterned pixel-defined film (PDL) can be formed by coating an organic material layer for the embankment layer and then performing exposure and development.

[0193] The pixel defining film (PDL) can be formed along the boundary of the pixel (PX) and can partially overlap with the anode electrode (ANO). The PDL can be formed to overlap with the sixth contact hole (CNT6). When the internal space of the sixth contact hole (CNT6) is not completely filled by the anode electrode (ANO) and is only partially filled by the anode electrode (ANO) (e.g., the anode electrode (ANO) formed on the surface of the second via layer (VIA2) defines a gap), the internal space (e.g., the gap) of the sixth contact hole (CNT6) can be completely filled by the pixel defining film (PDL).

[0194] As described above, according to the illustrated embodiment, the second electrode 141 of the capacitor Cst disposed in the silicon transistor region AR1 and the second gate electrode 142 of the transistor disposed in the oxide transistor region AR2 can be formed using a single mask. That is, when forming the second electrode 141 and the second gate electrode 142 of the capacitor Cst, two mask processes are not required, and only one mask process can be used to form both components. Therefore, the number of mask processes can be reduced, and thus, process efficiency can be improved.

[0195] Additional embodiments will be described below. In the embodiments below, the same configurations as those described above will be omitted or simplified, and the differences between the following embodiments and the embodiments described above will be described.

[0196] Figure 18 This is a cross-sectional view of a display device according to another embodiment.

[0197] Reference Figure 18 The display device 1_1 according to the illustrated embodiment and Figure 4 The difference in the display device in the embodiment is that the lower metal light-shielding pattern 112_1 is disposed on the first gate insulating film GI1 and forms the first conductive layer 110.

[0198] In the illustrated embodiment, the lower metal light-shielding pattern 112_1 can be disposed in the oxide transistor region AR2. Figure 4 The silicon lower light-shielding pattern 104 in the embodiment is different. The metal lower light-shielding pattern 112_1 can form a first conductive layer 110 and can be formed to be coplanar with the first gate electrode 111 of the transistor disposed in the silicon transistor region AR1.

[0199] In other words, the first conductive layer 110 in the illustrated embodiment may include a lower metal light-shielding pattern 112_1 and a first gate electrode 111. The lower metal light-shielding pattern 112_1 and the first gate electrode 111 may be disposed together on the first gate insulating film GI1 (e.g., at two different portions of the first gate insulating film GI1). Furthermore, in operation S02 of forming the first conductive layer 110, the lower metal light-shielding pattern 112_1 and the first gate electrode 111 can be formed together using a mask. Therefore, a separate process is not required to form the lower metal light-shielding pattern 112_1, and thus, the number of masks used to form the lower metal light-shielding pattern 112_1 and the first gate electrode 111 can be reduced compared to other mask processes.

[0200] Furthermore, in the illustrated embodiment, the lower metal shading pattern 112_1 can be used as another gate electrode of the transistor disposed in the oxide transistor region AR2. In this case, because the lower metal shading pattern 112_1 faces the oxide semiconductor layer 135, and only the first interlayer insulating film ILD1 is between the lower metal shading pattern 112_1 and the oxide semiconductor layer 135, the lower metal shading pattern 112_1 can be positioned closer to the oxide semiconductor layer 135. Therefore, the lower metal shading pattern 112_1 can operate more smoothly as a gate electrode.

[0201] In addition, the second gate electrode 142 and the second electrode 141 of the capacitor Cst are formed concurrently (e.g., simultaneously) using the same mask (e.g., a single mask), thus reducing the number of mask processes.

[0202] Figure 19 This is a cross-sectional view of a display device according to yet another embodiment.

[0203] Reference Figure 19 The display device 1_2 according to the illustrated embodiment and Figure 18 The difference between the display device 1_1 in the embodiment is that the display device 1_2 includes a silicon lower light-shielding pattern 104 and a metal lower light-shielding pattern 112_2.

[0204] Specifically, the display device 1_2 according to the illustrated embodiment may include both a silicon under-shielding pattern 104 and a metal under-shielding pattern 112_2 disposed in the oxide transistor region AR2. The silicon under-shielding pattern 104 may be formed coplanar with the silicon semiconductor layer 105 of the silicon semiconductor, and the metal under-shielding pattern 112_2 may be disposed above the silicon under-shielding pattern 104 and at least partially overlap with the silicon under-shielding pattern 104 (e.g., in the thickness direction).

[0205] Furthermore, in the illustrated embodiment, the second gate electrode 142 and the second electrode 141 of the capacitor Cst are formed concurrently (e.g., simultaneously) using the same mask, thus reducing the number of mask processes.

[0206] Figure 20 This is a cross-sectional view of a display device according to another embodiment.

[0207] Reference Figure 20 The display device 1_3 according to the illustrated embodiment and Figure 4 The difference in the embodiment of the display device 1 is that the oxide semiconductor layer 135_3 disposed in the oxide transistor region AR2 is disposed on the first gate insulating film GI1.

[0208] Specifically, such as Figure 4 As shown, a first interlayer insulating film ILD1 can be disposed on a first gate electrode 111, which is disposed in the silicon transistor region AR1. Figure 4 Unlike the embodiment where the oxide semiconductor layer 135 disposed in the oxide transistor region AR2 is disposed on the first interlayer insulating film ILD1, in the illustrated embodiment, the oxide semiconductor layer 135_3 disposed in the oxide transistor region AR2 can be disposed on the first gate insulating film GI1 and can be formed to be coplanar with the first gate electrode 111 disposed in the silicon transistor region AR1. In other words, the first gate electrode 111 and the oxide semiconductor layer 135_3 can both be disposed on the same insulating film (e.g., the first gate insulating film GI1).

[0209] Furthermore, only one insulating film (e.g., a second gate insulating film GI2) can be positioned between the first gate electrode 111 and the second electrode 141 of the capacitor Cst, and thus, the distance between the first electrode of the capacitor Cst connected to the first gate electrode 111 and the second electrode 141 of the capacitor Cst can be reduced. Therefore, the capacitance of the capacitor Cst formed between the first electrode of the capacitor Cst connected to the first gate electrode 111 and the second electrode 141 of the capacitor Cst can be further increased.

[0210] Furthermore, in the illustrated embodiment, the second gate electrode 142 and the second electrode 141 of the capacitor Cst are formed concurrently (e.g., simultaneously) using the same mask, and thus, the number of mask processes can be reduced.

[0211] Figure 21 This is a cross-sectional view of a display device according to another embodiment.

[0212] Reference Figure 21 The display device 1_4 according to the illustrated embodiment and Figure 4The difference in the embodiment of the display device 1 is that the display device 1_4 does not include the second via layer VIA2 and the fourth conductive layer 160, and includes a bent via layer VIA0 in the non-display area NDA.

[0213] Specifically, in the non-display area NDA, the bent opening OP1 may be filled with a bent via layer VIA0 instead of the first via layer VIA1. The bent via layer VIA0 may comprise inorganic or organic insulating materials, such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and / or BCB, etc. The bent via layer VIA0 may be a single film or a multilayer film formed as stacked films of different materials. The bent via layer VIA0 may be made of the same material as the first via layer VIA1, but this disclosure is not limited thereto.

[0214] The non-display area line 155_4 can be disposed on the curved via layer VIA0. The non-display area line 155_4 can be formed by the third conductive layer 150. The non-display area line 155_4 can be formed together with the first source / drain electrode 151 and the second source / drain electrode 152 of the transistor disposed in the silicon transistor region AR1 and the first source / drain electrode 153 and the second source / drain electrode 154 of the transistor disposed in the oxide transistor region AR2, and can be made of the same material as the material forming components 151, 152, 153 and 154.

[0215] The first via layer VIA1 can be disposed on the non-display area line 155_4, and the first via layer VIA1 can be formed concurrently (e.g., simultaneously) with the first via layer VIA1 located in the display area DA, so as to have a height substantially the same as the height of the first via layer VIA1 in the display area DA.

[0216] In the display area DA, the anode electrode ANO and the pixel defining film PDL can be formed on the first via layer VIA1, and the anode electrode ANO can be stacked in the fifth contact hole CNT5_4.

[0217] Furthermore, in the illustrated embodiment, the second gate electrode 142 and the second electrode 141 of the capacitor Cst are formed concurrently (e.g., simultaneously) using the same mask, and thus, the number of mask processes can be reduced.

[0218] The manufacturing process will be described below. Figure 21 The method of the display device in the embodiment of the present invention.

[0219] Figure 22 It shows the manufacturing basis Figure 21 A partial flowchart of a method for displaying a device according to an embodiment. Figures 23 to 25 It shows the manufacturing basis Figure 21 A cross-sectional view of the process operation of the method for displaying the device according to an embodiment.

[0220] Reference Figure 22 and Figure 23 As described above, the curved opening OP1 can be formed by operations S05 and S06, which form the first contact hole CNT1, the second contact hole CNT2, the third contact hole CNT3, and the fourth contact hole CNT4. After operations S05 and S06, a curved via layer VIA0 can be formed in the curved opening OP1 (S06_4). The curved opening OP1 can be filled with the curved via layer VIA0, and the curved via layer VIA0 can contact the upper surface of the substrate 101 in the curved opening OP1, and contact the side surfaces of the barrier layer 102, the buffer layer 103, the first gate insulating film GI1, the first interlayer insulating film ILD1, the second gate insulating film GI2, and the second interlayer insulating film ILD2, as well as the upper surface of the second interlayer insulating film ILD2.

[0221] Subsequently, referring to Figure 24 and Figure 25 A third conductive layer 150 can be formed on the second interlayer insulating film ILD2 and the bent via layer VIA0 (S07). The third conductive layer 150 may include a first source / drain electrode 151 and a second source / drain electrode 152 of a transistor disposed in the silicon transistor region AR1, a first source / drain electrode 153 and a second source / drain electrode 154 of a transistor disposed in the oxide transistor region AR2, and a non-display area line 155_4 disposed on the bent via layer VIA0.

[0222] A first via layer VIA1 (S08) can be formed on the third conductive layer 150. The first via layer VIA1 can have the same height in the display area DA and the non-display area NDA.

[0223] While embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications can be made without departing from the scope of the disclosure and without altering the essential features set forth in the claims and their equivalents. Therefore, the above embodiments should be considered in a descriptive sense only and not for limiting purposes.

Claims

1. A display device, wherein, The display device includes: substrate; A buffer layer is located on the substrate; A first semiconductor layer is located on the buffer layer; A first gate insulating film is located on the first semiconductor layer; A first conductive layer is located on the first gate insulating film, and the first conductive layer includes a first gate electrode and a first electrode of a capacitor connected to the first gate electrode; The first interlayer insulating film is located on the first conductive layer; The second semiconductor layer is located on the first interlayer insulating film, and the second semiconductor layer is located in a different layer than the first semiconductor layer; The second gate insulating film is located on the first conductive layer and the second semiconductor layer; The second conductive layer is located on the second gate insulating film, and the second conductive layer includes a second gate electrode that overlaps with the second semiconductor layer and a second electrode of the capacitor that overlaps with the first electrode of the capacitor; A second interlayer insulating film is located on the second conductive layer; and A third conductive layer is located on the second interlayer insulating film, and the third conductive layer includes a first source electrode and a first drain electrode connected to the first semiconductor layer, and a second source electrode and a second drain electrode connected to the second semiconductor layer. The first interlayer insulating film is located between the first conductive layer and the second semiconductor layer. The display device includes a display area and a non-display area arranged around the display area and including a curved region, the curved region including a curved opening through the buffer layer and exposing the surface of the substrate. In the curved region, the buffer layer includes a first portion and a second portion arranged sequentially from the curved opening, wherein the thickness of the first portion is less than the thickness of the second portion.

2. The display device according to claim 1, wherein, The curved opening also passes through the second interlayer insulating film, the second gate insulating film, the first interlayer insulating film, and the first gate insulating film, and The display device further includes a first via layer disposed on the third conductive layer, the first via layer filling the curved opening.

3. The display device according to claim 2, wherein, The second gate insulating film is located between the first gate electrode and the second electrode of the capacitor, and the second gate insulating film is located between the second semiconductor layer and the second gate electrode.

4. The display device according to claim 1, wherein, The display device further includes a lower light-shielding pattern that overlaps with at least a portion of the second semiconductor layer. The lower light-shielding pattern is located below the second semiconductor layer.

5. The display device according to claim 4, wherein, The lower light-shielding pattern is coplanar with the first semiconductor layer and comprises the same material as the first semiconductor layer.

6. The display device according to claim 4, wherein, The first interlayer insulating film is located between the lower light-shielding pattern and the second semiconductor layer.

7. The display device according to claim 6, wherein, The lower light-shielding pattern includes a metal lower light-shielding pattern that is coplanar with the first gate electrode, and includes the same material as the first gate electrode.

8. The display device according to claim 6, wherein, The second semiconductor layer is located above the first conductive layer.

9. The display device according to claim 6, wherein, Multiple insulating films are located between the first gate electrode and the second electrode of the capacitor, and at least one of the multiple insulating films is located between the second semiconductor layer and the second gate electrode.

10. The display device according to claim 4, wherein, The lower light-shielding pattern is connected to the second gate electrode, or to either the second source electrode or the second drain electrode.

11. A display device, wherein, The display device includes: Buffer layer; A first transistor is disposed on a buffer layer and includes a non-oxide semiconductor located on the first layer; A second transistor is disposed on a buffer layer and includes an oxide semiconductor located on a second layer, which is different from the first layer on which the non-oxide semiconductor is located; and capacitor, The first electrode of the capacitor and the gate electrode of the first transistor are formed by a first conductive layer, and the first electrode of the capacitor is connected to the gate electrode of the first transistor. The gate electrode of the second transistor and the second electrode of the capacitor are formed of a second conductive layer that is different from the first conductive layer. The source / drain electrodes of the first transistor and the source / drain electrodes of the second transistor are formed of a third conductive layer that is different from the first conductive layer and the second conductive layer. The gate electrode of the second transistor and the second electrode of the capacitor are coplanar. An interlayer insulating film is located between the gate electrode of the first transistor and the oxide semiconductor of the second transistor. The display device includes a display area and a non-display area arranged around the display area and including a curved area, the curved area including a curved opening through the buffer layer, and In the curved region, the buffer layer includes a first portion and a second portion arranged sequentially from the curved opening, wherein the thickness of the first portion is less than the thickness of the second portion.

12. The display device according to claim 11, wherein, The first transistor is a p-type metal-oxide-semiconductor transistor, and the second transistor is an n-type metal-oxide-semiconductor transistor, or The first transistor is an n-type metal-oxide-semiconductor transistor, and the second transistor is a p-type metal-oxide-semiconductor transistor.

13. The display device according to claim 11, wherein, The display device further includes a lower light-shielding pattern that overlaps with at least a portion of the oxide semiconductor of the second transistor. The lower light-shielding pattern is located below the second transistor.

14. The display device according to claim 13, wherein, The lower light-shielding pattern is coplanar with the non-oxide semiconductor of the first transistor and comprises the same material as the non-oxide semiconductor of the first transistor.

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